diff options
Diffstat (limited to 'drivers/gpu/drm/radeon/atombios_crtc.c')
| -rw-r--r-- | drivers/gpu/drm/radeon/atombios_crtc.c | 56 |
1 files changed, 21 insertions, 35 deletions
diff --git a/drivers/gpu/drm/radeon/atombios_crtc.c b/drivers/gpu/drm/radeon/atombios_crtc.c index a515b2a09d85..87921c88a95c 100644 --- a/drivers/gpu/drm/radeon/atombios_crtc.c +++ b/drivers/gpu/drm/radeon/atombios_crtc.c | |||
| @@ -558,7 +558,7 @@ static u32 atombios_adjust_pll(struct drm_crtc *crtc, | |||
| 558 | bpc = connector->display_info.bpc; | 558 | bpc = connector->display_info.bpc; |
| 559 | encoder_mode = atombios_get_encoder_mode(encoder); | 559 | encoder_mode = atombios_get_encoder_mode(encoder); |
| 560 | if ((radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT | ATOM_DEVICE_DFP_SUPPORT)) || | 560 | if ((radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT | ATOM_DEVICE_DFP_SUPPORT)) || |
| 561 | radeon_encoder_is_dp_bridge(encoder)) { | 561 | (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE)) { |
| 562 | if (connector) { | 562 | if (connector) { |
| 563 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); | 563 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
| 564 | struct radeon_connector_atom_dig *dig_connector = | 564 | struct radeon_connector_atom_dig *dig_connector = |
| @@ -638,44 +638,29 @@ static u32 atombios_adjust_pll(struct drm_crtc *crtc, | |||
| 638 | if (ss_enabled && ss->percentage) | 638 | if (ss_enabled && ss->percentage) |
| 639 | args.v3.sInput.ucDispPllConfig |= | 639 | args.v3.sInput.ucDispPllConfig |= |
| 640 | DISPPLL_CONFIG_SS_ENABLE; | 640 | DISPPLL_CONFIG_SS_ENABLE; |
| 641 | if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT) || | 641 | if (ENCODER_MODE_IS_DP(encoder_mode)) { |
| 642 | radeon_encoder_is_dp_bridge(encoder)) { | 642 | args.v3.sInput.ucDispPllConfig |= |
| 643 | DISPPLL_CONFIG_COHERENT_MODE; | ||
| 644 | /* 16200 or 27000 */ | ||
| 645 | args.v3.sInput.usPixelClock = cpu_to_le16(dp_clock / 10); | ||
| 646 | } else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) { | ||
| 643 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; | 647 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; |
| 644 | if (encoder_mode == ATOM_ENCODER_MODE_DP) { | 648 | if (encoder_mode == ATOM_ENCODER_MODE_HDMI) |
| 649 | /* deep color support */ | ||
| 650 | args.v3.sInput.usPixelClock = | ||
| 651 | cpu_to_le16((mode->clock * bpc / 8) / 10); | ||
| 652 | if (dig->coherent_mode) | ||
| 645 | args.v3.sInput.ucDispPllConfig |= | 653 | args.v3.sInput.ucDispPllConfig |= |
| 646 | DISPPLL_CONFIG_COHERENT_MODE; | 654 | DISPPLL_CONFIG_COHERENT_MODE; |
| 647 | /* 16200 or 27000 */ | 655 | if (mode->clock > 165000) |
| 648 | args.v3.sInput.usPixelClock = cpu_to_le16(dp_clock / 10); | ||
| 649 | } else { | ||
| 650 | if (encoder_mode == ATOM_ENCODER_MODE_HDMI) { | ||
| 651 | /* deep color support */ | ||
| 652 | args.v3.sInput.usPixelClock = | ||
| 653 | cpu_to_le16((mode->clock * bpc / 8) / 10); | ||
| 654 | } | ||
| 655 | if (dig->coherent_mode) | ||
| 656 | args.v3.sInput.ucDispPllConfig |= | ||
| 657 | DISPPLL_CONFIG_COHERENT_MODE; | ||
| 658 | if (mode->clock > 165000) | ||
| 659 | args.v3.sInput.ucDispPllConfig |= | ||
| 660 | DISPPLL_CONFIG_DUAL_LINK; | ||
| 661 | } | ||
| 662 | } else if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { | ||
| 663 | if (encoder_mode == ATOM_ENCODER_MODE_DP) { | ||
| 664 | args.v3.sInput.ucDispPllConfig |= | 656 | args.v3.sInput.ucDispPllConfig |= |
| 665 | DISPPLL_CONFIG_COHERENT_MODE; | 657 | DISPPLL_CONFIG_DUAL_LINK; |
| 666 | /* 16200 or 27000 */ | ||
| 667 | args.v3.sInput.usPixelClock = cpu_to_le16(dp_clock / 10); | ||
| 668 | } else if (encoder_mode != ATOM_ENCODER_MODE_LVDS) { | ||
| 669 | if (mode->clock > 165000) | ||
| 670 | args.v3.sInput.ucDispPllConfig |= | ||
| 671 | DISPPLL_CONFIG_DUAL_LINK; | ||
| 672 | } | ||
| 673 | } | 658 | } |
| 674 | if (radeon_encoder_is_dp_bridge(encoder)) { | 659 | if (radeon_encoder_get_dp_bridge_encoder_id(encoder) != |
| 675 | struct drm_encoder *ext_encoder = radeon_atom_get_external_encoder(encoder); | 660 | ENCODER_OBJECT_ID_NONE) |
| 676 | struct radeon_encoder *ext_radeon_encoder = to_radeon_encoder(ext_encoder); | 661 | args.v3.sInput.ucExtTransmitterID = |
| 677 | args.v3.sInput.ucExtTransmitterID = ext_radeon_encoder->encoder_id; | 662 | radeon_encoder_get_dp_bridge_encoder_id(encoder); |
| 678 | } else | 663 | else |
| 679 | args.v3.sInput.ucExtTransmitterID = 0; | 664 | args.v3.sInput.ucExtTransmitterID = 0; |
| 680 | 665 | ||
| 681 | atom_execute_table(rdev->mode_info.atom_context, | 666 | atom_execute_table(rdev->mode_info.atom_context, |
| @@ -945,6 +930,7 @@ static void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode | |||
| 945 | bpc = connector->display_info.bpc; | 930 | bpc = connector->display_info.bpc; |
| 946 | 931 | ||
| 947 | switch (encoder_mode) { | 932 | switch (encoder_mode) { |
| 933 | case ATOM_ENCODER_MODE_DP_MST: | ||
| 948 | case ATOM_ENCODER_MODE_DP: | 934 | case ATOM_ENCODER_MODE_DP: |
| 949 | /* DP/eDP */ | 935 | /* DP/eDP */ |
| 950 | dp_clock = dig_connector->dp_clock / 10; | 936 | dp_clock = dig_connector->dp_clock / 10; |
| @@ -1450,7 +1436,7 @@ static int radeon_atom_pick_pll(struct drm_crtc *crtc) | |||
| 1450 | * PPLL/DCPLL programming and only program the DP DTO for the | 1436 | * PPLL/DCPLL programming and only program the DP DTO for the |
| 1451 | * crtc virtual pixel clock. | 1437 | * crtc virtual pixel clock. |
| 1452 | */ | 1438 | */ |
| 1453 | if (atombios_get_encoder_mode(test_encoder) == ATOM_ENCODER_MODE_DP) { | 1439 | if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(test_encoder))) { |
| 1454 | if (ASIC_IS_DCE5(rdev) || rdev->clock.dp_extclk) | 1440 | if (ASIC_IS_DCE5(rdev) || rdev->clock.dp_extclk) |
| 1455 | return ATOM_PPLL_INVALID; | 1441 | return ATOM_PPLL_INVALID; |
| 1456 | } | 1442 | } |