11 files changed, 63 insertions, 20 deletions

diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/nv50.c b/drivers/gpu/drm/nouveau/core/engine/disp/nv50.c
index 05a909a17cee..15b182c84ce8 100644
--- a/drivers/gpu/drm/nouveau/core/engine/disp/nv50.c
+++ b/drivers/gpu/drm/nouveau/core/engine/disp/nv50.c
@@ -49,13 +49,7 @@ nv50_disp_intr_vblank(struct nv50_disp_priv *priv, int crtc)
                 if (chan->vblank.crtc != crtc)
                         continue;
 
-                if (nv_device(priv)->chipset == 0x50) {
-                        nv_wr32(priv, 0x001704, chan->vblank.channel);
-                        nv_wr32(priv, 0x001710, 0x80000000 | chan->vblank.ctxdma);
-                        bar->flush(bar);
-                        nv_wr32(priv, 0x001570, chan->vblank.offset);
-                        nv_wr32(priv, 0x001574, chan->vblank.value);
-                } else {
+                if (nv_device(priv)->chipset >= 0xc0) {
                         nv_wr32(priv, 0x001718, 0x80000000 | chan->vblank.channel);
                         bar->flush(bar);
                         nv_wr32(priv, 0x06000c,
@@ -63,6 +57,17 @@ nv50_disp_intr_vblank(struct nv50_disp_priv *priv, int crtc)
                         nv_wr32(priv, 0x060010,
                                 lower_32_bits(chan->vblank.offset));
                         nv_wr32(priv, 0x060014, chan->vblank.value);
+                } else {
+                        nv_wr32(priv, 0x001704, chan->vblank.channel);
+                        nv_wr32(priv, 0x001710, 0x80000000 | chan->vblank.ctxdma);
+                        bar->flush(bar);
+                        if (nv_device(priv)->chipset == 0x50) {
+                                nv_wr32(priv, 0x001570, chan->vblank.offset);
+                                nv_wr32(priv, 0x001574, chan->vblank.value);
+                        } else {
+                                nv_wr32(priv, 0x060010, chan->vblank.offset);
+                                nv_wr32(priv, 0x060014, chan->vblank.value);
+                        }
                 }
 
                 list_del(&chan->vblank.head);
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/ctxnv40.c b/drivers/gpu/drm/nouveau/core/engine/graph/ctxnv40.c
index e45035efb8ca..7bbb1e1b7a8d 100644
--- a/drivers/gpu/drm/nouveau/core/engine/graph/ctxnv40.c
+++ b/drivers/gpu/drm/nouveau/core/engine/graph/ctxnv40.c
@@ -669,21 +669,27 @@ nv40_grctx_fill(struct nouveau_device *device, struct nouveau_gpuobj *mem)
                            });
 }
 
-void
+int
 nv40_grctx_init(struct nouveau_device *device, u32 *size)
 {
-        u32 ctxprog[256], i;
+        u32 *ctxprog = kmalloc(256 * 4, GFP_KERNEL), i;
         struct nouveau_grctx ctx = {
                 .device = device,
                 .mode = NOUVEAU_GRCTX_PROG,
                 .data = ctxprog,
-                .ctxprog_max = ARRAY_SIZE(ctxprog)
+                .ctxprog_max = 256,
         };
 
+        if (!ctxprog)
+                return -ENOMEM;
+
         nv40_grctx_generate(&ctx);
 
         nv_wr32(device, 0x400324, 0);
         for (i = 0; i < ctx.ctxprog_len; i++)
                 nv_wr32(device, 0x400328, ctxprog[i]);
         *size = ctx.ctxvals_pos * 4;
+
+        kfree(ctxprog);
+        return 0;
 }
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/nv40.c b/drivers/gpu/drm/nouveau/core/engine/graph/nv40.c
index 425001204a89..cc6574eeb80e 100644
--- a/drivers/gpu/drm/nouveau/core/engine/graph/nv40.c
+++ b/drivers/gpu/drm/nouveau/core/engine/graph/nv40.c
@@ -346,7 +346,9 @@ nv40_graph_init(struct nouveau_object *object)
                 return ret;
 
         /* generate and upload context program */
-        nv40_grctx_init(nv_device(priv), &priv->size);
+        ret = nv40_grctx_init(nv_device(priv), &priv->size);
+        if (ret)
+                return ret;
 
         /* No context present currently */
         nv_wr32(priv, NV40_PGRAPH_CTXCTL_CUR, 0x00000000);
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/nv40.h b/drivers/gpu/drm/nouveau/core/engine/graph/nv40.h
index d2ac975afc2e..7da35a4e7970 100644
--- a/drivers/gpu/drm/nouveau/core/engine/graph/nv40.h
+++ b/drivers/gpu/drm/nouveau/core/engine/graph/nv40.h
@@ -15,7 +15,7 @@ nv44_graph_class(void *priv)
         return !(0x0baf & (1 << (device->chipset & 0x0f)));
 }
 
-void nv40_grctx_init(struct nouveau_device *, u32 *size);
+int  nv40_grctx_init(struct nouveau_device *, u32 *size);
 void nv40_grctx_fill(struct nouveau_device *, struct nouveau_gpuobj *);
 
 #endif
diff --git a/drivers/gpu/drm/nouveau/core/include/core/object.h b/drivers/gpu/drm/nouveau/core/include/core/object.h
index 818feabbf4a0..486f1a9217fd 100644
--- a/drivers/gpu/drm/nouveau/core/include/core/object.h
+++ b/drivers/gpu/drm/nouveau/core/include/core/object.h
@@ -175,14 +175,18 @@ nv_mo32(void *obj, u32 addr, u32 mask, u32 data)
         return temp;
 }
 
-static inline bool
-nv_strncmp(void *obj, u32 addr, u32 len, const char *str)
+static inline int
+nv_memcmp(void *obj, u32 addr, const char *str, u32 len)
 {
+        unsigned char c1, c2;
+
         while (len--) {
-                if (nv_ro08(obj, addr++) != *(str++))
-                        return false;
+                c1 = nv_ro08(obj, addr++);
+                c2 = *(str++);
+                if (c1 != c2)
+                        return c1 - c2;
         }
-        return true;
+        return 0;
 }
 
 #endif
diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/clock.h b/drivers/gpu/drm/nouveau/core/include/subdev/clock.h
index 39e73b91d360..41b7a6a76f19 100644
--- a/drivers/gpu/drm/nouveau/core/include/subdev/clock.h
+++ b/drivers/gpu/drm/nouveau/core/include/subdev/clock.h
@@ -54,6 +54,7 @@ int nv04_clock_pll_calc(struct nouveau_clock *, struct nvbios_pll *,
                         int clk, struct nouveau_pll_vals *);
 int nv04_clock_pll_prog(struct nouveau_clock *, u32 reg1,
                         struct nouveau_pll_vals *);
-
+int nva3_clock_pll_calc(struct nouveau_clock *, struct nvbios_pll *,
+                        int clk, struct nouveau_pll_vals *);
 
 #endif
diff --git a/drivers/gpu/drm/nouveau/core/subdev/bios/dcb.c b/drivers/gpu/drm/nouveau/core/subdev/bios/dcb.c
index 7d750382a833..c51197157749 100644
--- a/drivers/gpu/drm/nouveau/core/subdev/bios/dcb.c
+++ b/drivers/gpu/drm/nouveau/core/subdev/bios/dcb.c
@@ -64,7 +64,7 @@ dcb_table(struct nouveau_bios *bios, u8 *ver, u8 *hdr, u8 *cnt, u8 *len)
                 }
         } else
         if (*ver >= 0x15) {
-                if (!nv_strncmp(bios, dcb - 7, 7, "DEV_REC")) {
+                if (!nv_memcmp(bios, dcb - 7, "DEV_REC", 7)) {
                         u16 i2c = nv_ro16(bios, dcb + 2);
                         *hdr = 4;
                         *cnt = (i2c - dcb) / 10;
diff --git a/drivers/gpu/drm/nouveau/core/subdev/clock/nva3.c b/drivers/gpu/drm/nouveau/core/subdev/clock/nva3.c
index cc8d7d162d7c..9068c98b96f6 100644
--- a/drivers/gpu/drm/nouveau/core/subdev/clock/nva3.c
+++ b/drivers/gpu/drm/nouveau/core/subdev/clock/nva3.c
@@ -66,6 +66,24 @@ nva3_clock_pll_set(struct nouveau_clock *clk, u32 type, u32 freq)
         return ret;
 }
 
+int
+nva3_clock_pll_calc(struct nouveau_clock *clock, struct nvbios_pll *info,
+                    int clk, struct nouveau_pll_vals *pv)
+{
+        int ret, N, M, P;
+
+        ret = nva3_pll_calc(clock, info, clk, &N, NULL, &M, &P);
+
+        if (ret > 0) {
+                pv->refclk = info->refclk;
+                pv->N1 = N;
+                pv->M1 = M;
+                pv->log2P = P;
+        }
+        return ret;
+}
+
+
 static int
 nva3_clock_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
                 struct nouveau_oclass *oclass, void *data, u32 size,
@@ -80,6 +98,7 @@ nva3_clock_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
                 return ret;
 
         priv->base.pll_set = nva3_clock_pll_set;
+        priv->base.pll_calc = nva3_clock_pll_calc;
         return 0;
 }
 
diff --git a/drivers/gpu/drm/nouveau/core/subdev/clock/nvc0.c b/drivers/gpu/drm/nouveau/core/subdev/clock/nvc0.c
index 5ccce0b17bf3..f6962c9b6c36 100644
--- a/drivers/gpu/drm/nouveau/core/subdev/clock/nvc0.c
+++ b/drivers/gpu/drm/nouveau/core/subdev/clock/nvc0.c
@@ -79,6 +79,7 @@ nvc0_clock_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
                 return ret;
 
         priv->base.pll_set = nvc0_clock_pll_set;
+        priv->base.pll_calc = nva3_clock_pll_calc;
         return 0;
 }
 
diff --git a/drivers/gpu/drm/nouveau/nouveau_abi16.c b/drivers/gpu/drm/nouveau/nouveau_abi16.c
index cc79c796afee..cbf1fc60a386 100644
--- a/drivers/gpu/drm/nouveau/nouveau_abi16.c
+++ b/drivers/gpu/drm/nouveau/nouveau_abi16.c
@@ -241,6 +241,10 @@ nouveau_abi16_ioctl_channel_alloc(ABI16_IOCTL_ARGS)
 
         if (unlikely(!abi16))
                 return -ENOMEM;
+
+        if (!drm->channel)
+                return nouveau_abi16_put(abi16, -ENODEV);
+
         client = nv_client(abi16->client);
 
         if (init->fb_ctxdma_handle == ~0 || init->tt_ctxdma_handle == ~0)
diff --git a/drivers/gpu/drm/nouveau/nouveau_drm.c b/drivers/gpu/drm/nouveau/nouveau_drm.c
index 0910125cbbc3..8503b2ea570a 100644
--- a/drivers/gpu/drm/nouveau/nouveau_drm.c
+++ b/drivers/gpu/drm/nouveau/nouveau_drm.c
@@ -129,7 +129,8 @@ nouveau_accel_init(struct nouveau_drm *drm)
 
         /* initialise synchronisation routines */
         if      (device->card_type < NV_10) ret = nv04_fence_create(drm);
-        else if (device->chipset   <  0x84) ret = nv10_fence_create(drm);
+        else if (device->card_type < NV_50) ret = nv10_fence_create(drm);
+        else if (device->chipset   <  0x84) ret = nv50_fence_create(drm);
         else if (device->card_type < NV_C0) ret = nv84_fence_create(drm);
         else                                ret = nvc0_fence_create(drm);
         if (ret) {