7 files changed, 45 insertions, 14 deletions

diff --git a/drivers/gpu/drm/nouveau/nouveau_acpi.c b/drivers/gpu/drm/nouveau/nouveau_acpi.c
index fc841e87b343..26ebffebe710 100644
--- a/drivers/gpu/drm/nouveau/nouveau_acpi.c
+++ b/drivers/gpu/drm/nouveau/nouveau_acpi.c
@@ -211,11 +211,6 @@ static int nouveau_dsm_power_state(enum vga_switcheroo_client_id id,
         return nouveau_dsm_set_discrete_state(nouveau_dsm_priv.dhandle, state);
 }
 
-static int nouveau_dsm_init(void)
-{
-        return 0;
-}
-
 static int nouveau_dsm_get_client_id(struct pci_dev *pdev)
 {
         /* easy option one - intel vendor ID means Integrated */
@@ -232,7 +227,6 @@ static int nouveau_dsm_get_client_id(struct pci_dev *pdev)
 static struct vga_switcheroo_handler nouveau_dsm_handler = {
         .switchto = nouveau_dsm_switchto,
         .power_state = nouveau_dsm_power_state,
-        .init = nouveau_dsm_init,
         .get_client_id = nouveau_dsm_get_client_id,
 };
 
diff --git a/drivers/gpu/drm/nouveau/nouveau_i2c.c b/drivers/gpu/drm/nouveau/nouveau_i2c.c
index 77e564667b5c..240cf962c999 100644
--- a/drivers/gpu/drm/nouveau/nouveau_i2c.c
+++ b/drivers/gpu/drm/nouveau/nouveau_i2c.c
@@ -229,7 +229,7 @@ nouveau_i2c_init(struct drm_device *dev)
                         }
                         break;
                 case 6: /* NV50- DP AUX */
-                        port->drive = entry[0];
+                        port->drive = entry[0] & 0x0f;
                         port->sense = port->drive;
                         port->adapter.algo = &nouveau_dp_i2c_algo;
                         break;
diff --git a/drivers/gpu/drm/nouveau/nouveau_state.c b/drivers/gpu/drm/nouveau/nouveau_state.c
index 1cdfd6e757ce..1866dbb49979 100644
--- a/drivers/gpu/drm/nouveau/nouveau_state.c
+++ b/drivers/gpu/drm/nouveau/nouveau_state.c
@@ -731,7 +731,6 @@ nouveau_card_init(struct drm_device *dev)
                         case 0xa3:
                         case 0xa5:
                         case 0xa8:
-                        case 0xaf:
                                 nva3_copy_create(dev);
                                 break;
                         }
diff --git a/drivers/gpu/drm/nouveau/nv84_fifo.c b/drivers/gpu/drm/nouveau/nv84_fifo.c
index cc82d799fc3b..c564c5e4c30a 100644
--- a/drivers/gpu/drm/nouveau/nv84_fifo.c
+++ b/drivers/gpu/drm/nouveau/nv84_fifo.c
@@ -117,17 +117,22 @@ nv84_fifo_context_del(struct nouveau_channel *chan, int engine)
         struct drm_device *dev = chan->dev;
         struct drm_nouveau_private *dev_priv = dev->dev_private;
         unsigned long flags;
+        u32 save;
 
         /* remove channel from playlist, will context switch if active */
         spin_lock_irqsave(&dev_priv->context_switch_lock, flags);
         nv_mask(dev, 0x002600 + (chan->id * 4), 0x80000000, 0x00000000);
         nv50_fifo_playlist_update(dev);
 
+        save = nv_mask(dev, 0x002520, 0x0000003f, 0x15);
+
         /* tell any engines on this channel to unload their contexts */
         nv_wr32(dev, 0x0032fc, chan->ramin->vinst >> 12);
         if (!nv_wait_ne(dev, 0x0032fc, 0xffffffff, 0xffffffff))
                 NV_INFO(dev, "PFIFO: channel %d unload timeout\n", chan->id);
 
+        nv_wr32(dev, 0x002520, save);
+
         nv_wr32(dev, 0x002600 + (chan->id * 4), 0x00000000);
         spin_unlock_irqrestore(&dev_priv->context_switch_lock, flags);
 
@@ -184,10 +189,13 @@ nv84_fifo_fini(struct drm_device *dev, int engine, bool suspend)
         struct drm_nouveau_private *dev_priv = dev->dev_private;
         struct nv84_fifo_priv *priv = nv_engine(dev, engine);
         int i;
+        u32 save;
 
         /* set playlist length to zero, fifo will unload context */
         nv_wr32(dev, 0x0032ec, 0);
 
+        save = nv_mask(dev, 0x002520, 0x0000003f, 0x15);
+
         /* tell all connected engines to unload their contexts */
         for (i = 0; i < priv->base.channels; i++) {
                 struct nouveau_channel *chan = dev_priv->channels.ptr[i];
@@ -199,6 +207,7 @@ nv84_fifo_fini(struct drm_device *dev, int engine, bool suspend)
                 }
         }
 
+        nv_wr32(dev, 0x002520, save);
         nv_wr32(dev, 0x002140, 0);
         return 0;
 }
diff --git a/drivers/gpu/drm/nouveau/nvc0_pm.c b/drivers/gpu/drm/nouveau/nvc0_pm.c
index 7c95c44e2887..4e712b10ebdb 100644
--- a/drivers/gpu/drm/nouveau/nvc0_pm.c
+++ b/drivers/gpu/drm/nouveau/nvc0_pm.c
@@ -557,7 +557,7 @@ prog_mem(struct drm_device *dev, struct nvc0_pm_state *info)
         nouveau_mem_exec(&exec, info->perflvl);
 
         if (dev_priv->chipset < 0xd0)
-                nv_wr32(dev, 0x611200, 0x00003300);
+                nv_wr32(dev, 0x611200, 0x00003330);
         else
                 nv_wr32(dev, 0x62c000, 0x03030300);
 }
diff --git a/drivers/gpu/drm/nouveau/nvd0_display.c b/drivers/gpu/drm/nouveau/nvd0_display.c
index d0d60e1e7f95..dac525b2994e 100644
--- a/drivers/gpu/drm/nouveau/nvd0_display.c
+++ b/drivers/gpu/drm/nouveau/nvd0_display.c
@@ -790,7 +790,7 @@ nvd0_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
         struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
         int ch = EVO_CURS(nv_crtc->index);
 
-        evo_piow(crtc->dev, ch, 0x0084, (y << 16) | x);
+        evo_piow(crtc->dev, ch, 0x0084, (y << 16) | (x & 0xffff));
         evo_piow(crtc->dev, ch, 0x0080, 0x00000000);
         return 0;
 }
diff --git a/drivers/gpu/drm/nouveau/nve0_fifo.c b/drivers/gpu/drm/nouveau/nve0_fifo.c
index 1855ecbd843b..e98d144e6eb9 100644
--- a/drivers/gpu/drm/nouveau/nve0_fifo.c
+++ b/drivers/gpu/drm/nouveau/nve0_fifo.c
@@ -294,6 +294,25 @@ nve0_fifo_isr_vm_fault(struct drm_device *dev, int unit)
         printk(" on channel 0x%010llx\n", (u64)inst << 12);
 }
 
+static int
+nve0_fifo_page_flip(struct drm_device *dev, u32 chid)
+{
+        struct nve0_fifo_priv *priv = nv_engine(dev, NVOBJ_ENGINE_FIFO);
+        struct drm_nouveau_private *dev_priv = dev->dev_private;
+        struct nouveau_channel *chan = NULL;
+        unsigned long flags;
+        int ret = -EINVAL;
+
+        spin_lock_irqsave(&dev_priv->channels.lock, flags);
+        if (likely(chid >= 0 && chid < priv->base.channels)) {
+                chan = dev_priv->channels.ptr[chid];
+                if (likely(chan))
+                        ret = nouveau_finish_page_flip(chan, NULL);
+        }
+        spin_unlock_irqrestore(&dev_priv->channels.lock, flags);
+        return ret;
+}
+
 static void
 nve0_fifo_isr_subfifo_intr(struct drm_device *dev, int unit)
 {
@@ -303,11 +322,21 @@ nve0_fifo_isr_subfifo_intr(struct drm_device *dev, int unit)
         u32 chid = nv_rd32(dev, 0x040120 + (unit * 0x2000)) & 0x7f;
         u32 subc = (addr & 0x00070000);
         u32 mthd = (addr & 0x00003ffc);
+        u32 show = stat;
+
+        if (stat & 0x00200000) {
+                if (mthd == 0x0054) {
+                        if (!nve0_fifo_page_flip(dev, chid))
+                                show &= ~0x00200000;
+                }
+        }
 
-        NV_INFO(dev, "PSUBFIFO %d:", unit);
-        nouveau_bitfield_print(nve0_fifo_subfifo_intr, stat);
-        NV_INFO(dev, "PSUBFIFO %d: ch %d subc %d mthd 0x%04x data 0x%08x\n",
-                unit, chid, subc, mthd, data);
+        if (show) {
+                NV_INFO(dev, "PFIFO%d:", unit);
+                nouveau_bitfield_print(nve0_fifo_subfifo_intr, show);
+                NV_INFO(dev, "PFIFO%d: ch %d subc %d mthd 0x%04x data 0x%08x\n",
+                        unit, chid, subc, mthd, data);
+        }
 
         nv_wr32(dev, 0x0400c0 + (unit * 0x2000), 0x80600008);
         nv_wr32(dev, 0x040108 + (unit * 0x2000), stat);