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-rw-r--r--drivers/gpu/drm/nouveau/Makefile3
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_pm.h5
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_state.c5
-rw-r--r--drivers/gpu/drm/nouveau/nv50_pm.c126
4 files changed, 138 insertions, 1 deletions
diff --git a/drivers/gpu/drm/nouveau/Makefile b/drivers/gpu/drm/nouveau/Makefile
index 2fd61888a83d..c5319901e95c 100644
--- a/drivers/gpu/drm/nouveau/Makefile
+++ b/drivers/gpu/drm/nouveau/Makefile
@@ -24,7 +24,8 @@ nouveau-y := nouveau_drv.o nouveau_state.o nouveau_channel.o nouveau_mem.o \
24 nv04_dac.o nv04_dfp.o nv04_tv.o nv17_tv.o nv17_tv_modes.o \ 24 nv04_dac.o nv04_dfp.o nv04_tv.o nv17_tv.o nv17_tv_modes.o \
25 nv04_crtc.o nv04_display.o nv04_cursor.o nv04_fbcon.o \ 25 nv04_crtc.o nv04_display.o nv04_cursor.o nv04_fbcon.o \
26 nv10_gpio.o nv50_gpio.o \ 26 nv10_gpio.o nv50_gpio.o \
27 nv50_calc.o 27 nv50_calc.o \
28 nv50_pm.o
28 29
29nouveau-$(CONFIG_DRM_NOUVEAU_DEBUG) += nouveau_debugfs.o 30nouveau-$(CONFIG_DRM_NOUVEAU_DEBUG) += nouveau_debugfs.o
30nouveau-$(CONFIG_COMPAT) += nouveau_ioc32.o 31nouveau-$(CONFIG_COMPAT) += nouveau_ioc32.o
diff --git a/drivers/gpu/drm/nouveau/nouveau_pm.h b/drivers/gpu/drm/nouveau/nouveau_pm.h
index a401ec0a1269..81d27722964b 100644
--- a/drivers/gpu/drm/nouveau/nouveau_pm.h
+++ b/drivers/gpu/drm/nouveau/nouveau_pm.h
@@ -41,4 +41,9 @@ int nouveau_voltage_gpio_set(struct drm_device *, int voltage);
41void nouveau_perf_init(struct drm_device *); 41void nouveau_perf_init(struct drm_device *);
42void nouveau_perf_fini(struct drm_device *); 42void nouveau_perf_fini(struct drm_device *);
43 43
44/* nv50_pm.c */
45int nv50_pm_clock_get(struct drm_device *, u32 id);
46void *nv50_pm_clock_pre(struct drm_device *, u32 id, int khz);
47void nv50_pm_clock_set(struct drm_device *, void *);
48
44#endif 49#endif
diff --git a/drivers/gpu/drm/nouveau/nouveau_state.c b/drivers/gpu/drm/nouveau/nouveau_state.c
index 18c4a8a85940..bbe9ba015bca 100644
--- a/drivers/gpu/drm/nouveau/nouveau_state.c
+++ b/drivers/gpu/drm/nouveau/nouveau_state.c
@@ -355,6 +355,11 @@ static int nouveau_init_engine_ptrs(struct drm_device *dev)
355 engine->gpio.get = nv50_gpio_get; 355 engine->gpio.get = nv50_gpio_get;
356 engine->gpio.set = nv50_gpio_set; 356 engine->gpio.set = nv50_gpio_set;
357 engine->gpio.irq_enable = nv50_gpio_irq_enable; 357 engine->gpio.irq_enable = nv50_gpio_irq_enable;
358 engine->pm.clock_get = nv50_pm_clock_get;
359 engine->pm.clock_pre = nv50_pm_clock_pre;
360 engine->pm.clock_set = nv50_pm_clock_set;
361 engine->pm.voltage_get = nouveau_voltage_gpio_get;
362 engine->pm.voltage_set = nouveau_voltage_gpio_set;
358 break; 363 break;
359 case 0xC0: 364 case 0xC0:
360 engine->instmem.init = nvc0_instmem_init; 365 engine->instmem.init = nvc0_instmem_init;
diff --git a/drivers/gpu/drm/nouveau/nv50_pm.c b/drivers/gpu/drm/nouveau/nv50_pm.c
new file mode 100644
index 000000000000..a616e4240346
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/nv50_pm.c
@@ -0,0 +1,126 @@
1/*
2 * Copyright 2010 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs
23 */
24
25#include "drmP.h"
26#include "nouveau_drv.h"
27#include "nouveau_pm.h"
28
29/*XXX: boards using limits 0x40 need fixing, the register layout
30 * is correct here, but, there's some other funny magic
31 * that modifies things, so it's not likely we'll set/read
32 * the correct timings yet.. working on it...
33 */
34
35struct nv50_pm_state {
36 struct pll_lims pll;
37 enum pll_types type;
38 int N, M, P;
39};
40
41int
42nv50_pm_clock_get(struct drm_device *dev, u32 id)
43{
44 struct pll_lims pll;
45 int P, N, M, ret;
46 u32 reg0, reg1;
47
48 ret = get_pll_limits(dev, id, &pll);
49 if (ret)
50 return ret;
51
52 if (pll.vco2.maxfreq) {
53 reg0 = nv_rd32(dev, pll.reg + 0);
54 reg1 = nv_rd32(dev, pll.reg + 4);
55 P = (reg0 & 0x00070000) >> 16;
56 N = (reg1 & 0x0000ff00) >> 8;
57 M = (reg1 & 0x000000ff);
58
59 return ((pll.refclk * N / M) >> P);
60 }
61
62 reg0 = nv_rd32(dev, pll.reg + 4);
63 P = (reg0 & 0x003f0000) >> 16;
64 N = (reg0 & 0x0000ff00) >> 8;
65 M = (reg0 & 0x000000ff);
66 return pll.refclk * N / M / P;
67}
68
69void *
70nv50_pm_clock_pre(struct drm_device *dev, u32 id, int khz)
71{
72 struct nv50_pm_state *state;
73 int dummy, ret;
74
75 state = kzalloc(sizeof(*state), GFP_KERNEL);
76 if (!state)
77 return ERR_PTR(-ENOMEM);
78 state->type = id;
79
80 ret = get_pll_limits(dev, id, &state->pll);
81 if (ret < 0) {
82 kfree(state);
83 return ERR_PTR(ret);
84 }
85
86 ret = nv50_calc_pll(dev, &state->pll, khz, &state->N, &state->M,
87 &dummy, &dummy, &state->P);
88 if (ret < 0) {
89 kfree(state);
90 return ERR_PTR(ret);
91 }
92
93 return state;
94}
95
96void
97nv50_pm_clock_set(struct drm_device *dev, void *pre_state)
98{
99 struct nv50_pm_state *state = pre_state;
100 u32 reg = state->pll.reg, tmp;
101 int N = state->N;
102 int M = state->M;
103 int P = state->P;
104
105 if (state->pll.vco2.maxfreq) {
106 if (state->type == PLL_MEMORY) {
107 nv_wr32(dev, 0x100210, 0);
108 nv_wr32(dev, 0x1002dc, 1);
109 }
110
111 tmp = nv_rd32(dev, reg + 0) & 0xfff8ffff;
112 tmp |= 0x80000000 | (P << 16);
113 nv_wr32(dev, reg + 0, tmp);
114 nv_wr32(dev, reg + 4, (N << 8) | M);
115
116 if (state->type == PLL_MEMORY) {
117 nv_wr32(dev, 0x1002dc, 0);
118 nv_wr32(dev, 0x100210, 0x80000000);
119 }
120 } else {
121 nv_wr32(dev, reg + 4, (P << 16) | (N << 8) | M);
122 }
123
124 kfree(state);
125}
126