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Diffstat (limited to 'drivers/gpu/drm/nouveau')
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_bios.h5
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_display.c10
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_drv.c2
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_gem.c23
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_mxm.c9
-rw-r--r--drivers/gpu/drm/nouveau/nv50_pm.c4
6 files changed, 46 insertions, 7 deletions
diff --git a/drivers/gpu/drm/nouveau/nouveau_bios.h b/drivers/gpu/drm/nouveau/nouveau_bios.h
index 1e382ad5a2b8..a37c31e358aa 100644
--- a/drivers/gpu/drm/nouveau/nouveau_bios.h
+++ b/drivers/gpu/drm/nouveau/nouveau_bios.h
@@ -54,9 +54,10 @@ struct bit_entry {
54int bit_table(struct drm_device *, u8 id, struct bit_entry *); 54int bit_table(struct drm_device *, u8 id, struct bit_entry *);
55 55
56enum dcb_gpio_tag { 56enum dcb_gpio_tag {
57 DCB_GPIO_TVDAC0 = 0xc, 57 DCB_GPIO_PANEL_POWER = 0x01,
58 DCB_GPIO_TVDAC0 = 0x0c,
58 DCB_GPIO_TVDAC1 = 0x2d, 59 DCB_GPIO_TVDAC1 = 0x2d,
59 DCB_GPIO_PWM_FAN = 0x9, 60 DCB_GPIO_PWM_FAN = 0x09,
60 DCB_GPIO_FAN_SENSE = 0x3d, 61 DCB_GPIO_FAN_SENSE = 0x3d,
61 DCB_GPIO_UNUSED = 0xff 62 DCB_GPIO_UNUSED = 0xff
62}; 63};
diff --git a/drivers/gpu/drm/nouveau/nouveau_display.c b/drivers/gpu/drm/nouveau/nouveau_display.c
index 3cb52bc52b21..795a9e3c990a 100644
--- a/drivers/gpu/drm/nouveau/nouveau_display.c
+++ b/drivers/gpu/drm/nouveau/nouveau_display.c
@@ -219,6 +219,16 @@ nouveau_display_init(struct drm_device *dev)
219 if (ret) 219 if (ret)
220 return ret; 220 return ret;
221 221
222 /* power on internal panel if it's not already. the init tables of
223 * some vbios default this to off for some reason, causing the
224 * panel to not work after resume
225 */
226 if (nouveau_gpio_func_get(dev, DCB_GPIO_PANEL_POWER) == 0) {
227 nouveau_gpio_func_set(dev, DCB_GPIO_PANEL_POWER, true);
228 msleep(300);
229 }
230
231 /* enable polling for external displays */
222 drm_kms_helper_poll_enable(dev); 232 drm_kms_helper_poll_enable(dev);
223 233
224 /* enable hotplug interrupts */ 234 /* enable hotplug interrupts */
diff --git a/drivers/gpu/drm/nouveau/nouveau_drv.c b/drivers/gpu/drm/nouveau/nouveau_drv.c
index e4a7cfe7898d..81d7962e7252 100644
--- a/drivers/gpu/drm/nouveau/nouveau_drv.c
+++ b/drivers/gpu/drm/nouveau/nouveau_drv.c
@@ -124,7 +124,7 @@ MODULE_PARM_DESC(ctxfw, "Use external HUB/GPC ucode (fermi)\n");
124int nouveau_ctxfw; 124int nouveau_ctxfw;
125module_param_named(ctxfw, nouveau_ctxfw, int, 0400); 125module_param_named(ctxfw, nouveau_ctxfw, int, 0400);
126 126
127MODULE_PARM_DESC(ctxfw, "Santise DCB table according to MXM-SIS\n"); 127MODULE_PARM_DESC(mxmdcb, "Santise DCB table according to MXM-SIS\n");
128int nouveau_mxmdcb = 1; 128int nouveau_mxmdcb = 1;
129module_param_named(mxmdcb, nouveau_mxmdcb, int, 0400); 129module_param_named(mxmdcb, nouveau_mxmdcb, int, 0400);
130 130
diff --git a/drivers/gpu/drm/nouveau/nouveau_gem.c b/drivers/gpu/drm/nouveau/nouveau_gem.c
index 5f0bc57fdaab..7ce3fde40743 100644
--- a/drivers/gpu/drm/nouveau/nouveau_gem.c
+++ b/drivers/gpu/drm/nouveau/nouveau_gem.c
@@ -380,6 +380,25 @@ retry:
380} 380}
381 381
382static int 382static int
383validate_sync(struct nouveau_channel *chan, struct nouveau_bo *nvbo)
384{
385 struct nouveau_fence *fence = NULL;
386 int ret = 0;
387
388 spin_lock(&nvbo->bo.bdev->fence_lock);
389 if (nvbo->bo.sync_obj)
390 fence = nouveau_fence_ref(nvbo->bo.sync_obj);
391 spin_unlock(&nvbo->bo.bdev->fence_lock);
392
393 if (fence) {
394 ret = nouveau_fence_sync(fence, chan);
395 nouveau_fence_unref(&fence);
396 }
397
398 return ret;
399}
400
401static int
383validate_list(struct nouveau_channel *chan, struct list_head *list, 402validate_list(struct nouveau_channel *chan, struct list_head *list,
384 struct drm_nouveau_gem_pushbuf_bo *pbbo, uint64_t user_pbbo_ptr) 403 struct drm_nouveau_gem_pushbuf_bo *pbbo, uint64_t user_pbbo_ptr)
385{ 404{
@@ -393,7 +412,7 @@ validate_list(struct nouveau_channel *chan, struct list_head *list,
393 list_for_each_entry(nvbo, list, entry) { 412 list_for_each_entry(nvbo, list, entry) {
394 struct drm_nouveau_gem_pushbuf_bo *b = &pbbo[nvbo->pbbo_index]; 413 struct drm_nouveau_gem_pushbuf_bo *b = &pbbo[nvbo->pbbo_index];
395 414
396 ret = nouveau_fence_sync(nvbo->bo.sync_obj, chan); 415 ret = validate_sync(chan, nvbo);
397 if (unlikely(ret)) { 416 if (unlikely(ret)) {
398 NV_ERROR(dev, "fail pre-validate sync\n"); 417 NV_ERROR(dev, "fail pre-validate sync\n");
399 return ret; 418 return ret;
@@ -416,7 +435,7 @@ validate_list(struct nouveau_channel *chan, struct list_head *list,
416 return ret; 435 return ret;
417 } 436 }
418 437
419 ret = nouveau_fence_sync(nvbo->bo.sync_obj, chan); 438 ret = validate_sync(chan, nvbo);
420 if (unlikely(ret)) { 439 if (unlikely(ret)) {
421 NV_ERROR(dev, "fail post-validate sync\n"); 440 NV_ERROR(dev, "fail post-validate sync\n");
422 return ret; 441 return ret;
diff --git a/drivers/gpu/drm/nouveau/nouveau_mxm.c b/drivers/gpu/drm/nouveau/nouveau_mxm.c
index 8bccddf4eff0..e5a64f0f4cb7 100644
--- a/drivers/gpu/drm/nouveau/nouveau_mxm.c
+++ b/drivers/gpu/drm/nouveau/nouveau_mxm.c
@@ -656,7 +656,16 @@ nouveau_mxm_init(struct drm_device *dev)
656 656
657 if (mxm_shadow(dev, mxm[0])) { 657 if (mxm_shadow(dev, mxm[0])) {
658 MXM_MSG(dev, "failed to locate valid SIS\n"); 658 MXM_MSG(dev, "failed to locate valid SIS\n");
659#if 0
660 /* we should, perhaps, fall back to some kind of limited
661 * mode here if the x86 vbios hasn't already done the
662 * work for us (so we prevent loading with completely
663 * whacked vbios tables).
664 */
659 return -EINVAL; 665 return -EINVAL;
666#else
667 return 0;
668#endif
660 } 669 }
661 670
662 MXM_MSG(dev, "MXMS Version %d.%d\n", 671 MXM_MSG(dev, "MXMS Version %d.%d\n",
diff --git a/drivers/gpu/drm/nouveau/nv50_pm.c b/drivers/gpu/drm/nouveau/nv50_pm.c
index 03937212e9d8..ec5481dfcd82 100644
--- a/drivers/gpu/drm/nouveau/nv50_pm.c
+++ b/drivers/gpu/drm/nouveau/nv50_pm.c
@@ -495,9 +495,9 @@ nv50_pm_clocks_pre(struct drm_device *dev, struct nouveau_pm_level *perflvl)
495 struct drm_nouveau_private *dev_priv = dev->dev_private; 495 struct drm_nouveau_private *dev_priv = dev->dev_private;
496 struct nv50_pm_state *info; 496 struct nv50_pm_state *info;
497 struct pll_lims pll; 497 struct pll_lims pll;
498 int ret = -EINVAL; 498 int clk, ret = -EINVAL;
499 int N, M, P1, P2; 499 int N, M, P1, P2;
500 u32 clk, out; 500 u32 out;
501 501
502 if (dev_priv->chipset == 0xaa || 502 if (dev_priv->chipset == 0xaa ||
503 dev_priv->chipset == 0xac) 503 dev_priv->chipset == 0xac)