168 files changed, 15665 insertions, 13452 deletions

diff --git a/drivers/gpu/drm/nouveau/Kconfig b/drivers/gpu/drm/nouveau/Kconfig
index a7ff6d5a34b9..ff80f12480ea 100644
--- a/drivers/gpu/drm/nouveau/Kconfig
+++ b/drivers/gpu/drm/nouveau/Kconfig
@@ -15,6 +15,13 @@ config DRM_NOUVEAU
         select ACPI_WMI if ACPI && X86
         select MXM_WMI if ACPI && X86
         select POWER_SUPPLY
+        # Similar to i915, we need to select ACPI_VIDEO and it's dependencies
+        select BACKLIGHT_LCD_SUPPORT if ACPI && X86
+        select BACKLIGHT_CLASS_DEVICE if ACPI && X86
+        select VIDEO_OUTPUT_CONTROL if ACPI && X86
+        select INPUT if ACPI && X86
+        select THERMAL if ACPI && X86
+        select ACPI_VIDEO if ACPI && X86
         help
           Choose this option for open-source nVidia support.
 
diff --git a/drivers/gpu/drm/nouveau/Makefile b/drivers/gpu/drm/nouveau/Makefile
index 998e8b4444f3..d939a1da3203 100644
--- a/drivers/gpu/drm/nouveau/Makefile
+++ b/drivers/gpu/drm/nouveau/Makefile
@@ -12,7 +12,6 @@ nouveau-y += core/core/engctx.o
 nouveau-y += core/core/engine.o
 nouveau-y += core/core/enum.o
 nouveau-y += core/core/event.o
-nouveau-y += core/core/falcon.o
 nouveau-y += core/core/gpuobj.o
 nouveau-y += core/core/handle.o
 nouveau-y += core/core/mm.o
@@ -60,6 +59,8 @@ nouveau-y += core/subdev/devinit/nv10.o
 nouveau-y += core/subdev/devinit/nv1a.o
 nouveau-y += core/subdev/devinit/nv20.o
 nouveau-y += core/subdev/devinit/nv50.o
+nouveau-y += core/subdev/devinit/nva3.o
+nouveau-y += core/subdev/devinit/nvc0.o
 nouveau-y += core/subdev/fb/base.o
 nouveau-y += core/subdev/fb/nv04.o
 nouveau-y += core/subdev/fb/nv10.o
@@ -78,6 +79,17 @@ nouveau-y += core/subdev/fb/nv49.o
 nouveau-y += core/subdev/fb/nv4e.o
 nouveau-y += core/subdev/fb/nv50.o
 nouveau-y += core/subdev/fb/nvc0.o
+nouveau-y += core/subdev/fb/ramnv04.o
+nouveau-y += core/subdev/fb/ramnv10.o
+nouveau-y += core/subdev/fb/ramnv1a.o
+nouveau-y += core/subdev/fb/ramnv20.o
+nouveau-y += core/subdev/fb/ramnv40.o
+nouveau-y += core/subdev/fb/ramnv41.o
+nouveau-y += core/subdev/fb/ramnv44.o
+nouveau-y += core/subdev/fb/ramnv49.o
+nouveau-y += core/subdev/fb/ramnv4e.o
+nouveau-y += core/subdev/fb/ramnv50.o
+nouveau-y += core/subdev/fb/ramnvc0.o
 nouveau-y += core/subdev/gpio/base.o
 nouveau-y += core/subdev/gpio/nv10.o
 nouveau-y += core/subdev/gpio/nv50.o
@@ -129,12 +141,15 @@ nouveau-y += core/subdev/vm/nv44.o
 nouveau-y += core/subdev/vm/nv50.o
 nouveau-y += core/subdev/vm/nvc0.o
 
+nouveau-y += core/engine/falcon.o
+nouveau-y += core/engine/xtensa.o
 nouveau-y += core/engine/dmaobj/base.o
 nouveau-y += core/engine/dmaobj/nv04.o
 nouveau-y += core/engine/dmaobj/nv50.o
 nouveau-y += core/engine/dmaobj/nvc0.o
 nouveau-y += core/engine/dmaobj/nvd0.o
 nouveau-y += core/engine/bsp/nv84.o
+nouveau-y += core/engine/bsp/nv98.o
 nouveau-y += core/engine/bsp/nvc0.o
 nouveau-y += core/engine/bsp/nve0.o
 nouveau-y += core/engine/copy/nva3.o
@@ -185,7 +200,13 @@ nouveau-y += core/engine/fifo/nve0.o
 nouveau-y += core/engine/graph/ctxnv40.o
 nouveau-y += core/engine/graph/ctxnv50.o
 nouveau-y += core/engine/graph/ctxnvc0.o
-nouveau-y += core/engine/graph/ctxnve0.o
+nouveau-y += core/engine/graph/ctxnvc1.o
+nouveau-y += core/engine/graph/ctxnvc3.o
+nouveau-y += core/engine/graph/ctxnvc8.o
+nouveau-y += core/engine/graph/ctxnvd7.o
+nouveau-y += core/engine/graph/ctxnvd9.o
+nouveau-y += core/engine/graph/ctxnve4.o
+nouveau-y += core/engine/graph/ctxnvf0.o
 nouveau-y += core/engine/graph/nv04.o
 nouveau-y += core/engine/graph/nv10.o
 nouveau-y += core/engine/graph/nv20.o
@@ -197,7 +218,13 @@ nouveau-y += core/engine/graph/nv35.o
 nouveau-y += core/engine/graph/nv40.o
 nouveau-y += core/engine/graph/nv50.o
 nouveau-y += core/engine/graph/nvc0.o
-nouveau-y += core/engine/graph/nve0.o
+nouveau-y += core/engine/graph/nvc1.o
+nouveau-y += core/engine/graph/nvc3.o
+nouveau-y += core/engine/graph/nvc8.o
+nouveau-y += core/engine/graph/nvd7.o
+nouveau-y += core/engine/graph/nvd9.o
+nouveau-y += core/engine/graph/nve4.o
+nouveau-y += core/engine/graph/nvf0.o
 nouveau-y += core/engine/mpeg/nv31.o
 nouveau-y += core/engine/mpeg/nv40.o
 nouveau-y += core/engine/mpeg/nv50.o
@@ -209,6 +236,7 @@ nouveau-y += core/engine/software/nv10.o
 nouveau-y += core/engine/software/nv50.o
 nouveau-y += core/engine/software/nvc0.o
 nouveau-y += core/engine/vp/nv84.o
+nouveau-y += core/engine/vp/nv98.o
 nouveau-y += core/engine/vp/nvc0.o
 nouveau-y += core/engine/vp/nve0.o
 
diff --git a/drivers/gpu/drm/nouveau/core/core/mm.c b/drivers/gpu/drm/nouveau/core/core/mm.c
index 0261a11b2ae0..d8291724dbd4 100644
--- a/drivers/gpu/drm/nouveau/core/core/mm.c
+++ b/drivers/gpu/drm/nouveau/core/core/mm.c
@@ -208,7 +208,6 @@ nouveau_mm_init(struct nouveau_mm *mm, u32 offset, u32 length, u32 block)
         struct nouveau_mm_node *node;
 
         if (block) {
-                mutex_init(&mm->mutex);
                 INIT_LIST_HEAD(&mm->nodes);
                 INIT_LIST_HEAD(&mm->free);
                 mm->block_size = block;
diff --git a/drivers/gpu/drm/nouveau/core/engine/bsp/nv84.c b/drivers/gpu/drm/nouveau/core/engine/bsp/nv84.c
index 1d9f614cb97d..1e8e75c0684a 100644
--- a/drivers/gpu/drm/nouveau/core/engine/bsp/nv84.c
+++ b/drivers/gpu/drm/nouveau/core/engine/bsp/nv84.c
@@ -19,24 +19,19 @@
  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  * OTHER DEALINGS IN THE SOFTWARE.
  *
- * Authors: Ben Skeggs
+ * Authors: Ben Skeggs, Ilia Mirkin
  */
 
-#include <core/engctx.h>
-#include <core/class.h>
-
+#include <engine/xtensa.h>
 #include <engine/bsp.h>
 
-struct nv84_bsp_priv {
-        struct nouveau_engine base;
-};
-
 /*******************************************************************************
  * BSP object classes
  ******************************************************************************/
 
 static struct nouveau_oclass
 nv84_bsp_sclass[] = {
+        { 0x74b0, &nouveau_object_ofuncs },
         {},
 };
 
@@ -48,7 +43,7 @@ static struct nouveau_oclass
 nv84_bsp_cclass = {
         .handle = NV_ENGCTX(BSP, 0x84),
         .ofuncs = &(struct nouveau_ofuncs) {
-                .ctor = _nouveau_engctx_ctor,
+                .ctor = _nouveau_xtensa_engctx_ctor,
                 .dtor = _nouveau_engctx_dtor,
                 .init = _nouveau_engctx_init,
                 .fini = _nouveau_engctx_fini,
@@ -66,10 +61,10 @@ nv84_bsp_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
               struct nouveau_oclass *oclass, void *data, u32 size,
               struct nouveau_object **pobject)
 {
-        struct nv84_bsp_priv *priv;
+        struct nouveau_xtensa *priv;
         int ret;
 
-        ret = nouveau_engine_create(parent, engine, oclass, true,
+        ret = nouveau_xtensa_create(parent, engine, oclass, 0x103000, true,
                                     "PBSP", "bsp", &priv);
         *pobject = nv_object(priv);
         if (ret)
@@ -78,6 +73,8 @@ nv84_bsp_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
         nv_subdev(priv)->unit = 0x04008000;
         nv_engine(priv)->cclass = &nv84_bsp_cclass;
         nv_engine(priv)->sclass = nv84_bsp_sclass;
+        priv->fifo_val = 0x1111;
+        priv->unkd28 = 0x90044;
         return 0;
 }
 
@@ -86,8 +83,10 @@ nv84_bsp_oclass = {
         .handle = NV_ENGINE(BSP, 0x84),
         .ofuncs = &(struct nouveau_ofuncs) {
                 .ctor = nv84_bsp_ctor,
-                .dtor = _nouveau_engine_dtor,
-                .init = _nouveau_engine_init,
-                .fini = _nouveau_engine_fini,
+                .dtor = _nouveau_xtensa_dtor,
+                .init = _nouveau_xtensa_init,
+                .fini = _nouveau_xtensa_fini,
+                .rd32 = _nouveau_xtensa_rd32,
+                .wr32 = _nouveau_xtensa_wr32,
         },
 };
diff --git a/drivers/gpu/drm/nouveau/core/engine/bsp/nv98.c b/drivers/gpu/drm/nouveau/core/engine/bsp/nv98.c
new file mode 100644
index 000000000000..8bf92b0e6d82
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/core/engine/bsp/nv98.c
@@ -0,0 +1,93 @@
+/*
+ * Copyright 2012 Red Hat Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Ben Skeggs
+ */
+
+#include <core/engctx.h>
+#include <core/class.h>
+
+#include <engine/bsp.h>
+
+struct nv98_bsp_priv {
+        struct nouveau_engine base;
+};
+
+/*******************************************************************************
+ * BSP object classes
+ ******************************************************************************/
+
+static struct nouveau_oclass
+nv98_bsp_sclass[] = {
+        {},
+};
+
+/*******************************************************************************
+ * BSP context
+ ******************************************************************************/
+
+static struct nouveau_oclass
+nv98_bsp_cclass = {
+        .handle = NV_ENGCTX(BSP, 0x98),
+        .ofuncs = &(struct nouveau_ofuncs) {
+                .ctor = _nouveau_engctx_ctor,
+                .dtor = _nouveau_engctx_dtor,
+                .init = _nouveau_engctx_init,
+                .fini = _nouveau_engctx_fini,
+                .rd32 = _nouveau_engctx_rd32,
+                .wr32 = _nouveau_engctx_wr32,
+        },
+};
+
+/*******************************************************************************
+ * BSP engine/subdev functions
+ ******************************************************************************/
+
+static int
+nv98_bsp_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
+              struct nouveau_oclass *oclass, void *data, u32 size,
+              struct nouveau_object **pobject)
+{
+        struct nv98_bsp_priv *priv;
+        int ret;
+
+        ret = nouveau_engine_create(parent, engine, oclass, true,
+                                    "PBSP", "bsp", &priv);
+        *pobject = nv_object(priv);
+        if (ret)
+                return ret;
+
+        nv_subdev(priv)->unit = 0x04008000;
+        nv_engine(priv)->cclass = &nv98_bsp_cclass;
+        nv_engine(priv)->sclass = nv98_bsp_sclass;
+        return 0;
+}
+
+struct nouveau_oclass
+nv98_bsp_oclass = {
+        .handle = NV_ENGINE(BSP, 0x98),
+        .ofuncs = &(struct nouveau_ofuncs) {
+                .ctor = nv98_bsp_ctor,
+                .dtor = _nouveau_engine_dtor,
+                .init = _nouveau_engine_init,
+                .fini = _nouveau_engine_fini,
+        },
+};
diff --git a/drivers/gpu/drm/nouveau/core/engine/bsp/nvc0.c b/drivers/gpu/drm/nouveau/core/engine/bsp/nvc0.c
index 0a5aa6bb0870..262c9f5f5f60 100644
--- a/drivers/gpu/drm/nouveau/core/engine/bsp/nvc0.c
+++ b/drivers/gpu/drm/nouveau/core/engine/bsp/nvc0.c
@@ -22,8 +22,7 @@
  * Authors: Maarten Lankhorst
  */
 
-#include <core/falcon.h>
-
+#include <engine/falcon.h>
 #include <engine/bsp.h>
 
 struct nvc0_bsp_priv {
diff --git a/drivers/gpu/drm/nouveau/core/engine/bsp/nve0.c b/drivers/gpu/drm/nouveau/core/engine/bsp/nve0.c
index d4f23bbd75b4..c46882c83982 100644
--- a/drivers/gpu/drm/nouveau/core/engine/bsp/nve0.c
+++ b/drivers/gpu/drm/nouveau/core/engine/bsp/nve0.c
@@ -22,8 +22,7 @@
  * Authors: Ben Skeggs
  */
 
-#include <core/falcon.h>
-
+#include <engine/falcon.h>
 #include <engine/bsp.h>
 
 struct nve0_bsp_priv {
diff --git a/drivers/gpu/drm/nouveau/core/engine/copy/fuc/nva3.fuc.h b/drivers/gpu/drm/nouveau/core/engine/copy/fuc/nva3.fuc.h
index c92520f3ed46..241b27201206 100644
--- a/drivers/gpu/drm/nouveau/core/engine/copy/fuc/nva3.fuc.h
+++ b/drivers/gpu/drm/nouveau/core/engine/copy/fuc/nva3.fuc.h
@@ -1,4 +1,4 @@
-static u32 nva3_pcopy_data[] = {
+uint32_t nva3_pcopy_data[] = {
 /* 0x0000: ctx_object */
         0x00000000,
 /* 0x0004: ctx_dma */
@@ -183,7 +183,7 @@ static u32 nva3_pcopy_data[] = {
         0x00000800,
 };
 
-static u32 nva3_pcopy_code[] = {
+uint32_t nva3_pcopy_code[] = {
 /* 0x0000: main */
         0x04fe04bd,
         0x3517f000,
diff --git a/drivers/gpu/drm/nouveau/core/engine/copy/fuc/nvc0.fuc.h b/drivers/gpu/drm/nouveau/core/engine/copy/fuc/nvc0.fuc.h
index 0d98c6c0958d..98cc4216a372 100644
--- a/drivers/gpu/drm/nouveau/core/engine/copy/fuc/nvc0.fuc.h
+++ b/drivers/gpu/drm/nouveau/core/engine/copy/fuc/nvc0.fuc.h
@@ -1,4 +1,4 @@
-static u32 nvc0_pcopy_data[] = {
+uint32_t nvc0_pcopy_data[] = {
 /* 0x0000: ctx_object */
         0x00000000,
 /* 0x0004: ctx_query_address_high */
@@ -171,7 +171,7 @@ static u32 nvc0_pcopy_data[] = {
         0x00000800,
 };
 
-static u32 nvc0_pcopy_code[] = {
+uint32_t nvc0_pcopy_code[] = {
 /* 0x0000: main */
         0x04fe04bd,
         0x3517f000,
diff --git a/drivers/gpu/drm/nouveau/core/engine/copy/nva3.c b/drivers/gpu/drm/nouveau/core/engine/copy/nva3.c
index d6dc2a65ccd1..f31527733e00 100644
--- a/drivers/gpu/drm/nouveau/core/engine/copy/nva3.c
+++ b/drivers/gpu/drm/nouveau/core/engine/copy/nva3.c
@@ -22,16 +22,17 @@
  * Authors: Ben Skeggs
  */
 
-#include <core/client.h>
-#include <core/falcon.h>
-#include <core/class.h>
-#include <core/enum.h>
+#include <engine/falcon.h>
+#include <engine/fifo.h>
+#include <engine/copy.h>
 
 #include <subdev/fb.h>
 #include <subdev/vm.h>
 
-#include <engine/fifo.h>
-#include <engine/copy.h>
+#include <core/client.h>
+#include <core/class.h>
+#include <core/enum.h>
+
 
 #include "fuc/nva3.fuc.h"
 
@@ -117,13 +118,6 @@ nva3_copy_intr(struct nouveau_subdev *subdev)
 }
 
 static int
-nva3_copy_tlb_flush(struct nouveau_engine *engine)
-{
-        nv50_vm_flush_engine(&engine->base, 0x0d);
-        return 0;
-}
-
-static int
 nva3_copy_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
                struct nouveau_oclass *oclass, void *data, u32 size,
                struct nouveau_object **pobject)
@@ -142,7 +136,6 @@ nva3_copy_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
         nv_subdev(priv)->intr = nva3_copy_intr;
         nv_engine(priv)->cclass = &nva3_copy_cclass;
         nv_engine(priv)->sclass = nva3_copy_sclass;
-        nv_engine(priv)->tlb_flush = nva3_copy_tlb_flush;
         nv_falcon(priv)->code.data = nva3_pcopy_code;
         nv_falcon(priv)->code.size = sizeof(nva3_pcopy_code);
         nv_falcon(priv)->data.data = nva3_pcopy_data;
diff --git a/drivers/gpu/drm/nouveau/core/engine/copy/nvc0.c b/drivers/gpu/drm/nouveau/core/engine/copy/nvc0.c
index b3ed2737e21f..993df09ad643 100644
--- a/drivers/gpu/drm/nouveau/core/engine/copy/nvc0.c
+++ b/drivers/gpu/drm/nouveau/core/engine/copy/nvc0.c
@@ -22,13 +22,15 @@
  * Authors: Ben Skeggs
  */
 
-#include <core/falcon.h>
-#include <core/class.h>
-#include <core/enum.h>
-
+#include <engine/falcon.h>
 #include <engine/fifo.h>
 #include <engine/copy.h>
 
+#include <core/class.h>
+#include <core/enum.h>
+#include <core/class.h>
+#include <core/enum.h>
+
 #include "fuc/nvc0.fuc.h"
 
 struct nvc0_copy_priv {
diff --git a/drivers/gpu/drm/nouveau/core/engine/copy/nve0.c b/drivers/gpu/drm/nouveau/core/engine/copy/nve0.c
index dbbe9e8998fe..30f1ef1edcc5 100644
--- a/drivers/gpu/drm/nouveau/core/engine/copy/nve0.c
+++ b/drivers/gpu/drm/nouveau/core/engine/copy/nve0.c
@@ -67,6 +67,19 @@ nve0_copy_cclass = {
  * PCOPY engine/subdev functions
  ******************************************************************************/
 
+static void
+nve0_copy_intr(struct nouveau_subdev *subdev)
+{
+        const int ce = nv_subidx(nv_object(subdev)) - NVDEV_ENGINE_COPY0;
+        struct nve0_copy_priv *priv = (void *)subdev;
+        u32 stat = nv_rd32(priv, 0x104908 + (ce * 0x1000));
+
+        if (stat) {
+                nv_warn(priv, "unhandled intr 0x%08x\n", stat);
+                nv_wr32(priv, 0x104908 + (ce * 0x1000), stat);
+        }
+}
+
 static int
 nve0_copy0_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
                 struct nouveau_oclass *oclass, void *data, u32 size,
@@ -85,6 +98,7 @@ nve0_copy0_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
                 return ret;
 
         nv_subdev(priv)->unit = 0x00000040;
+        nv_subdev(priv)->intr = nve0_copy_intr;
         nv_engine(priv)->cclass = &nve0_copy_cclass;
         nv_engine(priv)->sclass = nve0_copy_sclass;
         return 0;
@@ -108,6 +122,28 @@ nve0_copy1_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
                 return ret;
 
         nv_subdev(priv)->unit = 0x00000080;
+        nv_subdev(priv)->intr = nve0_copy_intr;
+        nv_engine(priv)->cclass = &nve0_copy_cclass;
+        nv_engine(priv)->sclass = nve0_copy_sclass;
+        return 0;
+}
+
+static int
+nve0_copy2_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
+                struct nouveau_oclass *oclass, void *data, u32 size,
+                struct nouveau_object **pobject)
+{
+        struct nve0_copy_priv *priv;
+        int ret;
+
+        ret = nouveau_engine_create(parent, engine, oclass, true,
+                                    "PCE2", "copy2", &priv);
+        *pobject = nv_object(priv);
+        if (ret)
+                return ret;
+
+        nv_subdev(priv)->unit = 0x00200000;
+        nv_subdev(priv)->intr = nve0_copy_intr;
         nv_engine(priv)->cclass = &nve0_copy_cclass;
         nv_engine(priv)->sclass = nve0_copy_sclass;
         return 0;
@@ -134,3 +170,14 @@ nve0_copy1_oclass = {
                 .fini = _nouveau_engine_fini,
         },
 };
+
+struct nouveau_oclass
+nve0_copy2_oclass = {
+        .handle = NV_ENGINE(COPY2, 0xe0),
+        .ofuncs = &(struct nouveau_ofuncs) {
+                .ctor = nve0_copy2_ctor,
+                .dtor = _nouveau_engine_dtor,
+                .init = _nouveau_engine_init,
+                .fini = _nouveau_engine_fini,
+        },
+};
diff --git a/drivers/gpu/drm/nouveau/core/engine/crypt/fuc/nv98.fuc.h b/drivers/gpu/drm/nouveau/core/engine/crypt/fuc/nv98.fuc.h
index 09962e4210e9..38676c74e6e0 100644
--- a/drivers/gpu/drm/nouveau/core/engine/crypt/fuc/nv98.fuc.h
+++ b/drivers/gpu/drm/nouveau/core/engine/crypt/fuc/nv98.fuc.h
@@ -1,4 +1,4 @@
-static uint32_t nv98_pcrypt_data[] = {
+uint32_t nv98_pcrypt_data[] = {
 /* 0x0000: ctx_dma */
 /* 0x0000: ctx_dma_query */
         0x00000000,
@@ -150,7 +150,7 @@ static uint32_t nv98_pcrypt_data[] = {
         0x00000000,
 };
 
-static uint32_t nv98_pcrypt_code[] = {
+uint32_t nv98_pcrypt_code[] = {
         0x17f004bd,
         0x0010fe35,
         0xf10004fe,
diff --git a/drivers/gpu/drm/nouveau/core/engine/crypt/nv84.c b/drivers/gpu/drm/nouveau/core/engine/crypt/nv84.c
index 5bc021f471f9..2551dafbec73 100644
--- a/drivers/gpu/drm/nouveau/core/engine/crypt/nv84.c
+++ b/drivers/gpu/drm/nouveau/core/engine/crypt/nv84.c
@@ -141,13 +141,6 @@ nv84_crypt_intr(struct nouveau_subdev *subdev)
 }
 
 static int
-nv84_crypt_tlb_flush(struct nouveau_engine *engine)
-{
-        nv50_vm_flush_engine(&engine->base, 0x0a);
-        return 0;
-}
-
-static int
 nv84_crypt_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
                struct nouveau_oclass *oclass, void *data, u32 size,
                struct nouveau_object **pobject)
@@ -165,7 +158,6 @@ nv84_crypt_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
         nv_subdev(priv)->intr = nv84_crypt_intr;
         nv_engine(priv)->cclass = &nv84_crypt_cclass;
         nv_engine(priv)->sclass = nv84_crypt_sclass;
-        nv_engine(priv)->tlb_flush = nv84_crypt_tlb_flush;
         return 0;
 }
 
diff --git a/drivers/gpu/drm/nouveau/core/engine/crypt/nv98.c b/drivers/gpu/drm/nouveau/core/engine/crypt/nv98.c
index 8bf8955051d4..c7082377ec76 100644
--- a/drivers/gpu/drm/nouveau/core/engine/crypt/nv98.c
+++ b/drivers/gpu/drm/nouveau/core/engine/crypt/nv98.c
@@ -27,11 +27,11 @@
 #include <core/enum.h>
 #include <core/class.h>
 #include <core/engctx.h>
-#include <core/falcon.h>
 
 #include <subdev/timer.h>
 #include <subdev/fb.h>
 
+#include <engine/falcon.h>
 #include <engine/fifo.h>
 #include <engine/crypt.h>
 
@@ -119,13 +119,6 @@ nv98_crypt_intr(struct nouveau_subdev *subdev)
 }
 
 static int
-nv98_crypt_tlb_flush(struct nouveau_engine *engine)
-{
-        nv50_vm_flush_engine(&engine->base, 0x0a);
-        return 0;
-}
-
-static int
 nv98_crypt_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
                struct nouveau_oclass *oclass, void *data, u32 size,
                struct nouveau_object **pobject)
@@ -143,7 +136,6 @@ nv98_crypt_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
         nv_subdev(priv)->intr = nv98_crypt_intr;
         nv_engine(priv)->cclass = &nv98_crypt_cclass;
         nv_engine(priv)->sclass = nv98_crypt_sclass;
-        nv_engine(priv)->tlb_flush = nv98_crypt_tlb_flush;
         nv_falcon(priv)->code.data = nv98_pcrypt_code;
         nv_falcon(priv)->code.size = sizeof(nv98_pcrypt_code);
         nv_falcon(priv)->data.data = nv98_pcrypt_data;
diff --git a/drivers/gpu/drm/nouveau/core/engine/device/nv50.c b/drivers/gpu/drm/nouveau/core/engine/device/nv50.c
index 5e8c3de75593..ffc18b80c5d9 100644
--- a/drivers/gpu/drm/nouveau/core/engine/device/nv50.c
+++ b/drivers/gpu/drm/nouveau/core/engine/device/nv50.c
@@ -227,9 +227,9 @@ nv50_identify(struct nouveau_device *device)
                 device->oclass[NVDEV_ENGINE_FIFO   ] = &nv84_fifo_oclass;
                 device->oclass[NVDEV_ENGINE_SW     ] = &nv50_software_oclass;
                 device->oclass[NVDEV_ENGINE_GR     ] = &nv50_graph_oclass;
-                device->oclass[NVDEV_ENGINE_VP     ] = &nv84_vp_oclass;
+                device->oclass[NVDEV_ENGINE_VP     ] = &nv98_vp_oclass;
                 device->oclass[NVDEV_ENGINE_CRYPT  ] = &nv98_crypt_oclass;
-                device->oclass[NVDEV_ENGINE_BSP    ] = &nv84_bsp_oclass;
+                device->oclass[NVDEV_ENGINE_BSP    ] = &nv98_bsp_oclass;
                 device->oclass[NVDEV_ENGINE_PPP    ] = &nv98_ppp_oclass;
                 device->oclass[NVDEV_ENGINE_DISP   ] = &nv94_disp_oclass;
                 break;
@@ -279,9 +279,9 @@ nv50_identify(struct nouveau_device *device)
                 device->oclass[NVDEV_ENGINE_FIFO   ] = &nv84_fifo_oclass;
                 device->oclass[NVDEV_ENGINE_SW     ] = &nv50_software_oclass;
                 device->oclass[NVDEV_ENGINE_GR     ] = &nv50_graph_oclass;
-                device->oclass[NVDEV_ENGINE_VP     ] = &nv84_vp_oclass;
+                device->oclass[NVDEV_ENGINE_VP     ] = &nv98_vp_oclass;
                 device->oclass[NVDEV_ENGINE_CRYPT  ] = &nv98_crypt_oclass;
-                device->oclass[NVDEV_ENGINE_BSP    ] = &nv84_bsp_oclass;
+                device->oclass[NVDEV_ENGINE_BSP    ] = &nv98_bsp_oclass;
                 device->oclass[NVDEV_ENGINE_PPP    ] = &nv98_ppp_oclass;
                 device->oclass[NVDEV_ENGINE_DISP   ] = &nv94_disp_oclass;
                 break;
@@ -305,9 +305,9 @@ nv50_identify(struct nouveau_device *device)
                 device->oclass[NVDEV_ENGINE_FIFO   ] = &nv84_fifo_oclass;
                 device->oclass[NVDEV_ENGINE_SW     ] = &nv50_software_oclass;
                 device->oclass[NVDEV_ENGINE_GR     ] = &nv50_graph_oclass;
-                device->oclass[NVDEV_ENGINE_VP     ] = &nv84_vp_oclass;
+                device->oclass[NVDEV_ENGINE_VP     ] = &nv98_vp_oclass;
                 device->oclass[NVDEV_ENGINE_CRYPT  ] = &nv98_crypt_oclass;
-                device->oclass[NVDEV_ENGINE_BSP    ] = &nv84_bsp_oclass;
+                device->oclass[NVDEV_ENGINE_BSP    ] = &nv98_bsp_oclass;
                 device->oclass[NVDEV_ENGINE_PPP    ] = &nv98_ppp_oclass;
                 device->oclass[NVDEV_ENGINE_DISP   ] = &nv94_disp_oclass;
                 break;
@@ -319,7 +319,7 @@ nv50_identify(struct nouveau_device *device)
                 device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nva3_clock_oclass;
                 device->oclass[NVDEV_SUBDEV_THERM  ] = &nva3_therm_oclass;
                 device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
-                device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
+                device->oclass[NVDEV_SUBDEV_DEVINIT] = &nva3_devinit_oclass;
                 device->oclass[NVDEV_SUBDEV_MC     ] = &nv98_mc_oclass;
                 device->oclass[NVDEV_SUBDEV_BUS    ] = &nv50_bus_oclass;
                 device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
@@ -332,8 +332,8 @@ nv50_identify(struct nouveau_device *device)
                 device->oclass[NVDEV_ENGINE_SW     ] = &nv50_software_oclass;
                 device->oclass[NVDEV_ENGINE_GR     ] = &nv50_graph_oclass;
                 device->oclass[NVDEV_ENGINE_MPEG   ] = &nv84_mpeg_oclass;
-                device->oclass[NVDEV_ENGINE_VP     ] = &nv84_vp_oclass;
-                device->oclass[NVDEV_ENGINE_BSP    ] = &nv84_bsp_oclass;
+                device->oclass[NVDEV_ENGINE_VP     ] = &nv98_vp_oclass;
+                device->oclass[NVDEV_ENGINE_BSP    ] = &nv98_bsp_oclass;
                 device->oclass[NVDEV_ENGINE_PPP    ] = &nv98_ppp_oclass;
                 device->oclass[NVDEV_ENGINE_COPY0  ] = &nva3_copy_oclass;
                 device->oclass[NVDEV_ENGINE_DISP   ] = &nva3_disp_oclass;
@@ -346,7 +346,7 @@ nv50_identify(struct nouveau_device *device)
                 device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nva3_clock_oclass;
                 device->oclass[NVDEV_SUBDEV_THERM  ] = &nva3_therm_oclass;
                 device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
-                device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
+                device->oclass[NVDEV_SUBDEV_DEVINIT] = &nva3_devinit_oclass;
                 device->oclass[NVDEV_SUBDEV_MC     ] = &nv98_mc_oclass;
                 device->oclass[NVDEV_SUBDEV_BUS    ] = &nv50_bus_oclass;
                 device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
@@ -358,8 +358,8 @@ nv50_identify(struct nouveau_device *device)
                 device->oclass[NVDEV_ENGINE_FIFO   ] = &nv84_fifo_oclass;
                 device->oclass[NVDEV_ENGINE_SW     ] = &nv50_software_oclass;
                 device->oclass[NVDEV_ENGINE_GR     ] = &nv50_graph_oclass;
-                device->oclass[NVDEV_ENGINE_VP     ] = &nv84_vp_oclass;
-                device->oclass[NVDEV_ENGINE_BSP    ] = &nv84_bsp_oclass;
+                device->oclass[NVDEV_ENGINE_VP     ] = &nv98_vp_oclass;
+                device->oclass[NVDEV_ENGINE_BSP    ] = &nv98_bsp_oclass;
                 device->oclass[NVDEV_ENGINE_PPP    ] = &nv98_ppp_oclass;
                 device->oclass[NVDEV_ENGINE_COPY0  ] = &nva3_copy_oclass;
                 device->oclass[NVDEV_ENGINE_DISP   ] = &nva3_disp_oclass;
@@ -372,7 +372,7 @@ nv50_identify(struct nouveau_device *device)
                 device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nva3_clock_oclass;
                 device->oclass[NVDEV_SUBDEV_THERM  ] = &nva3_therm_oclass;
                 device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
-                device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
+                device->oclass[NVDEV_SUBDEV_DEVINIT] = &nva3_devinit_oclass;
                 device->oclass[NVDEV_SUBDEV_MC     ] = &nv98_mc_oclass;
                 device->oclass[NVDEV_SUBDEV_BUS    ] = &nv50_bus_oclass;
                 device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
@@ -384,8 +384,8 @@ nv50_identify(struct nouveau_device *device)
                 device->oclass[NVDEV_ENGINE_FIFO   ] = &nv84_fifo_oclass;
                 device->oclass[NVDEV_ENGINE_SW     ] = &nv50_software_oclass;
                 device->oclass[NVDEV_ENGINE_GR     ] = &nv50_graph_oclass;
-                device->oclass[NVDEV_ENGINE_VP     ] = &nv84_vp_oclass;
-                device->oclass[NVDEV_ENGINE_BSP    ] = &nv84_bsp_oclass;
+                device->oclass[NVDEV_ENGINE_VP     ] = &nv98_vp_oclass;
+                device->oclass[NVDEV_ENGINE_BSP    ] = &nv98_bsp_oclass;
                 device->oclass[NVDEV_ENGINE_PPP    ] = &nv98_ppp_oclass;
                 device->oclass[NVDEV_ENGINE_COPY0  ] = &nva3_copy_oclass;
                 device->oclass[NVDEV_ENGINE_DISP   ] = &nva3_disp_oclass;
@@ -398,7 +398,7 @@ nv50_identify(struct nouveau_device *device)
                 device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nva3_clock_oclass;
                 device->oclass[NVDEV_SUBDEV_THERM  ] = &nva3_therm_oclass;
                 device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
-                device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
+                device->oclass[NVDEV_SUBDEV_DEVINIT] = &nva3_devinit_oclass;
                 device->oclass[NVDEV_SUBDEV_MC     ] = &nv98_mc_oclass;
                 device->oclass[NVDEV_SUBDEV_BUS    ] = &nv50_bus_oclass;
                 device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
@@ -410,8 +410,8 @@ nv50_identify(struct nouveau_device *device)
                 device->oclass[NVDEV_ENGINE_FIFO   ] = &nv84_fifo_oclass;
                 device->oclass[NVDEV_ENGINE_SW     ] = &nv50_software_oclass;
                 device->oclass[NVDEV_ENGINE_GR     ] = &nv50_graph_oclass;
-                device->oclass[NVDEV_ENGINE_VP     ] = &nv84_vp_oclass;
-                device->oclass[NVDEV_ENGINE_BSP    ] = &nv84_bsp_oclass;
+                device->oclass[NVDEV_ENGINE_VP     ] = &nv98_vp_oclass;
+                device->oclass[NVDEV_ENGINE_BSP    ] = &nv98_bsp_oclass;
                 device->oclass[NVDEV_ENGINE_PPP    ] = &nv98_ppp_oclass;
                 device->oclass[NVDEV_ENGINE_COPY0  ] = &nva3_copy_oclass;
                 device->oclass[NVDEV_ENGINE_DISP   ] = &nva3_disp_oclass;
diff --git a/drivers/gpu/drm/nouveau/core/engine/device/nvc0.c b/drivers/gpu/drm/nouveau/core/engine/device/nvc0.c
index a36e64e98ef3..418f51f50d7a 100644
--- a/drivers/gpu/drm/nouveau/core/engine/device/nvc0.c
+++ b/drivers/gpu/drm/nouveau/core/engine/device/nvc0.c
@@ -62,7 +62,7 @@ nvc0_identify(struct nouveau_device *device)
                 device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nvc0_clock_oclass;
                 device->oclass[NVDEV_SUBDEV_THERM  ] = &nva3_therm_oclass;
                 device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
-                device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
+                device->oclass[NVDEV_SUBDEV_DEVINIT] = &nvc0_devinit_oclass;
                 device->oclass[NVDEV_SUBDEV_MC     ] = &nvc0_mc_oclass;
                 device->oclass[NVDEV_SUBDEV_BUS    ] = &nvc0_bus_oclass;
                 device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
@@ -75,7 +75,7 @@ nvc0_identify(struct nouveau_device *device)
                 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvc0_dmaeng_oclass;
                 device->oclass[NVDEV_ENGINE_FIFO   ] = &nvc0_fifo_oclass;
                 device->oclass[NVDEV_ENGINE_SW     ] = &nvc0_software_oclass;
-                device->oclass[NVDEV_ENGINE_GR     ] = &nvc0_graph_oclass;
+                device->oclass[NVDEV_ENGINE_GR     ] =  nvc0_graph_oclass;
                 device->oclass[NVDEV_ENGINE_VP     ] = &nvc0_vp_oclass;
                 device->oclass[NVDEV_ENGINE_BSP    ] = &nvc0_bsp_oclass;
                 device->oclass[NVDEV_ENGINE_PPP    ] = &nvc0_ppp_oclass;
@@ -91,7 +91,7 @@ nvc0_identify(struct nouveau_device *device)
                 device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nvc0_clock_oclass;
                 device->oclass[NVDEV_SUBDEV_THERM  ] = &nva3_therm_oclass;
                 device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
-                device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
+                device->oclass[NVDEV_SUBDEV_DEVINIT] = &nvc0_devinit_oclass;
                 device->oclass[NVDEV_SUBDEV_MC     ] = &nvc0_mc_oclass;
                 device->oclass[NVDEV_SUBDEV_BUS    ] = &nvc0_bus_oclass;
                 device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
@@ -104,7 +104,7 @@ nvc0_identify(struct nouveau_device *device)
                 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvc0_dmaeng_oclass;
                 device->oclass[NVDEV_ENGINE_FIFO   ] = &nvc0_fifo_oclass;
                 device->oclass[NVDEV_ENGINE_SW     ] = &nvc0_software_oclass;
-                device->oclass[NVDEV_ENGINE_GR     ] = &nvc0_graph_oclass;
+                device->oclass[NVDEV_ENGINE_GR     ] =  nvc3_graph_oclass;
                 device->oclass[NVDEV_ENGINE_VP     ] = &nvc0_vp_oclass;
                 device->oclass[NVDEV_ENGINE_BSP    ] = &nvc0_bsp_oclass;
                 device->oclass[NVDEV_ENGINE_PPP    ] = &nvc0_ppp_oclass;
@@ -120,7 +120,7 @@ nvc0_identify(struct nouveau_device *device)
                 device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nvc0_clock_oclass;
                 device->oclass[NVDEV_SUBDEV_THERM  ] = &nva3_therm_oclass;
                 device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
-                device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
+                device->oclass[NVDEV_SUBDEV_DEVINIT] = &nvc0_devinit_oclass;
                 device->oclass[NVDEV_SUBDEV_MC     ] = &nvc0_mc_oclass;
                 device->oclass[NVDEV_SUBDEV_BUS    ] = &nvc0_bus_oclass;
                 device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
@@ -133,7 +133,7 @@ nvc0_identify(struct nouveau_device *device)
                 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvc0_dmaeng_oclass;
                 device->oclass[NVDEV_ENGINE_FIFO   ] = &nvc0_fifo_oclass;
                 device->oclass[NVDEV_ENGINE_SW     ] = &nvc0_software_oclass;
-                device->oclass[NVDEV_ENGINE_GR     ] = &nvc0_graph_oclass;
+                device->oclass[NVDEV_ENGINE_GR     ] =  nvc3_graph_oclass;
                 device->oclass[NVDEV_ENGINE_VP     ] = &nvc0_vp_oclass;
                 device->oclass[NVDEV_ENGINE_BSP    ] = &nvc0_bsp_oclass;
                 device->oclass[NVDEV_ENGINE_PPP    ] = &nvc0_ppp_oclass;
@@ -148,7 +148,7 @@ nvc0_identify(struct nouveau_device *device)
                 device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nvc0_clock_oclass;
                 device->oclass[NVDEV_SUBDEV_THERM  ] = &nva3_therm_oclass;
                 device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
-                device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
+                device->oclass[NVDEV_SUBDEV_DEVINIT] = &nvc0_devinit_oclass;
                 device->oclass[NVDEV_SUBDEV_MC     ] = &nvc0_mc_oclass;
                 device->oclass[NVDEV_SUBDEV_BUS    ] = &nvc0_bus_oclass;
                 device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
@@ -161,7 +161,7 @@ nvc0_identify(struct nouveau_device *device)
                 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvc0_dmaeng_oclass;
                 device->oclass[NVDEV_ENGINE_FIFO   ] = &nvc0_fifo_oclass;
                 device->oclass[NVDEV_ENGINE_SW     ] = &nvc0_software_oclass;
-                device->oclass[NVDEV_ENGINE_GR     ] = &nvc0_graph_oclass;
+                device->oclass[NVDEV_ENGINE_GR     ] =  nvc3_graph_oclass;
                 device->oclass[NVDEV_ENGINE_VP     ] = &nvc0_vp_oclass;
                 device->oclass[NVDEV_ENGINE_BSP    ] = &nvc0_bsp_oclass;
                 device->oclass[NVDEV_ENGINE_PPP    ] = &nvc0_ppp_oclass;
@@ -177,7 +177,7 @@ nvc0_identify(struct nouveau_device *device)
                 device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nvc0_clock_oclass;
                 device->oclass[NVDEV_SUBDEV_THERM  ] = &nva3_therm_oclass;
                 device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
-                device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
+                device->oclass[NVDEV_SUBDEV_DEVINIT] = &nvc0_devinit_oclass;
                 device->oclass[NVDEV_SUBDEV_MC     ] = &nvc0_mc_oclass;
                 device->oclass[NVDEV_SUBDEV_BUS    ] = &nvc0_bus_oclass;
                 device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
@@ -190,7 +190,7 @@ nvc0_identify(struct nouveau_device *device)
                 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvc0_dmaeng_oclass;
                 device->oclass[NVDEV_ENGINE_FIFO   ] = &nvc0_fifo_oclass;
                 device->oclass[NVDEV_ENGINE_SW     ] = &nvc0_software_oclass;
-                device->oclass[NVDEV_ENGINE_GR     ] = &nvc0_graph_oclass;
+                device->oclass[NVDEV_ENGINE_GR     ] =  nvc3_graph_oclass;
                 device->oclass[NVDEV_ENGINE_VP     ] = &nvc0_vp_oclass;
                 device->oclass[NVDEV_ENGINE_BSP    ] = &nvc0_bsp_oclass;
                 device->oclass[NVDEV_ENGINE_PPP    ] = &nvc0_ppp_oclass;
@@ -206,7 +206,7 @@ nvc0_identify(struct nouveau_device *device)
                 device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nvc0_clock_oclass;
                 device->oclass[NVDEV_SUBDEV_THERM  ] = &nva3_therm_oclass;
                 device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
-                device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
+                device->oclass[NVDEV_SUBDEV_DEVINIT] = &nvc0_devinit_oclass;
                 device->oclass[NVDEV_SUBDEV_MC     ] = &nvc0_mc_oclass;
                 device->oclass[NVDEV_SUBDEV_BUS    ] = &nvc0_bus_oclass;
                 device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
@@ -219,7 +219,7 @@ nvc0_identify(struct nouveau_device *device)
                 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvc0_dmaeng_oclass;
                 device->oclass[NVDEV_ENGINE_FIFO   ] = &nvc0_fifo_oclass;
                 device->oclass[NVDEV_ENGINE_SW     ] = &nvc0_software_oclass;
-                device->oclass[NVDEV_ENGINE_GR     ] = &nvc0_graph_oclass;
+                device->oclass[NVDEV_ENGINE_GR     ] =  nvc1_graph_oclass;
                 device->oclass[NVDEV_ENGINE_VP     ] = &nvc0_vp_oclass;
                 device->oclass[NVDEV_ENGINE_BSP    ] = &nvc0_bsp_oclass;
                 device->oclass[NVDEV_ENGINE_PPP    ] = &nvc0_ppp_oclass;
@@ -234,7 +234,7 @@ nvc0_identify(struct nouveau_device *device)
                 device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nvc0_clock_oclass;
                 device->oclass[NVDEV_SUBDEV_THERM  ] = &nva3_therm_oclass;
                 device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
-                device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
+                device->oclass[NVDEV_SUBDEV_DEVINIT] = &nvc0_devinit_oclass;
                 device->oclass[NVDEV_SUBDEV_MC     ] = &nvc0_mc_oclass;
                 device->oclass[NVDEV_SUBDEV_BUS    ] = &nvc0_bus_oclass;
                 device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
@@ -247,7 +247,7 @@ nvc0_identify(struct nouveau_device *device)
                 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvc0_dmaeng_oclass;
                 device->oclass[NVDEV_ENGINE_FIFO   ] = &nvc0_fifo_oclass;
                 device->oclass[NVDEV_ENGINE_SW     ] = &nvc0_software_oclass;
-                device->oclass[NVDEV_ENGINE_GR     ] = &nvc0_graph_oclass;
+                device->oclass[NVDEV_ENGINE_GR     ] =  nvc8_graph_oclass;
                 device->oclass[NVDEV_ENGINE_VP     ] = &nvc0_vp_oclass;
                 device->oclass[NVDEV_ENGINE_BSP    ] = &nvc0_bsp_oclass;
                 device->oclass[NVDEV_ENGINE_PPP    ] = &nvc0_ppp_oclass;
@@ -263,7 +263,7 @@ nvc0_identify(struct nouveau_device *device)
                 device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nvc0_clock_oclass;
                 device->oclass[NVDEV_SUBDEV_THERM  ] = &nvd0_therm_oclass;
                 device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
-                device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
+                device->oclass[NVDEV_SUBDEV_DEVINIT] = &nvc0_devinit_oclass;
                 device->oclass[NVDEV_SUBDEV_MC     ] = &nvc0_mc_oclass;
                 device->oclass[NVDEV_SUBDEV_BUS    ] = &nvc0_bus_oclass;
                 device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
@@ -276,7 +276,7 @@ nvc0_identify(struct nouveau_device *device)
                 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvd0_dmaeng_oclass;
                 device->oclass[NVDEV_ENGINE_FIFO   ] = &nvc0_fifo_oclass;
                 device->oclass[NVDEV_ENGINE_SW     ] = &nvc0_software_oclass;
-                device->oclass[NVDEV_ENGINE_GR     ] = &nvc0_graph_oclass;
+                device->oclass[NVDEV_ENGINE_GR     ] =  nvd9_graph_oclass;
                 device->oclass[NVDEV_ENGINE_VP     ] = &nvc0_vp_oclass;
                 device->oclass[NVDEV_ENGINE_BSP    ] = &nvc0_bsp_oclass;
                 device->oclass[NVDEV_ENGINE_PPP    ] = &nvc0_ppp_oclass;
@@ -291,7 +291,7 @@ nvc0_identify(struct nouveau_device *device)
                 device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nvc0_clock_oclass;
                 device->oclass[NVDEV_SUBDEV_THERM  ] = &nvd0_therm_oclass;
                 device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
-                device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
+                device->oclass[NVDEV_SUBDEV_DEVINIT] = &nvc0_devinit_oclass;
                 device->oclass[NVDEV_SUBDEV_MC     ] = &nvc0_mc_oclass;
                 device->oclass[NVDEV_SUBDEV_BUS    ] = &nvc0_bus_oclass;
                 device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
@@ -304,7 +304,7 @@ nvc0_identify(struct nouveau_device *device)
                 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvd0_dmaeng_oclass;
                 device->oclass[NVDEV_ENGINE_FIFO   ] = &nvc0_fifo_oclass;
                 device->oclass[NVDEV_ENGINE_SW     ] = &nvc0_software_oclass;
-                device->oclass[NVDEV_ENGINE_GR     ] = &nvc0_graph_oclass;
+                device->oclass[NVDEV_ENGINE_GR     ] =  nvd7_graph_oclass;
                 device->oclass[NVDEV_ENGINE_VP     ] = &nvc0_vp_oclass;
                 device->oclass[NVDEV_ENGINE_BSP    ] = &nvc0_bsp_oclass;
                 device->oclass[NVDEV_ENGINE_PPP    ] = &nvc0_ppp_oclass;
diff --git a/drivers/gpu/drm/nouveau/core/engine/device/nve0.c b/drivers/gpu/drm/nouveau/core/engine/device/nve0.c
index a354e409cdff..7aca1877add4 100644
--- a/drivers/gpu/drm/nouveau/core/engine/device/nve0.c
+++ b/drivers/gpu/drm/nouveau/core/engine/device/nve0.c
@@ -62,7 +62,7 @@ nve0_identify(struct nouveau_device *device)
                 device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nvc0_clock_oclass;
                 device->oclass[NVDEV_SUBDEV_THERM  ] = &nvd0_therm_oclass;
                 device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
-                device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
+                device->oclass[NVDEV_SUBDEV_DEVINIT] = &nvc0_devinit_oclass;
                 device->oclass[NVDEV_SUBDEV_MC     ] = &nvc0_mc_oclass;
                 device->oclass[NVDEV_SUBDEV_BUS    ] = &nvc0_bus_oclass;
                 device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
@@ -75,10 +75,11 @@ nve0_identify(struct nouveau_device *device)
                 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvd0_dmaeng_oclass;
                 device->oclass[NVDEV_ENGINE_FIFO   ] = &nve0_fifo_oclass;
                 device->oclass[NVDEV_ENGINE_SW     ] = &nvc0_software_oclass;
-                device->oclass[NVDEV_ENGINE_GR     ] = &nve0_graph_oclass;
+                device->oclass[NVDEV_ENGINE_GR     ] =  nve4_graph_oclass;
                 device->oclass[NVDEV_ENGINE_DISP   ] = &nve0_disp_oclass;
                 device->oclass[NVDEV_ENGINE_COPY0  ] = &nve0_copy0_oclass;
                 device->oclass[NVDEV_ENGINE_COPY1  ] = &nve0_copy1_oclass;
+                device->oclass[NVDEV_ENGINE_COPY2  ] = &nve0_copy2_oclass;
                 device->oclass[NVDEV_ENGINE_BSP    ] = &nve0_bsp_oclass;
                 device->oclass[NVDEV_ENGINE_VP     ] = &nve0_vp_oclass;
                 device->oclass[NVDEV_ENGINE_PPP    ] = &nvc0_ppp_oclass;
@@ -91,7 +92,7 @@ nve0_identify(struct nouveau_device *device)
                 device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nvc0_clock_oclass;
                 device->oclass[NVDEV_SUBDEV_THERM  ] = &nvd0_therm_oclass;
                 device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
-                device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
+                device->oclass[NVDEV_SUBDEV_DEVINIT] = &nvc0_devinit_oclass;
                 device->oclass[NVDEV_SUBDEV_MC     ] = &nvc0_mc_oclass;
                 device->oclass[NVDEV_SUBDEV_BUS    ] = &nvc0_bus_oclass;
                 device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
@@ -104,10 +105,11 @@ nve0_identify(struct nouveau_device *device)
                 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvd0_dmaeng_oclass;
                 device->oclass[NVDEV_ENGINE_FIFO   ] = &nve0_fifo_oclass;
                 device->oclass[NVDEV_ENGINE_SW     ] = &nvc0_software_oclass;
-                device->oclass[NVDEV_ENGINE_GR     ] = &nve0_graph_oclass;
+                device->oclass[NVDEV_ENGINE_GR     ] =  nve4_graph_oclass;
                 device->oclass[NVDEV_ENGINE_DISP   ] = &nve0_disp_oclass;
                 device->oclass[NVDEV_ENGINE_COPY0  ] = &nve0_copy0_oclass;
                 device->oclass[NVDEV_ENGINE_COPY1  ] = &nve0_copy1_oclass;
+                device->oclass[NVDEV_ENGINE_COPY2  ] = &nve0_copy2_oclass;
                 device->oclass[NVDEV_ENGINE_BSP    ] = &nve0_bsp_oclass;
                 device->oclass[NVDEV_ENGINE_VP     ] = &nve0_vp_oclass;
                 device->oclass[NVDEV_ENGINE_PPP    ] = &nvc0_ppp_oclass;
@@ -120,7 +122,7 @@ nve0_identify(struct nouveau_device *device)
                 device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nvc0_clock_oclass;
                 device->oclass[NVDEV_SUBDEV_THERM  ] = &nvd0_therm_oclass;
                 device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
-                device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
+                device->oclass[NVDEV_SUBDEV_DEVINIT] = &nvc0_devinit_oclass;
                 device->oclass[NVDEV_SUBDEV_MC     ] = &nvc0_mc_oclass;
                 device->oclass[NVDEV_SUBDEV_BUS    ] = &nvc0_bus_oclass;
                 device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
@@ -133,10 +135,11 @@ nve0_identify(struct nouveau_device *device)
                 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvd0_dmaeng_oclass;
                 device->oclass[NVDEV_ENGINE_FIFO   ] = &nve0_fifo_oclass;
                 device->oclass[NVDEV_ENGINE_SW     ] = &nvc0_software_oclass;
-                device->oclass[NVDEV_ENGINE_GR     ] = &nve0_graph_oclass;
+                device->oclass[NVDEV_ENGINE_GR     ] =  nve4_graph_oclass;
                 device->oclass[NVDEV_ENGINE_DISP   ] = &nve0_disp_oclass;
                 device->oclass[NVDEV_ENGINE_COPY0  ] = &nve0_copy0_oclass;
                 device->oclass[NVDEV_ENGINE_COPY1  ] = &nve0_copy1_oclass;
+                device->oclass[NVDEV_ENGINE_COPY2  ] = &nve0_copy2_oclass;
                 device->oclass[NVDEV_ENGINE_BSP    ] = &nve0_bsp_oclass;
                 device->oclass[NVDEV_ENGINE_VP     ] = &nve0_vp_oclass;
                 device->oclass[NVDEV_ENGINE_PPP    ] = &nvc0_ppp_oclass;
@@ -149,7 +152,7 @@ nve0_identify(struct nouveau_device *device)
                 device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nvc0_clock_oclass;
                 device->oclass[NVDEV_SUBDEV_THERM  ] = &nvd0_therm_oclass;
                 device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
-                device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
+                device->oclass[NVDEV_SUBDEV_DEVINIT] = &nvc0_devinit_oclass;
                 device->oclass[NVDEV_SUBDEV_MC     ] = &nvc0_mc_oclass;
                 device->oclass[NVDEV_SUBDEV_BUS    ] = &nvc0_bus_oclass;
                 device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
@@ -160,16 +163,14 @@ nve0_identify(struct nouveau_device *device)
                 device->oclass[NVDEV_SUBDEV_VM     ] = &nvc0_vmmgr_oclass;
                 device->oclass[NVDEV_SUBDEV_BAR    ] = &nvc0_bar_oclass;
                 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvd0_dmaeng_oclass;
-#if 0
                 device->oclass[NVDEV_ENGINE_FIFO   ] = &nve0_fifo_oclass;
                 device->oclass[NVDEV_ENGINE_SW     ] = &nvc0_software_oclass;
-                device->oclass[NVDEV_ENGINE_GR     ] = &nve0_graph_oclass;
-#endif
+                device->oclass[NVDEV_ENGINE_GR     ] =  nvf0_graph_oclass;
                 device->oclass[NVDEV_ENGINE_DISP   ] = &nvf0_disp_oclass;
-#if 0
                 device->oclass[NVDEV_ENGINE_COPY0  ] = &nve0_copy0_oclass;
                 device->oclass[NVDEV_ENGINE_COPY1  ] = &nve0_copy1_oclass;
                 device->oclass[NVDEV_ENGINE_COPY2  ] = &nve0_copy2_oclass;
+#if 0
                 device->oclass[NVDEV_ENGINE_BSP    ] = &nve0_bsp_oclass;
                 device->oclass[NVDEV_ENGINE_VP     ] = &nve0_vp_oclass;
                 device->oclass[NVDEV_ENGINE_PPP    ] = &nvc0_ppp_oclass;
diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/hdminva3.c b/drivers/gpu/drm/nouveau/core/engine/disp/hdminva3.c
index f065fc248adf..db8c6fd46278 100644
--- a/drivers/gpu/drm/nouveau/core/engine/disp/hdminva3.c
+++ b/drivers/gpu/drm/nouveau/core/engine/disp/hdminva3.c
@@ -55,6 +55,10 @@ nva3_hdmi_ctrl(struct nv50_disp_priv *priv, int head, int or, u32 data)
         nv_wr32(priv, 0x61c510 + soff, 0x00000000);
         nv_mask(priv, 0x61c500 + soff, 0x00000001, 0x00000001);
 
+        nv_mask(priv, 0x61c5d0 + soff, 0x00070001, 0x00010001); /* SPARE, HW_CTS */
+        nv_mask(priv, 0x61c568 + soff, 0x00010101, 0x00000000); /* ACR_CTRL, ?? */
+        nv_mask(priv, 0x61c578 + soff, 0x80000000, 0x80000000); /* ACR_0441_ENABLE */
+
         /* ??? */
         nv_mask(priv, 0x61733c, 0x00100000, 0x00100000); /* RESETF */
         nv_mask(priv, 0x61733c, 0x10000000, 0x10000000); /* LOOKUP_EN */
diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/nv50.c b/drivers/gpu/drm/nouveau/core/engine/disp/nv50.c
index 6a38402fa56c..7ffe2f309f12 100644
--- a/drivers/gpu/drm/nouveau/core/engine/disp/nv50.c
+++ b/drivers/gpu/drm/nouveau/core/engine/disp/nv50.c
@@ -34,9 +34,9 @@
 #include <subdev/bios/disp.h>
 #include <subdev/bios/init.h>
 #include <subdev/bios/pll.h>
+#include <subdev/devinit.h>
 #include <subdev/timer.h>
 #include <subdev/fb.h>
-#include <subdev/clock.h>
 
 #include "nv50.h"
 
@@ -987,10 +987,10 @@ nv50_disp_intr_unk20_0(struct nv50_disp_priv *priv, int head)
 static void
 nv50_disp_intr_unk20_1(struct nv50_disp_priv *priv, int head)
 {
-        struct nouveau_clock *clk = nouveau_clock(priv);
+        struct nouveau_devinit *devinit = nouveau_devinit(priv);
         u32 pclk = nv_rd32(priv, 0x610ad0 + (head * 0x540)) & 0x3fffff;
         if (pclk)
-                clk->pll_set(clk, PLL_VPLL0 + head, pclk);
+                devinit->pll_set(devinit, PLL_VPLL0 + head, pclk);
 }
 
 static void
@@ -1107,6 +1107,7 @@ nv50_disp_intr_unk20_2(struct nv50_disp_priv *priv, int head)
         u32 pclk = nv_rd32(priv, 0x610ad0 + (head * 0x540)) & 0x3fffff;
         u32 hval, hreg = 0x614200 + (head * 0x800);
         u32 oval, oreg;
+        u32 mask;
         u32 conf = exec_clkcmp(priv, head, 0xff, pclk, &outp);
         if (conf != ~0) {
                 if (outp.location == 0 && outp.type == DCB_OUTPUT_DP) {
@@ -1133,6 +1134,7 @@ nv50_disp_intr_unk20_2(struct nv50_disp_priv *priv, int head)
                         oreg = 0x614280 + (ffs(outp.or) - 1) * 0x800;
                         oval = 0x00000000;
                         hval = 0x00000000;
+                        mask = 0xffffffff;
                 } else
                 if (!outp.location) {
                         if (outp.type == DCB_OUTPUT_DP)
@@ -1140,14 +1142,16 @@ nv50_disp_intr_unk20_2(struct nv50_disp_priv *priv, int head)
                         oreg = 0x614300 + (ffs(outp.or) - 1) * 0x800;
                         oval = (conf & 0x0100) ? 0x00000101 : 0x00000000;
                         hval = 0x00000000;
+                        mask = 0x00000707;
                 } else {
                         oreg = 0x614380 + (ffs(outp.or) - 1) * 0x800;
                         oval = 0x00000001;
                         hval = 0x00000001;
+                        mask = 0x00000707;
                 }
 
                 nv_mask(priv, hreg, 0x0000000f, hval);
-                nv_mask(priv, oreg, 0x00000707, oval);
+                nv_mask(priv, oreg, mask, oval);
         }
 }
 
diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/nvd0.c b/drivers/gpu/drm/nouveau/core/engine/disp/nvd0.c
index 019eacd8a68f..52dd7a1db729 100644
--- a/drivers/gpu/drm/nouveau/core/engine/disp/nvd0.c
+++ b/drivers/gpu/drm/nouveau/core/engine/disp/nvd0.c
@@ -29,15 +29,14 @@
 
 #include <engine/disp.h>
 
-#include <subdev/timer.h>
-#include <subdev/fb.h>
-#include <subdev/clock.h>
-
 #include <subdev/bios.h>
 #include <subdev/bios/dcb.h>
 #include <subdev/bios/disp.h>
 #include <subdev/bios/init.h>
 #include <subdev/bios/pll.h>
+#include <subdev/devinit.h>
+#include <subdev/fb.h>
+#include <subdev/timer.h>
 
 #include "nv50.h"
 
@@ -738,10 +737,10 @@ nvd0_disp_intr_unk2_0(struct nv50_disp_priv *priv, int head)
 static void
 nvd0_disp_intr_unk2_1(struct nv50_disp_priv *priv, int head)
 {
-        struct nouveau_clock *clk = nouveau_clock(priv);
+        struct nouveau_devinit *devinit = nouveau_devinit(priv);
         u32 pclk = nv_rd32(priv, 0x660450 + (head * 0x300)) / 1000;
         if (pclk)
-                clk->pll_set(clk, PLL_VPLL0 + head, pclk);
+                devinit->pll_set(devinit, PLL_VPLL0 + head, pclk);
         nv_wr32(priv, 0x612200 + (head * 0x800), 0x00000000);
 }
 
@@ -959,6 +958,9 @@ nvd0_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
         int heads = nv_rd32(parent, 0x022448);
         int ret;
 
+        if (nv_rd32(parent, 0x022500) & 0x00000001)
+                return -ENODEV;
+
         ret = nouveau_disp_create(parent, engine, oclass, heads,
                                   "PDISP", "display", &priv);
         *pobject = nv_object(priv);
diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/nve0.c b/drivers/gpu/drm/nouveau/core/engine/disp/nve0.c
index 20725b363d58..fb1fe6ae5e74 100644
--- a/drivers/gpu/drm/nouveau/core/engine/disp/nve0.c
+++ b/drivers/gpu/drm/nouveau/core/engine/disp/nve0.c
@@ -54,6 +54,9 @@ nve0_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
         int heads = nv_rd32(parent, 0x022448);
         int ret;
 
+        if (nv_rd32(parent, 0x022500) & 0x00000001)
+                return -ENODEV;
+
         ret = nouveau_disp_create(parent, engine, oclass, heads,
                                   "PDISP", "display", &priv);
         *pobject = nv_object(priv);
diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/nvf0.c b/drivers/gpu/drm/nouveau/core/engine/disp/nvf0.c
index a488c36e40f9..42aa6b97dbea 100644
--- a/drivers/gpu/drm/nouveau/core/engine/disp/nvf0.c
+++ b/drivers/gpu/drm/nouveau/core/engine/disp/nvf0.c
@@ -54,6 +54,9 @@ nvf0_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
         int heads = nv_rd32(parent, 0x022448);
         int ret;
 
+        if (nv_rd32(parent, 0x022500) & 0x00000001)
+                return -ENODEV;
+
         ret = nouveau_disp_create(parent, engine, oclass, heads,
                                   "PDISP", "display", &priv);
         *pobject = nv_object(priv);
diff --git a/drivers/gpu/drm/nouveau/core/core/falcon.c b/drivers/gpu/drm/nouveau/core/engine/falcon.c
index e05c15777588..3c7a31f7590e 100644
--- a/drivers/gpu/drm/nouveau/core/core/falcon.c
+++ b/drivers/gpu/drm/nouveau/core/engine/falcon.c
@@ -20,8 +20,7 @@
  * OTHER DEALINGS IN THE SOFTWARE.
  */
 
-#include <core/falcon.h>
-
+#include <engine/falcon.h>
 #include <subdev/timer.h>
 
 u32
diff --git a/drivers/gpu/drm/nouveau/core/engine/fifo/nv40.c b/drivers/gpu/drm/nouveau/core/engine/fifo/nv40.c
index 2b1f91721225..5c7433d5069f 100644
--- a/drivers/gpu/drm/nouveau/core/engine/fifo/nv40.c
+++ b/drivers/gpu/drm/nouveau/core/engine/fifo/nv40.c
@@ -320,7 +320,7 @@ nv40_fifo_init(struct nouveau_object *object)
                 break;
         default:
                 nv_wr32(priv, 0x002230, 0x00000000);
-                nv_wr32(priv, 0x002220, ((pfb->ram.size - 512 * 1024 +
+                nv_wr32(priv, 0x002220, ((pfb->ram->size - 512 * 1024 +
                                          priv->ramfc->addr) >> 16) |
                                         0x00030000);
                 break;
diff --git a/drivers/gpu/drm/nouveau/core/engine/fifo/nv84.c b/drivers/gpu/drm/nouveau/core/engine/fifo/nv84.c
index 35b94bd18808..7f53196cff52 100644
--- a/drivers/gpu/drm/nouveau/core/engine/fifo/nv84.c
+++ b/drivers/gpu/drm/nouveau/core/engine/fifo/nv84.c
@@ -56,7 +56,9 @@ nv84_fifo_context_attach(struct nouveau_object *parent,
         switch (nv_engidx(object->engine)) {
         case NVDEV_ENGINE_SW   : return 0;
         case NVDEV_ENGINE_GR   : addr = 0x0020; break;
+        case NVDEV_ENGINE_VP   : addr = 0x0040; break;
         case NVDEV_ENGINE_MPEG : addr = 0x0060; break;
+        case NVDEV_ENGINE_BSP  : addr = 0x0080; break;
         case NVDEV_ENGINE_CRYPT: addr = 0x00a0; break;
         case NVDEV_ENGINE_COPY0: addr = 0x00c0; break;
         default:
@@ -89,7 +91,9 @@ nv84_fifo_context_detach(struct nouveau_object *parent, bool suspend,
         switch (nv_engidx(object->engine)) {
         case NVDEV_ENGINE_SW   : return 0;
         case NVDEV_ENGINE_GR   : engn = 0; addr = 0x0020; break;
+        case NVDEV_ENGINE_VP   : engn = 3; addr = 0x0040; break;
         case NVDEV_ENGINE_MPEG : engn = 1; addr = 0x0060; break;
+        case NVDEV_ENGINE_BSP  : engn = 5; addr = 0x0080; break;
         case NVDEV_ENGINE_CRYPT: engn = 4; addr = 0x00a0; break;
         case NVDEV_ENGINE_COPY0: engn = 2; addr = 0x00c0; break;
         default:
diff --git a/drivers/gpu/drm/nouveau/core/engine/fifo/nve0.c b/drivers/gpu/drm/nouveau/core/engine/fifo/nve0.c
index 56192a7242ae..09644fa9602c 100644
--- a/drivers/gpu/drm/nouveau/core/engine/fifo/nve0.c
+++ b/drivers/gpu/drm/nouveau/core/engine/fifo/nve0.c
@@ -44,7 +44,8 @@ static const struct {
         u64 subdev;
         u64 mask;
 } fifo_engine[] = {
-        _(NVDEV_ENGINE_GR      , (1ULL << NVDEV_ENGINE_SW)),
+        _(NVDEV_ENGINE_GR      , (1ULL << NVDEV_ENGINE_SW) |
+                                 (1ULL << NVDEV_ENGINE_COPY2)),
         _(NVDEV_ENGINE_VP      , 0),
         _(NVDEV_ENGINE_PPP     , 0),
         _(NVDEV_ENGINE_BSP     , 0),
@@ -96,18 +97,6 @@ nve0_fifo_playlist_update(struct nve0_fifo_priv *priv, u32 engine)
 
         mutex_lock(&nv_subdev(priv)->mutex);
         cur = engn->playlist[engn->cur_playlist];
-        if (unlikely(cur == NULL)) {
-                int ret = nouveau_gpuobj_new(nv_object(priv), NULL,
-                                             0x8000, 0x1000, 0, &cur);
-                if (ret) {
-                        mutex_unlock(&nv_subdev(priv)->mutex);
-                        nv_error(priv, "playlist alloc failed\n");
-                        return;
-                }
-
-                engn->playlist[engn->cur_playlist] = cur;
-        }
-
         engn->cur_playlist = !engn->cur_playlist;
 
         for (i = 0, p = 0; i < priv->base.max; i++) {
@@ -138,10 +127,12 @@ nve0_fifo_context_attach(struct nouveau_object *parent,
         int ret;
 
         switch (nv_engidx(object->engine)) {
-        case NVDEV_ENGINE_SW   : return 0;
-        case NVDEV_ENGINE_GR   :
+        case NVDEV_ENGINE_SW   :
         case NVDEV_ENGINE_COPY0:
-        case NVDEV_ENGINE_COPY1: addr = 0x0210; break;
+        case NVDEV_ENGINE_COPY1:
+        case NVDEV_ENGINE_COPY2:
+                return 0;
+        case NVDEV_ENGINE_GR   : addr = 0x0210; break;
         case NVDEV_ENGINE_BSP  : addr = 0x0270; break;
         case NVDEV_ENGINE_VP   : addr = 0x0250; break;
         case NVDEV_ENGINE_PPP  : addr = 0x0260; break;
@@ -176,9 +167,10 @@ nve0_fifo_context_detach(struct nouveau_object *parent, bool suspend,
 
         switch (nv_engidx(object->engine)) {
         case NVDEV_ENGINE_SW   : return 0;
-        case NVDEV_ENGINE_GR   :
         case NVDEV_ENGINE_COPY0:
-        case NVDEV_ENGINE_COPY1: addr = 0x0210; break;
+        case NVDEV_ENGINE_COPY1:
+        case NVDEV_ENGINE_COPY2: addr = 0x0000; break;
+        case NVDEV_ENGINE_GR   : addr = 0x0210; break;
         case NVDEV_ENGINE_BSP  : addr = 0x0270; break;
         case NVDEV_ENGINE_VP   : addr = 0x0250; break;
         case NVDEV_ENGINE_PPP  : addr = 0x0260; break;
@@ -194,9 +186,12 @@ nve0_fifo_context_detach(struct nouveau_object *parent, bool suspend,
                         return -EBUSY;
         }
 
-        nv_wo32(base, addr + 0x00, 0x00000000);
-        nv_wo32(base, addr + 0x04, 0x00000000);
-        bar->flush(bar);
+        if (addr) {
+                nv_wo32(base, addr + 0x00, 0x00000000);
+                nv_wo32(base, addr + 0x04, 0x00000000);
+                bar->flush(bar);
+        }
+
         return 0;
 }
 
@@ -226,8 +221,10 @@ nve0_fifo_chan_ctor(struct nouveau_object *parent,
                 }
         }
 
-        if (i == FIFO_ENGINE_NR)
+        if (i == FIFO_ENGINE_NR) {
+                nv_error(priv, "unsupported engines 0x%08x\n", args->engine);
                 return -ENODEV;
+        }
 
         ret = nouveau_fifo_channel_create(parent, engine, oclass, 1,
                                           priv->user.bar.offset, 0x200,
@@ -592,13 +589,25 @@ nve0_fifo_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
                struct nouveau_object **pobject)
 {
         struct nve0_fifo_priv *priv;
-        int ret;
+        int ret, i;
 
         ret = nouveau_fifo_create(parent, engine, oclass, 0, 4095, &priv);
         *pobject = nv_object(priv);
         if (ret)
                 return ret;
 
+        for (i = 0; i < FIFO_ENGINE_NR; i++) {
+                ret = nouveau_gpuobj_new(nv_object(priv), NULL, 0x8000, 0x1000,
+                                         0, &priv->engine[i].playlist[0]);
+                if (ret)
+                        return ret;
+
+                ret = nouveau_gpuobj_new(nv_object(priv), NULL, 0x8000, 0x1000,
+                                         0, &priv->engine[i].playlist[1]);
+                if (ret)
+                        return ret;
+        }
+
         ret = nouveau_gpuobj_new(nv_object(priv), NULL, 4096 * 0x200, 0x1000,
                                  NVOBJ_FLAG_ZERO_ALLOC, &priv->user.mem);
         if (ret)
@@ -629,7 +638,7 @@ nve0_fifo_dtor(struct nouveau_object *object)
         nouveau_gpuobj_unmap(&priv->user.bar);
         nouveau_gpuobj_ref(NULL, &priv->user.mem);
 
-        for (i = 0; i < ARRAY_SIZE(priv->engine); i++) {
+        for (i = 0; i < FIFO_ENGINE_NR; i++) {
                 nouveau_gpuobj_ref(NULL, &priv->engine[i].playlist[1]);
                 nouveau_gpuobj_ref(NULL, &priv->engine[i].playlist[0]);
         }
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc0.c b/drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc0.c
index 4cc6269d4077..64dca260912f 100644
--- a/drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc0.c
+++ b/drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc0.c
@@ -24,3015 +24,1220 @@
 
 #include "nvc0.h"
 
-void
-nv_icmd(struct nvc0_graph_priv *priv, u32 icmd, u32 data)
-{
-        nv_wr32(priv, 0x400204, data);
-        nv_wr32(priv, 0x400200, icmd);
-        while (nv_rd32(priv, 0x400700) & 2) {}
-}
+struct nvc0_graph_init
+nvc0_grctx_init_icmd[] = {
+        { 0x001000,   1, 0x01, 0x00000004 },
+        { 0x0000a9,   1, 0x01, 0x0000ffff },
+        { 0x000038,   1, 0x01, 0x0fac6881 },
+        { 0x00003d,   1, 0x01, 0x00000001 },
+        { 0x0000e8,   8, 0x01, 0x00000400 },
+        { 0x000078,   8, 0x01, 0x00000300 },
+        { 0x000050,   1, 0x01, 0x00000011 },
+        { 0x000058,   8, 0x01, 0x00000008 },
+        { 0x000208,   8, 0x01, 0x00000001 },
+        { 0x000081,   1, 0x01, 0x00000001 },
+        { 0x000085,   1, 0x01, 0x00000004 },
+        { 0x000088,   1, 0x01, 0x00000400 },
+        { 0x000090,   1, 0x01, 0x00000300 },
+        { 0x000098,   1, 0x01, 0x00001001 },
+        { 0x0000e3,   1, 0x01, 0x00000001 },
+        { 0x0000da,   1, 0x01, 0x00000001 },
+        { 0x0000f8,   1, 0x01, 0x00000003 },
+        { 0x0000fa,   1, 0x01, 0x00000001 },
+        { 0x00009f,   4, 0x01, 0x0000ffff },
+        { 0x0000b1,   1, 0x01, 0x00000001 },
+        { 0x0000b2,  40, 0x01, 0x00000000 },
+        { 0x000210,   8, 0x01, 0x00000040 },
+        { 0x000218,   8, 0x01, 0x0000c080 },
+        { 0x0000ad,   1, 0x01, 0x0000013e },
+        { 0x0000e1,   1, 0x01, 0x00000010 },
+        { 0x000290,  16, 0x01, 0x00000000 },
+        { 0x0003b0,  16, 0x01, 0x00000000 },
+        { 0x0002a0,  16, 0x01, 0x00000000 },
+        { 0x000420,  16, 0x01, 0x00000000 },
+        { 0x0002b0,  16, 0x01, 0x00000000 },
+        { 0x000430,  16, 0x01, 0x00000000 },
+        { 0x0002c0,  16, 0x01, 0x00000000 },
+        { 0x0004d0,  16, 0x01, 0x00000000 },
+        { 0x000720,  16, 0x01, 0x00000000 },
+        { 0x0008c0,  16, 0x01, 0x00000000 },
+        { 0x000890,  16, 0x01, 0x00000000 },
+        { 0x0008e0,  16, 0x01, 0x00000000 },
+        { 0x0008a0,  16, 0x01, 0x00000000 },
+        { 0x0008f0,  16, 0x01, 0x00000000 },
+        { 0x00094c,   1, 0x01, 0x000000ff },
+        { 0x00094d,   1, 0x01, 0xffffffff },
+        { 0x00094e,   1, 0x01, 0x00000002 },
+        { 0x0002ec,   1, 0x01, 0x00000001 },
+        { 0x000303,   1, 0x01, 0x00000001 },
+        { 0x0002e6,   1, 0x01, 0x00000001 },
+        { 0x000466,   1, 0x01, 0x00000052 },
+        { 0x000301,   1, 0x01, 0x3f800000 },
+        { 0x000304,   1, 0x01, 0x30201000 },
+        { 0x000305,   1, 0x01, 0x70605040 },
+        { 0x000306,   1, 0x01, 0xb8a89888 },
+        { 0x000307,   1, 0x01, 0xf8e8d8c8 },
+        { 0x00030a,   1, 0x01, 0x00ffff00 },
+        { 0x00030b,   1, 0x01, 0x0000001a },
+        { 0x00030c,   1, 0x01, 0x00000001 },
+        { 0x000318,   1, 0x01, 0x00000001 },
+        { 0x000340,   1, 0x01, 0x00000000 },
+        { 0x000375,   1, 0x01, 0x00000001 },
+        { 0x000351,   1, 0x01, 0x00000100 },
+        { 0x00037d,   1, 0x01, 0x00000006 },
+        { 0x0003a0,   1, 0x01, 0x00000002 },
+        { 0x0003aa,   1, 0x01, 0x00000001 },
+        { 0x0003a9,   1, 0x01, 0x00000001 },
+        { 0x000380,   1, 0x01, 0x00000001 },
+        { 0x000360,   1, 0x01, 0x00000040 },
+        { 0x000366,   2, 0x01, 0x00000000 },
+        { 0x000368,   1, 0x01, 0x00001fff },
+        { 0x000370,   2, 0x01, 0x00000000 },
+        { 0x000372,   1, 0x01, 0x003fffff },
+        { 0x00037a,   1, 0x01, 0x00000012 },
+        { 0x0005e0,   5, 0x01, 0x00000022 },
+        { 0x000619,   1, 0x01, 0x00000003 },
+        { 0x000811,   1, 0x01, 0x00000003 },
+        { 0x000812,   1, 0x01, 0x00000004 },
+        { 0x000813,   1, 0x01, 0x00000006 },
+        { 0x000814,   1, 0x01, 0x00000008 },
+        { 0x000815,   1, 0x01, 0x0000000b },
+        { 0x000800,   6, 0x01, 0x00000001 },
+        { 0x000632,   1, 0x01, 0x00000001 },
+        { 0x000633,   1, 0x01, 0x00000002 },
+        { 0x000634,   1, 0x01, 0x00000003 },
+        { 0x000635,   1, 0x01, 0x00000004 },
+        { 0x000654,   1, 0x01, 0x3f800000 },
+        { 0x000657,   1, 0x01, 0x3f800000 },
+        { 0x000655,   2, 0x01, 0x3f800000 },
+        { 0x0006cd,   1, 0x01, 0x3f800000 },
+        { 0x0007f5,   1, 0x01, 0x3f800000 },
+        { 0x0007dc,   1, 0x01, 0x39291909 },
+        { 0x0007dd,   1, 0x01, 0x79695949 },
+        { 0x0007de,   1, 0x01, 0xb9a99989 },
+        { 0x0007df,   1, 0x01, 0xf9e9d9c9 },
+        { 0x0007e8,   1, 0x01, 0x00003210 },
+        { 0x0007e9,   1, 0x01, 0x00007654 },
+        { 0x0007ea,   1, 0x01, 0x00000098 },
+        { 0x0007ec,   1, 0x01, 0x39291909 },
+        { 0x0007ed,   1, 0x01, 0x79695949 },
+        { 0x0007ee,   1, 0x01, 0xb9a99989 },
+        { 0x0007ef,   1, 0x01, 0xf9e9d9c9 },
+        { 0x0007f0,   1, 0x01, 0x00003210 },
+        { 0x0007f1,   1, 0x01, 0x00007654 },
+        { 0x0007f2,   1, 0x01, 0x00000098 },
+        { 0x0005a5,   1, 0x01, 0x00000001 },
+        { 0x000980, 128, 0x01, 0x00000000 },
+        { 0x000468,   1, 0x01, 0x00000004 },
+        { 0x00046c,   1, 0x01, 0x00000001 },
+        { 0x000470,  96, 0x01, 0x00000000 },
+        { 0x000510,  16, 0x01, 0x3f800000 },
+        { 0x000520,   1, 0x01, 0x000002b6 },
+        { 0x000529,   1, 0x01, 0x00000001 },
+        { 0x000530,  16, 0x01, 0xffff0000 },
+        { 0x000585,   1, 0x01, 0x0000003f },
+        { 0x000576,   1, 0x01, 0x00000003 },
+        { 0x000586,   1, 0x01, 0x00000040 },
+        { 0x000582,   2, 0x01, 0x00000080 },
+        { 0x0005c2,   1, 0x01, 0x00000001 },
+        { 0x000638,   1, 0x01, 0x00000001 },
+        { 0x000639,   1, 0x01, 0x00000001 },
+        { 0x00063a,   1, 0x01, 0x00000002 },
+        { 0x00063b,   2, 0x01, 0x00000001 },
+        { 0x00063d,   1, 0x01, 0x00000002 },
+        { 0x00063e,   1, 0x01, 0x00000001 },
+        { 0x0008b8,   8, 0x01, 0x00000001 },
+        { 0x000900,   8, 0x01, 0x00000001 },
+        { 0x000908,   8, 0x01, 0x00000002 },
+        { 0x000910,  16, 0x01, 0x00000001 },
+        { 0x000920,   8, 0x01, 0x00000002 },
+        { 0x000928,   8, 0x01, 0x00000001 },
+        { 0x000648,   9, 0x01, 0x00000001 },
+        { 0x000658,   1, 0x01, 0x0000000f },
+        { 0x0007ff,   1, 0x01, 0x0000000a },
+        { 0x00066a,   1, 0x01, 0x40000000 },
+        { 0x00066b,   1, 0x01, 0x10000000 },
+        { 0x00066c,   2, 0x01, 0xffff0000 },
+        { 0x0007af,   2, 0x01, 0x00000008 },
+        { 0x0007f6,   1, 0x01, 0x00000001 },
+        { 0x0006b2,   1, 0x01, 0x00000055 },
+        { 0x0007ad,   1, 0x01, 0x00000003 },
+        { 0x000937,   1, 0x01, 0x00000001 },
+        { 0x000971,   1, 0x01, 0x00000008 },
+        { 0x000972,   1, 0x01, 0x00000040 },
+        { 0x000973,   1, 0x01, 0x0000012c },
+        { 0x00097c,   1, 0x01, 0x00000040 },
+        { 0x000979,   1, 0x01, 0x00000003 },
+        { 0x000975,   1, 0x01, 0x00000020 },
+        { 0x000976,   1, 0x01, 0x00000001 },
+        { 0x000977,   1, 0x01, 0x00000020 },
+        { 0x000978,   1, 0x01, 0x00000001 },
+        { 0x000957,   1, 0x01, 0x00000003 },
+        { 0x00095e,   1, 0x01, 0x20164010 },
+        { 0x00095f,   1, 0x01, 0x00000020 },
+        { 0x000683,   1, 0x01, 0x00000006 },
+        { 0x000685,   1, 0x01, 0x003fffff },
+        { 0x000687,   1, 0x01, 0x00000c48 },
+        { 0x0006a0,   1, 0x01, 0x00000005 },
+        { 0x000840,   1, 0x01, 0x00300008 },
+        { 0x000841,   1, 0x01, 0x04000080 },
+        { 0x000842,   1, 0x01, 0x00300008 },
+        { 0x000843,   1, 0x01, 0x04000080 },
+        { 0x000818,   8, 0x01, 0x00000000 },
+        { 0x000848,  16, 0x01, 0x00000000 },
+        { 0x000738,   1, 0x01, 0x00000000 },
+        { 0x0006aa,   1, 0x01, 0x00000001 },
+        { 0x0006ab,   1, 0x01, 0x00000002 },
+        { 0x0006ac,   1, 0x01, 0x00000080 },
+        { 0x0006ad,   2, 0x01, 0x00000100 },
+        { 0x0006b1,   1, 0x01, 0x00000011 },
+        { 0x0006bb,   1, 0x01, 0x000000cf },
+        { 0x0006ce,   1, 0x01, 0x2a712488 },
+        { 0x000739,   1, 0x01, 0x4085c000 },
+        { 0x00073a,   1, 0x01, 0x00000080 },
+        { 0x000786,   1, 0x01, 0x80000100 },
+        { 0x00073c,   1, 0x01, 0x00010100 },
+        { 0x00073d,   1, 0x01, 0x02800000 },
+        { 0x000787,   1, 0x01, 0x000000cf },
+        { 0x00078c,   1, 0x01, 0x00000008 },
+        { 0x000792,   1, 0x01, 0x00000001 },
+        { 0x000794,   1, 0x01, 0x00000001 },
+        { 0x000795,   2, 0x01, 0x00000001 },
+        { 0x000797,   1, 0x01, 0x000000cf },
+        { 0x000836,   1, 0x01, 0x00000001 },
+        { 0x00079a,   1, 0x01, 0x00000002 },
+        { 0x000833,   1, 0x01, 0x04444480 },
+        { 0x0007a1,   1, 0x01, 0x00000001 },
+        { 0x0007a3,   1, 0x01, 0x00000001 },
+        { 0x0007a4,   2, 0x01, 0x00000001 },
+        { 0x000831,   1, 0x01, 0x00000004 },
+        { 0x00080c,   1, 0x01, 0x00000002 },
+        { 0x00080d,   2, 0x01, 0x00000100 },
+        { 0x00080f,   1, 0x01, 0x00000001 },
+        { 0x000823,   1, 0x01, 0x00000002 },
+        { 0x000824,   2, 0x01, 0x00000100 },
+        { 0x000826,   1, 0x01, 0x00000001 },
+        { 0x00095d,   1, 0x01, 0x00000001 },
+        { 0x00082b,   1, 0x01, 0x00000004 },
+        { 0x000942,   1, 0x01, 0x00010001 },
+        { 0x000943,   1, 0x01, 0x00000001 },
+        { 0x000944,   1, 0x01, 0x00000022 },
+        { 0x0007c5,   1, 0x01, 0x00010001 },
+        { 0x000834,   1, 0x01, 0x00000001 },
+        { 0x0007c7,   1, 0x01, 0x00000001 },
+        { 0x00c1b0,   8, 0x01, 0x0000000f },
+        { 0x00c1b8,   1, 0x01, 0x0fac6881 },
+        { 0x00c1b9,   1, 0x01, 0x00fac688 },
+        { 0x01e100,   1, 0x01, 0x00000001 },
+        { 0x001000,   1, 0x01, 0x00000002 },
+        { 0x0006aa,   1, 0x01, 0x00000001 },
+        { 0x0006ad,   2, 0x01, 0x00000100 },
+        { 0x0006b1,   1, 0x01, 0x00000011 },
+        { 0x00078c,   1, 0x01, 0x00000008 },
+        { 0x000792,   1, 0x01, 0x00000001 },
+        { 0x000794,   1, 0x01, 0x00000001 },
+        { 0x000795,   2, 0x01, 0x00000001 },
+        { 0x000797,   1, 0x01, 0x000000cf },
+        { 0x00079a,   1, 0x01, 0x00000002 },
+        { 0x000833,   1, 0x01, 0x04444480 },
+        { 0x0007a1,   1, 0x01, 0x00000001 },
+        { 0x0007a3,   1, 0x01, 0x00000001 },
+        { 0x0007a4,   2, 0x01, 0x00000001 },
+        { 0x000831,   1, 0x01, 0x00000004 },
+        { 0x01e100,   1, 0x01, 0x00000001 },
+        { 0x001000,   1, 0x01, 0x00000014 },
+        { 0x000351,   1, 0x01, 0x00000100 },
+        { 0x000957,   1, 0x01, 0x00000003 },
+        { 0x00095d,   1, 0x01, 0x00000001 },
+        { 0x00082b,   1, 0x01, 0x00000004 },
+        { 0x000942,   1, 0x01, 0x00010001 },
+        { 0x000943,   1, 0x01, 0x00000001 },
+        { 0x0007c5,   1, 0x01, 0x00010001 },
+        { 0x000834,   1, 0x01, 0x00000001 },
+        { 0x0007c7,   1, 0x01, 0x00000001 },
+        { 0x01e100,   1, 0x01, 0x00000001 },
+        { 0x001000,   1, 0x01, 0x00000001 },
+        { 0x00080c,   1, 0x01, 0x00000002 },
+        { 0x00080d,   2, 0x01, 0x00000100 },
+        { 0x00080f,   1, 0x01, 0x00000001 },
+        { 0x000823,   1, 0x01, 0x00000002 },
+        { 0x000824,   2, 0x01, 0x00000100 },
+        { 0x000826,   1, 0x01, 0x00000001 },
+        { 0x01e100,   1, 0x01, 0x00000001 },
+        {}
+};
+
+struct nvc0_graph_init
+nvc0_grctx_init_9097[] = {
+        { 0x000800,   8, 0x40, 0x00000000 },
+        { 0x000804,   8, 0x40, 0x00000000 },
+        { 0x000808,   8, 0x40, 0x00000400 },
+        { 0x00080c,   8, 0x40, 0x00000300 },
+        { 0x000810,   1, 0x04, 0x000000cf },
+        { 0x000850,   7, 0x40, 0x00000000 },
+        { 0x000814,   8, 0x40, 0x00000040 },
+        { 0x000818,   8, 0x40, 0x00000001 },
+        { 0x00081c,   8, 0x40, 0x00000000 },
+        { 0x000820,   8, 0x40, 0x00000000 },
+        { 0x002700,   8, 0x20, 0x00000000 },
+        { 0x002704,   8, 0x20, 0x00000000 },
+        { 0x002708,   8, 0x20, 0x00000000 },
+        { 0x00270c,   8, 0x20, 0x00000000 },
+        { 0x002710,   8, 0x20, 0x00014000 },
+        { 0x002714,   8, 0x20, 0x00000040 },
+        { 0x001c00,  16, 0x10, 0x00000000 },
+        { 0x001c04,  16, 0x10, 0x00000000 },
+        { 0x001c08,  16, 0x10, 0x00000000 },
+        { 0x001c0c,  16, 0x10, 0x00000000 },
+        { 0x001d00,  16, 0x10, 0x00000000 },
+        { 0x001d04,  16, 0x10, 0x00000000 },
+        { 0x001d08,  16, 0x10, 0x00000000 },
+        { 0x001d0c,  16, 0x10, 0x00000000 },
+        { 0x001f00,  16, 0x08, 0x00000000 },
+        { 0x001f04,  16, 0x08, 0x00000000 },
+        { 0x001f80,  16, 0x08, 0x00000000 },
+        { 0x001f84,  16, 0x08, 0x00000000 },
+        { 0x002200,   5, 0x10, 0x00000022 },
+        { 0x002000,   1, 0x04, 0x00000000 },
+        { 0x002040,   1, 0x04, 0x00000011 },
+        { 0x002080,   1, 0x04, 0x00000020 },
+        { 0x0020c0,   1, 0x04, 0x00000030 },
+        { 0x002100,   1, 0x04, 0x00000040 },
+        { 0x002140,   1, 0x04, 0x00000051 },
+        { 0x00200c,   6, 0x40, 0x00000001 },
+        { 0x002010,   1, 0x04, 0x00000000 },
+        { 0x002050,   1, 0x04, 0x00000000 },
+        { 0x002090,   1, 0x04, 0x00000001 },
+        { 0x0020d0,   1, 0x04, 0x00000002 },
+        { 0x002110,   1, 0x04, 0x00000003 },
+        { 0x002150,   1, 0x04, 0x00000004 },
+        { 0x000380,   4, 0x20, 0x00000000 },
+        { 0x000384,   4, 0x20, 0x00000000 },
+        { 0x000388,   4, 0x20, 0x00000000 },
+        { 0x00038c,   4, 0x20, 0x00000000 },
+        { 0x000700,   4, 0x10, 0x00000000 },
+        { 0x000704,   4, 0x10, 0x00000000 },
+        { 0x000708,   4, 0x10, 0x00000000 },
+        { 0x002800, 128, 0x04, 0x00000000 },
+        { 0x000a00,  16, 0x20, 0x00000000 },
+        { 0x000a04,  16, 0x20, 0x00000000 },
+        { 0x000a08,  16, 0x20, 0x00000000 },
+        { 0x000a0c,  16, 0x20, 0x00000000 },
+        { 0x000a10,  16, 0x20, 0x00000000 },
+        { 0x000a14,  16, 0x20, 0x00000000 },
+        { 0x000c00,  16, 0x10, 0x00000000 },
+        { 0x000c04,  16, 0x10, 0x00000000 },
+        { 0x000c08,  16, 0x10, 0x00000000 },
+        { 0x000c0c,  16, 0x10, 0x3f800000 },
+        { 0x000d00,   8, 0x08, 0xffff0000 },
+        { 0x000d04,   8, 0x08, 0xffff0000 },
+        { 0x000e00,  16, 0x10, 0x00000000 },
+        { 0x000e04,  16, 0x10, 0xffff0000 },
+        { 0x000e08,  16, 0x10, 0xffff0000 },
+        { 0x000d40,   4, 0x08, 0x00000000 },
+        { 0x000d44,   4, 0x08, 0x00000000 },
+        { 0x001e00,   8, 0x20, 0x00000001 },
+        { 0x001e04,   8, 0x20, 0x00000001 },
+        { 0x001e08,   8, 0x20, 0x00000002 },
+        { 0x001e0c,   8, 0x20, 0x00000001 },
+        { 0x001e10,   8, 0x20, 0x00000001 },
+        { 0x001e14,   8, 0x20, 0x00000002 },
+        { 0x001e18,   8, 0x20, 0x00000001 },
+        { 0x003400, 128, 0x04, 0x00000000 },
+        { 0x00030c,   1, 0x04, 0x00000001 },
+        { 0x001944,   1, 0x04, 0x00000000 },
+        { 0x001514,   1, 0x04, 0x00000000 },
+        { 0x000d68,   1, 0x04, 0x0000ffff },
+        { 0x00121c,   1, 0x04, 0x0fac6881 },
+        { 0x000fac,   1, 0x04, 0x00000001 },
+        { 0x001538,   1, 0x04, 0x00000001 },
+        { 0x000fe0,   2, 0x04, 0x00000000 },
+        { 0x000fe8,   1, 0x04, 0x00000014 },
+        { 0x000fec,   1, 0x04, 0x00000040 },
+        { 0x000ff0,   1, 0x04, 0x00000000 },
+        { 0x00179c,   1, 0x04, 0x00000000 },
+        { 0x001228,   1, 0x04, 0x00000400 },
+        { 0x00122c,   1, 0x04, 0x00000300 },
+        { 0x001230,   1, 0x04, 0x00010001 },
+        { 0x0007f8,   1, 0x04, 0x00000000 },
+        { 0x0015b4,   1, 0x04, 0x00000001 },
+        { 0x0015cc,   1, 0x04, 0x00000000 },
+        { 0x001534,   1, 0x04, 0x00000000 },
+        { 0x000fb0,   1, 0x04, 0x00000000 },
+        { 0x0015d0,   1, 0x04, 0x00000000 },
+        { 0x00153c,   1, 0x04, 0x00000000 },
+        { 0x0016b4,   1, 0x04, 0x00000003 },
+        { 0x000fbc,   4, 0x04, 0x0000ffff },
+        { 0x000df8,   2, 0x04, 0x00000000 },
+        { 0x001948,   1, 0x04, 0x00000000 },
+        { 0x001970,   1, 0x04, 0x00000001 },
+        { 0x00161c,   1, 0x04, 0x000009f0 },
+        { 0x000dcc,   1, 0x04, 0x00000010 },
+        { 0x00163c,   1, 0x04, 0x00000000 },
+        { 0x0015e4,   1, 0x04, 0x00000000 },
+        { 0x001160,  32, 0x04, 0x25e00040 },
+        { 0x001880,  32, 0x04, 0x00000000 },
+        { 0x000f84,   2, 0x04, 0x00000000 },
+        { 0x0017c8,   2, 0x04, 0x00000000 },
+        { 0x0017d0,   1, 0x04, 0x000000ff },
+        { 0x0017d4,   1, 0x04, 0xffffffff },
+        { 0x0017d8,   1, 0x04, 0x00000002 },
+        { 0x0017dc,   1, 0x04, 0x00000000 },
+        { 0x0015f4,   2, 0x04, 0x00000000 },
+        { 0x001434,   2, 0x04, 0x00000000 },
+        { 0x000d74,   1, 0x04, 0x00000000 },
+        { 0x000dec,   1, 0x04, 0x00000001 },
+        { 0x0013a4,   1, 0x04, 0x00000000 },
+        { 0x001318,   1, 0x04, 0x00000001 },
+        { 0x001644,   1, 0x04, 0x00000000 },
+        { 0x000748,   1, 0x04, 0x00000000 },
+        { 0x000de8,   1, 0x04, 0x00000000 },
+        { 0x001648,   1, 0x04, 0x00000000 },
+        { 0x0012a4,   1, 0x04, 0x00000000 },
+        { 0x001120,   4, 0x04, 0x00000000 },
+        { 0x001118,   1, 0x04, 0x00000000 },
+        { 0x00164c,   1, 0x04, 0x00000000 },
+        { 0x001658,   1, 0x04, 0x00000000 },
+        { 0x001910,   1, 0x04, 0x00000290 },
+        { 0x001518,   1, 0x04, 0x00000000 },
+        { 0x00165c,   1, 0x04, 0x00000001 },
+        { 0x001520,   1, 0x04, 0x00000000 },
+        { 0x001604,   1, 0x04, 0x00000000 },
+        { 0x001570,   1, 0x04, 0x00000000 },
+        { 0x0013b0,   2, 0x04, 0x3f800000 },
+        { 0x00020c,   1, 0x04, 0x00000000 },
+        { 0x001670,   1, 0x04, 0x30201000 },
+        { 0x001674,   1, 0x04, 0x70605040 },
+        { 0x001678,   1, 0x04, 0xb8a89888 },
+        { 0x00167c,   1, 0x04, 0xf8e8d8c8 },
+        { 0x00166c,   1, 0x04, 0x00000000 },
+        { 0x001680,   1, 0x04, 0x00ffff00 },
+        { 0x0012d0,   1, 0x04, 0x00000003 },
+        { 0x0012d4,   1, 0x04, 0x00000002 },
+        { 0x001684,   2, 0x04, 0x00000000 },
+        { 0x000dac,   2, 0x04, 0x00001b02 },
+        { 0x000db4,   1, 0x04, 0x00000000 },
+        { 0x00168c,   1, 0x04, 0x00000000 },
+        { 0x0015bc,   1, 0x04, 0x00000000 },
+        { 0x00156c,   1, 0x04, 0x00000000 },
+        { 0x00187c,   1, 0x04, 0x00000000 },
+        { 0x001110,   1, 0x04, 0x00000001 },
+        { 0x000dc0,   3, 0x04, 0x00000000 },
+        { 0x001234,   1, 0x04, 0x00000000 },
+        { 0x001690,   1, 0x04, 0x00000000 },
+        { 0x0012ac,   1, 0x04, 0x00000001 },
+        { 0x0002c4,   1, 0x04, 0x00000000 },
+        { 0x000790,   5, 0x04, 0x00000000 },
+        { 0x00077c,   1, 0x04, 0x00000000 },
+        { 0x001000,   1, 0x04, 0x00000010 },
+        { 0x0010fc,   1, 0x04, 0x00000000 },
+        { 0x001290,   1, 0x04, 0x00000000 },
+        { 0x000218,   1, 0x04, 0x00000010 },
+        { 0x0012d8,   1, 0x04, 0x00000000 },
+        { 0x0012dc,   1, 0x04, 0x00000010 },
+        { 0x000d94,   1, 0x04, 0x00000001 },
+        { 0x00155c,   2, 0x04, 0x00000000 },
+        { 0x001564,   1, 0x04, 0x00001fff },
+        { 0x001574,   2, 0x04, 0x00000000 },
+        { 0x00157c,   1, 0x04, 0x003fffff },
+        { 0x001354,   1, 0x04, 0x00000000 },
+        { 0x001664,   1, 0x04, 0x00000000 },
+        { 0x001610,   1, 0x04, 0x00000012 },
+        { 0x001608,   2, 0x04, 0x00000000 },
+        { 0x00162c,   1, 0x04, 0x00000003 },
+        { 0x000210,   1, 0x04, 0x00000000 },
+        { 0x000320,   1, 0x04, 0x00000000 },
+        { 0x000324,   6, 0x04, 0x3f800000 },
+        { 0x000750,   1, 0x04, 0x00000000 },
+        { 0x000760,   1, 0x04, 0x39291909 },
+        { 0x000764,   1, 0x04, 0x79695949 },
+        { 0x000768,   1, 0x04, 0xb9a99989 },
+        { 0x00076c,   1, 0x04, 0xf9e9d9c9 },
+        { 0x000770,   1, 0x04, 0x30201000 },
+        { 0x000774,   1, 0x04, 0x70605040 },
+        { 0x000778,   1, 0x04, 0x00009080 },
+        { 0x000780,   1, 0x04, 0x39291909 },
+        { 0x000784,   1, 0x04, 0x79695949 },
+        { 0x000788,   1, 0x04, 0xb9a99989 },
+        { 0x00078c,   1, 0x04, 0xf9e9d9c9 },
+        { 0x0007d0,   1, 0x04, 0x30201000 },
+        { 0x0007d4,   1, 0x04, 0x70605040 },
+        { 0x0007d8,   1, 0x04, 0x00009080 },
+        { 0x00037c,   1, 0x04, 0x00000001 },
+        { 0x000740,   2, 0x04, 0x00000000 },
+        { 0x002600,   1, 0x04, 0x00000000 },
+        { 0x001918,   1, 0x04, 0x00000000 },
+        { 0x00191c,   1, 0x04, 0x00000900 },
+        { 0x001920,   1, 0x04, 0x00000405 },
+        { 0x001308,   1, 0x04, 0x00000001 },
+        { 0x001924,   1, 0x04, 0x00000000 },
+        { 0x0013ac,   1, 0x04, 0x00000000 },
+        { 0x00192c,   1, 0x04, 0x00000001 },
+        { 0x00193c,   1, 0x04, 0x00002c1c },
+        { 0x000d7c,   1, 0x04, 0x00000000 },
+        { 0x000f8c,   1, 0x04, 0x00000000 },
+        { 0x0002c0,   1, 0x04, 0x00000001 },
+        { 0x001510,   1, 0x04, 0x00000000 },
+        { 0x001940,   1, 0x04, 0x00000000 },
+        { 0x000ff4,   2, 0x04, 0x00000000 },
+        { 0x00194c,   2, 0x04, 0x00000000 },
+        { 0x001968,   1, 0x04, 0x00000000 },
+        { 0x001590,   1, 0x04, 0x0000003f },
+        { 0x0007e8,   4, 0x04, 0x00000000 },
+        { 0x00196c,   1, 0x04, 0x00000011 },
+        { 0x00197c,   1, 0x04, 0x00000000 },
+        { 0x000fcc,   2, 0x04, 0x00000000 },
+        { 0x0002d8,   1, 0x04, 0x00000040 },
+        { 0x001980,   1, 0x04, 0x00000080 },
+        { 0x001504,   1, 0x04, 0x00000080 },
+        { 0x001984,   1, 0x04, 0x00000000 },
+        { 0x000300,   1, 0x04, 0x00000001 },
+        { 0x0013a8,   1, 0x04, 0x00000000 },
+        { 0x0012ec,   1, 0x04, 0x00000000 },
+        { 0x001310,   1, 0x04, 0x00000000 },
+        { 0x001314,   1, 0x04, 0x00000001 },
+        { 0x001380,   1, 0x04, 0x00000000 },
+        { 0x001384,   4, 0x04, 0x00000001 },
+        { 0x001394,   1, 0x04, 0x00000000 },
+        { 0x00139c,   1, 0x04, 0x00000000 },
+        { 0x001398,   1, 0x04, 0x00000000 },
+        { 0x001594,   1, 0x04, 0x00000000 },
+        { 0x001598,   4, 0x04, 0x00000001 },
+        { 0x000f54,   3, 0x04, 0x00000000 },
+        { 0x0019bc,   1, 0x04, 0x00000000 },
+        { 0x000f9c,   2, 0x04, 0x00000000 },
+        { 0x0012cc,   1, 0x04, 0x00000000 },
+        { 0x0012e8,   1, 0x04, 0x00000000 },
+        { 0x00130c,   1, 0x04, 0x00000001 },
+        { 0x001360,   8, 0x04, 0x00000000 },
+        { 0x00133c,   2, 0x04, 0x00000001 },
+        { 0x001344,   1, 0x04, 0x00000002 },
+        { 0x001348,   2, 0x04, 0x00000001 },
+        { 0x001350,   1, 0x04, 0x00000002 },
+        { 0x001358,   1, 0x04, 0x00000001 },
+        { 0x0012e4,   1, 0x04, 0x00000000 },
+        { 0x00131c,   1, 0x04, 0x00000000 },
+        { 0x001320,   3, 0x04, 0x00000000 },
+        { 0x0019c0,   1, 0x04, 0x00000000 },
+        { 0x001140,   1, 0x04, 0x00000000 },
+        { 0x0019c4,   1, 0x04, 0x00000000 },
+        { 0x0019c8,   1, 0x04, 0x00001500 },
+        { 0x00135c,   1, 0x04, 0x00000000 },
+        { 0x000f90,   1, 0x04, 0x00000000 },
+        { 0x0019e0,   8, 0x04, 0x00000001 },
+        { 0x0019cc,   1, 0x04, 0x00000001 },
+        { 0x0015b8,   1, 0x04, 0x00000000 },
+        { 0x001a00,   1, 0x04, 0x00001111 },
+        { 0x001a04,   7, 0x04, 0x00000000 },
+        { 0x000d6c,   2, 0x04, 0xffff0000 },
+        { 0x0010f8,   1, 0x04, 0x00001010 },
+        { 0x000d80,   5, 0x04, 0x00000000 },
+        { 0x000da0,   1, 0x04, 0x00000000 },
+        { 0x001508,   1, 0x04, 0x80000000 },
+        { 0x00150c,   1, 0x04, 0x40000000 },
+        { 0x001668,   1, 0x04, 0x00000000 },
+        { 0x000318,   2, 0x04, 0x00000008 },
+        { 0x000d9c,   1, 0x04, 0x00000001 },
+        { 0x0007dc,   1, 0x04, 0x00000000 },
+        { 0x00074c,   1, 0x04, 0x00000055 },
+        { 0x001420,   1, 0x04, 0x00000003 },
+        { 0x0017bc,   2, 0x04, 0x00000000 },
+        { 0x0017c4,   1, 0x04, 0x00000001 },
+        { 0x001008,   1, 0x04, 0x00000008 },
+        { 0x00100c,   1, 0x04, 0x00000040 },
+        { 0x001010,   1, 0x04, 0x0000012c },
+        { 0x000d60,   1, 0x04, 0x00000040 },
+        { 0x00075c,   1, 0x04, 0x00000003 },
+        { 0x001018,   1, 0x04, 0x00000020 },
+        { 0x00101c,   1, 0x04, 0x00000001 },
+        { 0x001020,   1, 0x04, 0x00000020 },
+        { 0x001024,   1, 0x04, 0x00000001 },
+        { 0x001444,   3, 0x04, 0x00000000 },
+        { 0x000360,   1, 0x04, 0x20164010 },
+        { 0x000364,   1, 0x04, 0x00000020 },
+        { 0x000368,   1, 0x04, 0x00000000 },
+        { 0x000de4,   1, 0x04, 0x00000000 },
+        { 0x000204,   1, 0x04, 0x00000006 },
+        { 0x000208,   1, 0x04, 0x00000000 },
+        { 0x0002cc,   1, 0x04, 0x003fffff },
+        { 0x0002d0,   1, 0x04, 0x00000c48 },
+        { 0x001220,   1, 0x04, 0x00000005 },
+        { 0x000fdc,   1, 0x04, 0x00000000 },
+        { 0x000f98,   1, 0x04, 0x00300008 },
+        { 0x001284,   1, 0x04, 0x04000080 },
+        { 0x001450,   1, 0x04, 0x00300008 },
+        { 0x001454,   1, 0x04, 0x04000080 },
+        { 0x000214,   1, 0x04, 0x00000000 },
+        {}
+};
+
+struct nvc0_graph_init
+nvc0_grctx_init_902d[] = {
+        { 0x000200,   1, 0x04, 0x000000cf },
+        { 0x000204,   1, 0x04, 0x00000001 },
+        { 0x000208,   1, 0x04, 0x00000020 },
+        { 0x00020c,   1, 0x04, 0x00000001 },
+        { 0x000210,   1, 0x04, 0x00000000 },
+        { 0x000214,   1, 0x04, 0x00000080 },
+        { 0x000218,   2, 0x04, 0x00000100 },
+        { 0x000220,   2, 0x04, 0x00000000 },
+        { 0x000230,   1, 0x04, 0x000000cf },
+        { 0x000234,   1, 0x04, 0x00000001 },
+        { 0x000238,   1, 0x04, 0x00000020 },
+        { 0x00023c,   1, 0x04, 0x00000001 },
+        { 0x000244,   1, 0x04, 0x00000080 },
+        { 0x000248,   2, 0x04, 0x00000100 },
+        {}
+};
+
+struct nvc0_graph_init
+nvc0_grctx_init_9039[] = {
+        { 0x00030c,   3, 0x04, 0x00000000 },
+        { 0x000320,   1, 0x04, 0x00000000 },
+        { 0x000238,   2, 0x04, 0x00000000 },
+        { 0x000318,   2, 0x04, 0x00000000 },
+        {}
+};
+
+struct nvc0_graph_init
+nvc0_grctx_init_90c0[] = {
+        { 0x00270c,   8, 0x20, 0x00000000 },
+        { 0x00030c,   1, 0x04, 0x00000001 },
+        { 0x001944,   1, 0x04, 0x00000000 },
+        { 0x000758,   1, 0x04, 0x00000100 },
+        { 0x0002c4,   1, 0x04, 0x00000000 },
+        { 0x000790,   5, 0x04, 0x00000000 },
+        { 0x00077c,   1, 0x04, 0x00000000 },
+        { 0x000204,   3, 0x04, 0x00000000 },
+        { 0x000214,   1, 0x04, 0x00000000 },
+        { 0x00024c,   1, 0x04, 0x00000000 },
+        { 0x000d94,   1, 0x04, 0x00000001 },
+        { 0x001608,   2, 0x04, 0x00000000 },
+        { 0x001664,   1, 0x04, 0x00000000 },
+        {}
+};
+
+struct nvc0_graph_init
+nvc0_grctx_init_base[] = {
+        { 0x400204,   2, 0x04, 0x00000000 },
+        {}
+};
+
+struct nvc0_graph_init
+nvc0_grctx_init_unk40xx[] = {
+        { 0x404004,  10, 0x04, 0x00000000 },
+        { 0x404044,   1, 0x04, 0x00000000 },
+        { 0x404094,   1, 0x04, 0x00000000 },
+        { 0x404098,  12, 0x04, 0x00000000 },
+        { 0x4040c8,   1, 0x04, 0xf0000087 },
+        { 0x4040d0,   6, 0x04, 0x00000000 },
+        { 0x4040e8,   1, 0x04, 0x00001000 },
+        { 0x4040f8,   1, 0x04, 0x00000000 },
+        { 0x404130,   1, 0x04, 0x00000000 },
+        { 0x404134,   1, 0x04, 0x00000000 },
+        { 0x404138,   1, 0x04, 0x20000040 },
+        { 0x404150,   1, 0x04, 0x0000002e },
+        { 0x404154,   1, 0x04, 0x00000400 },
+        { 0x404158,   1, 0x04, 0x00000200 },
+        { 0x404164,   1, 0x04, 0x00000055 },
+        { 0x404168,   1, 0x04, 0x00000000 },
+        { 0x404174,   1, 0x04, 0x00000000 },
+        { 0x404178,   2, 0x04, 0x00000000 },
+        { 0x404200,   8, 0x04, 0x00000000 },
+        {}
+};
+
+struct nvc0_graph_init
+nvc0_grctx_init_unk44xx[] = {
+        { 0x404404,  14, 0x04, 0x00000000 },
+        { 0x404460,   2, 0x04, 0x00000000 },
+        { 0x404468,   1, 0x04, 0x00ffffff },
+        { 0x40446c,   1, 0x04, 0x00000000 },
+        { 0x404480,   1, 0x04, 0x00000001 },
+        { 0x404498,   1, 0x04, 0x00000001 },
+        {}
+};
+
+struct nvc0_graph_init
+nvc0_grctx_init_unk46xx[] = {
+        { 0x404604,   1, 0x04, 0x00000015 },
+        { 0x404608,   1, 0x04, 0x00000000 },
+        { 0x40460c,   1, 0x04, 0x00002e00 },
+        { 0x404610,   1, 0x04, 0x00000100 },
+        { 0x404618,   8, 0x04, 0x00000000 },
+        { 0x404638,   1, 0x04, 0x00000004 },
+        { 0x40463c,   8, 0x04, 0x00000000 },
+        { 0x40465c,   1, 0x04, 0x007f0100 },
+        { 0x404660,   7, 0x04, 0x00000000 },
+        { 0x40467c,   1, 0x04, 0x00000002 },
+        { 0x404680,   8, 0x04, 0x00000000 },
+        { 0x4046a0,   1, 0x04, 0x007f0080 },
+        { 0x4046a4,  18, 0x04, 0x00000000 },
+        { 0x4046f0,   2, 0x04, 0x00000000 },
+        {}
+};
+
+struct nvc0_graph_init
+nvc0_grctx_init_unk47xx[] = {
+        { 0x404700,  13, 0x04, 0x00000000 },
+        { 0x404734,   1, 0x04, 0x00000100 },
+        { 0x404738,   8, 0x04, 0x00000000 },
+        {}
+};
+
+struct nvc0_graph_init
+nvc0_grctx_init_unk58xx[] = {
+        { 0x405800,   1, 0x04, 0x078000bf },
+        { 0x405830,   1, 0x04, 0x02180000 },
+        { 0x405834,   2, 0x04, 0x00000000 },
+        { 0x405854,   1, 0x04, 0x00000000 },
+        { 0x405870,   4, 0x04, 0x00000001 },
+        { 0x405a00,   2, 0x04, 0x00000000 },
+        { 0x405a18,   1, 0x04, 0x00000000 },
+        {}
+};
+
+struct nvc0_graph_init
+nvc0_grctx_init_unk60xx[] = {
+        { 0x406020,   1, 0x04, 0x000103c1 },
+        { 0x406028,   4, 0x04, 0x00000001 },
+        {}
+};
+
+struct nvc0_graph_init
+nvc0_grctx_init_unk64xx[] = {
+        { 0x4064a8,   1, 0x04, 0x00000000 },
+        { 0x4064ac,   1, 0x04, 0x00003fff },
+        { 0x4064b4,   2, 0x04, 0x00000000 },
+        {}
+};
+
+struct nvc0_graph_init
+nvc0_grctx_init_unk78xx[] = {
+        { 0x407804,   1, 0x04, 0x00000023 },
+        { 0x40780c,   1, 0x04, 0x0a418820 },
+        { 0x407810,   1, 0x04, 0x062080e6 },
+        { 0x407814,   1, 0x04, 0x020398a4 },
+        { 0x407818,   1, 0x04, 0x0e629062 },
+        { 0x40781c,   1, 0x04, 0x0a418820 },
+        { 0x407820,   1, 0x04, 0x000000e6 },
+        { 0x4078bc,   1, 0x04, 0x00000103 },
+        {}
+};
+
+struct nvc0_graph_init
+nvc0_grctx_init_unk80xx[] = {
+        { 0x408000,   2, 0x04, 0x00000000 },
+        { 0x408008,   1, 0x04, 0x00000018 },
+        { 0x40800c,   2, 0x04, 0x00000000 },
+        { 0x408014,   1, 0x04, 0x00000069 },
+        { 0x408018,   1, 0x04, 0xe100e100 },
+        { 0x408064,   1, 0x04, 0x00000000 },
+        {}
+};
+
+struct nvc0_graph_init
+nvc0_grctx_init_rop[] = {
+        { 0x408800,   1, 0x04, 0x02802a3c },
+        { 0x408804,   1, 0x04, 0x00000040 },
+        { 0x408808,   1, 0x04, 0x0003e00d },
+        { 0x408900,   1, 0x04, 0x3080b801 },
+        { 0x408904,   1, 0x04, 0x02000001 },
+        { 0x408908,   1, 0x04, 0x00c80929 },
+        { 0x408980,   1, 0x04, 0x0000011d },
+        {}
+};
+
+struct nvc0_graph_init
+nvc0_grctx_init_gpc_0[] = {
+        { 0x418380,   1, 0x04, 0x00000016 },
+        { 0x418400,   1, 0x04, 0x38004e00 },
+        { 0x418404,   1, 0x04, 0x71e0ffff },
+        { 0x418408,   1, 0x04, 0x00000000 },
+        { 0x41840c,   1, 0x04, 0x00001008 },
+        { 0x418410,   1, 0x04, 0x0fff0fff },
+        { 0x418414,   1, 0x04, 0x00200fff },
+        { 0x418450,   6, 0x04, 0x00000000 },
+        { 0x418468,   1, 0x04, 0x00000001 },
+        { 0x41846c,   2, 0x04, 0x00000000 },
+        { 0x418600,   1, 0x04, 0x0000001f },
+        { 0x418684,   1, 0x04, 0x0000000f },
+        { 0x418700,   1, 0x04, 0x00000002 },
+        { 0x418704,   1, 0x04, 0x00000080 },
+        { 0x418708,   1, 0x04, 0x00000000 },
+        { 0x41870c,   1, 0x04, 0x07c80000 },
+        { 0x418710,   1, 0x04, 0x00000000 },
+        { 0x418800,   1, 0x04, 0x0006860a },
+        { 0x418808,   3, 0x04, 0x00000000 },
+        { 0x418828,   1, 0x04, 0x00008442 },
+        { 0x418830,   1, 0x04, 0x00000001 },
+        { 0x4188d8,   1, 0x04, 0x00000008 },
+        { 0x4188e0,   1, 0x04, 0x01000000 },
+        { 0x4188e8,   5, 0x04, 0x00000000 },
+        { 0x4188fc,   1, 0x04, 0x00100000 },
+        { 0x41891c,   1, 0x04, 0x00ff00ff },
+        { 0x418924,   1, 0x04, 0x00000000 },
+        { 0x418928,   1, 0x04, 0x00ffff00 },
+        { 0x41892c,   1, 0x04, 0x0000ff00 },
+        { 0x418b00,   1, 0x04, 0x00000000 },
+        { 0x418b08,   1, 0x04, 0x0a418820 },
+        { 0x418b0c,   1, 0x04, 0x062080e6 },
+        { 0x418b10,   1, 0x04, 0x020398a4 },
+        { 0x418b14,   1, 0x04, 0x0e629062 },
+        { 0x418b18,   1, 0x04, 0x0a418820 },
+        { 0x418b1c,   1, 0x04, 0x000000e6 },
+        { 0x418bb8,   1, 0x04, 0x00000103 },
+        { 0x418c08,   1, 0x04, 0x00000001 },
+        { 0x418c10,   8, 0x04, 0x00000000 },
+        { 0x418c80,   1, 0x04, 0x20200004 },
+        { 0x418c8c,   1, 0x04, 0x00000001 },
+        { 0x419000,   1, 0x04, 0x00000780 },
+        { 0x419004,   2, 0x04, 0x00000000 },
+        { 0x419014,   1, 0x04, 0x00000004 },
+        {}
+};
+
+struct nvc0_graph_init
+nvc0_grctx_init_gpc_1[] = {
+        { 0x418a00,   3, 0x04, 0x00000000 },
+        { 0x418a0c,   1, 0x04, 0x00010000 },
+        { 0x418a10,   3, 0x04, 0x00000000 },
+        { 0x418a20,   3, 0x04, 0x00000000 },
+        { 0x418a2c,   1, 0x04, 0x00010000 },
+        { 0x418a30,   3, 0x04, 0x00000000 },
+        { 0x418a40,   3, 0x04, 0x00000000 },
+        { 0x418a4c,   1, 0x04, 0x00010000 },
+        { 0x418a50,   3, 0x04, 0x00000000 },
+        { 0x418a60,   3, 0x04, 0x00000000 },
+        { 0x418a6c,   1, 0x04, 0x00010000 },
+        { 0x418a70,   3, 0x04, 0x00000000 },
+        { 0x418a80,   3, 0x04, 0x00000000 },
+        { 0x418a8c,   1, 0x04, 0x00010000 },
+        { 0x418a90,   3, 0x04, 0x00000000 },
+        { 0x418aa0,   3, 0x04, 0x00000000 },
+        { 0x418aac,   1, 0x04, 0x00010000 },
+        { 0x418ab0,   3, 0x04, 0x00000000 },
+        { 0x418ac0,   3, 0x04, 0x00000000 },
+        { 0x418acc,   1, 0x04, 0x00010000 },
+        { 0x418ad0,   3, 0x04, 0x00000000 },
+        { 0x418ae0,   3, 0x04, 0x00000000 },
+        { 0x418aec,   1, 0x04, 0x00010000 },
+        { 0x418af0,   3, 0x04, 0x00000000 },
+        {}
+};
+
+struct nvc0_graph_init
+nvc0_grctx_init_tpc[] = {
+        { 0x419818,   1, 0x04, 0x00000000 },
+        { 0x41983c,   1, 0x04, 0x00038bc7 },
+        { 0x419848,   1, 0x04, 0x00000000 },
+        { 0x419864,   1, 0x04, 0x0000012a },
+        { 0x419888,   1, 0x04, 0x00000000 },
+        { 0x419a00,   1, 0x04, 0x000001f0 },
+        { 0x419a04,   1, 0x04, 0x00000001 },
+        { 0x419a08,   1, 0x04, 0x00000023 },
+        { 0x419a0c,   1, 0x04, 0x00020000 },
+        { 0x419a10,   1, 0x04, 0x00000000 },
+        { 0x419a14,   1, 0x04, 0x00000200 },
+        { 0x419b00,   1, 0x04, 0x0a418820 },
+        { 0x419b04,   1, 0x04, 0x062080e6 },
+        { 0x419b08,   1, 0x04, 0x020398a4 },
+        { 0x419b0c,   1, 0x04, 0x0e629062 },
+        { 0x419b10,   1, 0x04, 0x0a418820 },
+        { 0x419b14,   1, 0x04, 0x000000e6 },
+        { 0x419bd0,   1, 0x04, 0x00900103 },
+        { 0x419be0,   1, 0x04, 0x00000001 },
+        { 0x419be4,   1, 0x04, 0x00000000 },
+        { 0x419c00,   1, 0x04, 0x00000002 },
+        { 0x419c04,   1, 0x04, 0x00000006 },
+        { 0x419c08,   1, 0x04, 0x00000002 },
+        { 0x419c20,   1, 0x04, 0x00000000 },
+        { 0x419cb0,   1, 0x04, 0x00060048 },
+        { 0x419ce8,   1, 0x04, 0x00000000 },
+        { 0x419cf4,   1, 0x04, 0x00000183 },
+        { 0x419d20,   1, 0x04, 0x02180000 },
+        { 0x419d24,   1, 0x04, 0x00001fff },
+        { 0x419e04,   3, 0x04, 0x00000000 },
+        { 0x419e10,   1, 0x04, 0x00000002 },
+        { 0x419e44,   1, 0x04, 0x001beff2 },
+        { 0x419e48,   1, 0x04, 0x00000000 },
+        { 0x419e4c,   1, 0x04, 0x0000000f },
+        { 0x419e50,  17, 0x04, 0x00000000 },
+        { 0x419e98,   1, 0x04, 0x00000000 },
+        { 0x419f50,   2, 0x04, 0x00000000 },
+        {}
+};
 
-int
-nvc0_grctx_init(struct nvc0_graph_priv *priv, struct nvc0_grctx *info)
+void
+nvc0_grctx_generate_mods(struct nvc0_graph_priv *priv, struct nvc0_grctx *info)
 {
-        struct nouveau_bar *bar = nouveau_bar(priv);
-        struct nouveau_gpuobj *chan;
-        u32 size = (0x80000 + priv->size + 4095) & ~4095;
-        int ret, i;
-
-        /* allocate memory to for a "channel", which we'll use to generate
-         * the default context values
-         */
-        ret = nouveau_gpuobj_new(nv_object(priv), NULL, size, 0x1000,
-                                 NVOBJ_FLAG_ZERO_ALLOC, &info->chan);
-        chan = info->chan;
-        if (ret) {
-                nv_error(priv, "failed to allocate channel memory, %d\n", ret);
-                return ret;
-        }
-
-        /* PGD pointer */
-        nv_wo32(chan, 0x0200, lower_32_bits(chan->addr + 0x1000));
-        nv_wo32(chan, 0x0204, upper_32_bits(chan->addr + 0x1000));
-        nv_wo32(chan, 0x0208, 0xffffffff);
-        nv_wo32(chan, 0x020c, 0x000000ff);
-
-        /* PGT[0] pointer */
-        nv_wo32(chan, 0x1000, 0x00000000);
-        nv_wo32(chan, 0x1004, 0x00000001 | (chan->addr + 0x2000) >> 8);
-
-        /* identity-map the whole "channel" into its own vm */
-        for (i = 0; i < size / 4096; i++) {
-                u64 addr = ((chan->addr + (i * 4096)) >> 8) | 1;
-                nv_wo32(chan, 0x2000 + (i * 8), lower_32_bits(addr));
-                nv_wo32(chan, 0x2004 + (i * 8), upper_32_bits(addr));
-        }
-
-        /* context pointer (virt) */
-        nv_wo32(chan, 0x0210, 0x00080004);
-        nv_wo32(chan, 0x0214, 0x00000000);
+        int gpc, tpc;
+        u32 offset;
 
-        bar->flush(bar);
-
-        nv_wr32(priv, 0x100cb8, (chan->addr + 0x1000) >> 8);
-        nv_wr32(priv, 0x100cbc, 0x80000001);
-        nv_wait(priv, 0x100c80, 0x00008000, 0x00008000);
-
-        /* setup default state for mmio list construction */
-        info->data = priv->mmio_data;
-        info->mmio = priv->mmio_list;
-        info->addr = 0x2000 + (i * 8);
-        info->priv = priv;
-        info->buffer_nr = 0;
+        mmio_data(0x002000, 0x0100, NV_MEM_ACCESS_RW | NV_MEM_ACCESS_SYS);
+        mmio_data(0x008000, 0x0100, NV_MEM_ACCESS_RW | NV_MEM_ACCESS_SYS);
+        mmio_data(0x060000, 0x1000, NV_MEM_ACCESS_RW);
 
-        if (priv->firmware) {
-                nv_wr32(priv, 0x409840, 0x00000030);
-                nv_wr32(priv, 0x409500, 0x80000000 | chan->addr >> 12);
-                nv_wr32(priv, 0x409504, 0x00000003);
-                if (!nv_wait(priv, 0x409800, 0x00000010, 0x00000010))
-                        nv_error(priv, "load_ctx timeout\n");
+        mmio_list(0x408004, 0x00000000,  8, 0);
+        mmio_list(0x408008, 0x80000018,  0, 0);
+        mmio_list(0x40800c, 0x00000000,  8, 1);
+        mmio_list(0x408010, 0x80000000,  0, 0);
+        mmio_list(0x418810, 0x80000000, 12, 2);
+        mmio_list(0x419848, 0x10000000, 12, 2);
+        mmio_list(0x419004, 0x00000000,  8, 1);
+        mmio_list(0x419008, 0x00000000,  0, 0);
+        mmio_list(0x418808, 0x00000000,  8, 0);
+        mmio_list(0x41880c, 0x80000018,  0, 0);
 
-                nv_wo32(chan, 0x8001c, 1);
-                nv_wo32(chan, 0x80020, 0);
-                nv_wo32(chan, 0x80028, 0);
-                nv_wo32(chan, 0x8002c, 0);
-                bar->flush(bar);
-                return 0;
-        }
+        mmio_list(0x405830, 0x02180000, 0, 0);
 
-        /* HUB_FUC(SET_CHAN) */
-        nv_wr32(priv, 0x409840, 0x80000000);
-        nv_wr32(priv, 0x409500, 0x80000000 | chan->addr >> 12);
-        nv_wr32(priv, 0x409504, 0x00000001);
-        if (!nv_wait(priv, 0x409800, 0x80000000, 0x80000000)) {
-                nv_error(priv, "HUB_SET_CHAN timeout\n");
-                nvc0_graph_ctxctl_debug(priv);
-                nouveau_gpuobj_ref(NULL, &info->chan);
-                return -EBUSY;
+        for (gpc = 0, offset = 0; gpc < priv->gpc_nr; gpc++) {
+                for (tpc = 0; tpc < priv->tpc_nr[gpc]; tpc++) {
+                        u32 addr = TPC_UNIT(gpc, tpc, 0x0520);
+                        mmio_list(addr, 0x02180000 | offset, 0, 0);
+                        offset += 0x0324;
+                }
         }
-
-        return 0;
 }
 
 void
-nvc0_grctx_data(struct nvc0_grctx *info, u32 size, u32 align, u32 access)
+nvc0_grctx_generate_unkn(struct nvc0_graph_priv *priv)
 {
-        info->buffer[info->buffer_nr]  = info->addr;
-        info->buffer[info->buffer_nr] +=  (align - 1);
-        info->buffer[info->buffer_nr] &= ~(align - 1);
-        info->addr = info->buffer[info->buffer_nr++] + size;
-
-        info->data->size = size;
-        info->data->align = align;
-        info->data->access = access;
-        info->data++;
 }
 
 void
-nvc0_grctx_mmio(struct nvc0_grctx *info, u32 addr, u32 data, u32 shift, u32 buf)
+nvc0_grctx_generate_tpcid(struct nvc0_graph_priv *priv)
 {
-        struct nvc0_graph_priv *priv = info->priv;
-
-        info->mmio->addr = addr;
-        info->mmio->data = data;
-        info->mmio->shift = shift;
-        info->mmio->buffer = buf;
-        info->mmio++;
+        int gpc, tpc, id;
 
-        if (shift)
-                data |= info->buffer[buf] >> shift;
-        nv_wr32(priv, addr, data);
-}
-
-int
-nvc0_grctx_fini(struct nvc0_grctx *info)
-{
-        struct nvc0_graph_priv *priv = info->priv;
-        int i;
-
-        /* trigger a context unload by unsetting the "next channel valid" bit
-         * and faking a context switch interrupt
-         */
-        nv_mask(priv, 0x409b04, 0x80000000, 0x00000000);
-        nv_wr32(priv, 0x409000, 0x00000100);
-        if (!nv_wait(priv, 0x409b00, 0x80000000, 0x00000000)) {
-                nv_error(priv, "grctx template channel unload timeout\n");
-                return -EBUSY;
-        }
-
-        priv->data = kmalloc(priv->size, GFP_KERNEL);
-        if (priv->data) {
-                for (i = 0; i < priv->size; i += 4)
-                        priv->data[i / 4] = nv_ro32(info->chan, 0x80000 + i);
-        }
-
-        nouveau_gpuobj_ref(NULL, &info->chan);
-        return priv->data ? 0 : -ENOMEM;
-}
+        for (tpc = 0, id = 0; tpc < 4; tpc++) {
+                for (gpc = 0; gpc < priv->gpc_nr; gpc++) {
+                        if (tpc < priv->tpc_nr[gpc]) {
+                                nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x698), id);
+                                nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x4e8), id);
+                                nv_wr32(priv, GPC_UNIT(gpc, 0x0c10 + tpc * 4), id);
+                                nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x088), id);
+                                id++;
+                        }
 
-static void
-nvc0_grctx_generate_9097(struct nvc0_graph_priv *priv)
-{
-        u32 fermi = nvc0_graph_class(priv);
-        u32 mthd;
-
-        nv_mthd(priv, 0x9097, 0x0800, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x0840, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x0880, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x08c0, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x0900, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x0940, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x0980, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x09c0, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x0804, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x0844, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x0884, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x08c4, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x0904, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x0944, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x0984, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x09c4, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x0808, 0x00000400);
-        nv_mthd(priv, 0x9097, 0x0848, 0x00000400);
-        nv_mthd(priv, 0x9097, 0x0888, 0x00000400);
-        nv_mthd(priv, 0x9097, 0x08c8, 0x00000400);
-        nv_mthd(priv, 0x9097, 0x0908, 0x00000400);
-        nv_mthd(priv, 0x9097, 0x0948, 0x00000400);
-        nv_mthd(priv, 0x9097, 0x0988, 0x00000400);
-        nv_mthd(priv, 0x9097, 0x09c8, 0x00000400);
-        nv_mthd(priv, 0x9097, 0x080c, 0x00000300);
-        nv_mthd(priv, 0x9097, 0x084c, 0x00000300);
-        nv_mthd(priv, 0x9097, 0x088c, 0x00000300);
-        nv_mthd(priv, 0x9097, 0x08cc, 0x00000300);
-        nv_mthd(priv, 0x9097, 0x090c, 0x00000300);
-        nv_mthd(priv, 0x9097, 0x094c, 0x00000300);
-        nv_mthd(priv, 0x9097, 0x098c, 0x00000300);
-        nv_mthd(priv, 0x9097, 0x09cc, 0x00000300);
-        nv_mthd(priv, 0x9097, 0x0810, 0x000000cf);
-        nv_mthd(priv, 0x9097, 0x0850, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x0890, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x08d0, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x0910, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x0950, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x0990, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x09d0, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x0814, 0x00000040);
-        nv_mthd(priv, 0x9097, 0x0854, 0x00000040);
-        nv_mthd(priv, 0x9097, 0x0894, 0x00000040);
-        nv_mthd(priv, 0x9097, 0x08d4, 0x00000040);
-        nv_mthd(priv, 0x9097, 0x0914, 0x00000040);
-        nv_mthd(priv, 0x9097, 0x0954, 0x00000040);
-        nv_mthd(priv, 0x9097, 0x0994, 0x00000040);
-        nv_mthd(priv, 0x9097, 0x09d4, 0x00000040);
-        nv_mthd(priv, 0x9097, 0x0818, 0x00000001);
-        nv_mthd(priv, 0x9097, 0x0858, 0x00000001);
-        nv_mthd(priv, 0x9097, 0x0898, 0x00000001);
-        nv_mthd(priv, 0x9097, 0x08d8, 0x00000001);
-        nv_mthd(priv, 0x9097, 0x0918, 0x00000001);
-        nv_mthd(priv, 0x9097, 0x0958, 0x00000001);
-        nv_mthd(priv, 0x9097, 0x0998, 0x00000001);
-        nv_mthd(priv, 0x9097, 0x09d8, 0x00000001);
-        nv_mthd(priv, 0x9097, 0x081c, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x085c, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x089c, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x08dc, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x091c, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x095c, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x099c, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x09dc, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x0820, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x0860, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x08a0, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x08e0, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x0920, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x0960, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x09a0, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x09e0, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x2700, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x2720, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x2740, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x2760, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x2780, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x27a0, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x27c0, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x27e0, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x2704, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x2724, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x2744, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x2764, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x2784, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x27a4, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x27c4, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x27e4, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x2708, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x2728, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x2748, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x2768, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x2788, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x27a8, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x27c8, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x27e8, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x270c, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x272c, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x274c, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x276c, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x278c, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x27ac, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x27cc, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x27ec, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x2710, 0x00014000);
-        nv_mthd(priv, 0x9097, 0x2730, 0x00014000);
-        nv_mthd(priv, 0x9097, 0x2750, 0x00014000);
-        nv_mthd(priv, 0x9097, 0x2770, 0x00014000);
-        nv_mthd(priv, 0x9097, 0x2790, 0x00014000);
-        nv_mthd(priv, 0x9097, 0x27b0, 0x00014000);
-        nv_mthd(priv, 0x9097, 0x27d0, 0x00014000);
-        nv_mthd(priv, 0x9097, 0x27f0, 0x00014000);
-        nv_mthd(priv, 0x9097, 0x2714, 0x00000040);
-        nv_mthd(priv, 0x9097, 0x2734, 0x00000040);
-        nv_mthd(priv, 0x9097, 0x2754, 0x00000040);
-        nv_mthd(priv, 0x9097, 0x2774, 0x00000040);
-        nv_mthd(priv, 0x9097, 0x2794, 0x00000040);
-        nv_mthd(priv, 0x9097, 0x27b4, 0x00000040);
-        nv_mthd(priv, 0x9097, 0x27d4, 0x00000040);
-        nv_mthd(priv, 0x9097, 0x27f4, 0x00000040);
-        nv_mthd(priv, 0x9097, 0x1c00, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x1c10, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x1c20, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x1c30, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x1c40, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x1c50, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x1c60, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x1c70, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x1c80, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x1c90, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x1ca0, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x1cb0, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x1cc0, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x1cd0, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x1ce0, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x1cf0, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x1c04, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x1c14, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x1c24, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x1c34, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x1c44, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x1c54, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x1c64, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x1c74, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x1c84, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x1c94, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x1ca4, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x1cb4, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x1cc4, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x1cd4, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x1ce4, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x1cf4, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x1c08, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x1c18, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x1c28, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x1c38, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x1c48, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x1c58, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x1c68, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x1c78, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x1c88, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x1c98, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x1ca8, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x1cb8, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x1cc8, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x1cd8, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x1ce8, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x1cf8, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x1c0c, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x1c1c, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x1c2c, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x1c3c, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x1c4c, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x1c5c, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x1c6c, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x1c7c, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x1c8c, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x1c9c, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x1cac, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x1cbc, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x1ccc, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x1cdc, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x1cec, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x1cfc, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x1d00, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x1d10, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x1d20, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x1d30, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x1d40, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x1d50, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x1d60, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x1d70, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x1d80, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x1d90, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x1da0, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x1db0, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x1dc0, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x1dd0, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x1de0, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x1df0, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x1d04, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x1d14, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x1d24, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x1d34, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x1d44, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x1d54, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x1d64, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x1d74, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x1d84, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x1d94, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x1da4, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x1db4, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x1dc4, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x1dd4, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x1de4, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x1df4, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x1d08, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x1d18, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x1d28, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x1d38, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x1d48, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x1d58, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x1d68, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x1d78, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x1d88, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x1d98, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x1da8, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x1db8, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x1dc8, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x1dd8, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x1de8, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x1df8, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x1d0c, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x1d1c, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x1d2c, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x1d3c, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x1d4c, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x1d5c, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x1d6c, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x1d7c, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x1d8c, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x1d9c, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x1dac, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x1dbc, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x1dcc, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x1ddc, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x1dec, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x1dfc, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x1f00, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x1f08, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x1f10, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x1f18, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x1f20, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x1f28, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x1f30, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x1f38, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x1f40, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x1f48, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x1f50, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x1f58, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x1f60, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x1f68, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x1f70, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x1f78, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x1f04, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x1f0c, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x1f14, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x1f1c, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x1f24, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x1f2c, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x1f34, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x1f3c, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x1f44, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x1f4c, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x1f54, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x1f5c, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x1f64, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x1f6c, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x1f74, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x1f7c, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x1f80, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x1f88, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x1f90, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x1f98, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x1fa0, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x1fa8, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x1fb0, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x1fb8, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x1fc0, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x1fc8, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x1fd0, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x1fd8, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x1fe0, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x1fe8, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x1ff0, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x1ff8, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x1f84, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x1f8c, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x1f94, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x1f9c, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x1fa4, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x1fac, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x1fb4, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x1fbc, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x1fc4, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x1fcc, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x1fd4, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x1fdc, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x1fe4, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x1fec, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x1ff4, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x1ffc, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x2200, 0x00000022);
-        nv_mthd(priv, 0x9097, 0x2210, 0x00000022);
-        nv_mthd(priv, 0x9097, 0x2220, 0x00000022);
-        nv_mthd(priv, 0x9097, 0x2230, 0x00000022);
-        nv_mthd(priv, 0x9097, 0x2240, 0x00000022);
-        nv_mthd(priv, 0x9097, 0x2000, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x2040, 0x00000011);
-        nv_mthd(priv, 0x9097, 0x2080, 0x00000020);
-        nv_mthd(priv, 0x9097, 0x20c0, 0x00000030);
-        nv_mthd(priv, 0x9097, 0x2100, 0x00000040);
-        nv_mthd(priv, 0x9097, 0x2140, 0x00000051);
-        nv_mthd(priv, 0x9097, 0x200c, 0x00000001);
-        nv_mthd(priv, 0x9097, 0x204c, 0x00000001);
-        nv_mthd(priv, 0x9097, 0x208c, 0x00000001);
-        nv_mthd(priv, 0x9097, 0x20cc, 0x00000001);
-        nv_mthd(priv, 0x9097, 0x210c, 0x00000001);
-        nv_mthd(priv, 0x9097, 0x214c, 0x00000001);
-        nv_mthd(priv, 0x9097, 0x2010, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x2050, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x2090, 0x00000001);
-        nv_mthd(priv, 0x9097, 0x20d0, 0x00000002);
-        nv_mthd(priv, 0x9097, 0x2110, 0x00000003);
-        nv_mthd(priv, 0x9097, 0x2150, 0x00000004);
-        nv_mthd(priv, 0x9097, 0x0380, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x03a0, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x03c0, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x03e0, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x0384, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x03a4, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x03c4, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x03e4, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x0388, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x03a8, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x03c8, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x03e8, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x038c, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x03ac, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x03cc, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x03ec, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x0700, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x0710, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x0720, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x0730, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x0704, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x0714, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x0724, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x0734, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x0708, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x0718, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x0728, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x0738, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x2800, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x2804, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x2808, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x280c, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x2810, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x2814, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x2818, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x281c, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x2820, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x2824, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x2828, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x282c, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x2830, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x2834, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x2838, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x283c, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x2840, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x2844, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x2848, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x284c, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x2850, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x2854, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x2858, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x285c, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x2860, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x2864, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x2868, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x286c, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x2870, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x2874, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x2878, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x287c, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x2880, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x2884, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x2888, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x288c, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x2890, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x2894, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x2898, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x289c, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x28a0, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x28a4, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x28a8, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x28ac, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x28b0, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x28b4, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x28b8, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x28bc, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x28c0, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x28c4, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x28c8, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x28cc, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x28d0, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x28d4, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x28d8, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x28dc, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x28e0, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x28e4, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x28e8, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x28ec, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x28f0, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x28f4, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x28f8, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x28fc, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x2900, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x2904, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x2908, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x290c, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x2910, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x2914, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x2918, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x291c, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x2920, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x2924, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x2928, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x292c, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x2930, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x2934, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x2938, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x293c, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x2940, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x2944, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x2948, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x294c, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x2950, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x2954, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x2958, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x295c, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x2960, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x2964, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x2968, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x296c, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x2970, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x2974, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x2978, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x297c, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x2980, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x2984, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x2988, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x298c, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x2990, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x2994, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x2998, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x299c, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x29a0, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x29a4, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x29a8, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x29ac, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x29b0, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x29b4, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x29b8, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x29bc, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x29c0, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x29c4, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x29c8, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x29cc, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x29d0, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x29d4, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x29d8, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x29dc, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x29e0, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x29e4, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x29e8, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x29ec, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x29f0, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x29f4, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x29f8, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x29fc, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x0a00, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x0a20, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x0a40, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x0a60, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x0a80, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x0aa0, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x0ac0, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x0ae0, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x0b00, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x0b20, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x0b40, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x0b60, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x0b80, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x0ba0, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x0bc0, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x0be0, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x0a04, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x0a24, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x0a44, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x0a64, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x0a84, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x0aa4, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x0ac4, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x0ae4, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x0b04, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x0b24, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x0b44, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x0b64, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x0b84, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x0ba4, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x0bc4, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x0be4, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x0a08, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x0a28, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x0a48, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x0a68, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x0a88, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x0aa8, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x0ac8, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x0ae8, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x0b08, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x0b28, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x0b48, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x0b68, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x0b88, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x0ba8, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x0bc8, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x0be8, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x0a0c, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x0a2c, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x0a4c, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x0a6c, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x0a8c, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x0aac, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x0acc, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x0aec, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x0b0c, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x0b2c, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x0b4c, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x0b6c, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x0b8c, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x0bac, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x0bcc, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x0bec, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x0a10, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x0a30, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x0a50, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x0a70, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x0a90, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x0ab0, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x0ad0, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x0af0, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x0b10, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x0b30, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x0b50, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x0b70, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x0b90, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x0bb0, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x0bd0, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x0bf0, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x0a14, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x0a34, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x0a54, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x0a74, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x0a94, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x0ab4, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x0ad4, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x0af4, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x0b14, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x0b34, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x0b54, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x0b74, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x0b94, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x0bb4, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x0bd4, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x0bf4, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x0c00, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x0c10, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x0c20, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x0c30, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x0c40, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x0c50, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x0c60, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x0c70, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x0c80, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x0c90, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x0ca0, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x0cb0, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x0cc0, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x0cd0, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x0ce0, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x0cf0, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x0c04, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x0c14, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x0c24, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x0c34, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x0c44, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x0c54, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x0c64, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x0c74, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x0c84, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x0c94, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x0ca4, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x0cb4, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x0cc4, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x0cd4, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x0ce4, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x0cf4, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x0c08, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x0c18, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x0c28, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x0c38, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x0c48, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x0c58, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x0c68, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x0c78, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x0c88, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x0c98, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x0ca8, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x0cb8, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x0cc8, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x0cd8, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x0ce8, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x0cf8, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x0c0c, 0x3f800000);
-        nv_mthd(priv, 0x9097, 0x0c1c, 0x3f800000);
-        nv_mthd(priv, 0x9097, 0x0c2c, 0x3f800000);
-        nv_mthd(priv, 0x9097, 0x0c3c, 0x3f800000);
-        nv_mthd(priv, 0x9097, 0x0c4c, 0x3f800000);
-        nv_mthd(priv, 0x9097, 0x0c5c, 0x3f800000);
-        nv_mthd(priv, 0x9097, 0x0c6c, 0x3f800000);
-        nv_mthd(priv, 0x9097, 0x0c7c, 0x3f800000);
-        nv_mthd(priv, 0x9097, 0x0c8c, 0x3f800000);
-        nv_mthd(priv, 0x9097, 0x0c9c, 0x3f800000);
-        nv_mthd(priv, 0x9097, 0x0cac, 0x3f800000);
-        nv_mthd(priv, 0x9097, 0x0cbc, 0x3f800000);
-        nv_mthd(priv, 0x9097, 0x0ccc, 0x3f800000);
-        nv_mthd(priv, 0x9097, 0x0cdc, 0x3f800000);
-        nv_mthd(priv, 0x9097, 0x0cec, 0x3f800000);
-        nv_mthd(priv, 0x9097, 0x0cfc, 0x3f800000);
-        nv_mthd(priv, 0x9097, 0x0d00, 0xffff0000);
-        nv_mthd(priv, 0x9097, 0x0d08, 0xffff0000);
-        nv_mthd(priv, 0x9097, 0x0d10, 0xffff0000);
-        nv_mthd(priv, 0x9097, 0x0d18, 0xffff0000);
-        nv_mthd(priv, 0x9097, 0x0d20, 0xffff0000);
-        nv_mthd(priv, 0x9097, 0x0d28, 0xffff0000);
-        nv_mthd(priv, 0x9097, 0x0d30, 0xffff0000);
-        nv_mthd(priv, 0x9097, 0x0d38, 0xffff0000);
-        nv_mthd(priv, 0x9097, 0x0d04, 0xffff0000);
-        nv_mthd(priv, 0x9097, 0x0d0c, 0xffff0000);
-        nv_mthd(priv, 0x9097, 0x0d14, 0xffff0000);
-        nv_mthd(priv, 0x9097, 0x0d1c, 0xffff0000);
-        nv_mthd(priv, 0x9097, 0x0d24, 0xffff0000);
-        nv_mthd(priv, 0x9097, 0x0d2c, 0xffff0000);
-        nv_mthd(priv, 0x9097, 0x0d34, 0xffff0000);
-        nv_mthd(priv, 0x9097, 0x0d3c, 0xffff0000);
-        nv_mthd(priv, 0x9097, 0x0e00, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x0e10, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x0e20, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x0e30, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x0e40, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x0e50, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x0e60, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x0e70, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x0e80, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x0e90, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x0ea0, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x0eb0, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x0ec0, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x0ed0, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x0ee0, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x0ef0, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x0e04, 0xffff0000);
-        nv_mthd(priv, 0x9097, 0x0e14, 0xffff0000);
-        nv_mthd(priv, 0x9097, 0x0e24, 0xffff0000);
-        nv_mthd(priv, 0x9097, 0x0e34, 0xffff0000);
-        nv_mthd(priv, 0x9097, 0x0e44, 0xffff0000);
-        nv_mthd(priv, 0x9097, 0x0e54, 0xffff0000);
-        nv_mthd(priv, 0x9097, 0x0e64, 0xffff0000);
-        nv_mthd(priv, 0x9097, 0x0e74, 0xffff0000);
-        nv_mthd(priv, 0x9097, 0x0e84, 0xffff0000);
-        nv_mthd(priv, 0x9097, 0x0e94, 0xffff0000);
-        nv_mthd(priv, 0x9097, 0x0ea4, 0xffff0000);
-        nv_mthd(priv, 0x9097, 0x0eb4, 0xffff0000);
-        nv_mthd(priv, 0x9097, 0x0ec4, 0xffff0000);
-        nv_mthd(priv, 0x9097, 0x0ed4, 0xffff0000);
-        nv_mthd(priv, 0x9097, 0x0ee4, 0xffff0000);
-        nv_mthd(priv, 0x9097, 0x0ef4, 0xffff0000);
-        nv_mthd(priv, 0x9097, 0x0e08, 0xffff0000);
-        nv_mthd(priv, 0x9097, 0x0e18, 0xffff0000);
-        nv_mthd(priv, 0x9097, 0x0e28, 0xffff0000);
-        nv_mthd(priv, 0x9097, 0x0e38, 0xffff0000);
-        nv_mthd(priv, 0x9097, 0x0e48, 0xffff0000);
-        nv_mthd(priv, 0x9097, 0x0e58, 0xffff0000);
-        nv_mthd(priv, 0x9097, 0x0e68, 0xffff0000);
-        nv_mthd(priv, 0x9097, 0x0e78, 0xffff0000);
-        nv_mthd(priv, 0x9097, 0x0e88, 0xffff0000);
-        nv_mthd(priv, 0x9097, 0x0e98, 0xffff0000);
-        nv_mthd(priv, 0x9097, 0x0ea8, 0xffff0000);
-        nv_mthd(priv, 0x9097, 0x0eb8, 0xffff0000);
-        nv_mthd(priv, 0x9097, 0x0ec8, 0xffff0000);
-        nv_mthd(priv, 0x9097, 0x0ed8, 0xffff0000);
-        nv_mthd(priv, 0x9097, 0x0ee8, 0xffff0000);
-        nv_mthd(priv, 0x9097, 0x0ef8, 0xffff0000);
-        nv_mthd(priv, 0x9097, 0x0d40, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x0d48, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x0d50, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x0d58, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x0d44, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x0d4c, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x0d54, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x0d5c, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x1e00, 0x00000001);
-        nv_mthd(priv, 0x9097, 0x1e20, 0x00000001);
-        nv_mthd(priv, 0x9097, 0x1e40, 0x00000001);
-        nv_mthd(priv, 0x9097, 0x1e60, 0x00000001);
-        nv_mthd(priv, 0x9097, 0x1e80, 0x00000001);
-        nv_mthd(priv, 0x9097, 0x1ea0, 0x00000001);
-        nv_mthd(priv, 0x9097, 0x1ec0, 0x00000001);
-        nv_mthd(priv, 0x9097, 0x1ee0, 0x00000001);
-        nv_mthd(priv, 0x9097, 0x1e04, 0x00000001);
-        nv_mthd(priv, 0x9097, 0x1e24, 0x00000001);
-        nv_mthd(priv, 0x9097, 0x1e44, 0x00000001);
-        nv_mthd(priv, 0x9097, 0x1e64, 0x00000001);
-        nv_mthd(priv, 0x9097, 0x1e84, 0x00000001);
-        nv_mthd(priv, 0x9097, 0x1ea4, 0x00000001);
-        nv_mthd(priv, 0x9097, 0x1ec4, 0x00000001);
-        nv_mthd(priv, 0x9097, 0x1ee4, 0x00000001);
-        nv_mthd(priv, 0x9097, 0x1e08, 0x00000002);
-        nv_mthd(priv, 0x9097, 0x1e28, 0x00000002);
-        nv_mthd(priv, 0x9097, 0x1e48, 0x00000002);
-        nv_mthd(priv, 0x9097, 0x1e68, 0x00000002);
-        nv_mthd(priv, 0x9097, 0x1e88, 0x00000002);
-        nv_mthd(priv, 0x9097, 0x1ea8, 0x00000002);
-        nv_mthd(priv, 0x9097, 0x1ec8, 0x00000002);
-        nv_mthd(priv, 0x9097, 0x1ee8, 0x00000002);
-        nv_mthd(priv, 0x9097, 0x1e0c, 0x00000001);
-        nv_mthd(priv, 0x9097, 0x1e2c, 0x00000001);
-        nv_mthd(priv, 0x9097, 0x1e4c, 0x00000001);
-        nv_mthd(priv, 0x9097, 0x1e6c, 0x00000001);
-        nv_mthd(priv, 0x9097, 0x1e8c, 0x00000001);
-        nv_mthd(priv, 0x9097, 0x1eac, 0x00000001);
-        nv_mthd(priv, 0x9097, 0x1ecc, 0x00000001);
-        nv_mthd(priv, 0x9097, 0x1eec, 0x00000001);
-        nv_mthd(priv, 0x9097, 0x1e10, 0x00000001);
-        nv_mthd(priv, 0x9097, 0x1e30, 0x00000001);
-        nv_mthd(priv, 0x9097, 0x1e50, 0x00000001);
-        nv_mthd(priv, 0x9097, 0x1e70, 0x00000001);
-        nv_mthd(priv, 0x9097, 0x1e90, 0x00000001);
-        nv_mthd(priv, 0x9097, 0x1eb0, 0x00000001);
-        nv_mthd(priv, 0x9097, 0x1ed0, 0x00000001);
-        nv_mthd(priv, 0x9097, 0x1ef0, 0x00000001);
-        nv_mthd(priv, 0x9097, 0x1e14, 0x00000002);
-        nv_mthd(priv, 0x9097, 0x1e34, 0x00000002);
-        nv_mthd(priv, 0x9097, 0x1e54, 0x00000002);
-        nv_mthd(priv, 0x9097, 0x1e74, 0x00000002);
-        nv_mthd(priv, 0x9097, 0x1e94, 0x00000002);
-        nv_mthd(priv, 0x9097, 0x1eb4, 0x00000002);
-        nv_mthd(priv, 0x9097, 0x1ed4, 0x00000002);
-        nv_mthd(priv, 0x9097, 0x1ef4, 0x00000002);
-        nv_mthd(priv, 0x9097, 0x1e18, 0x00000001);
-        nv_mthd(priv, 0x9097, 0x1e38, 0x00000001);
-        nv_mthd(priv, 0x9097, 0x1e58, 0x00000001);
-        nv_mthd(priv, 0x9097, 0x1e78, 0x00000001);
-        nv_mthd(priv, 0x9097, 0x1e98, 0x00000001);
-        nv_mthd(priv, 0x9097, 0x1eb8, 0x00000001);
-        nv_mthd(priv, 0x9097, 0x1ed8, 0x00000001);
-        nv_mthd(priv, 0x9097, 0x1ef8, 0x00000001);
-        if (fermi == 0x9097) {
-                for (mthd = 0x3400; mthd <= 0x35fc; mthd += 4)
-                        nv_mthd(priv, 0x9097, mthd, 0x00000000);
+                        nv_wr32(priv, GPC_UNIT(gpc, 0x0c08), priv->tpc_nr[gpc]);
+                        nv_wr32(priv, GPC_UNIT(gpc, 0x0c8c), priv->tpc_nr[gpc]);
+                }
         }
-        nv_mthd(priv, 0x9097, 0x030c, 0x00000001);
-        nv_mthd(priv, 0x9097, 0x1944, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x1514, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x0d68, 0x0000ffff);
-        nv_mthd(priv, 0x9097, 0x121c, 0x0fac6881);
-        nv_mthd(priv, 0x9097, 0x0fac, 0x00000001);
-        nv_mthd(priv, 0x9097, 0x1538, 0x00000001);
-        nv_mthd(priv, 0x9097, 0x0fe0, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x0fe4, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x0fe8, 0x00000014);
-        nv_mthd(priv, 0x9097, 0x0fec, 0x00000040);
-        nv_mthd(priv, 0x9097, 0x0ff0, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x179c, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x1228, 0x00000400);
-        nv_mthd(priv, 0x9097, 0x122c, 0x00000300);
-        nv_mthd(priv, 0x9097, 0x1230, 0x00010001);
-        nv_mthd(priv, 0x9097, 0x07f8, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x15b4, 0x00000001);
-        nv_mthd(priv, 0x9097, 0x15cc, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x1534, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x0fb0, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x15d0, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x153c, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x16b4, 0x00000003);
-        nv_mthd(priv, 0x9097, 0x0fbc, 0x0000ffff);
-        nv_mthd(priv, 0x9097, 0x0fc0, 0x0000ffff);
-        nv_mthd(priv, 0x9097, 0x0fc4, 0x0000ffff);
-        nv_mthd(priv, 0x9097, 0x0fc8, 0x0000ffff);
-        nv_mthd(priv, 0x9097, 0x0df8, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x0dfc, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x1948, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x1970, 0x00000001);
-        nv_mthd(priv, 0x9097, 0x161c, 0x000009f0);
-        nv_mthd(priv, 0x9097, 0x0dcc, 0x00000010);
-        nv_mthd(priv, 0x9097, 0x163c, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x15e4, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x1160, 0x25e00040);
-        nv_mthd(priv, 0x9097, 0x1164, 0x25e00040);
-        nv_mthd(priv, 0x9097, 0x1168, 0x25e00040);
-        nv_mthd(priv, 0x9097, 0x116c, 0x25e00040);
-        nv_mthd(priv, 0x9097, 0x1170, 0x25e00040);
-        nv_mthd(priv, 0x9097, 0x1174, 0x25e00040);
-        nv_mthd(priv, 0x9097, 0x1178, 0x25e00040);
-        nv_mthd(priv, 0x9097, 0x117c, 0x25e00040);
-        nv_mthd(priv, 0x9097, 0x1180, 0x25e00040);
-        nv_mthd(priv, 0x9097, 0x1184, 0x25e00040);
-        nv_mthd(priv, 0x9097, 0x1188, 0x25e00040);
-        nv_mthd(priv, 0x9097, 0x118c, 0x25e00040);
-        nv_mthd(priv, 0x9097, 0x1190, 0x25e00040);
-        nv_mthd(priv, 0x9097, 0x1194, 0x25e00040);
-        nv_mthd(priv, 0x9097, 0x1198, 0x25e00040);
-        nv_mthd(priv, 0x9097, 0x119c, 0x25e00040);
-        nv_mthd(priv, 0x9097, 0x11a0, 0x25e00040);
-        nv_mthd(priv, 0x9097, 0x11a4, 0x25e00040);
-        nv_mthd(priv, 0x9097, 0x11a8, 0x25e00040);
-        nv_mthd(priv, 0x9097, 0x11ac, 0x25e00040);
-        nv_mthd(priv, 0x9097, 0x11b0, 0x25e00040);
-        nv_mthd(priv, 0x9097, 0x11b4, 0x25e00040);
-        nv_mthd(priv, 0x9097, 0x11b8, 0x25e00040);
-        nv_mthd(priv, 0x9097, 0x11bc, 0x25e00040);
-        nv_mthd(priv, 0x9097, 0x11c0, 0x25e00040);
-        nv_mthd(priv, 0x9097, 0x11c4, 0x25e00040);
-        nv_mthd(priv, 0x9097, 0x11c8, 0x25e00040);
-        nv_mthd(priv, 0x9097, 0x11cc, 0x25e00040);
-        nv_mthd(priv, 0x9097, 0x11d0, 0x25e00040);
-        nv_mthd(priv, 0x9097, 0x11d4, 0x25e00040);
-        nv_mthd(priv, 0x9097, 0x11d8, 0x25e00040);
-        nv_mthd(priv, 0x9097, 0x11dc, 0x25e00040);
-        nv_mthd(priv, 0x9097, 0x1880, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x1884, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x1888, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x188c, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x1890, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x1894, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x1898, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x189c, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x18a0, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x18a4, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x18a8, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x18ac, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x18b0, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x18b4, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x18b8, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x18bc, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x18c0, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x18c4, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x18c8, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x18cc, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x18d0, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x18d4, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x18d8, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x18dc, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x18e0, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x18e4, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x18e8, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x18ec, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x18f0, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x18f4, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x18f8, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x18fc, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x0f84, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x0f88, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x17c8, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x17cc, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x17d0, 0x000000ff);
-        nv_mthd(priv, 0x9097, 0x17d4, 0xffffffff);
-        nv_mthd(priv, 0x9097, 0x17d8, 0x00000002);
-        nv_mthd(priv, 0x9097, 0x17dc, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x15f4, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x15f8, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x1434, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x1438, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x0d74, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x0dec, 0x00000001);
-        nv_mthd(priv, 0x9097, 0x13a4, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x1318, 0x00000001);
-        nv_mthd(priv, 0x9097, 0x1644, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x0748, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x0de8, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x1648, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x12a4, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x1120, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x1124, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x1128, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x112c, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x1118, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x164c, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x1658, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x1910, 0x00000290);
-        nv_mthd(priv, 0x9097, 0x1518, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x165c, 0x00000001);
-        nv_mthd(priv, 0x9097, 0x1520, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x1604, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x1570, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x13b0, 0x3f800000);
-        nv_mthd(priv, 0x9097, 0x13b4, 0x3f800000);
-        nv_mthd(priv, 0x9097, 0x020c, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x1670, 0x30201000);
-        nv_mthd(priv, 0x9097, 0x1674, 0x70605040);
-        nv_mthd(priv, 0x9097, 0x1678, 0xb8a89888);
-        nv_mthd(priv, 0x9097, 0x167c, 0xf8e8d8c8);
-        nv_mthd(priv, 0x9097, 0x166c, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x1680, 0x00ffff00);
-        nv_mthd(priv, 0x9097, 0x12d0, 0x00000003);
-        nv_mthd(priv, 0x9097, 0x12d4, 0x00000002);
-        nv_mthd(priv, 0x9097, 0x1684, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x1688, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x0dac, 0x00001b02);
-        nv_mthd(priv, 0x9097, 0x0db0, 0x00001b02);
-        nv_mthd(priv, 0x9097, 0x0db4, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x168c, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x15bc, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x156c, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x187c, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x1110, 0x00000001);
-        nv_mthd(priv, 0x9097, 0x0dc0, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x0dc4, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x0dc8, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x1234, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x1690, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x12ac, 0x00000001);
-        nv_mthd(priv, 0x9097, 0x02c4, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x0790, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x0794, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x0798, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x079c, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x07a0, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x077c, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x1000, 0x00000010);
-        nv_mthd(priv, 0x9097, 0x10fc, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x1290, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x0218, 0x00000010);
-        nv_mthd(priv, 0x9097, 0x12d8, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x12dc, 0x00000010);
-        nv_mthd(priv, 0x9097, 0x0d94, 0x00000001);
-        nv_mthd(priv, 0x9097, 0x155c, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x1560, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x1564, 0x00001fff);
-        nv_mthd(priv, 0x9097, 0x1574, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x1578, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x157c, 0x003fffff);
-        nv_mthd(priv, 0x9097, 0x1354, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x1664, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x1610, 0x00000012);
-        nv_mthd(priv, 0x9097, 0x1608, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x160c, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x162c, 0x00000003);
-        nv_mthd(priv, 0x9097, 0x0210, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x0320, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x0324, 0x3f800000);
-        nv_mthd(priv, 0x9097, 0x0328, 0x3f800000);
-        nv_mthd(priv, 0x9097, 0x032c, 0x3f800000);
-        nv_mthd(priv, 0x9097, 0x0330, 0x3f800000);
-        nv_mthd(priv, 0x9097, 0x0334, 0x3f800000);
-        nv_mthd(priv, 0x9097, 0x0338, 0x3f800000);
-        nv_mthd(priv, 0x9097, 0x0750, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x0760, 0x39291909);
-        nv_mthd(priv, 0x9097, 0x0764, 0x79695949);
-        nv_mthd(priv, 0x9097, 0x0768, 0xb9a99989);
-        nv_mthd(priv, 0x9097, 0x076c, 0xf9e9d9c9);
-        nv_mthd(priv, 0x9097, 0x0770, 0x30201000);
-        nv_mthd(priv, 0x9097, 0x0774, 0x70605040);
-        nv_mthd(priv, 0x9097, 0x0778, 0x00009080);
-        nv_mthd(priv, 0x9097, 0x0780, 0x39291909);
-        nv_mthd(priv, 0x9097, 0x0784, 0x79695949);
-        nv_mthd(priv, 0x9097, 0x0788, 0xb9a99989);
-        nv_mthd(priv, 0x9097, 0x078c, 0xf9e9d9c9);
-        nv_mthd(priv, 0x9097, 0x07d0, 0x30201000);
-        nv_mthd(priv, 0x9097, 0x07d4, 0x70605040);
-        nv_mthd(priv, 0x9097, 0x07d8, 0x00009080);
-        nv_mthd(priv, 0x9097, 0x037c, 0x00000001);
-        nv_mthd(priv, 0x9097, 0x0740, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x0744, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x2600, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x1918, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x191c, 0x00000900);
-        nv_mthd(priv, 0x9097, 0x1920, 0x00000405);
-        nv_mthd(priv, 0x9097, 0x1308, 0x00000001);
-        nv_mthd(priv, 0x9097, 0x1924, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x13ac, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x192c, 0x00000001);
-        nv_mthd(priv, 0x9097, 0x193c, 0x00002c1c);
-        nv_mthd(priv, 0x9097, 0x0d7c, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x0f8c, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x02c0, 0x00000001);
-        nv_mthd(priv, 0x9097, 0x1510, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x1940, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x0ff4, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x0ff8, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x194c, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x1950, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x1968, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x1590, 0x0000003f);
-        nv_mthd(priv, 0x9097, 0x07e8, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x07ec, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x07f0, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x07f4, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x196c, 0x00000011);
-        nv_mthd(priv, 0x9097, 0x197c, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x0fcc, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x0fd0, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x02d8, 0x00000040);
-        nv_mthd(priv, 0x9097, 0x1980, 0x00000080);
-        nv_mthd(priv, 0x9097, 0x1504, 0x00000080);
-        nv_mthd(priv, 0x9097, 0x1984, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x0300, 0x00000001);
-        nv_mthd(priv, 0x9097, 0x13a8, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x12ec, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x1310, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x1314, 0x00000001);
-        nv_mthd(priv, 0x9097, 0x1380, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x1384, 0x00000001);
-        nv_mthd(priv, 0x9097, 0x1388, 0x00000001);
-        nv_mthd(priv, 0x9097, 0x138c, 0x00000001);
-        nv_mthd(priv, 0x9097, 0x1390, 0x00000001);
-        nv_mthd(priv, 0x9097, 0x1394, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x139c, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x1398, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x1594, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x1598, 0x00000001);
-        nv_mthd(priv, 0x9097, 0x159c, 0x00000001);
-        nv_mthd(priv, 0x9097, 0x15a0, 0x00000001);
-        nv_mthd(priv, 0x9097, 0x15a4, 0x00000001);
-        nv_mthd(priv, 0x9097, 0x0f54, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x0f58, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x0f5c, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x19bc, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x0f9c, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x0fa0, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x12cc, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x12e8, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x130c, 0x00000001);
-        nv_mthd(priv, 0x9097, 0x1360, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x1364, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x1368, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x136c, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x1370, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x1374, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x1378, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x137c, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x133c, 0x00000001);
-        nv_mthd(priv, 0x9097, 0x1340, 0x00000001);
-        nv_mthd(priv, 0x9097, 0x1344, 0x00000002);
-        nv_mthd(priv, 0x9097, 0x1348, 0x00000001);
-        nv_mthd(priv, 0x9097, 0x134c, 0x00000001);
-        nv_mthd(priv, 0x9097, 0x1350, 0x00000002);
-        nv_mthd(priv, 0x9097, 0x1358, 0x00000001);
-        nv_mthd(priv, 0x9097, 0x12e4, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x131c, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x1320, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x1324, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x1328, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x19c0, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x1140, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x19c4, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x19c8, 0x00001500);
-        nv_mthd(priv, 0x9097, 0x135c, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x0f90, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x19e0, 0x00000001);
-        nv_mthd(priv, 0x9097, 0x19e4, 0x00000001);
-        nv_mthd(priv, 0x9097, 0x19e8, 0x00000001);
-        nv_mthd(priv, 0x9097, 0x19ec, 0x00000001);
-        nv_mthd(priv, 0x9097, 0x19f0, 0x00000001);
-        nv_mthd(priv, 0x9097, 0x19f4, 0x00000001);
-        nv_mthd(priv, 0x9097, 0x19f8, 0x00000001);
-        nv_mthd(priv, 0x9097, 0x19fc, 0x00000001);
-        nv_mthd(priv, 0x9097, 0x19cc, 0x00000001);
-        nv_mthd(priv, 0x9097, 0x15b8, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x1a00, 0x00001111);
-        nv_mthd(priv, 0x9097, 0x1a04, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x1a08, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x1a0c, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x1a10, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x1a14, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x1a18, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x1a1c, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x0d6c, 0xffff0000);
-        nv_mthd(priv, 0x9097, 0x0d70, 0xffff0000);
-        nv_mthd(priv, 0x9097, 0x10f8, 0x00001010);
-        nv_mthd(priv, 0x9097, 0x0d80, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x0d84, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x0d88, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x0d8c, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x0d90, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x0da0, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x1508, 0x80000000);
-        nv_mthd(priv, 0x9097, 0x150c, 0x40000000);
-        nv_mthd(priv, 0x9097, 0x1668, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x0318, 0x00000008);
-        nv_mthd(priv, 0x9097, 0x031c, 0x00000008);
-        nv_mthd(priv, 0x9097, 0x0d9c, 0x00000001);
-        nv_mthd(priv, 0x9097, 0x07dc, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x074c, 0x00000055);
-        nv_mthd(priv, 0x9097, 0x1420, 0x00000003);
-        nv_mthd(priv, 0x9097, 0x17bc, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x17c0, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x17c4, 0x00000001);
-        nv_mthd(priv, 0x9097, 0x1008, 0x00000008);
-        nv_mthd(priv, 0x9097, 0x100c, 0x00000040);
-        nv_mthd(priv, 0x9097, 0x1010, 0x0000012c);
-        nv_mthd(priv, 0x9097, 0x0d60, 0x00000040);
-        nv_mthd(priv, 0x9097, 0x075c, 0x00000003);
-        nv_mthd(priv, 0x9097, 0x1018, 0x00000020);
-        nv_mthd(priv, 0x9097, 0x101c, 0x00000001);
-        nv_mthd(priv, 0x9097, 0x1020, 0x00000020);
-        nv_mthd(priv, 0x9097, 0x1024, 0x00000001);
-        nv_mthd(priv, 0x9097, 0x1444, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x1448, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x144c, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x0360, 0x20164010);
-        nv_mthd(priv, 0x9097, 0x0364, 0x00000020);
-        nv_mthd(priv, 0x9097, 0x0368, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x0de4, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x0204, 0x00000006);
-        nv_mthd(priv, 0x9097, 0x0208, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x02cc, 0x003fffff);
-        nv_mthd(priv, 0x9097, 0x02d0, 0x00000c48);
-        nv_mthd(priv, 0x9097, 0x1220, 0x00000005);
-        nv_mthd(priv, 0x9097, 0x0fdc, 0x00000000);
-        nv_mthd(priv, 0x9097, 0x0f98, 0x00300008);
-        nv_mthd(priv, 0x9097, 0x1284, 0x04000080);
-        nv_mthd(priv, 0x9097, 0x1450, 0x00300008);
-        nv_mthd(priv, 0x9097, 0x1454, 0x04000080);
-        nv_mthd(priv, 0x9097, 0x0214, 0x00000000);
-        /* in trace, right after 0x90c0, not here */
-        nv_mthd(priv, 0x9097, 0x3410, 0x80002006);
 }
 
-static void
-nvc0_grctx_generate_9197(struct nvc0_graph_priv *priv)
+void
+nvc0_grctx_generate_r406028(struct nvc0_graph_priv *priv)
 {
-        u32 fermi = nvc0_graph_class(priv);
-        u32 mthd;
-
-        if (fermi == 0x9197) {
-                for (mthd = 0x3400; mthd <= 0x35fc; mthd += 4)
-                        nv_mthd(priv, 0x9197, mthd, 0x00000000);
+        u32 tmp[GPC_MAX / 8] = {}, i = 0;
+        for (i = 0; i < priv->gpc_nr; i++)
+                tmp[i / 8] |= priv->tpc_nr[i] << ((i % 8) * 4);
+        for (i = 0; i < 4; i++) {
+                nv_wr32(priv, 0x406028 + (i * 4), tmp[i]);
+                nv_wr32(priv, 0x405870 + (i * 4), tmp[i]);
         }
-        nv_mthd(priv, 0x9197, 0x02e4, 0x0000b001);
 }
 
-static void
-nvc0_grctx_generate_9297(struct nvc0_graph_priv *priv)
+void
+nvc0_grctx_generate_r4060a8(struct nvc0_graph_priv *priv)
 {
-        u32 fermi = nvc0_graph_class(priv);
-        u32 mthd;
-
-        if (fermi == 0x9297) {
-                for (mthd = 0x3400; mthd <= 0x35fc; mthd += 4)
-                        nv_mthd(priv, 0x9297, mthd, 0x00000000);
+        u8  tpcnr[GPC_MAX], data[TPC_MAX];
+        int gpc, tpc, i;
+
+        memcpy(tpcnr, priv->tpc_nr, sizeof(priv->tpc_nr));
+        memset(data, 0x1f, sizeof(data));
+
+        gpc = -1;
+        for (tpc = 0; tpc < priv->tpc_total; tpc++) {
+                do {
+                        gpc = (gpc + 1) % priv->gpc_nr;
+                } while (!tpcnr[gpc]);
+                tpcnr[gpc]--;
+                data[tpc] = gpc;
         }
-        nv_mthd(priv, 0x9297, 0x036c, 0x00000000);
-        nv_mthd(priv, 0x9297, 0x0370, 0x00000000);
-        nv_mthd(priv, 0x9297, 0x07a4, 0x00000000);
-        nv_mthd(priv, 0x9297, 0x07a8, 0x00000000);
-        nv_mthd(priv, 0x9297, 0x0374, 0x00000000);
-        nv_mthd(priv, 0x9297, 0x0378, 0x00000020);
-}
 
-static void
-nvc0_grctx_generate_902d(struct nvc0_graph_priv *priv)
-{
-        nv_mthd(priv, 0x902d, 0x0200, 0x000000cf);
-        nv_mthd(priv, 0x902d, 0x0204, 0x00000001);
-        nv_mthd(priv, 0x902d, 0x0208, 0x00000020);
-        nv_mthd(priv, 0x902d, 0x020c, 0x00000001);
-        nv_mthd(priv, 0x902d, 0x0210, 0x00000000);
-        nv_mthd(priv, 0x902d, 0x0214, 0x00000080);
-        nv_mthd(priv, 0x902d, 0x0218, 0x00000100);
-        nv_mthd(priv, 0x902d, 0x021c, 0x00000100);
-        nv_mthd(priv, 0x902d, 0x0220, 0x00000000);
-        nv_mthd(priv, 0x902d, 0x0224, 0x00000000);
-        nv_mthd(priv, 0x902d, 0x0230, 0x000000cf);
-        nv_mthd(priv, 0x902d, 0x0234, 0x00000001);
-        nv_mthd(priv, 0x902d, 0x0238, 0x00000020);
-        nv_mthd(priv, 0x902d, 0x023c, 0x00000001);
-        nv_mthd(priv, 0x902d, 0x0244, 0x00000080);
-        nv_mthd(priv, 0x902d, 0x0248, 0x00000100);
-        nv_mthd(priv, 0x902d, 0x024c, 0x00000100);
-}
-
-static void
-nvc0_grctx_generate_9039(struct nvc0_graph_priv *priv)
-{
-        nv_mthd(priv, 0x9039, 0x030c, 0x00000000);
-        nv_mthd(priv, 0x9039, 0x0310, 0x00000000);
-        nv_mthd(priv, 0x9039, 0x0314, 0x00000000);
-        nv_mthd(priv, 0x9039, 0x0320, 0x00000000);
-        nv_mthd(priv, 0x9039, 0x0238, 0x00000000);
-        nv_mthd(priv, 0x9039, 0x023c, 0x00000000);
-        nv_mthd(priv, 0x9039, 0x0318, 0x00000000);
-        nv_mthd(priv, 0x9039, 0x031c, 0x00000000);
+        for (i = 0; i < 4; i++)
+                nv_wr32(priv, 0x4060a8 + (i * 4), ((u32 *)data)[i]);
 }
 
-static void
-nvc0_grctx_generate_90c0(struct nvc0_graph_priv *priv)
+void
+nvc0_grctx_generate_r418bb8(struct nvc0_graph_priv *priv)
 {
-        int i;
-
-        for (i = 0; nv_device(priv)->chipset >= 0xd0 && i < 4; i++) {
-                nv_mthd(priv, 0x90c0, 0x2700 + (i * 0x40), 0x00000000);
-                nv_mthd(priv, 0x90c0, 0x2720 + (i * 0x40), 0x00000000);
-                nv_mthd(priv, 0x90c0, 0x2704 + (i * 0x40), 0x00000000);
-                nv_mthd(priv, 0x90c0, 0x2724 + (i * 0x40), 0x00000000);
-                nv_mthd(priv, 0x90c0, 0x2708 + (i * 0x40), 0x00000000);
-                nv_mthd(priv, 0x90c0, 0x2728 + (i * 0x40), 0x00000000);
+        u32 data[6] = {}, data2[2] = {};
+        u8  tpcnr[GPC_MAX];
+        u8  shift, ntpcv;
+        int gpc, tpc, i;
+
+        /* calculate first set of magics */
+        memcpy(tpcnr, priv->tpc_nr, sizeof(priv->tpc_nr));
+
+        gpc = -1;
+        for (tpc = 0; tpc < priv->tpc_total; tpc++) {
+                do {
+                        gpc = (gpc + 1) % priv->gpc_nr;
+                } while (!tpcnr[gpc]);
+                tpcnr[gpc]--;
+
+                data[tpc / 6] |= gpc << ((tpc % 6) * 5);
         }
-        nv_mthd(priv, 0x90c0, 0x270c, 0x00000000);
-        nv_mthd(priv, 0x90c0, 0x272c, 0x00000000);
-        nv_mthd(priv, 0x90c0, 0x274c, 0x00000000);
-        nv_mthd(priv, 0x90c0, 0x276c, 0x00000000);
-        nv_mthd(priv, 0x90c0, 0x278c, 0x00000000);
-        nv_mthd(priv, 0x90c0, 0x27ac, 0x00000000);
-        nv_mthd(priv, 0x90c0, 0x27cc, 0x00000000);
-        nv_mthd(priv, 0x90c0, 0x27ec, 0x00000000);
-        for (i = 0; nv_device(priv)->chipset >= 0xd0 && i < 4; i++) {
-                nv_mthd(priv, 0x90c0, 0x2710 + (i * 0x40), 0x00014000);
-                nv_mthd(priv, 0x90c0, 0x2730 + (i * 0x40), 0x00014000);
-                nv_mthd(priv, 0x90c0, 0x2714 + (i * 0x40), 0x00000040);
-                nv_mthd(priv, 0x90c0, 0x2734 + (i * 0x40), 0x00000040);
-        }
-        nv_mthd(priv, 0x90c0, 0x030c, 0x00000001);
-        nv_mthd(priv, 0x90c0, 0x1944, 0x00000000);
-        nv_mthd(priv, 0x90c0, 0x0758, 0x00000100);
-        nv_mthd(priv, 0x90c0, 0x02c4, 0x00000000);
-        nv_mthd(priv, 0x90c0, 0x0790, 0x00000000);
-        nv_mthd(priv, 0x90c0, 0x0794, 0x00000000);
-        nv_mthd(priv, 0x90c0, 0x0798, 0x00000000);
-        nv_mthd(priv, 0x90c0, 0x079c, 0x00000000);
-        nv_mthd(priv, 0x90c0, 0x07a0, 0x00000000);
-        nv_mthd(priv, 0x90c0, 0x077c, 0x00000000);
-        nv_mthd(priv, 0x90c0, 0x0204, 0x00000000);
-        nv_mthd(priv, 0x90c0, 0x0208, 0x00000000);
-        nv_mthd(priv, 0x90c0, 0x020c, 0x00000000);
-        nv_mthd(priv, 0x90c0, 0x0214, 0x00000000);
-        nv_mthd(priv, 0x90c0, 0x024c, 0x00000000);
-        nv_mthd(priv, 0x90c0, 0x0d94, 0x00000001);
-        nv_mthd(priv, 0x90c0, 0x1608, 0x00000000);
-        nv_mthd(priv, 0x90c0, 0x160c, 0x00000000);
-        nv_mthd(priv, 0x90c0, 0x1664, 0x00000000);
-}
 
-static void
-nvc0_grctx_generate_dispatch(struct nvc0_graph_priv *priv)
-{
-        int i;
+        for (; tpc < 32; tpc++)
+                data[tpc / 6] |= 7 << ((tpc % 6) * 5);
 
-        nv_wr32(priv, 0x404004, 0x00000000);
-        nv_wr32(priv, 0x404008, 0x00000000);
-        nv_wr32(priv, 0x40400c, 0x00000000);
-        nv_wr32(priv, 0x404010, 0x00000000);
-        nv_wr32(priv, 0x404014, 0x00000000);
-        nv_wr32(priv, 0x404018, 0x00000000);
-        nv_wr32(priv, 0x40401c, 0x00000000);
-        nv_wr32(priv, 0x404020, 0x00000000);
-        nv_wr32(priv, 0x404024, 0x00000000);
-        nv_wr32(priv, 0x404028, 0x00000000);
-        nv_wr32(priv, 0x40402c, 0x00000000);
-        nv_wr32(priv, 0x404044, 0x00000000);
-        nv_wr32(priv, 0x404094, 0x00000000);
-        nv_wr32(priv, 0x404098, 0x00000000);
-        nv_wr32(priv, 0x40409c, 0x00000000);
-        nv_wr32(priv, 0x4040a0, 0x00000000);
-        nv_wr32(priv, 0x4040a4, 0x00000000);
-        nv_wr32(priv, 0x4040a8, 0x00000000);
-        nv_wr32(priv, 0x4040ac, 0x00000000);
-        nv_wr32(priv, 0x4040b0, 0x00000000);
-        nv_wr32(priv, 0x4040b4, 0x00000000);
-        nv_wr32(priv, 0x4040b8, 0x00000000);
-        nv_wr32(priv, 0x4040bc, 0x00000000);
-        nv_wr32(priv, 0x4040c0, 0x00000000);
-        nv_wr32(priv, 0x4040c4, 0x00000000);
-        nv_wr32(priv, 0x4040c8, 0xf0000087);
-        nv_wr32(priv, 0x4040d4, 0x00000000);
-        nv_wr32(priv, 0x4040d8, 0x00000000);
-        nv_wr32(priv, 0x4040dc, 0x00000000);
-        nv_wr32(priv, 0x4040e0, 0x00000000);
-        nv_wr32(priv, 0x4040e4, 0x00000000);
-        nv_wr32(priv, 0x4040e8, 0x00001000);
-        nv_wr32(priv, 0x4040f8, 0x00000000);
-        nv_wr32(priv, 0x404130, 0x00000000);
-        nv_wr32(priv, 0x404134, 0x00000000);
-        nv_wr32(priv, 0x404138, 0x20000040);
-        nv_wr32(priv, 0x404150, 0x0000002e);
-        nv_wr32(priv, 0x404154, 0x00000400);
-        nv_wr32(priv, 0x404158, 0x00000200);
-        nv_wr32(priv, 0x404164, 0x00000055);
-        nv_wr32(priv, 0x404168, 0x00000000);
-        nv_wr32(priv, 0x404174, 0x00000000);
-        nv_wr32(priv, 0x404178, 0x00000000);
-        nv_wr32(priv, 0x40417c, 0x00000000);
-        for (i = 0; i < 8; i++)
-                nv_wr32(priv, 0x404200 + (i * 4), 0x00000000); /* subc */
-}
-
-static void
-nvc0_grctx_generate_macro(struct nvc0_graph_priv *priv)
-{
-        nv_wr32(priv, 0x404404, 0x00000000);
-        nv_wr32(priv, 0x404408, 0x00000000);
-        nv_wr32(priv, 0x40440c, 0x00000000);
-        nv_wr32(priv, 0x404410, 0x00000000);
-        nv_wr32(priv, 0x404414, 0x00000000);
-        nv_wr32(priv, 0x404418, 0x00000000);
-        nv_wr32(priv, 0x40441c, 0x00000000);
-        nv_wr32(priv, 0x404420, 0x00000000);
-        nv_wr32(priv, 0x404424, 0x00000000);
-        nv_wr32(priv, 0x404428, 0x00000000);
-        nv_wr32(priv, 0x40442c, 0x00000000);
-        nv_wr32(priv, 0x404430, 0x00000000);
-        nv_wr32(priv, 0x404434, 0x00000000);
-        nv_wr32(priv, 0x404438, 0x00000000);
-        nv_wr32(priv, 0x404460, 0x00000000);
-        nv_wr32(priv, 0x404464, 0x00000000);
-        nv_wr32(priv, 0x404468, 0x00ffffff);
-        nv_wr32(priv, 0x40446c, 0x00000000);
-        nv_wr32(priv, 0x404480, 0x00000001);
-        nv_wr32(priv, 0x404498, 0x00000001);
-}
-
-static void
-nvc0_grctx_generate_m2mf(struct nvc0_graph_priv *priv)
-{
-        nv_wr32(priv, 0x404604, 0x00000015);
-        nv_wr32(priv, 0x404608, 0x00000000);
-        nv_wr32(priv, 0x40460c, 0x00002e00);
-        nv_wr32(priv, 0x404610, 0x00000100);
-        nv_wr32(priv, 0x404618, 0x00000000);
-        nv_wr32(priv, 0x40461c, 0x00000000);
-        nv_wr32(priv, 0x404620, 0x00000000);
-        nv_wr32(priv, 0x404624, 0x00000000);
-        nv_wr32(priv, 0x404628, 0x00000000);
-        nv_wr32(priv, 0x40462c, 0x00000000);
-        nv_wr32(priv, 0x404630, 0x00000000);
-        nv_wr32(priv, 0x404634, 0x00000000);
-        nv_wr32(priv, 0x404638, 0x00000004);
-        nv_wr32(priv, 0x40463c, 0x00000000);
-        nv_wr32(priv, 0x404640, 0x00000000);
-        nv_wr32(priv, 0x404644, 0x00000000);
-        nv_wr32(priv, 0x404648, 0x00000000);
-        nv_wr32(priv, 0x40464c, 0x00000000);
-        nv_wr32(priv, 0x404650, 0x00000000);
-        nv_wr32(priv, 0x404654, 0x00000000);
-        nv_wr32(priv, 0x404658, 0x00000000);
-        nv_wr32(priv, 0x40465c, 0x007f0100);
-        nv_wr32(priv, 0x404660, 0x00000000);
-        nv_wr32(priv, 0x404664, 0x00000000);
-        nv_wr32(priv, 0x404668, 0x00000000);
-        nv_wr32(priv, 0x40466c, 0x00000000);
-        nv_wr32(priv, 0x404670, 0x00000000);
-        nv_wr32(priv, 0x404674, 0x00000000);
-        nv_wr32(priv, 0x404678, 0x00000000);
-        nv_wr32(priv, 0x40467c, 0x00000002);
-        nv_wr32(priv, 0x404680, 0x00000000);
-        nv_wr32(priv, 0x404684, 0x00000000);
-        nv_wr32(priv, 0x404688, 0x00000000);
-        nv_wr32(priv, 0x40468c, 0x00000000);
-        nv_wr32(priv, 0x404690, 0x00000000);
-        nv_wr32(priv, 0x404694, 0x00000000);
-        nv_wr32(priv, 0x404698, 0x00000000);
-        nv_wr32(priv, 0x40469c, 0x00000000);
-        nv_wr32(priv, 0x4046a0, 0x007f0080);
-        nv_wr32(priv, 0x4046a4, 0x00000000);
-        nv_wr32(priv, 0x4046a8, 0x00000000);
-        nv_wr32(priv, 0x4046ac, 0x00000000);
-        nv_wr32(priv, 0x4046b0, 0x00000000);
-        nv_wr32(priv, 0x4046b4, 0x00000000);
-        nv_wr32(priv, 0x4046b8, 0x00000000);
-        nv_wr32(priv, 0x4046bc, 0x00000000);
-        nv_wr32(priv, 0x4046c0, 0x00000000);
-        nv_wr32(priv, 0x4046c4, 0x00000000);
-        nv_wr32(priv, 0x4046c8, 0x00000000);
-        nv_wr32(priv, 0x4046cc, 0x00000000);
-        nv_wr32(priv, 0x4046d0, 0x00000000);
-        nv_wr32(priv, 0x4046d4, 0x00000000);
-        nv_wr32(priv, 0x4046d8, 0x00000000);
-        nv_wr32(priv, 0x4046dc, 0x00000000);
-        nv_wr32(priv, 0x4046e0, 0x00000000);
-        nv_wr32(priv, 0x4046e4, 0x00000000);
-        nv_wr32(priv, 0x4046e8, 0x00000000);
-        nv_wr32(priv, 0x4046f0, 0x00000000);
-        nv_wr32(priv, 0x4046f4, 0x00000000);
-}
+        /* and the second... */
+        shift = 0;
+        ntpcv = priv->tpc_total;
+        while (!(ntpcv & (1 << 4))) {
+                ntpcv <<= 1;
+                shift++;
+        }
 
-static void
-nvc0_grctx_generate_unk47xx(struct nvc0_graph_priv *priv)
-{
-        nv_wr32(priv, 0x404700, 0x00000000);
-        nv_wr32(priv, 0x404704, 0x00000000);
-        nv_wr32(priv, 0x404708, 0x00000000);
-        nv_wr32(priv, 0x40470c, 0x00000000);
-        nv_wr32(priv, 0x404710, 0x00000000);
-        nv_wr32(priv, 0x404714, 0x00000000);
-        nv_wr32(priv, 0x404718, 0x00000000);
-        nv_wr32(priv, 0x40471c, 0x00000000);
-        nv_wr32(priv, 0x404720, 0x00000000);
-        nv_wr32(priv, 0x404724, 0x00000000);
-        nv_wr32(priv, 0x404728, 0x00000000);
-        nv_wr32(priv, 0x40472c, 0x00000000);
-        nv_wr32(priv, 0x404730, 0x00000000);
-        nv_wr32(priv, 0x404734, 0x00000100);
-        nv_wr32(priv, 0x404738, 0x00000000);
-        nv_wr32(priv, 0x40473c, 0x00000000);
-        nv_wr32(priv, 0x404740, 0x00000000);
-        nv_wr32(priv, 0x404744, 0x00000000);
-        nv_wr32(priv, 0x404748, 0x00000000);
-        nv_wr32(priv, 0x40474c, 0x00000000);
-        nv_wr32(priv, 0x404750, 0x00000000);
-        nv_wr32(priv, 0x404754, 0x00000000);
-}
+        data2[0]  = (ntpcv << 16);
+        data2[0] |= (shift << 21);
+        data2[0] |= (((1 << (0 + 5)) % ntpcv) << 24);
+        for (i = 1; i < 7; i++)
+                data2[1] |= ((1 << (i + 5)) % ntpcv) << ((i - 1) * 5);
 
-static void
-nvc0_grctx_generate_shaders(struct nvc0_graph_priv *priv)
-{
+        /* GPC_BROADCAST */
+        nv_wr32(priv, 0x418bb8, (priv->tpc_total << 8) |
+                                 priv->magic_not_rop_nr);
+        for (i = 0; i < 6; i++)
+                nv_wr32(priv, 0x418b08 + (i * 4), data[i]);
 
-        if (nv_device(priv)->chipset >= 0xd0) {
-                nv_wr32(priv, 0x405800, 0x0f8000bf);
-                nv_wr32(priv, 0x405830, 0x02180218);
-                nv_wr32(priv, 0x405834, 0x08000000);
-        } else
-        if (nv_device(priv)->chipset == 0xc1) {
-                nv_wr32(priv, 0x405800, 0x0f8000bf);
-                nv_wr32(priv, 0x405830, 0x02180218);
-                nv_wr32(priv, 0x405834, 0x00000000);
-        } else {
-                nv_wr32(priv, 0x405800, 0x078000bf);
-                nv_wr32(priv, 0x405830, 0x02180000);
-                nv_wr32(priv, 0x405834, 0x00000000);
-        }
-        nv_wr32(priv, 0x405838, 0x00000000);
-        nv_wr32(priv, 0x405854, 0x00000000);
-        nv_wr32(priv, 0x405870, 0x00000001);
-        nv_wr32(priv, 0x405874, 0x00000001);
-        nv_wr32(priv, 0x405878, 0x00000001);
-        nv_wr32(priv, 0x40587c, 0x00000001);
-        nv_wr32(priv, 0x405a00, 0x00000000);
-        nv_wr32(priv, 0x405a04, 0x00000000);
-        nv_wr32(priv, 0x405a18, 0x00000000);
+        /* GPC_BROADCAST.TP_BROADCAST */
+        nv_wr32(priv, 0x419bd0, (priv->tpc_total << 8) |
+                                 priv->magic_not_rop_nr | data2[0]);
+        nv_wr32(priv, 0x419be4, data2[1]);
+        for (i = 0; i < 6; i++)
+                nv_wr32(priv, 0x419b00 + (i * 4), data[i]);
+
+        /* UNK78xx */
+        nv_wr32(priv, 0x4078bc, (priv->tpc_total << 8) |
+                                 priv->magic_not_rop_nr);
+        for (i = 0; i < 6; i++)
+                nv_wr32(priv, 0x40780c + (i * 4), data[i]);
 }
 
-static void
-nvc0_grctx_generate_unk60xx(struct nvc0_graph_priv *priv)
+void
+nvc0_grctx_generate_r406800(struct nvc0_graph_priv *priv)
 {
-        nv_wr32(priv, 0x406020, 0x000103c1);
-        nv_wr32(priv, 0x406028, 0x00000001);
-        nv_wr32(priv, 0x40602c, 0x00000001);
-        nv_wr32(priv, 0x406030, 0x00000001);
-        nv_wr32(priv, 0x406034, 0x00000001);
-}
+        u64 tpc_mask = 0, tpc_set = 0;
+        u8  tpcnr[GPC_MAX];
+        int gpc, tpc;
+        int i, a, b;
+
+        memcpy(tpcnr, priv->tpc_nr, sizeof(priv->tpc_nr));
+        for (gpc = 0; gpc < priv->gpc_nr; gpc++)
+                tpc_mask |= ((1ULL << priv->tpc_nr[gpc]) - 1) << (gpc * 8);
+
+        for (i = 0, gpc = -1, b = -1; i < 32; i++) {
+                a = (i * (priv->tpc_total - 1)) / 32;
+                if (a != b) {
+                        b = a;
+                        do {
+                                gpc = (gpc + 1) % priv->gpc_nr;
+                        } while (!tpcnr[gpc]);
+                        tpc = priv->tpc_nr[gpc] - tpcnr[gpc]--;
 
-static void
-nvc0_grctx_generate_unk64xx(struct nvc0_graph_priv *priv)
-{
+                        tpc_set |= 1 << ((gpc * 8) + tpc);
+                }
 
-        nv_wr32(priv, 0x4064a8, 0x00000000);
-        nv_wr32(priv, 0x4064ac, 0x00003fff);
-        nv_wr32(priv, 0x4064b4, 0x00000000);
-        nv_wr32(priv, 0x4064b8, 0x00000000);
-        if (nv_device(priv)->chipset >= 0xd0)
-                nv_wr32(priv, 0x4064bc, 0x00000000);
-        if (nv_device(priv)->chipset == 0xc1 ||
-            nv_device(priv)->chipset >= 0xd0) {
-                nv_wr32(priv, 0x4064c0, 0x80140078);
-                nv_wr32(priv, 0x4064c4, 0x0086ffff);
+                nv_wr32(priv, 0x406800 + (i * 0x20), lower_32_bits(tpc_set));
+                nv_wr32(priv, 0x406c00 + (i * 0x20), lower_32_bits(tpc_set ^ tpc_mask));
+                if (priv->gpc_nr > 4) {
+                        nv_wr32(priv, 0x406804 + (i * 0x20), upper_32_bits(tpc_set));
+                        nv_wr32(priv, 0x406c04 + (i * 0x20), upper_32_bits(tpc_set ^ tpc_mask));
+                }
         }
 }
 
-static void
-nvc0_grctx_generate_tpbus(struct nvc0_graph_priv *priv)
+void
+nvc0_grctx_generate_main(struct nvc0_graph_priv *priv, struct nvc0_grctx *info)
 {
-        nv_wr32(priv, 0x407804, 0x00000023);
-        nv_wr32(priv, 0x40780c, 0x0a418820);
-        nv_wr32(priv, 0x407810, 0x062080e6);
-        nv_wr32(priv, 0x407814, 0x020398a4);
-        nv_wr32(priv, 0x407818, 0x0e629062);
-        nv_wr32(priv, 0x40781c, 0x0a418820);
-        nv_wr32(priv, 0x407820, 0x000000e6);
-        nv_wr32(priv, 0x4078bc, 0x00000103);
-}
+        struct nvc0_grctx_oclass *oclass = (void *)nv_engine(priv)->cclass;
+        int i;
 
-static void
-nvc0_grctx_generate_ccache(struct nvc0_graph_priv *priv)
-{
-        nv_wr32(priv, 0x408000, 0x00000000);
-        nv_wr32(priv, 0x408004, 0x00000000);
-        nv_wr32(priv, 0x408008, 0x00000018);
-        nv_wr32(priv, 0x40800c, 0x00000000);
-        nv_wr32(priv, 0x408010, 0x00000000);
-        nv_wr32(priv, 0x408014, 0x00000069);
-        nv_wr32(priv, 0x408018, 0xe100e100);
-        nv_wr32(priv, 0x408064, 0x00000000);
-}
+        nv_mask(priv, 0x000260, 0x00000001, 0x00000000);
 
-static void
-nvc0_grctx_generate_rop(struct nvc0_graph_priv *priv)
-{
-        int chipset = nv_device(priv)->chipset;
-
-        /* ROPC_BROADCAST */
-        nv_wr32(priv, 0x408800, 0x02802a3c);
-        nv_wr32(priv, 0x408804, 0x00000040);
-        if (chipset >= 0xd0) {
-                nv_wr32(priv, 0x408808, 0x1043e005);
-                nv_wr32(priv, 0x408900, 0x3080b801);
-                nv_wr32(priv, 0x408904, 0x1043e005);
-                nv_wr32(priv, 0x408908, 0x00c8102f);
-        } else
-        if (chipset == 0xc1) {
-                nv_wr32(priv, 0x408808, 0x1003e005);
-                nv_wr32(priv, 0x408900, 0x3080b801);
-                nv_wr32(priv, 0x408904, 0x62000001);
-                nv_wr32(priv, 0x408908, 0x00c80929);
-        } else {
-                nv_wr32(priv, 0x408808, 0x0003e00d);
-                nv_wr32(priv, 0x408900, 0x3080b801);
-                nv_wr32(priv, 0x408904, 0x02000001);
-                nv_wr32(priv, 0x408908, 0x00c80929);
-        }
-        nv_wr32(priv, 0x40890c, 0x00000000);
-        nv_wr32(priv, 0x408980, 0x0000011d);
-}
+        for (i = 0; oclass->hub[i]; i++)
+                nvc0_graph_mmio(priv, oclass->hub[i]);
+        for (i = 0; oclass->gpc[i]; i++)
+                nvc0_graph_mmio(priv, oclass->gpc[i]);
 
-static void
-nvc0_grctx_generate_gpc(struct nvc0_graph_priv *priv)
-{
-        int chipset = nv_device(priv)->chipset;
-        int i;
+        nv_wr32(priv, 0x404154, 0x00000000);
 
-        /* GPC_BROADCAST */
-        nv_wr32(priv, 0x418380, 0x00000016);
-        nv_wr32(priv, 0x418400, 0x38004e00);
-        nv_wr32(priv, 0x418404, 0x71e0ffff);
-        nv_wr32(priv, 0x418408, 0x00000000);
-        nv_wr32(priv, 0x41840c, 0x00001008);
-        nv_wr32(priv, 0x418410, 0x0fff0fff);
-        nv_wr32(priv, 0x418414, chipset < 0xd0 ? 0x00200fff : 0x02200fff);
-        nv_wr32(priv, 0x418450, 0x00000000);
-        nv_wr32(priv, 0x418454, 0x00000000);
-        nv_wr32(priv, 0x418458, 0x00000000);
-        nv_wr32(priv, 0x41845c, 0x00000000);
-        nv_wr32(priv, 0x418460, 0x00000000);
-        nv_wr32(priv, 0x418464, 0x00000000);
-        nv_wr32(priv, 0x418468, 0x00000001);
-        nv_wr32(priv, 0x41846c, 0x00000000);
-        nv_wr32(priv, 0x418470, 0x00000000);
-        nv_wr32(priv, 0x418600, 0x0000001f);
-        nv_wr32(priv, 0x418684, 0x0000000f);
-        nv_wr32(priv, 0x418700, 0x00000002);
-        nv_wr32(priv, 0x418704, 0x00000080);
-        nv_wr32(priv, 0x418708, 0x00000000);
-        nv_wr32(priv, 0x41870c, chipset < 0xd0 ? 0x07c80000 : 0x00000000);
-        nv_wr32(priv, 0x418710, 0x00000000);
-        nv_wr32(priv, 0x418800, chipset < 0xd0 ? 0x0006860a : 0x7006860a);
-        nv_wr32(priv, 0x418808, 0x00000000);
-        nv_wr32(priv, 0x41880c, 0x00000000);
-        nv_wr32(priv, 0x418810, 0x00000000);
-        nv_wr32(priv, 0x418828, 0x00008442);
-        if (chipset == 0xc1 || chipset >= 0xd0)
-                nv_wr32(priv, 0x418830, 0x10000001);
-        else
-                nv_wr32(priv, 0x418830, 0x00000001);
-        nv_wr32(priv, 0x4188d8, 0x00000008);
-        nv_wr32(priv, 0x4188e0, 0x01000000);
-        nv_wr32(priv, 0x4188e8, 0x00000000);
-        nv_wr32(priv, 0x4188ec, 0x00000000);
-        nv_wr32(priv, 0x4188f0, 0x00000000);
-        nv_wr32(priv, 0x4188f4, 0x00000000);
-        nv_wr32(priv, 0x4188f8, 0x00000000);
-        if (chipset >= 0xd0)
-                nv_wr32(priv, 0x4188fc, 0x20100008);
-        else if (chipset == 0xc1)
-                nv_wr32(priv, 0x4188fc, 0x00100018);
-        else
-                nv_wr32(priv, 0x4188fc, 0x00100000);
-        nv_wr32(priv, 0x41891c, 0x00ff00ff);
-        nv_wr32(priv, 0x418924, 0x00000000);
-        nv_wr32(priv, 0x418928, 0x00ffff00);
-        nv_wr32(priv, 0x41892c, 0x0000ff00);
-        for (i = 0; i < 8; i++) {
-                nv_wr32(priv, 0x418a00 + (i * 0x20), 0x00000000);
-                nv_wr32(priv, 0x418a04 + (i * 0x20), 0x00000000);
-                nv_wr32(priv, 0x418a08 + (i * 0x20), 0x00000000);
-                nv_wr32(priv, 0x418a0c + (i * 0x20), 0x00010000);
-                nv_wr32(priv, 0x418a10 + (i * 0x20), 0x00000000);
-                nv_wr32(priv, 0x418a14 + (i * 0x20), 0x00000000);
-                nv_wr32(priv, 0x418a18 + (i * 0x20), 0x00000000);
-        }
-        nv_wr32(priv, 0x418b00, chipset < 0xd0 ? 0x00000000 : 0x00000006);
-        nv_wr32(priv, 0x418b08, 0x0a418820);
-        nv_wr32(priv, 0x418b0c, 0x062080e6);
-        nv_wr32(priv, 0x418b10, 0x020398a4);
-        nv_wr32(priv, 0x418b14, 0x0e629062);
-        nv_wr32(priv, 0x418b18, 0x0a418820);
-        nv_wr32(priv, 0x418b1c, 0x000000e6);
-        nv_wr32(priv, 0x418bb8, 0x00000103);
-        nv_wr32(priv, 0x418c08, 0x00000001);
-        nv_wr32(priv, 0x418c10, 0x00000000);
-        nv_wr32(priv, 0x418c14, 0x00000000);
-        nv_wr32(priv, 0x418c18, 0x00000000);
-        nv_wr32(priv, 0x418c1c, 0x00000000);
-        nv_wr32(priv, 0x418c20, 0x00000000);
-        nv_wr32(priv, 0x418c24, 0x00000000);
-        nv_wr32(priv, 0x418c28, 0x00000000);
-        nv_wr32(priv, 0x418c2c, 0x00000000);
-        if (chipset == 0xc1 || chipset >= 0xd0)
-                nv_wr32(priv, 0x418c6c, 0x00000001);
-        nv_wr32(priv, 0x418c80, 0x20200004);
-        nv_wr32(priv, 0x418c8c, 0x00000001);
-        nv_wr32(priv, 0x419000, 0x00000780);
-        nv_wr32(priv, 0x419004, 0x00000000);
-        nv_wr32(priv, 0x419008, 0x00000000);
-        nv_wr32(priv, 0x419014, 0x00000004);
-}
+        oclass->mods(priv, info);
+        oclass->unkn(priv);
 
-static void
-nvc0_grctx_generate_tp(struct nvc0_graph_priv *priv)
-{
-        int chipset = nv_device(priv)->chipset;
+        nvc0_grctx_generate_tpcid(priv);
+        nvc0_grctx_generate_r406028(priv);
+        nvc0_grctx_generate_r4060a8(priv);
+        nvc0_grctx_generate_r418bb8(priv);
+        nvc0_grctx_generate_r406800(priv);
 
-        /* GPC_BROADCAST.TP_BROADCAST */
-        nv_wr32(priv, 0x419818, 0x00000000);
-        nv_wr32(priv, 0x41983c, 0x00038bc7);
-        nv_wr32(priv, 0x419848, 0x00000000);
-        if (chipset == 0xc1 || chipset >= 0xd0)
-                nv_wr32(priv, 0x419864, 0x00000129);
-        else
-                nv_wr32(priv, 0x419864, 0x0000012a);
-        nv_wr32(priv, 0x419888, 0x00000000);
-        nv_wr32(priv, 0x419a00, 0x000001f0);
-        nv_wr32(priv, 0x419a04, 0x00000001);
-        nv_wr32(priv, 0x419a08, 0x00000023);
-        nv_wr32(priv, 0x419a0c, 0x00020000);
-        nv_wr32(priv, 0x419a10, 0x00000000);
-        nv_wr32(priv, 0x419a14, 0x00000200);
-        nv_wr32(priv, 0x419a1c, 0x00000000);
-        nv_wr32(priv, 0x419a20, 0x00000800);
-        if (chipset >= 0xd0)
-                nv_wr32(priv, 0x00419ac4, 0x0017f440);
-        else if (chipset != 0xc0 && chipset != 0xc8)
-                nv_wr32(priv, 0x00419ac4, 0x0007f440);
-        nv_wr32(priv, 0x419b00, 0x0a418820);
-        nv_wr32(priv, 0x419b04, 0x062080e6);
-        nv_wr32(priv, 0x419b08, 0x020398a4);
-        nv_wr32(priv, 0x419b0c, 0x0e629062);
-        nv_wr32(priv, 0x419b10, 0x0a418820);
-        nv_wr32(priv, 0x419b14, 0x000000e6);
-        nv_wr32(priv, 0x419bd0, 0x00900103);
-        if (chipset == 0xc1 || chipset >= 0xd0)
-                nv_wr32(priv, 0x419be0, 0x00400001);
-        else
-                nv_wr32(priv, 0x419be0, 0x00000001);
-        nv_wr32(priv, 0x419be4, 0x00000000);
-        nv_wr32(priv, 0x419c00, chipset < 0xd0 ? 0x00000002 : 0x0000000a);
-        nv_wr32(priv, 0x419c04, 0x00000006);
-        nv_wr32(priv, 0x419c08, 0x00000002);
-        nv_wr32(priv, 0x419c20, 0x00000000);
-        if (nv_device(priv)->chipset >= 0xd0) {
-                nv_wr32(priv, 0x419c24, 0x00084210);
-                nv_wr32(priv, 0x419c28, 0x3cf3cf3c);
-                nv_wr32(priv, 0x419cb0, 0x00020048);
-        } else
-        if (chipset == 0xce || chipset == 0xcf) {
-                nv_wr32(priv, 0x419cb0, 0x00020048);
-        } else {
-                nv_wr32(priv, 0x419cb0, 0x00060048);
-        }
-        nv_wr32(priv, 0x419ce8, 0x00000000);
-        nv_wr32(priv, 0x419cf4, 0x00000183);
-        if (chipset == 0xc1 || chipset >= 0xd0)
-                nv_wr32(priv, 0x419d20, 0x12180000);
-        else
-                nv_wr32(priv, 0x419d20, 0x02180000);
-        nv_wr32(priv, 0x419d24, 0x00001fff);
-        if (chipset == 0xc1 || chipset >= 0xd0)
-                nv_wr32(priv, 0x419d44, 0x02180218);
-        nv_wr32(priv, 0x419e04, 0x00000000);
-        nv_wr32(priv, 0x419e08, 0x00000000);
-        nv_wr32(priv, 0x419e0c, 0x00000000);
-        nv_wr32(priv, 0x419e10, 0x00000002);
-        nv_wr32(priv, 0x419e44, 0x001beff2);
-        nv_wr32(priv, 0x419e48, 0x00000000);
-        nv_wr32(priv, 0x419e4c, 0x0000000f);
-        nv_wr32(priv, 0x419e50, 0x00000000);
-        nv_wr32(priv, 0x419e54, 0x00000000);
-        nv_wr32(priv, 0x419e58, 0x00000000);
-        nv_wr32(priv, 0x419e5c, 0x00000000);
-        nv_wr32(priv, 0x419e60, 0x00000000);
-        nv_wr32(priv, 0x419e64, 0x00000000);
-        nv_wr32(priv, 0x419e68, 0x00000000);
-        nv_wr32(priv, 0x419e6c, 0x00000000);
-        nv_wr32(priv, 0x419e70, 0x00000000);
-        nv_wr32(priv, 0x419e74, 0x00000000);
-        nv_wr32(priv, 0x419e78, 0x00000000);
-        nv_wr32(priv, 0x419e7c, 0x00000000);
-        nv_wr32(priv, 0x419e80, 0x00000000);
-        nv_wr32(priv, 0x419e84, 0x00000000);
-        nv_wr32(priv, 0x419e88, 0x00000000);
-        nv_wr32(priv, 0x419e8c, 0x00000000);
-        nv_wr32(priv, 0x419e90, 0x00000000);
-        nv_wr32(priv, 0x419e98, 0x00000000);
-        if (chipset != 0xc0 && chipset != 0xc8)
-                nv_wr32(priv, 0x419ee0, 0x00011110);
-        nv_wr32(priv, 0x419f50, 0x00000000);
-        nv_wr32(priv, 0x419f54, 0x00000000);
-        if (chipset != 0xc0 && chipset != 0xc8)
-                nv_wr32(priv, 0x419f58, 0x00000000);
+        nvc0_graph_icmd(priv, oclass->icmd);
+        nv_wr32(priv, 0x404154, 0x00000400);
+        nvc0_graph_mthd(priv, oclass->mthd);
+        nv_mask(priv, 0x000260, 0x00000001, 0x00000001);
 }
 
 int
 nvc0_grctx_generate(struct nvc0_graph_priv *priv)
 {
+        struct nvc0_grctx_oclass *oclass = (void *)nv_engine(priv)->cclass;
+        struct nouveau_bar *bar = nouveau_bar(priv);
+        struct nouveau_gpuobj *chan;
         struct nvc0_grctx info;
-        int ret, i, gpc, tpc, id;
-        u32 fermi = nvc0_graph_class(priv);
-        u32 r000260, tmp;
+        int ret, i;
 
-        ret = nvc0_grctx_init(priv, &info);
-        if (ret)
+        /* allocate memory to for a "channel", which we'll use to generate
+         * the default context values
+         */
+        ret = nouveau_gpuobj_new(nv_object(priv), NULL, 0x80000 + priv->size,
+                                 0x1000, NVOBJ_FLAG_ZERO_ALLOC, &chan);
+        if (ret) {
+                nv_error(priv, "failed to allocate channel memory, %d\n", ret);
                 return ret;
-
-        r000260 = nv_rd32(priv, 0x000260);
-        nv_wr32(priv, 0x000260, r000260 & ~1);
-        nv_wr32(priv, 0x400208, 0x00000000);
-
-        nvc0_grctx_generate_dispatch(priv);
-        nvc0_grctx_generate_macro(priv);
-        nvc0_grctx_generate_m2mf(priv);
-        nvc0_grctx_generate_unk47xx(priv);
-        nvc0_grctx_generate_shaders(priv);
-        nvc0_grctx_generate_unk60xx(priv);
-        nvc0_grctx_generate_unk64xx(priv);
-        nvc0_grctx_generate_tpbus(priv);
-        nvc0_grctx_generate_ccache(priv);
-        nvc0_grctx_generate_rop(priv);
-        nvc0_grctx_generate_gpc(priv);
-        nvc0_grctx_generate_tp(priv);
-
-        nv_wr32(priv, 0x404154, 0x00000000);
-
-        /* generate per-context mmio list data */
-        mmio_data(0x002000, 0x0100, NV_MEM_ACCESS_RW | NV_MEM_ACCESS_SYS);
-        mmio_data(0x008000, 0x0100, NV_MEM_ACCESS_RW | NV_MEM_ACCESS_SYS);
-        mmio_data(0x060000, 0x1000, NV_MEM_ACCESS_RW);
-        mmio_list(0x408004, 0x00000000,  8, 0);
-        mmio_list(0x408008, 0x80000018,  0, 0);
-        mmio_list(0x40800c, 0x00000000,  8, 1);
-        mmio_list(0x408010, 0x80000000,  0, 0);
-        mmio_list(0x418810, 0x80000000, 12, 2);
-        mmio_list(0x419848, 0x10000000, 12, 2);
-        mmio_list(0x419004, 0x00000000,  8, 1);
-        mmio_list(0x419008, 0x00000000,  0, 0);
-        mmio_list(0x418808, 0x00000000,  8, 0);
-        mmio_list(0x41880c, 0x80000018,  0, 0);
-        if (nv_device(priv)->chipset != 0xc1) {
-                tmp = 0x02180000;
-                mmio_list(0x405830, tmp, 0, 0);
-                for (gpc = 0; gpc < priv->gpc_nr; gpc++) {
-                        for (tpc = 0; tpc < priv->tpc_nr[gpc]; tpc++) {
-                                u32 reg = TPC_UNIT(gpc, tpc, 0x0520);
-                                mmio_list(reg, tmp, 0, 0);
-                                tmp += 0x0324;
-                        }
-                }
-        } else {
-                tmp = 0x02180000;
-                mmio_list(0x405830, 0x00000218 | tmp, 0, 0);
-                mmio_list(0x4064c4, 0x0086ffff, 0, 0);
-                for (gpc = 0; gpc < priv->gpc_nr; gpc++) {
-                        for (tpc = 0; tpc < priv->tpc_nr[gpc]; tpc++) {
-                                u32 reg = TPC_UNIT(gpc, tpc, 0x0520);
-                                mmio_list(reg, 0x10000000 | tmp, 0, 0);
-                                tmp += 0x0324;
-                        }
-                        for (tpc = 0; tpc < priv->tpc_nr[gpc]; tpc++) {
-                                u32 reg = TPC_UNIT(gpc, tpc, 0x0544);
-                                mmio_list(reg, tmp, 0, 0);
-                                tmp += 0x0324;
-                        }
-                }
         }
 
-        for (tpc = 0, id = 0; tpc < 4; tpc++) {
-                for (gpc = 0; gpc < priv->gpc_nr; gpc++) {
-                        if (tpc < priv->tpc_nr[gpc]) {
-                                nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x698), id);
-                                nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x4e8), id);
-                                nv_wr32(priv, GPC_UNIT(gpc, 0x0c10 + tpc * 4), id);
-                                nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x088), id);
-                                id++;
-                        }
-
-                        nv_wr32(priv, GPC_UNIT(gpc, 0x0c08), priv->tpc_nr[gpc]);
-                        nv_wr32(priv, GPC_UNIT(gpc, 0x0c8c), priv->tpc_nr[gpc]);
-                }
-        }
-
-        tmp = 0;
-        for (i = 0; i < priv->gpc_nr; i++)
-                tmp |= priv->tpc_nr[i] << (i * 4);
-        nv_wr32(priv, 0x406028, tmp);
-        nv_wr32(priv, 0x405870, tmp);
-
-        nv_wr32(priv, 0x40602c, 0x00000000);
-        nv_wr32(priv, 0x405874, 0x00000000);
-        nv_wr32(priv, 0x406030, 0x00000000);
-        nv_wr32(priv, 0x405878, 0x00000000);
-        nv_wr32(priv, 0x406034, 0x00000000);
-        nv_wr32(priv, 0x40587c, 0x00000000);
-
-        if (1) {
-                u8 tpcnr[GPC_MAX], data[TPC_MAX];
-
-                memcpy(tpcnr, priv->tpc_nr, sizeof(priv->tpc_nr));
-                memset(data, 0x1f, sizeof(data));
+        /* PGD pointer */
+        nv_wo32(chan, 0x0200, lower_32_bits(chan->addr + 0x1000));
+        nv_wo32(chan, 0x0204, upper_32_bits(chan->addr + 0x1000));
+        nv_wo32(chan, 0x0208, 0xffffffff);
+        nv_wo32(chan, 0x020c, 0x000000ff);
 
-                gpc = -1;
-                for (tpc = 0; tpc < priv->tpc_total; tpc++) {
-                        do {
-                                gpc = (gpc + 1) % priv->gpc_nr;
-                        } while (!tpcnr[gpc]);
-                        tpcnr[gpc]--;
-                        data[tpc] = gpc;
-                }
+        /* PGT[0] pointer */
+        nv_wo32(chan, 0x1000, 0x00000000);
+        nv_wo32(chan, 0x1004, 0x00000001 | (chan->addr + 0x2000) >> 8);
 
-                for (i = 0; i < 4; i++)
-                        nv_wr32(priv, 0x4060a8 + (i * 4), ((u32 *)data)[i]);
+        /* identity-map the whole "channel" into its own vm */
+        for (i = 0; i < chan->size / 4096; i++) {
+                u64 addr = ((chan->addr + (i * 4096)) >> 8) | 1;
+                nv_wo32(chan, 0x2000 + (i * 8), lower_32_bits(addr));
+                nv_wo32(chan, 0x2004 + (i * 8), upper_32_bits(addr));
         }
 
-        if (1) {
-                u32 data[6] = {}, data2[2] = {};
-                u8 tpcnr[GPC_MAX];
-                u8 shift, ntpcv;
-
-                /* calculate first set of magics */
-                memcpy(tpcnr, priv->tpc_nr, sizeof(priv->tpc_nr));
+        /* context pointer (virt) */
+        nv_wo32(chan, 0x0210, 0x00080004);
+        nv_wo32(chan, 0x0214, 0x00000000);
 
-                gpc = -1;
-                for (tpc = 0; tpc < priv->tpc_total; tpc++) {
-                        do {
-                                gpc = (gpc + 1) % priv->gpc_nr;
-                        } while (!tpcnr[gpc]);
-                        tpcnr[gpc]--;
+        bar->flush(bar);
 
-                        data[tpc / 6] |= gpc << ((tpc % 6) * 5);
-                }
+        nv_wr32(priv, 0x100cb8, (chan->addr + 0x1000) >> 8);
+        nv_wr32(priv, 0x100cbc, 0x80000001);
+        nv_wait(priv, 0x100c80, 0x00008000, 0x00008000);
 
-                for (; tpc < 32; tpc++)
-                        data[tpc / 6] |= 7 << ((tpc % 6) * 5);
+        /* setup default state for mmio list construction */
+        info.priv = priv;
+        info.data = priv->mmio_data;
+        info.mmio = priv->mmio_list;
+        info.addr = 0x2000 + (i * 8);
+        info.buffer_nr = 0;
 
-                /* and the second... */
-                shift = 0;
-                ntpcv = priv->tpc_total;
-                while (!(ntpcv & (1 << 4))) {
-                        ntpcv <<= 1;
-                        shift++;
-                }
+        /* make channel current */
+        if (priv->firmware) {
+                nv_wr32(priv, 0x409840, 0x00000030);
+                nv_wr32(priv, 0x409500, 0x80000000 | chan->addr >> 12);
+                nv_wr32(priv, 0x409504, 0x00000003);
+                if (!nv_wait(priv, 0x409800, 0x00000010, 0x00000010))
+                        nv_error(priv, "load_ctx timeout\n");
 
-                data2[0]  = (ntpcv << 16);
-                data2[0] |= (shift << 21);
-                data2[0] |= (((1 << (0 + 5)) % ntpcv) << 24);
-                for (i = 1; i < 7; i++)
-                        data2[1] |= ((1 << (i + 5)) % ntpcv) << ((i - 1) * 5);
-
-                /* GPC_BROADCAST */
-                nv_wr32(priv, 0x418bb8, (priv->tpc_total << 8) |
-                                        priv->magic_not_rop_nr);
-                for (i = 0; i < 6; i++)
-                        nv_wr32(priv, 0x418b08 + (i * 4), data[i]);
-
-                /* GPC_BROADCAST.TP_BROADCAST */
-                nv_wr32(priv, 0x419bd0, (priv->tpc_total << 8) |
-                                       priv->magic_not_rop_nr |
-                                       data2[0]);
-                nv_wr32(priv, 0x419be4, data2[1]);
-                for (i = 0; i < 6; i++)
-                        nv_wr32(priv, 0x419b00 + (i * 4), data[i]);
-
-                /* UNK78xx */
-                nv_wr32(priv, 0x4078bc, (priv->tpc_total << 8) |
-                                        priv->magic_not_rop_nr);
-                for (i = 0; i < 6; i++)
-                        nv_wr32(priv, 0x40780c + (i * 4), data[i]);
+                nv_wo32(chan, 0x8001c, 1);
+                nv_wo32(chan, 0x80020, 0);
+                nv_wo32(chan, 0x80028, 0);
+                nv_wo32(chan, 0x8002c, 0);
+                bar->flush(bar);
+        } else {
+                nv_wr32(priv, 0x409840, 0x80000000);
+                nv_wr32(priv, 0x409500, 0x80000000 | chan->addr >> 12);
+                nv_wr32(priv, 0x409504, 0x00000001);
+                if (!nv_wait(priv, 0x409800, 0x80000000, 0x80000000))
+                        nv_error(priv, "HUB_SET_CHAN timeout\n");
         }
 
-        if (1) {
-                u32 tpc_mask = 0, tpc_set = 0;
-                u8  tpcnr[GPC_MAX], a, b;
-
-                memcpy(tpcnr, priv->tpc_nr, sizeof(priv->tpc_nr));
-                for (gpc = 0; gpc < priv->gpc_nr; gpc++)
-                        tpc_mask |= ((1 << priv->tpc_nr[gpc]) - 1) << (gpc * 8);
-
-                for (i = 0, gpc = -1, b = -1; i < 32; i++) {
-                        a = (i * (priv->tpc_total - 1)) / 32;
-                        if (a != b) {
-                                b = a;
-                                do {
-                                        gpc = (gpc + 1) % priv->gpc_nr;
-                                } while (!tpcnr[gpc]);
-                                tpc = priv->tpc_nr[gpc] - tpcnr[gpc]--;
-
-                                tpc_set |= 1 << ((gpc * 8) + tpc);
-                        }
+        oclass->main(priv, &info);
 
-                        nv_wr32(priv, 0x406800 + (i * 0x20), tpc_set);
-                        nv_wr32(priv, 0x406c00 + (i * 0x20), tpc_set ^ tpc_mask);
-                }
+        /* trigger a context unload by unsetting the "next channel valid" bit
+         * and faking a context switch interrupt
+         */
+        nv_mask(priv, 0x409b04, 0x80000000, 0x00000000);
+        nv_wr32(priv, 0x409000, 0x00000100);
+        if (!nv_wait(priv, 0x409b00, 0x80000000, 0x00000000)) {
+                nv_error(priv, "grctx template channel unload timeout\n");
+                ret = -EBUSY;
+                goto done;
         }
 
-        nv_wr32(priv, 0x400208, 0x80000000);
-
-        nv_icmd(priv, 0x00001000, 0x00000004);
-        nv_icmd(priv, 0x000000a9, 0x0000ffff);
-        nv_icmd(priv, 0x00000038, 0x0fac6881);
-        nv_icmd(priv, 0x0000003d, 0x00000001);
-        nv_icmd(priv, 0x000000e8, 0x00000400);
-        nv_icmd(priv, 0x000000e9, 0x00000400);
-        nv_icmd(priv, 0x000000ea, 0x00000400);
-        nv_icmd(priv, 0x000000eb, 0x00000400);
-        nv_icmd(priv, 0x000000ec, 0x00000400);
-        nv_icmd(priv, 0x000000ed, 0x00000400);
-        nv_icmd(priv, 0x000000ee, 0x00000400);
-        nv_icmd(priv, 0x000000ef, 0x00000400);
-        nv_icmd(priv, 0x00000078, 0x00000300);
-        nv_icmd(priv, 0x00000079, 0x00000300);
-        nv_icmd(priv, 0x0000007a, 0x00000300);
-        nv_icmd(priv, 0x0000007b, 0x00000300);
-        nv_icmd(priv, 0x0000007c, 0x00000300);
-        nv_icmd(priv, 0x0000007d, 0x00000300);
-        nv_icmd(priv, 0x0000007e, 0x00000300);
-        nv_icmd(priv, 0x0000007f, 0x00000300);
-        nv_icmd(priv, 0x00000050, 0x00000011);
-        nv_icmd(priv, 0x00000058, 0x00000008);
-        nv_icmd(priv, 0x00000059, 0x00000008);
-        nv_icmd(priv, 0x0000005a, 0x00000008);
-        nv_icmd(priv, 0x0000005b, 0x00000008);
-        nv_icmd(priv, 0x0000005c, 0x00000008);
-        nv_icmd(priv, 0x0000005d, 0x00000008);
-        nv_icmd(priv, 0x0000005e, 0x00000008);
-        nv_icmd(priv, 0x0000005f, 0x00000008);
-        nv_icmd(priv, 0x00000208, 0x00000001);
-        nv_icmd(priv, 0x00000209, 0x00000001);
-        nv_icmd(priv, 0x0000020a, 0x00000001);
-        nv_icmd(priv, 0x0000020b, 0x00000001);
-        nv_icmd(priv, 0x0000020c, 0x00000001);
-        nv_icmd(priv, 0x0000020d, 0x00000001);
-        nv_icmd(priv, 0x0000020e, 0x00000001);
-        nv_icmd(priv, 0x0000020f, 0x00000001);
-        nv_icmd(priv, 0x00000081, 0x00000001);
-        nv_icmd(priv, 0x00000085, 0x00000004);
-        nv_icmd(priv, 0x00000088, 0x00000400);
-        nv_icmd(priv, 0x00000090, 0x00000300);
-        nv_icmd(priv, 0x00000098, 0x00001001);
-        nv_icmd(priv, 0x000000e3, 0x00000001);
-        nv_icmd(priv, 0x000000da, 0x00000001);
-        nv_icmd(priv, 0x000000f8, 0x00000003);
-        nv_icmd(priv, 0x000000fa, 0x00000001);
-        nv_icmd(priv, 0x0000009f, 0x0000ffff);
-        nv_icmd(priv, 0x000000a0, 0x0000ffff);
-        nv_icmd(priv, 0x000000a1, 0x0000ffff);
-        nv_icmd(priv, 0x000000a2, 0x0000ffff);
-        nv_icmd(priv, 0x000000b1, 0x00000001);
-        nv_icmd(priv, 0x000000b2, 0x00000000);
-        nv_icmd(priv, 0x000000b3, 0x00000000);
-        nv_icmd(priv, 0x000000b4, 0x00000000);
-        nv_icmd(priv, 0x000000b5, 0x00000000);
-        nv_icmd(priv, 0x000000b6, 0x00000000);
-        nv_icmd(priv, 0x000000b7, 0x00000000);
-        nv_icmd(priv, 0x000000b8, 0x00000000);
-        nv_icmd(priv, 0x000000b9, 0x00000000);
-        nv_icmd(priv, 0x000000ba, 0x00000000);
-        nv_icmd(priv, 0x000000bb, 0x00000000);
-        nv_icmd(priv, 0x000000bc, 0x00000000);
-        nv_icmd(priv, 0x000000bd, 0x00000000);
-        nv_icmd(priv, 0x000000be, 0x00000000);
-        nv_icmd(priv, 0x000000bf, 0x00000000);
-        nv_icmd(priv, 0x000000c0, 0x00000000);
-        nv_icmd(priv, 0x000000c1, 0x00000000);
-        nv_icmd(priv, 0x000000c2, 0x00000000);
-        nv_icmd(priv, 0x000000c3, 0x00000000);
-        nv_icmd(priv, 0x000000c4, 0x00000000);
-        nv_icmd(priv, 0x000000c5, 0x00000000);
-        nv_icmd(priv, 0x000000c6, 0x00000000);
-        nv_icmd(priv, 0x000000c7, 0x00000000);
-        nv_icmd(priv, 0x000000c8, 0x00000000);
-        nv_icmd(priv, 0x000000c9, 0x00000000);
-        nv_icmd(priv, 0x000000ca, 0x00000000);
-        nv_icmd(priv, 0x000000cb, 0x00000000);
-        nv_icmd(priv, 0x000000cc, 0x00000000);
-        nv_icmd(priv, 0x000000cd, 0x00000000);
-        nv_icmd(priv, 0x000000ce, 0x00000000);
-        nv_icmd(priv, 0x000000cf, 0x00000000);
-        nv_icmd(priv, 0x000000d0, 0x00000000);
-        nv_icmd(priv, 0x000000d1, 0x00000000);
-        nv_icmd(priv, 0x000000d2, 0x00000000);
-        nv_icmd(priv, 0x000000d3, 0x00000000);
-        nv_icmd(priv, 0x000000d4, 0x00000000);
-        nv_icmd(priv, 0x000000d5, 0x00000000);
-        nv_icmd(priv, 0x000000d6, 0x00000000);
-        nv_icmd(priv, 0x000000d7, 0x00000000);
-        nv_icmd(priv, 0x000000d8, 0x00000000);
-        nv_icmd(priv, 0x000000d9, 0x00000000);
-        nv_icmd(priv, 0x00000210, 0x00000040);
-        nv_icmd(priv, 0x00000211, 0x00000040);
-        nv_icmd(priv, 0x00000212, 0x00000040);
-        nv_icmd(priv, 0x00000213, 0x00000040);
-        nv_icmd(priv, 0x00000214, 0x00000040);
-        nv_icmd(priv, 0x00000215, 0x00000040);
-        nv_icmd(priv, 0x00000216, 0x00000040);
-        nv_icmd(priv, 0x00000217, 0x00000040);
-        if (nv_device(priv)->chipset >= 0xd0) {
-                for (i = 0x0400; i <= 0x0417; i++)
-                        nv_icmd(priv, i, 0x00000040);
-        }
-        nv_icmd(priv, 0x00000218, 0x0000c080);
-        nv_icmd(priv, 0x00000219, 0x0000c080);
-        nv_icmd(priv, 0x0000021a, 0x0000c080);
-        nv_icmd(priv, 0x0000021b, 0x0000c080);
-        nv_icmd(priv, 0x0000021c, 0x0000c080);
-        nv_icmd(priv, 0x0000021d, 0x0000c080);
-        nv_icmd(priv, 0x0000021e, 0x0000c080);
-        nv_icmd(priv, 0x0000021f, 0x0000c080);
-        if (nv_device(priv)->chipset >= 0xd0) {
-                for (i = 0x0440; i <= 0x0457; i++)
-                        nv_icmd(priv, i, 0x0000c080);
+        priv->data = kmalloc(priv->size, GFP_KERNEL);
+        if (priv->data) {
+                for (i = 0; i < priv->size; i += 4)
+                        priv->data[i / 4] = nv_ro32(chan, 0x80000 + i);
+                ret = 0;
+        } else {
+                ret = -ENOMEM;
         }
-        nv_icmd(priv, 0x000000ad, 0x0000013e);
-        nv_icmd(priv, 0x000000e1, 0x00000010);
-        nv_icmd(priv, 0x00000290, 0x00000000);
-        nv_icmd(priv, 0x00000291, 0x00000000);
-        nv_icmd(priv, 0x00000292, 0x00000000);
-        nv_icmd(priv, 0x00000293, 0x00000000);
-        nv_icmd(priv, 0x00000294, 0x00000000);
-        nv_icmd(priv, 0x00000295, 0x00000000);
-        nv_icmd(priv, 0x00000296, 0x00000000);
-        nv_icmd(priv, 0x00000297, 0x00000000);
-        nv_icmd(priv, 0x00000298, 0x00000000);
-        nv_icmd(priv, 0x00000299, 0x00000000);
-        nv_icmd(priv, 0x0000029a, 0x00000000);
-        nv_icmd(priv, 0x0000029b, 0x00000000);
-        nv_icmd(priv, 0x0000029c, 0x00000000);
-        nv_icmd(priv, 0x0000029d, 0x00000000);
-        nv_icmd(priv, 0x0000029e, 0x00000000);
-        nv_icmd(priv, 0x0000029f, 0x00000000);
-        nv_icmd(priv, 0x000003b0, 0x00000000);
-        nv_icmd(priv, 0x000003b1, 0x00000000);
-        nv_icmd(priv, 0x000003b2, 0x00000000);
-        nv_icmd(priv, 0x000003b3, 0x00000000);
-        nv_icmd(priv, 0x000003b4, 0x00000000);
-        nv_icmd(priv, 0x000003b5, 0x00000000);
-        nv_icmd(priv, 0x000003b6, 0x00000000);
-        nv_icmd(priv, 0x000003b7, 0x00000000);
-        nv_icmd(priv, 0x000003b8, 0x00000000);
-        nv_icmd(priv, 0x000003b9, 0x00000000);
-        nv_icmd(priv, 0x000003ba, 0x00000000);
-        nv_icmd(priv, 0x000003bb, 0x00000000);
-        nv_icmd(priv, 0x000003bc, 0x00000000);
-        nv_icmd(priv, 0x000003bd, 0x00000000);
-        nv_icmd(priv, 0x000003be, 0x00000000);
-        nv_icmd(priv, 0x000003bf, 0x00000000);
-        nv_icmd(priv, 0x000002a0, 0x00000000);
-        nv_icmd(priv, 0x000002a1, 0x00000000);
-        nv_icmd(priv, 0x000002a2, 0x00000000);
-        nv_icmd(priv, 0x000002a3, 0x00000000);
-        nv_icmd(priv, 0x000002a4, 0x00000000);
-        nv_icmd(priv, 0x000002a5, 0x00000000);
-        nv_icmd(priv, 0x000002a6, 0x00000000);
-        nv_icmd(priv, 0x000002a7, 0x00000000);
-        nv_icmd(priv, 0x000002a8, 0x00000000);
-        nv_icmd(priv, 0x000002a9, 0x00000000);
-        nv_icmd(priv, 0x000002aa, 0x00000000);
-        nv_icmd(priv, 0x000002ab, 0x00000000);
-        nv_icmd(priv, 0x000002ac, 0x00000000);
-        nv_icmd(priv, 0x000002ad, 0x00000000);
-        nv_icmd(priv, 0x000002ae, 0x00000000);
-        nv_icmd(priv, 0x000002af, 0x00000000);
-        nv_icmd(priv, 0x00000420, 0x00000000);
-        nv_icmd(priv, 0x00000421, 0x00000000);
-        nv_icmd(priv, 0x00000422, 0x00000000);
-        nv_icmd(priv, 0x00000423, 0x00000000);
-        nv_icmd(priv, 0x00000424, 0x00000000);
-        nv_icmd(priv, 0x00000425, 0x00000000);
-        nv_icmd(priv, 0x00000426, 0x00000000);
-        nv_icmd(priv, 0x00000427, 0x00000000);
-        nv_icmd(priv, 0x00000428, 0x00000000);
-        nv_icmd(priv, 0x00000429, 0x00000000);
-        nv_icmd(priv, 0x0000042a, 0x00000000);
-        nv_icmd(priv, 0x0000042b, 0x00000000);
-        nv_icmd(priv, 0x0000042c, 0x00000000);
-        nv_icmd(priv, 0x0000042d, 0x00000000);
-        nv_icmd(priv, 0x0000042e, 0x00000000);
-        nv_icmd(priv, 0x0000042f, 0x00000000);
-        nv_icmd(priv, 0x000002b0, 0x00000000);
-        nv_icmd(priv, 0x000002b1, 0x00000000);
-        nv_icmd(priv, 0x000002b2, 0x00000000);
-        nv_icmd(priv, 0x000002b3, 0x00000000);
-        nv_icmd(priv, 0x000002b4, 0x00000000);
-        nv_icmd(priv, 0x000002b5, 0x00000000);
-        nv_icmd(priv, 0x000002b6, 0x00000000);
-        nv_icmd(priv, 0x000002b7, 0x00000000);
-        nv_icmd(priv, 0x000002b8, 0x00000000);
-        nv_icmd(priv, 0x000002b9, 0x00000000);
-        nv_icmd(priv, 0x000002ba, 0x00000000);
-        nv_icmd(priv, 0x000002bb, 0x00000000);
-        nv_icmd(priv, 0x000002bc, 0x00000000);
-        nv_icmd(priv, 0x000002bd, 0x00000000);
-        nv_icmd(priv, 0x000002be, 0x00000000);
-        nv_icmd(priv, 0x000002bf, 0x00000000);
-        nv_icmd(priv, 0x00000430, 0x00000000);
-        nv_icmd(priv, 0x00000431, 0x00000000);
-        nv_icmd(priv, 0x00000432, 0x00000000);
-        nv_icmd(priv, 0x00000433, 0x00000000);
-        nv_icmd(priv, 0x00000434, 0x00000000);
-        nv_icmd(priv, 0x00000435, 0x00000000);
-        nv_icmd(priv, 0x00000436, 0x00000000);
-        nv_icmd(priv, 0x00000437, 0x00000000);
-        nv_icmd(priv, 0x00000438, 0x00000000);
-        nv_icmd(priv, 0x00000439, 0x00000000);
-        nv_icmd(priv, 0x0000043a, 0x00000000);
-        nv_icmd(priv, 0x0000043b, 0x00000000);
-        nv_icmd(priv, 0x0000043c, 0x00000000);
-        nv_icmd(priv, 0x0000043d, 0x00000000);
-        nv_icmd(priv, 0x0000043e, 0x00000000);
-        nv_icmd(priv, 0x0000043f, 0x00000000);
-        nv_icmd(priv, 0x000002c0, 0x00000000);
-        nv_icmd(priv, 0x000002c1, 0x00000000);
-        nv_icmd(priv, 0x000002c2, 0x00000000);
-        nv_icmd(priv, 0x000002c3, 0x00000000);
-        nv_icmd(priv, 0x000002c4, 0x00000000);
-        nv_icmd(priv, 0x000002c5, 0x00000000);
-        nv_icmd(priv, 0x000002c6, 0x00000000);
-        nv_icmd(priv, 0x000002c7, 0x00000000);
-        nv_icmd(priv, 0x000002c8, 0x00000000);
-        nv_icmd(priv, 0x000002c9, 0x00000000);
-        nv_icmd(priv, 0x000002ca, 0x00000000);
-        nv_icmd(priv, 0x000002cb, 0x00000000);
-        nv_icmd(priv, 0x000002cc, 0x00000000);
-        nv_icmd(priv, 0x000002cd, 0x00000000);
-        nv_icmd(priv, 0x000002ce, 0x00000000);
-        nv_icmd(priv, 0x000002cf, 0x00000000);
-        nv_icmd(priv, 0x000004d0, 0x00000000);
-        nv_icmd(priv, 0x000004d1, 0x00000000);
-        nv_icmd(priv, 0x000004d2, 0x00000000);
-        nv_icmd(priv, 0x000004d3, 0x00000000);
-        nv_icmd(priv, 0x000004d4, 0x00000000);
-        nv_icmd(priv, 0x000004d5, 0x00000000);
-        nv_icmd(priv, 0x000004d6, 0x00000000);
-        nv_icmd(priv, 0x000004d7, 0x00000000);
-        nv_icmd(priv, 0x000004d8, 0x00000000);
-        nv_icmd(priv, 0x000004d9, 0x00000000);
-        nv_icmd(priv, 0x000004da, 0x00000000);
-        nv_icmd(priv, 0x000004db, 0x00000000);
-        nv_icmd(priv, 0x000004dc, 0x00000000);
-        nv_icmd(priv, 0x000004dd, 0x00000000);
-        nv_icmd(priv, 0x000004de, 0x00000000);
-        nv_icmd(priv, 0x000004df, 0x00000000);
-        nv_icmd(priv, 0x00000720, 0x00000000);
-        nv_icmd(priv, 0x00000721, 0x00000000);
-        nv_icmd(priv, 0x00000722, 0x00000000);
-        nv_icmd(priv, 0x00000723, 0x00000000);
-        nv_icmd(priv, 0x00000724, 0x00000000);
-        nv_icmd(priv, 0x00000725, 0x00000000);
-        nv_icmd(priv, 0x00000726, 0x00000000);
-        nv_icmd(priv, 0x00000727, 0x00000000);
-        nv_icmd(priv, 0x00000728, 0x00000000);
-        nv_icmd(priv, 0x00000729, 0x00000000);
-        nv_icmd(priv, 0x0000072a, 0x00000000);
-        nv_icmd(priv, 0x0000072b, 0x00000000);
-        nv_icmd(priv, 0x0000072c, 0x00000000);
-        nv_icmd(priv, 0x0000072d, 0x00000000);
-        nv_icmd(priv, 0x0000072e, 0x00000000);
-        nv_icmd(priv, 0x0000072f, 0x00000000);
-        nv_icmd(priv, 0x000008c0, 0x00000000);
-        nv_icmd(priv, 0x000008c1, 0x00000000);
-        nv_icmd(priv, 0x000008c2, 0x00000000);
-        nv_icmd(priv, 0x000008c3, 0x00000000);
-        nv_icmd(priv, 0x000008c4, 0x00000000);
-        nv_icmd(priv, 0x000008c5, 0x00000000);
-        nv_icmd(priv, 0x000008c6, 0x00000000);
-        nv_icmd(priv, 0x000008c7, 0x00000000);
-        nv_icmd(priv, 0x000008c8, 0x00000000);
-        nv_icmd(priv, 0x000008c9, 0x00000000);
-        nv_icmd(priv, 0x000008ca, 0x00000000);
-        nv_icmd(priv, 0x000008cb, 0x00000000);
-        nv_icmd(priv, 0x000008cc, 0x00000000);
-        nv_icmd(priv, 0x000008cd, 0x00000000);
-        nv_icmd(priv, 0x000008ce, 0x00000000);
-        nv_icmd(priv, 0x000008cf, 0x00000000);
-        nv_icmd(priv, 0x00000890, 0x00000000);
-        nv_icmd(priv, 0x00000891, 0x00000000);
-        nv_icmd(priv, 0x00000892, 0x00000000);
-        nv_icmd(priv, 0x00000893, 0x00000000);
-        nv_icmd(priv, 0x00000894, 0x00000000);
-        nv_icmd(priv, 0x00000895, 0x00000000);
-        nv_icmd(priv, 0x00000896, 0x00000000);
-        nv_icmd(priv, 0x00000897, 0x00000000);
-        nv_icmd(priv, 0x00000898, 0x00000000);
-        nv_icmd(priv, 0x00000899, 0x00000000);
-        nv_icmd(priv, 0x0000089a, 0x00000000);
-        nv_icmd(priv, 0x0000089b, 0x00000000);
-        nv_icmd(priv, 0x0000089c, 0x00000000);
-        nv_icmd(priv, 0x0000089d, 0x00000000);
-        nv_icmd(priv, 0x0000089e, 0x00000000);
-        nv_icmd(priv, 0x0000089f, 0x00000000);
-        nv_icmd(priv, 0x000008e0, 0x00000000);
-        nv_icmd(priv, 0x000008e1, 0x00000000);
-        nv_icmd(priv, 0x000008e2, 0x00000000);
-        nv_icmd(priv, 0x000008e3, 0x00000000);
-        nv_icmd(priv, 0x000008e4, 0x00000000);
-        nv_icmd(priv, 0x000008e5, 0x00000000);
-        nv_icmd(priv, 0x000008e6, 0x00000000);
-        nv_icmd(priv, 0x000008e7, 0x00000000);
-        nv_icmd(priv, 0x000008e8, 0x00000000);
-        nv_icmd(priv, 0x000008e9, 0x00000000);
-        nv_icmd(priv, 0x000008ea, 0x00000000);
-        nv_icmd(priv, 0x000008eb, 0x00000000);
-        nv_icmd(priv, 0x000008ec, 0x00000000);
-        nv_icmd(priv, 0x000008ed, 0x00000000);
-        nv_icmd(priv, 0x000008ee, 0x00000000);
-        nv_icmd(priv, 0x000008ef, 0x00000000);
-        nv_icmd(priv, 0x000008a0, 0x00000000);
-        nv_icmd(priv, 0x000008a1, 0x00000000);
-        nv_icmd(priv, 0x000008a2, 0x00000000);
-        nv_icmd(priv, 0x000008a3, 0x00000000);
-        nv_icmd(priv, 0x000008a4, 0x00000000);
-        nv_icmd(priv, 0x000008a5, 0x00000000);
-        nv_icmd(priv, 0x000008a6, 0x00000000);
-        nv_icmd(priv, 0x000008a7, 0x00000000);
-        nv_icmd(priv, 0x000008a8, 0x00000000);
-        nv_icmd(priv, 0x000008a9, 0x00000000);
-        nv_icmd(priv, 0x000008aa, 0x00000000);
-        nv_icmd(priv, 0x000008ab, 0x00000000);
-        nv_icmd(priv, 0x000008ac, 0x00000000);
-        nv_icmd(priv, 0x000008ad, 0x00000000);
-        nv_icmd(priv, 0x000008ae, 0x00000000);
-        nv_icmd(priv, 0x000008af, 0x00000000);
-        nv_icmd(priv, 0x000008f0, 0x00000000);
-        nv_icmd(priv, 0x000008f1, 0x00000000);
-        nv_icmd(priv, 0x000008f2, 0x00000000);
-        nv_icmd(priv, 0x000008f3, 0x00000000);
-        nv_icmd(priv, 0x000008f4, 0x00000000);
-        nv_icmd(priv, 0x000008f5, 0x00000000);
-        nv_icmd(priv, 0x000008f6, 0x00000000);
-        nv_icmd(priv, 0x000008f7, 0x00000000);
-        nv_icmd(priv, 0x000008f8, 0x00000000);
-        nv_icmd(priv, 0x000008f9, 0x00000000);
-        nv_icmd(priv, 0x000008fa, 0x00000000);
-        nv_icmd(priv, 0x000008fb, 0x00000000);
-        nv_icmd(priv, 0x000008fc, 0x00000000);
-        nv_icmd(priv, 0x000008fd, 0x00000000);
-        nv_icmd(priv, 0x000008fe, 0x00000000);
-        nv_icmd(priv, 0x000008ff, 0x00000000);
-        nv_icmd(priv, 0x0000094c, 0x000000ff);
-        nv_icmd(priv, 0x0000094d, 0xffffffff);
-        nv_icmd(priv, 0x0000094e, 0x00000002);
-        nv_icmd(priv, 0x000002ec, 0x00000001);
-        nv_icmd(priv, 0x00000303, 0x00000001);
-        nv_icmd(priv, 0x000002e6, 0x00000001);
-        nv_icmd(priv, 0x00000466, 0x00000052);
-        nv_icmd(priv, 0x00000301, 0x3f800000);
-        nv_icmd(priv, 0x00000304, 0x30201000);
-        nv_icmd(priv, 0x00000305, 0x70605040);
-        nv_icmd(priv, 0x00000306, 0xb8a89888);
-        nv_icmd(priv, 0x00000307, 0xf8e8d8c8);
-        nv_icmd(priv, 0x0000030a, 0x00ffff00);
-        nv_icmd(priv, 0x0000030b, 0x0000001a);
-        nv_icmd(priv, 0x0000030c, 0x00000001);
-        nv_icmd(priv, 0x00000318, 0x00000001);
-        nv_icmd(priv, 0x00000340, 0x00000000);
-        nv_icmd(priv, 0x00000375, 0x00000001);
-        nv_icmd(priv, 0x00000351, 0x00000100);
-        nv_icmd(priv, 0x0000037d, 0x00000006);
-        nv_icmd(priv, 0x000003a0, 0x00000002);
-        nv_icmd(priv, 0x000003aa, 0x00000001);
-        nv_icmd(priv, 0x000003a9, 0x00000001);
-        nv_icmd(priv, 0x00000380, 0x00000001);
-        nv_icmd(priv, 0x00000360, 0x00000040);
-        nv_icmd(priv, 0x00000366, 0x00000000);
-        nv_icmd(priv, 0x00000367, 0x00000000);
-        nv_icmd(priv, 0x00000368, 0x00001fff);
-        nv_icmd(priv, 0x00000370, 0x00000000);
-        nv_icmd(priv, 0x00000371, 0x00000000);
-        nv_icmd(priv, 0x00000372, 0x003fffff);
-        nv_icmd(priv, 0x0000037a, 0x00000012);
-        nv_icmd(priv, 0x000005e0, 0x00000022);
-        nv_icmd(priv, 0x000005e1, 0x00000022);
-        nv_icmd(priv, 0x000005e2, 0x00000022);
-        nv_icmd(priv, 0x000005e3, 0x00000022);
-        nv_icmd(priv, 0x000005e4, 0x00000022);
-        nv_icmd(priv, 0x00000619, 0x00000003);
-        nv_icmd(priv, 0x00000811, 0x00000003);
-        nv_icmd(priv, 0x00000812, 0x00000004);
-        nv_icmd(priv, 0x00000813, 0x00000006);
-        nv_icmd(priv, 0x00000814, 0x00000008);
-        nv_icmd(priv, 0x00000815, 0x0000000b);
-        nv_icmd(priv, 0x00000800, 0x00000001);
-        nv_icmd(priv, 0x00000801, 0x00000001);
-        nv_icmd(priv, 0x00000802, 0x00000001);
-        nv_icmd(priv, 0x00000803, 0x00000001);
-        nv_icmd(priv, 0x00000804, 0x00000001);
-        nv_icmd(priv, 0x00000805, 0x00000001);
-        nv_icmd(priv, 0x00000632, 0x00000001);
-        nv_icmd(priv, 0x00000633, 0x00000002);
-        nv_icmd(priv, 0x00000634, 0x00000003);
-        nv_icmd(priv, 0x00000635, 0x00000004);
-        nv_icmd(priv, 0x00000654, 0x3f800000);
-        nv_icmd(priv, 0x00000657, 0x3f800000);
-        nv_icmd(priv, 0x00000655, 0x3f800000);
-        nv_icmd(priv, 0x00000656, 0x3f800000);
-        nv_icmd(priv, 0x000006cd, 0x3f800000);
-        nv_icmd(priv, 0x000007f5, 0x3f800000);
-        nv_icmd(priv, 0x000007dc, 0x39291909);
-        nv_icmd(priv, 0x000007dd, 0x79695949);
-        nv_icmd(priv, 0x000007de, 0xb9a99989);
-        nv_icmd(priv, 0x000007df, 0xf9e9d9c9);
-        nv_icmd(priv, 0x000007e8, 0x00003210);
-        nv_icmd(priv, 0x000007e9, 0x00007654);
-        nv_icmd(priv, 0x000007ea, 0x00000098);
-        nv_icmd(priv, 0x000007ec, 0x39291909);
-        nv_icmd(priv, 0x000007ed, 0x79695949);
-        nv_icmd(priv, 0x000007ee, 0xb9a99989);
-        nv_icmd(priv, 0x000007ef, 0xf9e9d9c9);
-        nv_icmd(priv, 0x000007f0, 0x00003210);
-        nv_icmd(priv, 0x000007f1, 0x00007654);
-        nv_icmd(priv, 0x000007f2, 0x00000098);
-        nv_icmd(priv, 0x000005a5, 0x00000001);
-        nv_icmd(priv, 0x00000980, 0x00000000);
-        nv_icmd(priv, 0x00000981, 0x00000000);
-        nv_icmd(priv, 0x00000982, 0x00000000);
-        nv_icmd(priv, 0x00000983, 0x00000000);
-        nv_icmd(priv, 0x00000984, 0x00000000);
-        nv_icmd(priv, 0x00000985, 0x00000000);
-        nv_icmd(priv, 0x00000986, 0x00000000);
-        nv_icmd(priv, 0x00000987, 0x00000000);
-        nv_icmd(priv, 0x00000988, 0x00000000);
-        nv_icmd(priv, 0x00000989, 0x00000000);
-        nv_icmd(priv, 0x0000098a, 0x00000000);
-        nv_icmd(priv, 0x0000098b, 0x00000000);
-        nv_icmd(priv, 0x0000098c, 0x00000000);
-        nv_icmd(priv, 0x0000098d, 0x00000000);
-        nv_icmd(priv, 0x0000098e, 0x00000000);
-        nv_icmd(priv, 0x0000098f, 0x00000000);
-        nv_icmd(priv, 0x00000990, 0x00000000);
-        nv_icmd(priv, 0x00000991, 0x00000000);
-        nv_icmd(priv, 0x00000992, 0x00000000);
-        nv_icmd(priv, 0x00000993, 0x00000000);
-        nv_icmd(priv, 0x00000994, 0x00000000);
-        nv_icmd(priv, 0x00000995, 0x00000000);
-        nv_icmd(priv, 0x00000996, 0x00000000);
-        nv_icmd(priv, 0x00000997, 0x00000000);
-        nv_icmd(priv, 0x00000998, 0x00000000);
-        nv_icmd(priv, 0x00000999, 0x00000000);
-        nv_icmd(priv, 0x0000099a, 0x00000000);
-        nv_icmd(priv, 0x0000099b, 0x00000000);
-        nv_icmd(priv, 0x0000099c, 0x00000000);
-        nv_icmd(priv, 0x0000099d, 0x00000000);
-        nv_icmd(priv, 0x0000099e, 0x00000000);
-        nv_icmd(priv, 0x0000099f, 0x00000000);
-        nv_icmd(priv, 0x000009a0, 0x00000000);
-        nv_icmd(priv, 0x000009a1, 0x00000000);
-        nv_icmd(priv, 0x000009a2, 0x00000000);
-        nv_icmd(priv, 0x000009a3, 0x00000000);
-        nv_icmd(priv, 0x000009a4, 0x00000000);
-        nv_icmd(priv, 0x000009a5, 0x00000000);
-        nv_icmd(priv, 0x000009a6, 0x00000000);
-        nv_icmd(priv, 0x000009a7, 0x00000000);
-        nv_icmd(priv, 0x000009a8, 0x00000000);
-        nv_icmd(priv, 0x000009a9, 0x00000000);
-        nv_icmd(priv, 0x000009aa, 0x00000000);
-        nv_icmd(priv, 0x000009ab, 0x00000000);
-        nv_icmd(priv, 0x000009ac, 0x00000000);
-        nv_icmd(priv, 0x000009ad, 0x00000000);
-        nv_icmd(priv, 0x000009ae, 0x00000000);
-        nv_icmd(priv, 0x000009af, 0x00000000);
-        nv_icmd(priv, 0x000009b0, 0x00000000);
-        nv_icmd(priv, 0x000009b1, 0x00000000);
-        nv_icmd(priv, 0x000009b2, 0x00000000);
-        nv_icmd(priv, 0x000009b3, 0x00000000);
-        nv_icmd(priv, 0x000009b4, 0x00000000);
-        nv_icmd(priv, 0x000009b5, 0x00000000);
-        nv_icmd(priv, 0x000009b6, 0x00000000);
-        nv_icmd(priv, 0x000009b7, 0x00000000);
-        nv_icmd(priv, 0x000009b8, 0x00000000);
-        nv_icmd(priv, 0x000009b9, 0x00000000);
-        nv_icmd(priv, 0x000009ba, 0x00000000);
-        nv_icmd(priv, 0x000009bb, 0x00000000);
-        nv_icmd(priv, 0x000009bc, 0x00000000);
-        nv_icmd(priv, 0x000009bd, 0x00000000);
-        nv_icmd(priv, 0x000009be, 0x00000000);
-        nv_icmd(priv, 0x000009bf, 0x00000000);
-        nv_icmd(priv, 0x000009c0, 0x00000000);
-        nv_icmd(priv, 0x000009c1, 0x00000000);
-        nv_icmd(priv, 0x000009c2, 0x00000000);
-        nv_icmd(priv, 0x000009c3, 0x00000000);
-        nv_icmd(priv, 0x000009c4, 0x00000000);
-        nv_icmd(priv, 0x000009c5, 0x00000000);
-        nv_icmd(priv, 0x000009c6, 0x00000000);
-        nv_icmd(priv, 0x000009c7, 0x00000000);
-        nv_icmd(priv, 0x000009c8, 0x00000000);
-        nv_icmd(priv, 0x000009c9, 0x00000000);
-        nv_icmd(priv, 0x000009ca, 0x00000000);
-        nv_icmd(priv, 0x000009cb, 0x00000000);
-        nv_icmd(priv, 0x000009cc, 0x00000000);
-        nv_icmd(priv, 0x000009cd, 0x00000000);
-        nv_icmd(priv, 0x000009ce, 0x00000000);
-        nv_icmd(priv, 0x000009cf, 0x00000000);
-        nv_icmd(priv, 0x000009d0, 0x00000000);
-        nv_icmd(priv, 0x000009d1, 0x00000000);
-        nv_icmd(priv, 0x000009d2, 0x00000000);
-        nv_icmd(priv, 0x000009d3, 0x00000000);
-        nv_icmd(priv, 0x000009d4, 0x00000000);
-        nv_icmd(priv, 0x000009d5, 0x00000000);
-        nv_icmd(priv, 0x000009d6, 0x00000000);
-        nv_icmd(priv, 0x000009d7, 0x00000000);
-        nv_icmd(priv, 0x000009d8, 0x00000000);
-        nv_icmd(priv, 0x000009d9, 0x00000000);
-        nv_icmd(priv, 0x000009da, 0x00000000);
-        nv_icmd(priv, 0x000009db, 0x00000000);
-        nv_icmd(priv, 0x000009dc, 0x00000000);
-        nv_icmd(priv, 0x000009dd, 0x00000000);
-        nv_icmd(priv, 0x000009de, 0x00000000);
-        nv_icmd(priv, 0x000009df, 0x00000000);
-        nv_icmd(priv, 0x000009e0, 0x00000000);
-        nv_icmd(priv, 0x000009e1, 0x00000000);
-        nv_icmd(priv, 0x000009e2, 0x00000000);
-        nv_icmd(priv, 0x000009e3, 0x00000000);
-        nv_icmd(priv, 0x000009e4, 0x00000000);
-        nv_icmd(priv, 0x000009e5, 0x00000000);
-        nv_icmd(priv, 0x000009e6, 0x00000000);
-        nv_icmd(priv, 0x000009e7, 0x00000000);
-        nv_icmd(priv, 0x000009e8, 0x00000000);
-        nv_icmd(priv, 0x000009e9, 0x00000000);
-        nv_icmd(priv, 0x000009ea, 0x00000000);
-        nv_icmd(priv, 0x000009eb, 0x00000000);
-        nv_icmd(priv, 0x000009ec, 0x00000000);
-        nv_icmd(priv, 0x000009ed, 0x00000000);
-        nv_icmd(priv, 0x000009ee, 0x00000000);
-        nv_icmd(priv, 0x000009ef, 0x00000000);
-        nv_icmd(priv, 0x000009f0, 0x00000000);
-        nv_icmd(priv, 0x000009f1, 0x00000000);
-        nv_icmd(priv, 0x000009f2, 0x00000000);
-        nv_icmd(priv, 0x000009f3, 0x00000000);
-        nv_icmd(priv, 0x000009f4, 0x00000000);
-        nv_icmd(priv, 0x000009f5, 0x00000000);
-        nv_icmd(priv, 0x000009f6, 0x00000000);
-        nv_icmd(priv, 0x000009f7, 0x00000000);
-        nv_icmd(priv, 0x000009f8, 0x00000000);
-        nv_icmd(priv, 0x000009f9, 0x00000000);
-        nv_icmd(priv, 0x000009fa, 0x00000000);
-        nv_icmd(priv, 0x000009fb, 0x00000000);
-        nv_icmd(priv, 0x000009fc, 0x00000000);
-        nv_icmd(priv, 0x000009fd, 0x00000000);
-        nv_icmd(priv, 0x000009fe, 0x00000000);
-        nv_icmd(priv, 0x000009ff, 0x00000000);
-        nv_icmd(priv, 0x00000468, 0x00000004);
-        nv_icmd(priv, 0x0000046c, 0x00000001);
-        nv_icmd(priv, 0x00000470, 0x00000000);
-        nv_icmd(priv, 0x00000471, 0x00000000);
-        nv_icmd(priv, 0x00000472, 0x00000000);
-        nv_icmd(priv, 0x00000473, 0x00000000);
-        nv_icmd(priv, 0x00000474, 0x00000000);
-        nv_icmd(priv, 0x00000475, 0x00000000);
-        nv_icmd(priv, 0x00000476, 0x00000000);
-        nv_icmd(priv, 0x00000477, 0x00000000);
-        nv_icmd(priv, 0x00000478, 0x00000000);
-        nv_icmd(priv, 0x00000479, 0x00000000);
-        nv_icmd(priv, 0x0000047a, 0x00000000);
-        nv_icmd(priv, 0x0000047b, 0x00000000);
-        nv_icmd(priv, 0x0000047c, 0x00000000);
-        nv_icmd(priv, 0x0000047d, 0x00000000);
-        nv_icmd(priv, 0x0000047e, 0x00000000);
-        nv_icmd(priv, 0x0000047f, 0x00000000);
-        nv_icmd(priv, 0x00000480, 0x00000000);
-        nv_icmd(priv, 0x00000481, 0x00000000);
-        nv_icmd(priv, 0x00000482, 0x00000000);
-        nv_icmd(priv, 0x00000483, 0x00000000);
-        nv_icmd(priv, 0x00000484, 0x00000000);
-        nv_icmd(priv, 0x00000485, 0x00000000);
-        nv_icmd(priv, 0x00000486, 0x00000000);
-        nv_icmd(priv, 0x00000487, 0x00000000);
-        nv_icmd(priv, 0x00000488, 0x00000000);
-        nv_icmd(priv, 0x00000489, 0x00000000);
-        nv_icmd(priv, 0x0000048a, 0x00000000);
-        nv_icmd(priv, 0x0000048b, 0x00000000);
-        nv_icmd(priv, 0x0000048c, 0x00000000);
-        nv_icmd(priv, 0x0000048d, 0x00000000);
-        nv_icmd(priv, 0x0000048e, 0x00000000);
-        nv_icmd(priv, 0x0000048f, 0x00000000);
-        nv_icmd(priv, 0x00000490, 0x00000000);
-        nv_icmd(priv, 0x00000491, 0x00000000);
-        nv_icmd(priv, 0x00000492, 0x00000000);
-        nv_icmd(priv, 0x00000493, 0x00000000);
-        nv_icmd(priv, 0x00000494, 0x00000000);
-        nv_icmd(priv, 0x00000495, 0x00000000);
-        nv_icmd(priv, 0x00000496, 0x00000000);
-        nv_icmd(priv, 0x00000497, 0x00000000);
-        nv_icmd(priv, 0x00000498, 0x00000000);
-        nv_icmd(priv, 0x00000499, 0x00000000);
-        nv_icmd(priv, 0x0000049a, 0x00000000);
-        nv_icmd(priv, 0x0000049b, 0x00000000);
-        nv_icmd(priv, 0x0000049c, 0x00000000);
-        nv_icmd(priv, 0x0000049d, 0x00000000);
-        nv_icmd(priv, 0x0000049e, 0x00000000);
-        nv_icmd(priv, 0x0000049f, 0x00000000);
-        nv_icmd(priv, 0x000004a0, 0x00000000);
-        nv_icmd(priv, 0x000004a1, 0x00000000);
-        nv_icmd(priv, 0x000004a2, 0x00000000);
-        nv_icmd(priv, 0x000004a3, 0x00000000);
-        nv_icmd(priv, 0x000004a4, 0x00000000);
-        nv_icmd(priv, 0x000004a5, 0x00000000);
-        nv_icmd(priv, 0x000004a6, 0x00000000);
-        nv_icmd(priv, 0x000004a7, 0x00000000);
-        nv_icmd(priv, 0x000004a8, 0x00000000);
-        nv_icmd(priv, 0x000004a9, 0x00000000);
-        nv_icmd(priv, 0x000004aa, 0x00000000);
-        nv_icmd(priv, 0x000004ab, 0x00000000);
-        nv_icmd(priv, 0x000004ac, 0x00000000);
-        nv_icmd(priv, 0x000004ad, 0x00000000);
-        nv_icmd(priv, 0x000004ae, 0x00000000);
-        nv_icmd(priv, 0x000004af, 0x00000000);
-        nv_icmd(priv, 0x000004b0, 0x00000000);
-        nv_icmd(priv, 0x000004b1, 0x00000000);
-        nv_icmd(priv, 0x000004b2, 0x00000000);
-        nv_icmd(priv, 0x000004b3, 0x00000000);
-        nv_icmd(priv, 0x000004b4, 0x00000000);
-        nv_icmd(priv, 0x000004b5, 0x00000000);
-        nv_icmd(priv, 0x000004b6, 0x00000000);
-        nv_icmd(priv, 0x000004b7, 0x00000000);
-        nv_icmd(priv, 0x000004b8, 0x00000000);
-        nv_icmd(priv, 0x000004b9, 0x00000000);
-        nv_icmd(priv, 0x000004ba, 0x00000000);
-        nv_icmd(priv, 0x000004bb, 0x00000000);
-        nv_icmd(priv, 0x000004bc, 0x00000000);
-        nv_icmd(priv, 0x000004bd, 0x00000000);
-        nv_icmd(priv, 0x000004be, 0x00000000);
-        nv_icmd(priv, 0x000004bf, 0x00000000);
-        nv_icmd(priv, 0x000004c0, 0x00000000);
-        nv_icmd(priv, 0x000004c1, 0x00000000);
-        nv_icmd(priv, 0x000004c2, 0x00000000);
-        nv_icmd(priv, 0x000004c3, 0x00000000);
-        nv_icmd(priv, 0x000004c4, 0x00000000);
-        nv_icmd(priv, 0x000004c5, 0x00000000);
-        nv_icmd(priv, 0x000004c6, 0x00000000);
-        nv_icmd(priv, 0x000004c7, 0x00000000);
-        nv_icmd(priv, 0x000004c8, 0x00000000);
-        nv_icmd(priv, 0x000004c9, 0x00000000);
-        nv_icmd(priv, 0x000004ca, 0x00000000);
-        nv_icmd(priv, 0x000004cb, 0x00000000);
-        nv_icmd(priv, 0x000004cc, 0x00000000);
-        nv_icmd(priv, 0x000004cd, 0x00000000);
-        nv_icmd(priv, 0x000004ce, 0x00000000);
-        nv_icmd(priv, 0x000004cf, 0x00000000);
-        nv_icmd(priv, 0x00000510, 0x3f800000);
-        nv_icmd(priv, 0x00000511, 0x3f800000);
-        nv_icmd(priv, 0x00000512, 0x3f800000);
-        nv_icmd(priv, 0x00000513, 0x3f800000);
-        nv_icmd(priv, 0x00000514, 0x3f800000);
-        nv_icmd(priv, 0x00000515, 0x3f800000);
-        nv_icmd(priv, 0x00000516, 0x3f800000);
-        nv_icmd(priv, 0x00000517, 0x3f800000);
-        nv_icmd(priv, 0x00000518, 0x3f800000);
-        nv_icmd(priv, 0x00000519, 0x3f800000);
-        nv_icmd(priv, 0x0000051a, 0x3f800000);
-        nv_icmd(priv, 0x0000051b, 0x3f800000);
-        nv_icmd(priv, 0x0000051c, 0x3f800000);
-        nv_icmd(priv, 0x0000051d, 0x3f800000);
-        nv_icmd(priv, 0x0000051e, 0x3f800000);
-        nv_icmd(priv, 0x0000051f, 0x3f800000);
-        nv_icmd(priv, 0x00000520, 0x000002b6);
-        nv_icmd(priv, 0x00000529, 0x00000001);
-        nv_icmd(priv, 0x00000530, 0xffff0000);
-        nv_icmd(priv, 0x00000531, 0xffff0000);
-        nv_icmd(priv, 0x00000532, 0xffff0000);
-        nv_icmd(priv, 0x00000533, 0xffff0000);
-        nv_icmd(priv, 0x00000534, 0xffff0000);
-        nv_icmd(priv, 0x00000535, 0xffff0000);
-        nv_icmd(priv, 0x00000536, 0xffff0000);
-        nv_icmd(priv, 0x00000537, 0xffff0000);
-        nv_icmd(priv, 0x00000538, 0xffff0000);
-        nv_icmd(priv, 0x00000539, 0xffff0000);
-        nv_icmd(priv, 0x0000053a, 0xffff0000);
-        nv_icmd(priv, 0x0000053b, 0xffff0000);
-        nv_icmd(priv, 0x0000053c, 0xffff0000);
-        nv_icmd(priv, 0x0000053d, 0xffff0000);
-        nv_icmd(priv, 0x0000053e, 0xffff0000);
-        nv_icmd(priv, 0x0000053f, 0xffff0000);
-        nv_icmd(priv, 0x00000585, 0x0000003f);
-        nv_icmd(priv, 0x00000576, 0x00000003);
-        if (nv_device(priv)->chipset == 0xc1 ||
-            nv_device(priv)->chipset >= 0xd0)
-                nv_icmd(priv, 0x0000057b, 0x00000059);
-        nv_icmd(priv, 0x00000586, 0x00000040);
-        nv_icmd(priv, 0x00000582, 0x00000080);
-        nv_icmd(priv, 0x00000583, 0x00000080);
-        nv_icmd(priv, 0x000005c2, 0x00000001);
-        nv_icmd(priv, 0x00000638, 0x00000001);
-        nv_icmd(priv, 0x00000639, 0x00000001);
-        nv_icmd(priv, 0x0000063a, 0x00000002);
-        nv_icmd(priv, 0x0000063b, 0x00000001);
-        nv_icmd(priv, 0x0000063c, 0x00000001);
-        nv_icmd(priv, 0x0000063d, 0x00000002);
-        nv_icmd(priv, 0x0000063e, 0x00000001);
-        nv_icmd(priv, 0x000008b8, 0x00000001);
-        nv_icmd(priv, 0x000008b9, 0x00000001);
-        nv_icmd(priv, 0x000008ba, 0x00000001);
-        nv_icmd(priv, 0x000008bb, 0x00000001);
-        nv_icmd(priv, 0x000008bc, 0x00000001);
-        nv_icmd(priv, 0x000008bd, 0x00000001);
-        nv_icmd(priv, 0x000008be, 0x00000001);
-        nv_icmd(priv, 0x000008bf, 0x00000001);
-        nv_icmd(priv, 0x00000900, 0x00000001);
-        nv_icmd(priv, 0x00000901, 0x00000001);
-        nv_icmd(priv, 0x00000902, 0x00000001);
-        nv_icmd(priv, 0x00000903, 0x00000001);
-        nv_icmd(priv, 0x00000904, 0x00000001);
-        nv_icmd(priv, 0x00000905, 0x00000001);
-        nv_icmd(priv, 0x00000906, 0x00000001);
-        nv_icmd(priv, 0x00000907, 0x00000001);
-        nv_icmd(priv, 0x00000908, 0x00000002);
-        nv_icmd(priv, 0x00000909, 0x00000002);
-        nv_icmd(priv, 0x0000090a, 0x00000002);
-        nv_icmd(priv, 0x0000090b, 0x00000002);
-        nv_icmd(priv, 0x0000090c, 0x00000002);
-        nv_icmd(priv, 0x0000090d, 0x00000002);
-        nv_icmd(priv, 0x0000090e, 0x00000002);
-        nv_icmd(priv, 0x0000090f, 0x00000002);
-        nv_icmd(priv, 0x00000910, 0x00000001);
-        nv_icmd(priv, 0x00000911, 0x00000001);
-        nv_icmd(priv, 0x00000912, 0x00000001);
-        nv_icmd(priv, 0x00000913, 0x00000001);
-        nv_icmd(priv, 0x00000914, 0x00000001);
-        nv_icmd(priv, 0x00000915, 0x00000001);
-        nv_icmd(priv, 0x00000916, 0x00000001);
-        nv_icmd(priv, 0x00000917, 0x00000001);
-        nv_icmd(priv, 0x00000918, 0x00000001);
-        nv_icmd(priv, 0x00000919, 0x00000001);
-        nv_icmd(priv, 0x0000091a, 0x00000001);
-        nv_icmd(priv, 0x0000091b, 0x00000001);
-        nv_icmd(priv, 0x0000091c, 0x00000001);
-        nv_icmd(priv, 0x0000091d, 0x00000001);
-        nv_icmd(priv, 0x0000091e, 0x00000001);
-        nv_icmd(priv, 0x0000091f, 0x00000001);
-        nv_icmd(priv, 0x00000920, 0x00000002);
-        nv_icmd(priv, 0x00000921, 0x00000002);
-        nv_icmd(priv, 0x00000922, 0x00000002);
-        nv_icmd(priv, 0x00000923, 0x00000002);
-        nv_icmd(priv, 0x00000924, 0x00000002);
-        nv_icmd(priv, 0x00000925, 0x00000002);
-        nv_icmd(priv, 0x00000926, 0x00000002);
-        nv_icmd(priv, 0x00000927, 0x00000002);
-        nv_icmd(priv, 0x00000928, 0x00000001);
-        nv_icmd(priv, 0x00000929, 0x00000001);
-        nv_icmd(priv, 0x0000092a, 0x00000001);
-        nv_icmd(priv, 0x0000092b, 0x00000001);
-        nv_icmd(priv, 0x0000092c, 0x00000001);
-        nv_icmd(priv, 0x0000092d, 0x00000001);
-        nv_icmd(priv, 0x0000092e, 0x00000001);
-        nv_icmd(priv, 0x0000092f, 0x00000001);
-        nv_icmd(priv, 0x00000648, 0x00000001);
-        nv_icmd(priv, 0x00000649, 0x00000001);
-        nv_icmd(priv, 0x0000064a, 0x00000001);
-        nv_icmd(priv, 0x0000064b, 0x00000001);
-        nv_icmd(priv, 0x0000064c, 0x00000001);
-        nv_icmd(priv, 0x0000064d, 0x00000001);
-        nv_icmd(priv, 0x0000064e, 0x00000001);
-        nv_icmd(priv, 0x0000064f, 0x00000001);
-        nv_icmd(priv, 0x00000650, 0x00000001);
-        nv_icmd(priv, 0x00000658, 0x0000000f);
-        nv_icmd(priv, 0x000007ff, 0x0000000a);
-        nv_icmd(priv, 0x0000066a, 0x40000000);
-        nv_icmd(priv, 0x0000066b, 0x10000000);
-        nv_icmd(priv, 0x0000066c, 0xffff0000);
-        nv_icmd(priv, 0x0000066d, 0xffff0000);
-        nv_icmd(priv, 0x000007af, 0x00000008);
-        nv_icmd(priv, 0x000007b0, 0x00000008);
-        nv_icmd(priv, 0x000007f6, 0x00000001);
-        nv_icmd(priv, 0x000006b2, 0x00000055);
-        nv_icmd(priv, 0x000007ad, 0x00000003);
-        nv_icmd(priv, 0x00000937, 0x00000001);
-        nv_icmd(priv, 0x00000971, 0x00000008);
-        nv_icmd(priv, 0x00000972, 0x00000040);
-        nv_icmd(priv, 0x00000973, 0x0000012c);
-        nv_icmd(priv, 0x0000097c, 0x00000040);
-        nv_icmd(priv, 0x00000979, 0x00000003);
-        nv_icmd(priv, 0x00000975, 0x00000020);
-        nv_icmd(priv, 0x00000976, 0x00000001);
-        nv_icmd(priv, 0x00000977, 0x00000020);
-        nv_icmd(priv, 0x00000978, 0x00000001);
-        nv_icmd(priv, 0x00000957, 0x00000003);
-        nv_icmd(priv, 0x0000095e, 0x20164010);
-        nv_icmd(priv, 0x0000095f, 0x00000020);
-        if (nv_device(priv)->chipset >= 0xd0)
-                nv_icmd(priv, 0x0000097d, 0x00000020);
-        nv_icmd(priv, 0x00000683, 0x00000006);
-        nv_icmd(priv, 0x00000685, 0x003fffff);
-        nv_icmd(priv, 0x00000687, 0x00000c48);
-        nv_icmd(priv, 0x000006a0, 0x00000005);
-        nv_icmd(priv, 0x00000840, 0x00300008);
-        nv_icmd(priv, 0x00000841, 0x04000080);
-        nv_icmd(priv, 0x00000842, 0x00300008);
-        nv_icmd(priv, 0x00000843, 0x04000080);
-        nv_icmd(priv, 0x00000818, 0x00000000);
-        nv_icmd(priv, 0x00000819, 0x00000000);
-        nv_icmd(priv, 0x0000081a, 0x00000000);
-        nv_icmd(priv, 0x0000081b, 0x00000000);
-        nv_icmd(priv, 0x0000081c, 0x00000000);
-        nv_icmd(priv, 0x0000081d, 0x00000000);
-        nv_icmd(priv, 0x0000081e, 0x00000000);
-        nv_icmd(priv, 0x0000081f, 0x00000000);
-        nv_icmd(priv, 0x00000848, 0x00000000);
-        nv_icmd(priv, 0x00000849, 0x00000000);
-        nv_icmd(priv, 0x0000084a, 0x00000000);
-        nv_icmd(priv, 0x0000084b, 0x00000000);
-        nv_icmd(priv, 0x0000084c, 0x00000000);
-        nv_icmd(priv, 0x0000084d, 0x00000000);
-        nv_icmd(priv, 0x0000084e, 0x00000000);
-        nv_icmd(priv, 0x0000084f, 0x00000000);
-        nv_icmd(priv, 0x00000850, 0x00000000);
-        nv_icmd(priv, 0x00000851, 0x00000000);
-        nv_icmd(priv, 0x00000852, 0x00000000);
-        nv_icmd(priv, 0x00000853, 0x00000000);
-        nv_icmd(priv, 0x00000854, 0x00000000);
-        nv_icmd(priv, 0x00000855, 0x00000000);
-        nv_icmd(priv, 0x00000856, 0x00000000);
-        nv_icmd(priv, 0x00000857, 0x00000000);
-        nv_icmd(priv, 0x00000738, 0x00000000);
-        nv_icmd(priv, 0x000006aa, 0x00000001);
-        nv_icmd(priv, 0x000006ab, 0x00000002);
-        nv_icmd(priv, 0x000006ac, 0x00000080);
-        nv_icmd(priv, 0x000006ad, 0x00000100);
-        nv_icmd(priv, 0x000006ae, 0x00000100);
-        nv_icmd(priv, 0x000006b1, 0x00000011);
-        nv_icmd(priv, 0x000006bb, 0x000000cf);
-        nv_icmd(priv, 0x000006ce, 0x2a712488);
-        nv_icmd(priv, 0x00000739, 0x4085c000);
-        nv_icmd(priv, 0x0000073a, 0x00000080);
-        nv_icmd(priv, 0x00000786, 0x80000100);
-        nv_icmd(priv, 0x0000073c, 0x00010100);
-        nv_icmd(priv, 0x0000073d, 0x02800000);
-        nv_icmd(priv, 0x00000787, 0x000000cf);
-        nv_icmd(priv, 0x0000078c, 0x00000008);
-        nv_icmd(priv, 0x00000792, 0x00000001);
-        nv_icmd(priv, 0x00000794, 0x00000001);
-        nv_icmd(priv, 0x00000795, 0x00000001);
-        nv_icmd(priv, 0x00000796, 0x00000001);
-        nv_icmd(priv, 0x00000797, 0x000000cf);
-        nv_icmd(priv, 0x00000836, 0x00000001);
-        nv_icmd(priv, 0x0000079a, 0x00000002);
-        nv_icmd(priv, 0x00000833, 0x04444480);
-        nv_icmd(priv, 0x000007a1, 0x00000001);
-        nv_icmd(priv, 0x000007a3, 0x00000001);
-        nv_icmd(priv, 0x000007a4, 0x00000001);
-        nv_icmd(priv, 0x000007a5, 0x00000001);
-        nv_icmd(priv, 0x00000831, 0x00000004);
-        nv_icmd(priv, 0x0000080c, 0x00000002);
-        nv_icmd(priv, 0x0000080d, 0x00000100);
-        nv_icmd(priv, 0x0000080e, 0x00000100);
-        nv_icmd(priv, 0x0000080f, 0x00000001);
-        nv_icmd(priv, 0x00000823, 0x00000002);
-        nv_icmd(priv, 0x00000824, 0x00000100);
-        nv_icmd(priv, 0x00000825, 0x00000100);
-        nv_icmd(priv, 0x00000826, 0x00000001);
-        nv_icmd(priv, 0x0000095d, 0x00000001);
-        nv_icmd(priv, 0x0000082b, 0x00000004);
-        nv_icmd(priv, 0x00000942, 0x00010001);
-        nv_icmd(priv, 0x00000943, 0x00000001);
-        nv_icmd(priv, 0x00000944, 0x00000022);
-        nv_icmd(priv, 0x000007c5, 0x00010001);
-        nv_icmd(priv, 0x00000834, 0x00000001);
-        nv_icmd(priv, 0x000007c7, 0x00000001);
-        nv_icmd(priv, 0x0000c1b0, 0x0000000f);
-        nv_icmd(priv, 0x0000c1b1, 0x0000000f);
-        nv_icmd(priv, 0x0000c1b2, 0x0000000f);
-        nv_icmd(priv, 0x0000c1b3, 0x0000000f);
-        nv_icmd(priv, 0x0000c1b4, 0x0000000f);
-        nv_icmd(priv, 0x0000c1b5, 0x0000000f);
-        nv_icmd(priv, 0x0000c1b6, 0x0000000f);
-        nv_icmd(priv, 0x0000c1b7, 0x0000000f);
-        nv_icmd(priv, 0x0000c1b8, 0x0fac6881);
-        nv_icmd(priv, 0x0000c1b9, 0x00fac688);
-        nv_icmd(priv, 0x0001e100, 0x00000001);
-        nv_icmd(priv, 0x00001000, 0x00000002);
-        nv_icmd(priv, 0x000006aa, 0x00000001);
-        nv_icmd(priv, 0x000006ad, 0x00000100);
-        nv_icmd(priv, 0x000006ae, 0x00000100);
-        nv_icmd(priv, 0x000006b1, 0x00000011);
-        nv_icmd(priv, 0x0000078c, 0x00000008);
-        nv_icmd(priv, 0x00000792, 0x00000001);
-        nv_icmd(priv, 0x00000794, 0x00000001);
-        nv_icmd(priv, 0x00000795, 0x00000001);
-        nv_icmd(priv, 0x00000796, 0x00000001);
-        nv_icmd(priv, 0x00000797, 0x000000cf);
-        nv_icmd(priv, 0x0000079a, 0x00000002);
-        nv_icmd(priv, 0x00000833, 0x04444480);
-        nv_icmd(priv, 0x000007a1, 0x00000001);
-        nv_icmd(priv, 0x000007a3, 0x00000001);
-        nv_icmd(priv, 0x000007a4, 0x00000001);
-        nv_icmd(priv, 0x000007a5, 0x00000001);
-        nv_icmd(priv, 0x00000831, 0x00000004);
-        nv_icmd(priv, 0x0001e100, 0x00000001);
-        nv_icmd(priv, 0x00001000, 0x00000014);
-        nv_icmd(priv, 0x00000351, 0x00000100);
-        nv_icmd(priv, 0x00000957, 0x00000003);
-        nv_icmd(priv, 0x0000095d, 0x00000001);
-        nv_icmd(priv, 0x0000082b, 0x00000004);
-        nv_icmd(priv, 0x00000942, 0x00010001);
-        nv_icmd(priv, 0x00000943, 0x00000001);
-        nv_icmd(priv, 0x000007c5, 0x00010001);
-        nv_icmd(priv, 0x00000834, 0x00000001);
-        nv_icmd(priv, 0x000007c7, 0x00000001);
-        nv_icmd(priv, 0x0001e100, 0x00000001);
-        nv_icmd(priv, 0x00001000, 0x00000001);
-        nv_icmd(priv, 0x0000080c, 0x00000002);
-        nv_icmd(priv, 0x0000080d, 0x00000100);
-        nv_icmd(priv, 0x0000080e, 0x00000100);
-        nv_icmd(priv, 0x0000080f, 0x00000001);
-        nv_icmd(priv, 0x00000823, 0x00000002);
-        nv_icmd(priv, 0x00000824, 0x00000100);
-        nv_icmd(priv, 0x00000825, 0x00000100);
-        nv_icmd(priv, 0x00000826, 0x00000001);
-        nv_icmd(priv, 0x0001e100, 0x00000001);
-        nv_wr32(priv, 0x400208, 0x00000000);
-        nv_wr32(priv, 0x404154, 0x00000400);
-
-        nvc0_grctx_generate_9097(priv);
-        if (fermi >= 0x9197)
-                nvc0_grctx_generate_9197(priv);
-        if (fermi >= 0x9297)
-                nvc0_grctx_generate_9297(priv);
-        nvc0_grctx_generate_902d(priv);
-        nvc0_grctx_generate_9039(priv);
-        nvc0_grctx_generate_90c0(priv);
 
-        nv_wr32(priv, 0x000260, r000260);
-
-        return nvc0_grctx_fini(&info);
+done:
+        nouveau_gpuobj_ref(NULL, &chan);
+        return ret;
 }
+
+struct nvc0_graph_init *
+nvc0_grctx_init_hub[] = {
+        nvc0_grctx_init_base,
+        nvc0_grctx_init_unk40xx,
+        nvc0_grctx_init_unk44xx,
+        nvc0_grctx_init_unk46xx,
+        nvc0_grctx_init_unk47xx,
+        nvc0_grctx_init_unk58xx,
+        nvc0_grctx_init_unk60xx,
+        nvc0_grctx_init_unk64xx,
+        nvc0_grctx_init_unk78xx,
+        nvc0_grctx_init_unk80xx,
+        nvc0_grctx_init_rop,
+        NULL
+};
+
+static struct nvc0_graph_init *
+nvc0_grctx_init_gpc[] = {
+        nvc0_grctx_init_gpc_0,
+        nvc0_grctx_init_gpc_1,
+        nvc0_grctx_init_tpc,
+        NULL
+};
+
+struct nvc0_graph_init
+nvc0_grctx_init_mthd_magic[] = {
+        { 0x3410, 1, 0x04, 0x00000000 },
+        {}
+};
+
+struct nvc0_graph_mthd
+nvc0_grctx_init_mthd[] = {
+        { 0x9097, nvc0_grctx_init_9097, },
+        { 0x902d, nvc0_grctx_init_902d, },
+        { 0x9039, nvc0_grctx_init_9039, },
+        { 0x90c0, nvc0_grctx_init_90c0, },
+        { 0x902d, nvc0_grctx_init_mthd_magic, },
+        {}
+};
+
+struct nouveau_oclass *
+nvc0_grctx_oclass = &(struct nvc0_grctx_oclass) {
+        .base.handle = NV_ENGCTX(GR, 0xc0),
+        .base.ofuncs = &(struct nouveau_ofuncs) {
+                .ctor = nvc0_graph_context_ctor,
+                .dtor = nvc0_graph_context_dtor,
+                .init = _nouveau_graph_context_init,
+                .fini = _nouveau_graph_context_fini,
+                .rd32 = _nouveau_graph_context_rd32,
+                .wr32 = _nouveau_graph_context_wr32,
+        },
+        .main = nvc0_grctx_generate_main,
+        .mods = nvc0_grctx_generate_mods,
+        .unkn = nvc0_grctx_generate_unkn,
+        .hub  = nvc0_grctx_init_hub,
+        .gpc  = nvc0_grctx_init_gpc,
+        .icmd = nvc0_grctx_init_icmd,
+        .mthd = nvc0_grctx_init_mthd,
+}.base;
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc1.c b/drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc1.c
new file mode 100644
index 000000000000..e5be3ee7f172
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc1.c
@@ -0,0 +1,823 @@
+/*
+ * Copyright 2013 Red Hat Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Ben Skeggs <bskeggs@redhat.com>
+ */
+
+#include "nvc0.h"
+
+static struct nvc0_graph_init
+nvc1_grctx_init_icmd[] = {
+        { 0x001000,   1, 0x01, 0x00000004 },
+        { 0x0000a9,   1, 0x01, 0x0000ffff },
+        { 0x000038,   1, 0x01, 0x0fac6881 },
+        { 0x00003d,   1, 0x01, 0x00000001 },
+        { 0x0000e8,   8, 0x01, 0x00000400 },
+        { 0x000078,   8, 0x01, 0x00000300 },
+        { 0x000050,   1, 0x01, 0x00000011 },
+        { 0x000058,   8, 0x01, 0x00000008 },
+        { 0x000208,   8, 0x01, 0x00000001 },
+        { 0x000081,   1, 0x01, 0x00000001 },
+        { 0x000085,   1, 0x01, 0x00000004 },
+        { 0x000088,   1, 0x01, 0x00000400 },
+        { 0x000090,   1, 0x01, 0x00000300 },
+        { 0x000098,   1, 0x01, 0x00001001 },
+        { 0x0000e3,   1, 0x01, 0x00000001 },
+        { 0x0000da,   1, 0x01, 0x00000001 },
+        { 0x0000f8,   1, 0x01, 0x00000003 },
+        { 0x0000fa,   1, 0x01, 0x00000001 },
+        { 0x00009f,   4, 0x01, 0x0000ffff },
+        { 0x0000b1,   1, 0x01, 0x00000001 },
+        { 0x0000b2,  40, 0x01, 0x00000000 },
+        { 0x000210,   8, 0x01, 0x00000040 },
+        { 0x000218,   8, 0x01, 0x0000c080 },
+        { 0x0000ad,   1, 0x01, 0x0000013e },
+        { 0x0000e1,   1, 0x01, 0x00000010 },
+        { 0x000290,  16, 0x01, 0x00000000 },
+        { 0x0003b0,  16, 0x01, 0x00000000 },
+        { 0x0002a0,  16, 0x01, 0x00000000 },
+        { 0x000420,  16, 0x01, 0x00000000 },
+        { 0x0002b0,  16, 0x01, 0x00000000 },
+        { 0x000430,  16, 0x01, 0x00000000 },
+        { 0x0002c0,  16, 0x01, 0x00000000 },
+        { 0x0004d0,  16, 0x01, 0x00000000 },
+        { 0x000720,  16, 0x01, 0x00000000 },
+        { 0x0008c0,  16, 0x01, 0x00000000 },
+        { 0x000890,  16, 0x01, 0x00000000 },
+        { 0x0008e0,  16, 0x01, 0x00000000 },
+        { 0x0008a0,  16, 0x01, 0x00000000 },
+        { 0x0008f0,  16, 0x01, 0x00000000 },
+        { 0x00094c,   1, 0x01, 0x000000ff },
+        { 0x00094d,   1, 0x01, 0xffffffff },
+        { 0x00094e,   1, 0x01, 0x00000002 },
+        { 0x0002ec,   1, 0x01, 0x00000001 },
+        { 0x000303,   1, 0x01, 0x00000001 },
+        { 0x0002e6,   1, 0x01, 0x00000001 },
+        { 0x000466,   1, 0x01, 0x00000052 },
+        { 0x000301,   1, 0x01, 0x3f800000 },
+        { 0x000304,   1, 0x01, 0x30201000 },
+        { 0x000305,   1, 0x01, 0x70605040 },
+        { 0x000306,   1, 0x01, 0xb8a89888 },
+        { 0x000307,   1, 0x01, 0xf8e8d8c8 },
+        { 0x00030a,   1, 0x01, 0x00ffff00 },
+        { 0x00030b,   1, 0x01, 0x0000001a },
+        { 0x00030c,   1, 0x01, 0x00000001 },
+        { 0x000318,   1, 0x01, 0x00000001 },
+        { 0x000340,   1, 0x01, 0x00000000 },
+        { 0x000375,   1, 0x01, 0x00000001 },
+        { 0x000351,   1, 0x01, 0x00000100 },
+        { 0x00037d,   1, 0x01, 0x00000006 },
+        { 0x0003a0,   1, 0x01, 0x00000002 },
+        { 0x0003aa,   1, 0x01, 0x00000001 },
+        { 0x0003a9,   1, 0x01, 0x00000001 },
+        { 0x000380,   1, 0x01, 0x00000001 },
+        { 0x000360,   1, 0x01, 0x00000040 },
+        { 0x000366,   2, 0x01, 0x00000000 },
+        { 0x000368,   1, 0x01, 0x00001fff },
+        { 0x000370,   2, 0x01, 0x00000000 },
+        { 0x000372,   1, 0x01, 0x003fffff },
+        { 0x00037a,   1, 0x01, 0x00000012 },
+        { 0x0005e0,   5, 0x01, 0x00000022 },
+        { 0x000619,   1, 0x01, 0x00000003 },
+        { 0x000811,   1, 0x01, 0x00000003 },
+        { 0x000812,   1, 0x01, 0x00000004 },
+        { 0x000813,   1, 0x01, 0x00000006 },
+        { 0x000814,   1, 0x01, 0x00000008 },
+        { 0x000815,   1, 0x01, 0x0000000b },
+        { 0x000800,   6, 0x01, 0x00000001 },
+        { 0x000632,   1, 0x01, 0x00000001 },
+        { 0x000633,   1, 0x01, 0x00000002 },
+        { 0x000634,   1, 0x01, 0x00000003 },
+        { 0x000635,   1, 0x01, 0x00000004 },
+        { 0x000654,   1, 0x01, 0x3f800000 },
+        { 0x000657,   1, 0x01, 0x3f800000 },
+        { 0x000655,   2, 0x01, 0x3f800000 },
+        { 0x0006cd,   1, 0x01, 0x3f800000 },
+        { 0x0007f5,   1, 0x01, 0x3f800000 },
+        { 0x0007dc,   1, 0x01, 0x39291909 },
+        { 0x0007dd,   1, 0x01, 0x79695949 },
+        { 0x0007de,   1, 0x01, 0xb9a99989 },
+        { 0x0007df,   1, 0x01, 0xf9e9d9c9 },
+        { 0x0007e8,   1, 0x01, 0x00003210 },
+        { 0x0007e9,   1, 0x01, 0x00007654 },
+        { 0x0007ea,   1, 0x01, 0x00000098 },
+        { 0x0007ec,   1, 0x01, 0x39291909 },
+        { 0x0007ed,   1, 0x01, 0x79695949 },
+        { 0x0007ee,   1, 0x01, 0xb9a99989 },
+        { 0x0007ef,   1, 0x01, 0xf9e9d9c9 },
+        { 0x0007f0,   1, 0x01, 0x00003210 },
+        { 0x0007f1,   1, 0x01, 0x00007654 },
+        { 0x0007f2,   1, 0x01, 0x00000098 },
+        { 0x0005a5,   1, 0x01, 0x00000001 },
+        { 0x000980, 128, 0x01, 0x00000000 },
+        { 0x000468,   1, 0x01, 0x00000004 },
+        { 0x00046c,   1, 0x01, 0x00000001 },
+        { 0x000470,  96, 0x01, 0x00000000 },
+        { 0x000510,  16, 0x01, 0x3f800000 },
+        { 0x000520,   1, 0x01, 0x000002b6 },
+        { 0x000529,   1, 0x01, 0x00000001 },
+        { 0x000530,  16, 0x01, 0xffff0000 },
+        { 0x000585,   1, 0x01, 0x0000003f },
+        { 0x000576,   1, 0x01, 0x00000003 },
+        { 0x00057b,   1, 0x01, 0x00000059 },
+        { 0x000586,   1, 0x01, 0x00000040 },
+        { 0x000582,   2, 0x01, 0x00000080 },
+        { 0x0005c2,   1, 0x01, 0x00000001 },
+        { 0x000638,   1, 0x01, 0x00000001 },
+        { 0x000639,   1, 0x01, 0x00000001 },
+        { 0x00063a,   1, 0x01, 0x00000002 },
+        { 0x00063b,   2, 0x01, 0x00000001 },
+        { 0x00063d,   1, 0x01, 0x00000002 },
+        { 0x00063e,   1, 0x01, 0x00000001 },
+        { 0x0008b8,   8, 0x01, 0x00000001 },
+        { 0x000900,   8, 0x01, 0x00000001 },
+        { 0x000908,   8, 0x01, 0x00000002 },
+        { 0x000910,  16, 0x01, 0x00000001 },
+        { 0x000920,   8, 0x01, 0x00000002 },
+        { 0x000928,   8, 0x01, 0x00000001 },
+        { 0x000648,   9, 0x01, 0x00000001 },
+        { 0x000658,   1, 0x01, 0x0000000f },
+        { 0x0007ff,   1, 0x01, 0x0000000a },
+        { 0x00066a,   1, 0x01, 0x40000000 },
+        { 0x00066b,   1, 0x01, 0x10000000 },
+        { 0x00066c,   2, 0x01, 0xffff0000 },
+        { 0x0007af,   2, 0x01, 0x00000008 },
+        { 0x0007f6,   1, 0x01, 0x00000001 },
+        { 0x0006b2,   1, 0x01, 0x00000055 },
+        { 0x0007ad,   1, 0x01, 0x00000003 },
+        { 0x000937,   1, 0x01, 0x00000001 },
+        { 0x000971,   1, 0x01, 0x00000008 },
+        { 0x000972,   1, 0x01, 0x00000040 },
+        { 0x000973,   1, 0x01, 0x0000012c },
+        { 0x00097c,   1, 0x01, 0x00000040 },
+        { 0x000979,   1, 0x01, 0x00000003 },
+        { 0x000975,   1, 0x01, 0x00000020 },
+        { 0x000976,   1, 0x01, 0x00000001 },
+        { 0x000977,   1, 0x01, 0x00000020 },
+        { 0x000978,   1, 0x01, 0x00000001 },
+        { 0x000957,   1, 0x01, 0x00000003 },
+        { 0x00095e,   1, 0x01, 0x20164010 },
+        { 0x00095f,   1, 0x01, 0x00000020 },
+        { 0x000683,   1, 0x01, 0x00000006 },
+        { 0x000685,   1, 0x01, 0x003fffff },
+        { 0x000687,   1, 0x01, 0x00000c48 },
+        { 0x0006a0,   1, 0x01, 0x00000005 },
+        { 0x000840,   1, 0x01, 0x00300008 },
+        { 0x000841,   1, 0x01, 0x04000080 },
+        { 0x000842,   1, 0x01, 0x00300008 },
+        { 0x000843,   1, 0x01, 0x04000080 },
+        { 0x000818,   8, 0x01, 0x00000000 },
+        { 0x000848,  16, 0x01, 0x00000000 },
+        { 0x000738,   1, 0x01, 0x00000000 },
+        { 0x0006aa,   1, 0x01, 0x00000001 },
+        { 0x0006ab,   1, 0x01, 0x00000002 },
+        { 0x0006ac,   1, 0x01, 0x00000080 },
+        { 0x0006ad,   2, 0x01, 0x00000100 },
+        { 0x0006b1,   1, 0x01, 0x00000011 },
+        { 0x0006bb,   1, 0x01, 0x000000cf },
+        { 0x0006ce,   1, 0x01, 0x2a712488 },
+        { 0x000739,   1, 0x01, 0x4085c000 },
+        { 0x00073a,   1, 0x01, 0x00000080 },
+        { 0x000786,   1, 0x01, 0x80000100 },
+        { 0x00073c,   1, 0x01, 0x00010100 },
+        { 0x00073d,   1, 0x01, 0x02800000 },
+        { 0x000787,   1, 0x01, 0x000000cf },
+        { 0x00078c,   1, 0x01, 0x00000008 },
+        { 0x000792,   1, 0x01, 0x00000001 },
+        { 0x000794,   1, 0x01, 0x00000001 },
+        { 0x000795,   2, 0x01, 0x00000001 },
+        { 0x000797,   1, 0x01, 0x000000cf },
+        { 0x000836,   1, 0x01, 0x00000001 },
+        { 0x00079a,   1, 0x01, 0x00000002 },
+        { 0x000833,   1, 0x01, 0x04444480 },
+        { 0x0007a1,   1, 0x01, 0x00000001 },
+        { 0x0007a3,   1, 0x01, 0x00000001 },
+        { 0x0007a4,   2, 0x01, 0x00000001 },
+        { 0x000831,   1, 0x01, 0x00000004 },
+        { 0x00080c,   1, 0x01, 0x00000002 },
+        { 0x00080d,   2, 0x01, 0x00000100 },
+        { 0x00080f,   1, 0x01, 0x00000001 },
+        { 0x000823,   1, 0x01, 0x00000002 },
+        { 0x000824,   2, 0x01, 0x00000100 },
+        { 0x000826,   1, 0x01, 0x00000001 },
+        { 0x00095d,   1, 0x01, 0x00000001 },
+        { 0x00082b,   1, 0x01, 0x00000004 },
+        { 0x000942,   1, 0x01, 0x00010001 },
+        { 0x000943,   1, 0x01, 0x00000001 },
+        { 0x000944,   1, 0x01, 0x00000022 },
+        { 0x0007c5,   1, 0x01, 0x00010001 },
+        { 0x000834,   1, 0x01, 0x00000001 },
+        { 0x0007c7,   1, 0x01, 0x00000001 },
+        { 0x00c1b0,   8, 0x01, 0x0000000f },
+        { 0x00c1b8,   1, 0x01, 0x0fac6881 },
+        { 0x00c1b9,   1, 0x01, 0x00fac688 },
+        { 0x01e100,   1, 0x01, 0x00000001 },
+        { 0x001000,   1, 0x01, 0x00000002 },
+        { 0x0006aa,   1, 0x01, 0x00000001 },
+        { 0x0006ad,   2, 0x01, 0x00000100 },
+        { 0x0006b1,   1, 0x01, 0x00000011 },
+        { 0x00078c,   1, 0x01, 0x00000008 },
+        { 0x000792,   1, 0x01, 0x00000001 },
+        { 0x000794,   1, 0x01, 0x00000001 },
+        { 0x000795,   2, 0x01, 0x00000001 },
+        { 0x000797,   1, 0x01, 0x000000cf },
+        { 0x00079a,   1, 0x01, 0x00000002 },
+        { 0x000833,   1, 0x01, 0x04444480 },
+        { 0x0007a1,   1, 0x01, 0x00000001 },
+        { 0x0007a3,   1, 0x01, 0x00000001 },
+        { 0x0007a4,   2, 0x01, 0x00000001 },
+        { 0x000831,   1, 0x01, 0x00000004 },
+        { 0x01e100,   1, 0x01, 0x00000001 },
+        { 0x001000,   1, 0x01, 0x00000014 },
+        { 0x000351,   1, 0x01, 0x00000100 },
+        { 0x000957,   1, 0x01, 0x00000003 },
+        { 0x00095d,   1, 0x01, 0x00000001 },
+        { 0x00082b,   1, 0x01, 0x00000004 },
+        { 0x000942,   1, 0x01, 0x00010001 },
+        { 0x000943,   1, 0x01, 0x00000001 },
+        { 0x0007c5,   1, 0x01, 0x00010001 },
+        { 0x000834,   1, 0x01, 0x00000001 },
+        { 0x0007c7,   1, 0x01, 0x00000001 },
+        { 0x01e100,   1, 0x01, 0x00000001 },
+        { 0x001000,   1, 0x01, 0x00000001 },
+        { 0x00080c,   1, 0x01, 0x00000002 },
+        { 0x00080d,   2, 0x01, 0x00000100 },
+        { 0x00080f,   1, 0x01, 0x00000001 },
+        { 0x000823,   1, 0x01, 0x00000002 },
+        { 0x000824,   2, 0x01, 0x00000100 },
+        { 0x000826,   1, 0x01, 0x00000001 },
+        { 0x01e100,   1, 0x01, 0x00000001 },
+        {}
+};
+
+struct nvc0_graph_init
+nvc1_grctx_init_9097[] = {
+        { 0x000800,   8, 0x40, 0x00000000 },
+        { 0x000804,   8, 0x40, 0x00000000 },
+        { 0x000808,   8, 0x40, 0x00000400 },
+        { 0x00080c,   8, 0x40, 0x00000300 },
+        { 0x000810,   1, 0x04, 0x000000cf },
+        { 0x000850,   7, 0x40, 0x00000000 },
+        { 0x000814,   8, 0x40, 0x00000040 },
+        { 0x000818,   8, 0x40, 0x00000001 },
+        { 0x00081c,   8, 0x40, 0x00000000 },
+        { 0x000820,   8, 0x40, 0x00000000 },
+        { 0x002700,   8, 0x20, 0x00000000 },
+        { 0x002704,   8, 0x20, 0x00000000 },
+        { 0x002708,   8, 0x20, 0x00000000 },
+        { 0x00270c,   8, 0x20, 0x00000000 },
+        { 0x002710,   8, 0x20, 0x00014000 },
+        { 0x002714,   8, 0x20, 0x00000040 },
+        { 0x001c00,  16, 0x10, 0x00000000 },
+        { 0x001c04,  16, 0x10, 0x00000000 },
+        { 0x001c08,  16, 0x10, 0x00000000 },
+        { 0x001c0c,  16, 0x10, 0x00000000 },
+        { 0x001d00,  16, 0x10, 0x00000000 },
+        { 0x001d04,  16, 0x10, 0x00000000 },
+        { 0x001d08,  16, 0x10, 0x00000000 },
+        { 0x001d0c,  16, 0x10, 0x00000000 },
+        { 0x001f00,  16, 0x08, 0x00000000 },
+        { 0x001f04,  16, 0x08, 0x00000000 },
+        { 0x001f80,  16, 0x08, 0x00000000 },
+        { 0x001f84,  16, 0x08, 0x00000000 },
+        { 0x002200,   5, 0x10, 0x00000022 },
+        { 0x002000,   1, 0x04, 0x00000000 },
+        { 0x002040,   1, 0x04, 0x00000011 },
+        { 0x002080,   1, 0x04, 0x00000020 },
+        { 0x0020c0,   1, 0x04, 0x00000030 },
+        { 0x002100,   1, 0x04, 0x00000040 },
+        { 0x002140,   1, 0x04, 0x00000051 },
+        { 0x00200c,   6, 0x40, 0x00000001 },
+        { 0x002010,   1, 0x04, 0x00000000 },
+        { 0x002050,   1, 0x04, 0x00000000 },
+        { 0x002090,   1, 0x04, 0x00000001 },
+        { 0x0020d0,   1, 0x04, 0x00000002 },
+        { 0x002110,   1, 0x04, 0x00000003 },
+        { 0x002150,   1, 0x04, 0x00000004 },
+        { 0x000380,   4, 0x20, 0x00000000 },
+        { 0x000384,   4, 0x20, 0x00000000 },
+        { 0x000388,   4, 0x20, 0x00000000 },
+        { 0x00038c,   4, 0x20, 0x00000000 },
+        { 0x000700,   4, 0x10, 0x00000000 },
+        { 0x000704,   4, 0x10, 0x00000000 },
+        { 0x000708,   4, 0x10, 0x00000000 },
+        { 0x002800, 128, 0x04, 0x00000000 },
+        { 0x000a00,  16, 0x20, 0x00000000 },
+        { 0x000a04,  16, 0x20, 0x00000000 },
+        { 0x000a08,  16, 0x20, 0x00000000 },
+        { 0x000a0c,  16, 0x20, 0x00000000 },
+        { 0x000a10,  16, 0x20, 0x00000000 },
+        { 0x000a14,  16, 0x20, 0x00000000 },
+        { 0x000c00,  16, 0x10, 0x00000000 },
+        { 0x000c04,  16, 0x10, 0x00000000 },
+        { 0x000c08,  16, 0x10, 0x00000000 },
+        { 0x000c0c,  16, 0x10, 0x3f800000 },
+        { 0x000d00,   8, 0x08, 0xffff0000 },
+        { 0x000d04,   8, 0x08, 0xffff0000 },
+        { 0x000e00,  16, 0x10, 0x00000000 },
+        { 0x000e04,  16, 0x10, 0xffff0000 },
+        { 0x000e08,  16, 0x10, 0xffff0000 },
+        { 0x000d40,   4, 0x08, 0x00000000 },
+        { 0x000d44,   4, 0x08, 0x00000000 },
+        { 0x001e00,   8, 0x20, 0x00000001 },
+        { 0x001e04,   8, 0x20, 0x00000001 },
+        { 0x001e08,   8, 0x20, 0x00000002 },
+        { 0x001e0c,   8, 0x20, 0x00000001 },
+        { 0x001e10,   8, 0x20, 0x00000001 },
+        { 0x001e14,   8, 0x20, 0x00000002 },
+        { 0x001e18,   8, 0x20, 0x00000001 },
+        { 0x00030c,   1, 0x04, 0x00000001 },
+        { 0x001944,   1, 0x04, 0x00000000 },
+        { 0x001514,   1, 0x04, 0x00000000 },
+        { 0x000d68,   1, 0x04, 0x0000ffff },
+        { 0x00121c,   1, 0x04, 0x0fac6881 },
+        { 0x000fac,   1, 0x04, 0x00000001 },
+        { 0x001538,   1, 0x04, 0x00000001 },
+        { 0x000fe0,   2, 0x04, 0x00000000 },
+        { 0x000fe8,   1, 0x04, 0x00000014 },
+        { 0x000fec,   1, 0x04, 0x00000040 },
+        { 0x000ff0,   1, 0x04, 0x00000000 },
+        { 0x00179c,   1, 0x04, 0x00000000 },
+        { 0x001228,   1, 0x04, 0x00000400 },
+        { 0x00122c,   1, 0x04, 0x00000300 },
+        { 0x001230,   1, 0x04, 0x00010001 },
+        { 0x0007f8,   1, 0x04, 0x00000000 },
+        { 0x0015b4,   1, 0x04, 0x00000001 },
+        { 0x0015cc,   1, 0x04, 0x00000000 },
+        { 0x001534,   1, 0x04, 0x00000000 },
+        { 0x000fb0,   1, 0x04, 0x00000000 },
+        { 0x0015d0,   1, 0x04, 0x00000000 },
+        { 0x00153c,   1, 0x04, 0x00000000 },
+        { 0x0016b4,   1, 0x04, 0x00000003 },
+        { 0x000fbc,   4, 0x04, 0x0000ffff },
+        { 0x000df8,   2, 0x04, 0x00000000 },
+        { 0x001948,   1, 0x04, 0x00000000 },
+        { 0x001970,   1, 0x04, 0x00000001 },
+        { 0x00161c,   1, 0x04, 0x000009f0 },
+        { 0x000dcc,   1, 0x04, 0x00000010 },
+        { 0x00163c,   1, 0x04, 0x00000000 },
+        { 0x0015e4,   1, 0x04, 0x00000000 },
+        { 0x001160,  32, 0x04, 0x25e00040 },
+        { 0x001880,  32, 0x04, 0x00000000 },
+        { 0x000f84,   2, 0x04, 0x00000000 },
+        { 0x0017c8,   2, 0x04, 0x00000000 },
+        { 0x0017d0,   1, 0x04, 0x000000ff },
+        { 0x0017d4,   1, 0x04, 0xffffffff },
+        { 0x0017d8,   1, 0x04, 0x00000002 },
+        { 0x0017dc,   1, 0x04, 0x00000000 },
+        { 0x0015f4,   2, 0x04, 0x00000000 },
+        { 0x001434,   2, 0x04, 0x00000000 },
+        { 0x000d74,   1, 0x04, 0x00000000 },
+        { 0x000dec,   1, 0x04, 0x00000001 },
+        { 0x0013a4,   1, 0x04, 0x00000000 },
+        { 0x001318,   1, 0x04, 0x00000001 },
+        { 0x001644,   1, 0x04, 0x00000000 },
+        { 0x000748,   1, 0x04, 0x00000000 },
+        { 0x000de8,   1, 0x04, 0x00000000 },
+        { 0x001648,   1, 0x04, 0x00000000 },
+        { 0x0012a4,   1, 0x04, 0x00000000 },
+        { 0x001120,   4, 0x04, 0x00000000 },
+        { 0x001118,   1, 0x04, 0x00000000 },
+        { 0x00164c,   1, 0x04, 0x00000000 },
+        { 0x001658,   1, 0x04, 0x00000000 },
+        { 0x001910,   1, 0x04, 0x00000290 },
+        { 0x001518,   1, 0x04, 0x00000000 },
+        { 0x00165c,   1, 0x04, 0x00000001 },
+        { 0x001520,   1, 0x04, 0x00000000 },
+        { 0x001604,   1, 0x04, 0x00000000 },
+        { 0x001570,   1, 0x04, 0x00000000 },
+        { 0x0013b0,   2, 0x04, 0x3f800000 },
+        { 0x00020c,   1, 0x04, 0x00000000 },
+        { 0x001670,   1, 0x04, 0x30201000 },
+        { 0x001674,   1, 0x04, 0x70605040 },
+        { 0x001678,   1, 0x04, 0xb8a89888 },
+        { 0x00167c,   1, 0x04, 0xf8e8d8c8 },
+        { 0x00166c,   1, 0x04, 0x00000000 },
+        { 0x001680,   1, 0x04, 0x00ffff00 },
+        { 0x0012d0,   1, 0x04, 0x00000003 },
+        { 0x0012d4,   1, 0x04, 0x00000002 },
+        { 0x001684,   2, 0x04, 0x00000000 },
+        { 0x000dac,   2, 0x04, 0x00001b02 },
+        { 0x000db4,   1, 0x04, 0x00000000 },
+        { 0x00168c,   1, 0x04, 0x00000000 },
+        { 0x0015bc,   1, 0x04, 0x00000000 },
+        { 0x00156c,   1, 0x04, 0x00000000 },
+        { 0x00187c,   1, 0x04, 0x00000000 },
+        { 0x001110,   1, 0x04, 0x00000001 },
+        { 0x000dc0,   3, 0x04, 0x00000000 },
+        { 0x001234,   1, 0x04, 0x00000000 },
+        { 0x001690,   1, 0x04, 0x00000000 },
+        { 0x0012ac,   1, 0x04, 0x00000001 },
+        { 0x0002c4,   1, 0x04, 0x00000000 },
+        { 0x000790,   5, 0x04, 0x00000000 },
+        { 0x00077c,   1, 0x04, 0x00000000 },
+        { 0x001000,   1, 0x04, 0x00000010 },
+        { 0x0010fc,   1, 0x04, 0x00000000 },
+        { 0x001290,   1, 0x04, 0x00000000 },
+        { 0x000218,   1, 0x04, 0x00000010 },
+        { 0x0012d8,   1, 0x04, 0x00000000 },
+        { 0x0012dc,   1, 0x04, 0x00000010 },
+        { 0x000d94,   1, 0x04, 0x00000001 },
+        { 0x00155c,   2, 0x04, 0x00000000 },
+        { 0x001564,   1, 0x04, 0x00001fff },
+        { 0x001574,   2, 0x04, 0x00000000 },
+        { 0x00157c,   1, 0x04, 0x003fffff },
+        { 0x001354,   1, 0x04, 0x00000000 },
+        { 0x001664,   1, 0x04, 0x00000000 },
+        { 0x001610,   1, 0x04, 0x00000012 },
+        { 0x001608,   2, 0x04, 0x00000000 },
+        { 0x00162c,   1, 0x04, 0x00000003 },
+        { 0x000210,   1, 0x04, 0x00000000 },
+        { 0x000320,   1, 0x04, 0x00000000 },
+        { 0x000324,   6, 0x04, 0x3f800000 },
+        { 0x000750,   1, 0x04, 0x00000000 },
+        { 0x000760,   1, 0x04, 0x39291909 },
+        { 0x000764,   1, 0x04, 0x79695949 },
+        { 0x000768,   1, 0x04, 0xb9a99989 },
+        { 0x00076c,   1, 0x04, 0xf9e9d9c9 },
+        { 0x000770,   1, 0x04, 0x30201000 },
+        { 0x000774,   1, 0x04, 0x70605040 },
+        { 0x000778,   1, 0x04, 0x00009080 },
+        { 0x000780,   1, 0x04, 0x39291909 },
+        { 0x000784,   1, 0x04, 0x79695949 },
+        { 0x000788,   1, 0x04, 0xb9a99989 },
+        { 0x00078c,   1, 0x04, 0xf9e9d9c9 },
+        { 0x0007d0,   1, 0x04, 0x30201000 },
+        { 0x0007d4,   1, 0x04, 0x70605040 },
+        { 0x0007d8,   1, 0x04, 0x00009080 },
+        { 0x00037c,   1, 0x04, 0x00000001 },
+        { 0x000740,   2, 0x04, 0x00000000 },
+        { 0x002600,   1, 0x04, 0x00000000 },
+        { 0x001918,   1, 0x04, 0x00000000 },
+        { 0x00191c,   1, 0x04, 0x00000900 },
+        { 0x001920,   1, 0x04, 0x00000405 },
+        { 0x001308,   1, 0x04, 0x00000001 },
+        { 0x001924,   1, 0x04, 0x00000000 },
+        { 0x0013ac,   1, 0x04, 0x00000000 },
+        { 0x00192c,   1, 0x04, 0x00000001 },
+        { 0x00193c,   1, 0x04, 0x00002c1c },
+        { 0x000d7c,   1, 0x04, 0x00000000 },
+        { 0x000f8c,   1, 0x04, 0x00000000 },
+        { 0x0002c0,   1, 0x04, 0x00000001 },
+        { 0x001510,   1, 0x04, 0x00000000 },
+        { 0x001940,   1, 0x04, 0x00000000 },
+        { 0x000ff4,   2, 0x04, 0x00000000 },
+        { 0x00194c,   2, 0x04, 0x00000000 },
+        { 0x001968,   1, 0x04, 0x00000000 },
+        { 0x001590,   1, 0x04, 0x0000003f },
+        { 0x0007e8,   4, 0x04, 0x00000000 },
+        { 0x00196c,   1, 0x04, 0x00000011 },
+        { 0x00197c,   1, 0x04, 0x00000000 },
+        { 0x000fcc,   2, 0x04, 0x00000000 },
+        { 0x0002d8,   1, 0x04, 0x00000040 },
+        { 0x001980,   1, 0x04, 0x00000080 },
+        { 0x001504,   1, 0x04, 0x00000080 },
+        { 0x001984,   1, 0x04, 0x00000000 },
+        { 0x000300,   1, 0x04, 0x00000001 },
+        { 0x0013a8,   1, 0x04, 0x00000000 },
+        { 0x0012ec,   1, 0x04, 0x00000000 },
+        { 0x001310,   1, 0x04, 0x00000000 },
+        { 0x001314,   1, 0x04, 0x00000001 },
+        { 0x001380,   1, 0x04, 0x00000000 },
+        { 0x001384,   4, 0x04, 0x00000001 },
+        { 0x001394,   1, 0x04, 0x00000000 },
+        { 0x00139c,   1, 0x04, 0x00000000 },
+        { 0x001398,   1, 0x04, 0x00000000 },
+        { 0x001594,   1, 0x04, 0x00000000 },
+        { 0x001598,   4, 0x04, 0x00000001 },
+        { 0x000f54,   3, 0x04, 0x00000000 },
+        { 0x0019bc,   1, 0x04, 0x00000000 },
+        { 0x000f9c,   2, 0x04, 0x00000000 },
+        { 0x0012cc,   1, 0x04, 0x00000000 },
+        { 0x0012e8,   1, 0x04, 0x00000000 },
+        { 0x00130c,   1, 0x04, 0x00000001 },
+        { 0x001360,   8, 0x04, 0x00000000 },
+        { 0x00133c,   2, 0x04, 0x00000001 },
+        { 0x001344,   1, 0x04, 0x00000002 },
+        { 0x001348,   2, 0x04, 0x00000001 },
+        { 0x001350,   1, 0x04, 0x00000002 },
+        { 0x001358,   1, 0x04, 0x00000001 },
+        { 0x0012e4,   1, 0x04, 0x00000000 },
+        { 0x00131c,   1, 0x04, 0x00000000 },
+        { 0x001320,   3, 0x04, 0x00000000 },
+        { 0x0019c0,   1, 0x04, 0x00000000 },
+        { 0x001140,   1, 0x04, 0x00000000 },
+        { 0x0019c4,   1, 0x04, 0x00000000 },
+        { 0x0019c8,   1, 0x04, 0x00001500 },
+        { 0x00135c,   1, 0x04, 0x00000000 },
+        { 0x000f90,   1, 0x04, 0x00000000 },
+        { 0x0019e0,   8, 0x04, 0x00000001 },
+        { 0x0019cc,   1, 0x04, 0x00000001 },
+        { 0x0015b8,   1, 0x04, 0x00000000 },
+        { 0x001a00,   1, 0x04, 0x00001111 },
+        { 0x001a04,   7, 0x04, 0x00000000 },
+        { 0x000d6c,   2, 0x04, 0xffff0000 },
+        { 0x0010f8,   1, 0x04, 0x00001010 },
+        { 0x000d80,   5, 0x04, 0x00000000 },
+        { 0x000da0,   1, 0x04, 0x00000000 },
+        { 0x001508,   1, 0x04, 0x80000000 },
+        { 0x00150c,   1, 0x04, 0x40000000 },
+        { 0x001668,   1, 0x04, 0x00000000 },
+        { 0x000318,   2, 0x04, 0x00000008 },
+        { 0x000d9c,   1, 0x04, 0x00000001 },
+        { 0x0007dc,   1, 0x04, 0x00000000 },
+        { 0x00074c,   1, 0x04, 0x00000055 },
+        { 0x001420,   1, 0x04, 0x00000003 },
+        { 0x0017bc,   2, 0x04, 0x00000000 },
+        { 0x0017c4,   1, 0x04, 0x00000001 },
+        { 0x001008,   1, 0x04, 0x00000008 },
+        { 0x00100c,   1, 0x04, 0x00000040 },
+        { 0x001010,   1, 0x04, 0x0000012c },
+        { 0x000d60,   1, 0x04, 0x00000040 },
+        { 0x00075c,   1, 0x04, 0x00000003 },
+        { 0x001018,   1, 0x04, 0x00000020 },
+        { 0x00101c,   1, 0x04, 0x00000001 },
+        { 0x001020,   1, 0x04, 0x00000020 },
+        { 0x001024,   1, 0x04, 0x00000001 },
+        { 0x001444,   3, 0x04, 0x00000000 },
+        { 0x000360,   1, 0x04, 0x20164010 },
+        { 0x000364,   1, 0x04, 0x00000020 },
+        { 0x000368,   1, 0x04, 0x00000000 },
+        { 0x000de4,   1, 0x04, 0x00000000 },
+        { 0x000204,   1, 0x04, 0x00000006 },
+        { 0x000208,   1, 0x04, 0x00000000 },
+        { 0x0002cc,   1, 0x04, 0x003fffff },
+        { 0x0002d0,   1, 0x04, 0x00000c48 },
+        { 0x001220,   1, 0x04, 0x00000005 },
+        { 0x000fdc,   1, 0x04, 0x00000000 },
+        { 0x000f98,   1, 0x04, 0x00300008 },
+        { 0x001284,   1, 0x04, 0x04000080 },
+        { 0x001450,   1, 0x04, 0x00300008 },
+        { 0x001454,   1, 0x04, 0x04000080 },
+        { 0x000214,   1, 0x04, 0x00000000 },
+        {}
+};
+
+static struct nvc0_graph_init
+nvc1_grctx_init_9197[] = {
+        { 0x003400, 128, 0x04, 0x00000000 },
+        { 0x0002e4,   1, 0x04, 0x0000b001 },
+        {}
+};
+
+static struct nvc0_graph_init
+nvc1_grctx_init_unk58xx[] = {
+        { 0x405800,   1, 0x04, 0x0f8000bf },
+        { 0x405830,   1, 0x04, 0x02180218 },
+        { 0x405834,   2, 0x04, 0x00000000 },
+        { 0x405854,   1, 0x04, 0x00000000 },
+        { 0x405870,   4, 0x04, 0x00000001 },
+        { 0x405a00,   2, 0x04, 0x00000000 },
+        { 0x405a18,   1, 0x04, 0x00000000 },
+};
+
+static struct nvc0_graph_init
+nvc1_grctx_init_rop[] = {
+        { 0x408800,   1, 0x04, 0x02802a3c },
+        { 0x408804,   1, 0x04, 0x00000040 },
+        { 0x408808,   1, 0x04, 0x1003e005 },
+        { 0x408900,   1, 0x04, 0x3080b801 },
+        { 0x408904,   1, 0x04, 0x62000001 },
+        { 0x408908,   1, 0x04, 0x00c80929 },
+        { 0x408980,   1, 0x04, 0x0000011d },
+};
+
+static struct nvc0_graph_init
+nvc1_grctx_init_gpc_0[] = {
+        { 0x418380,   1, 0x04, 0x00000016 },
+        { 0x418400,   1, 0x04, 0x38004e00 },
+        { 0x418404,   1, 0x04, 0x71e0ffff },
+        { 0x418408,   1, 0x04, 0x00000000 },
+        { 0x41840c,   1, 0x04, 0x00001008 },
+        { 0x418410,   1, 0x04, 0x0fff0fff },
+        { 0x418414,   1, 0x04, 0x00200fff },
+        { 0x418450,   6, 0x04, 0x00000000 },
+        { 0x418468,   1, 0x04, 0x00000001 },
+        { 0x41846c,   2, 0x04, 0x00000000 },
+        { 0x418600,   1, 0x04, 0x0000001f },
+        { 0x418684,   1, 0x04, 0x0000000f },
+        { 0x418700,   1, 0x04, 0x00000002 },
+        { 0x418704,   1, 0x04, 0x00000080 },
+        { 0x418708,   1, 0x04, 0x00000000 },
+        { 0x41870c,   1, 0x04, 0x07c80000 },
+        { 0x418710,   1, 0x04, 0x00000000 },
+        { 0x418800,   1, 0x04, 0x0006860a },
+        { 0x418808,   3, 0x04, 0x00000000 },
+        { 0x418828,   1, 0x04, 0x00008442 },
+        { 0x418830,   1, 0x04, 0x10000001 },
+        { 0x4188d8,   1, 0x04, 0x00000008 },
+        { 0x4188e0,   1, 0x04, 0x01000000 },
+        { 0x4188e8,   5, 0x04, 0x00000000 },
+        { 0x4188fc,   1, 0x04, 0x00100018 },
+        { 0x41891c,   1, 0x04, 0x00ff00ff },
+        { 0x418924,   1, 0x04, 0x00000000 },
+        { 0x418928,   1, 0x04, 0x00ffff00 },
+        { 0x41892c,   1, 0x04, 0x0000ff00 },
+        { 0x418a00,   3, 0x04, 0x00000000 },
+        { 0x418a0c,   1, 0x04, 0x00010000 },
+        { 0x418a10,   3, 0x04, 0x00000000 },
+        { 0x418a20,   3, 0x04, 0x00000000 },
+        { 0x418a2c,   1, 0x04, 0x00010000 },
+        { 0x418a30,   3, 0x04, 0x00000000 },
+        { 0x418a40,   3, 0x04, 0x00000000 },
+        { 0x418a4c,   1, 0x04, 0x00010000 },
+        { 0x418a50,   3, 0x04, 0x00000000 },
+        { 0x418a60,   3, 0x04, 0x00000000 },
+        { 0x418a6c,   1, 0x04, 0x00010000 },
+        { 0x418a70,   3, 0x04, 0x00000000 },
+        { 0x418a80,   3, 0x04, 0x00000000 },
+        { 0x418a8c,   1, 0x04, 0x00010000 },
+        { 0x418a90,   3, 0x04, 0x00000000 },
+        { 0x418aa0,   3, 0x04, 0x00000000 },
+        { 0x418aac,   1, 0x04, 0x00010000 },
+        { 0x418ab0,   3, 0x04, 0x00000000 },
+        { 0x418ac0,   3, 0x04, 0x00000000 },
+        { 0x418acc,   1, 0x04, 0x00010000 },
+        { 0x418ad0,   3, 0x04, 0x00000000 },
+        { 0x418ae0,   3, 0x04, 0x00000000 },
+        { 0x418aec,   1, 0x04, 0x00010000 },
+        { 0x418af0,   3, 0x04, 0x00000000 },
+        { 0x418b00,   1, 0x04, 0x00000000 },
+        { 0x418b08,   1, 0x04, 0x0a418820 },
+        { 0x418b0c,   1, 0x04, 0x062080e6 },
+        { 0x418b10,   1, 0x04, 0x020398a4 },
+        { 0x418b14,   1, 0x04, 0x0e629062 },
+        { 0x418b18,   1, 0x04, 0x0a418820 },
+        { 0x418b1c,   1, 0x04, 0x000000e6 },
+        { 0x418bb8,   1, 0x04, 0x00000103 },
+        { 0x418c08,   1, 0x04, 0x00000001 },
+        { 0x418c10,   8, 0x04, 0x00000000 },
+        { 0x418c6c,   1, 0x04, 0x00000001 },
+        { 0x418c80,   1, 0x04, 0x20200004 },
+        { 0x418c8c,   1, 0x04, 0x00000001 },
+        { 0x419000,   1, 0x04, 0x00000780 },
+        { 0x419004,   2, 0x04, 0x00000000 },
+        { 0x419014,   1, 0x04, 0x00000004 },
+};
+
+static struct nvc0_graph_init
+nvc1_grctx_init_tpc[] = {
+        { 0x419818,   1, 0x04, 0x00000000 },
+        { 0x41983c,   1, 0x04, 0x00038bc7 },
+        { 0x419848,   1, 0x04, 0x00000000 },
+        { 0x419864,   1, 0x04, 0x00000129 },
+        { 0x419888,   1, 0x04, 0x00000000 },
+        { 0x419a00,   1, 0x04, 0x000001f0 },
+        { 0x419a04,   1, 0x04, 0x00000001 },
+        { 0x419a08,   1, 0x04, 0x00000023 },
+        { 0x419a0c,   1, 0x04, 0x00020000 },
+        { 0x419a10,   1, 0x04, 0x00000000 },
+        { 0x419a14,   1, 0x04, 0x00000200 },
+        { 0x419a1c,   1, 0x04, 0x00000000 },
+        { 0x419a20,   1, 0x04, 0x00000800 },
+        { 0x419ac4,   1, 0x04, 0x0007f440 },
+        { 0x419b00,   1, 0x04, 0x0a418820 },
+        { 0x419b04,   1, 0x04, 0x062080e6 },
+        { 0x419b08,   1, 0x04, 0x020398a4 },
+        { 0x419b0c,   1, 0x04, 0x0e629062 },
+        { 0x419b10,   1, 0x04, 0x0a418820 },
+        { 0x419b14,   1, 0x04, 0x000000e6 },
+        { 0x419bd0,   1, 0x04, 0x00900103 },
+        { 0x419be0,   1, 0x04, 0x00400001 },
+        { 0x419be4,   1, 0x04, 0x00000000 },
+        { 0x419c00,   1, 0x04, 0x00000002 },
+        { 0x419c04,   1, 0x04, 0x00000006 },
+        { 0x419c08,   1, 0x04, 0x00000002 },
+        { 0x419c20,   1, 0x04, 0x00000000 },
+        { 0x419cb0,   1, 0x04, 0x00020048 },
+        { 0x419ce8,   1, 0x04, 0x00000000 },
+        { 0x419cf4,   1, 0x04, 0x00000183 },
+        { 0x419d20,   1, 0x04, 0x12180000 },
+        { 0x419d24,   1, 0x04, 0x00001fff },
+        { 0x419d44,   1, 0x04, 0x02180218 },
+        { 0x419e04,   3, 0x04, 0x00000000 },
+        { 0x419e10,   1, 0x04, 0x00000002 },
+        { 0x419e44,   1, 0x04, 0x001beff2 },
+        { 0x419e48,   1, 0x04, 0x00000000 },
+        { 0x419e4c,   1, 0x04, 0x0000000f },
+        { 0x419e50,  17, 0x04, 0x00000000 },
+        { 0x419e98,   1, 0x04, 0x00000000 },
+        { 0x419ee0,   1, 0x04, 0x00011110 },
+        { 0x419f30,  11, 0x04, 0x00000000 },
+};
+
+void
+nvc1_grctx_generate_mods(struct nvc0_graph_priv *priv, struct nvc0_grctx *info)
+{
+        int gpc, tpc;
+        u32 offset;
+
+        mmio_data(0x002000, 0x0100, NV_MEM_ACCESS_RW | NV_MEM_ACCESS_SYS);
+        mmio_data(0x008000, 0x0100, NV_MEM_ACCESS_RW | NV_MEM_ACCESS_SYS);
+        mmio_data(0x060000, 0x1000, NV_MEM_ACCESS_RW);
+        mmio_list(0x408004, 0x00000000,  8, 0);
+        mmio_list(0x408008, 0x80000018,  0, 0);
+        mmio_list(0x40800c, 0x00000000,  8, 1);
+        mmio_list(0x408010, 0x80000000,  0, 0);
+        mmio_list(0x418810, 0x80000000, 12, 2);
+        mmio_list(0x419848, 0x10000000, 12, 2);
+        mmio_list(0x419004, 0x00000000,  8, 1);
+        mmio_list(0x419008, 0x00000000,  0, 0);
+        mmio_list(0x418808, 0x00000000,  8, 0);
+        mmio_list(0x41880c, 0x80000018,  0, 0);
+
+        mmio_list(0x405830, 0x02180218, 0, 0);
+        mmio_list(0x4064c4, 0x0086ffff, 0, 0);
+
+        for (gpc = 0, offset = 0; gpc < priv->gpc_nr; gpc++) {
+                for (tpc = 0; tpc < priv->tpc_nr[gpc]; tpc++) {
+                        u32 addr = TPC_UNIT(gpc, tpc, 0x0520);
+                        mmio_list(addr, 0x12180000 | offset, 0, 0);
+                        offset += 0x0324;
+                }
+                for (tpc = 0; tpc < priv->tpc_nr[gpc]; tpc++) {
+                        u32 addr = TPC_UNIT(gpc, tpc, 0x0544);
+                        mmio_list(addr, 0x02180000 | offset, 0, 0);
+                        offset += 0x0324;
+                }
+        }
+}
+
+void
+nvc1_grctx_generate_unkn(struct nvc0_graph_priv *priv)
+{
+        nv_mask(priv, 0x418c6c, 0x00000001, 0x00000001);
+        nv_mask(priv, 0x41980c, 0x00000010, 0x00000010);
+        nv_mask(priv, 0x419814, 0x00000004, 0x00000004);
+        nv_mask(priv, 0x4064c0, 0x80000000, 0x80000000);
+        nv_mask(priv, 0x405800, 0x08000000, 0x08000000);
+        nv_mask(priv, 0x419c00, 0x00000008, 0x00000008);
+}
+
+static struct nvc0_graph_init *
+nvc1_grctx_init_hub[] = {
+        nvc0_grctx_init_base,
+        nvc0_grctx_init_unk40xx,
+        nvc0_grctx_init_unk44xx,
+        nvc0_grctx_init_unk46xx,
+        nvc0_grctx_init_unk47xx,
+        nvc1_grctx_init_unk58xx,
+        nvc0_grctx_init_unk60xx,
+        nvc0_grctx_init_unk64xx,
+        nvc0_grctx_init_unk78xx,
+        nvc0_grctx_init_unk80xx,
+        nvc1_grctx_init_rop,
+        NULL
+};
+
+struct nvc0_graph_init *
+nvc1_grctx_init_gpc[] = {
+        nvc1_grctx_init_gpc_0,
+        nvc0_grctx_init_gpc_1,
+        nvc1_grctx_init_tpc,
+        NULL
+};
+
+static struct nvc0_graph_mthd
+nvc1_grctx_init_mthd[] = {
+        { 0x9097, nvc1_grctx_init_9097, },
+        { 0x9197, nvc1_grctx_init_9197, },
+        { 0x902d, nvc0_grctx_init_902d, },
+        { 0x9039, nvc0_grctx_init_9039, },
+        { 0x90c0, nvc0_grctx_init_90c0, },
+        { 0x902d, nvc0_grctx_init_mthd_magic, },
+        {}
+};
+
+struct nouveau_oclass *
+nvc1_grctx_oclass = &(struct nvc0_grctx_oclass) {
+        .base.handle = NV_ENGCTX(GR, 0xc1),
+        .base.ofuncs = &(struct nouveau_ofuncs) {
+                .ctor = nvc0_graph_context_ctor,
+                .dtor = nvc0_graph_context_dtor,
+                .init = _nouveau_graph_context_init,
+                .fini = _nouveau_graph_context_fini,
+                .rd32 = _nouveau_graph_context_rd32,
+                .wr32 = _nouveau_graph_context_wr32,
+        },
+        .main = nvc0_grctx_generate_main,
+        .mods = nvc1_grctx_generate_mods,
+        .unkn = nvc1_grctx_generate_unkn,
+        .hub  = nvc1_grctx_init_hub,
+        .gpc  = nvc1_grctx_init_gpc,
+        .icmd = nvc1_grctx_init_icmd,
+        .mthd = nvc1_grctx_init_mthd,
+}.base;
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc3.c b/drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc3.c
new file mode 100644
index 000000000000..8f237b3bd8c6
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc3.c
@@ -0,0 +1,99 @@
+/*
+ * Copyright 2013 Red Hat Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Ben Skeggs <bskeggs@redhat.com>
+ */
+
+#include "nvc0.h"
+
+static struct nvc0_graph_init
+nvc3_grctx_init_tpc[] = {
+        { 0x419818,   1, 0x04, 0x00000000 },
+        { 0x41983c,   1, 0x04, 0x00038bc7 },
+        { 0x419848,   1, 0x04, 0x00000000 },
+        { 0x419864,   1, 0x04, 0x0000012a },
+        { 0x419888,   1, 0x04, 0x00000000 },
+        { 0x419a00,   1, 0x04, 0x000001f0 },
+        { 0x419a04,   1, 0x04, 0x00000001 },
+        { 0x419a08,   1, 0x04, 0x00000023 },
+        { 0x419a0c,   1, 0x04, 0x00020000 },
+        { 0x419a10,   1, 0x04, 0x00000000 },
+        { 0x419a14,   1, 0x04, 0x00000200 },
+        { 0x419a1c,   1, 0x04, 0x00000000 },
+        { 0x419a20,   1, 0x04, 0x00000800 },
+        { 0x419ac4,   1, 0x04, 0x0007f440 },
+        { 0x419b00,   1, 0x04, 0x0a418820 },
+        { 0x419b04,   1, 0x04, 0x062080e6 },
+        { 0x419b08,   1, 0x04, 0x020398a4 },
+        { 0x419b0c,   1, 0x04, 0x0e629062 },
+        { 0x419b10,   1, 0x04, 0x0a418820 },
+        { 0x419b14,   1, 0x04, 0x000000e6 },
+        { 0x419bd0,   1, 0x04, 0x00900103 },
+        { 0x419be0,   1, 0x04, 0x00000001 },
+        { 0x419be4,   1, 0x04, 0x00000000 },
+        { 0x419c00,   1, 0x04, 0x00000002 },
+        { 0x419c04,   1, 0x04, 0x00000006 },
+        { 0x419c08,   1, 0x04, 0x00000002 },
+        { 0x419c20,   1, 0x04, 0x00000000 },
+        { 0x419cb0,   1, 0x04, 0x00020048 },
+        { 0x419ce8,   1, 0x04, 0x00000000 },
+        { 0x419cf4,   1, 0x04, 0x00000183 },
+        { 0x419d20,   1, 0x04, 0x02180000 },
+        { 0x419d24,   1, 0x04, 0x00001fff },
+        { 0x419e04,   3, 0x04, 0x00000000 },
+        { 0x419e10,   1, 0x04, 0x00000002 },
+        { 0x419e44,   1, 0x04, 0x001beff2 },
+        { 0x419e48,   1, 0x04, 0x00000000 },
+        { 0x419e4c,   1, 0x04, 0x0000000f },
+        { 0x419e50,  17, 0x04, 0x00000000 },
+        { 0x419e98,   1, 0x04, 0x00000000 },
+        { 0x419ee0,   1, 0x04, 0x00011110 },
+        { 0x419f30,  11, 0x04, 0x00000000 },
+        {}
+};
+
+struct nvc0_graph_init *
+nvc3_grctx_init_gpc[] = {
+        nvc0_grctx_init_gpc_0,
+        nvc0_grctx_init_gpc_1,
+        nvc3_grctx_init_tpc,
+        NULL
+};
+
+struct nouveau_oclass *
+nvc3_grctx_oclass = &(struct nvc0_grctx_oclass) {
+        .base.handle = NV_ENGCTX(GR, 0xc3),
+        .base.ofuncs = &(struct nouveau_ofuncs) {
+                .ctor = nvc0_graph_context_ctor,
+                .dtor = nvc0_graph_context_dtor,
+                .init = _nouveau_graph_context_init,
+                .fini = _nouveau_graph_context_fini,
+                .rd32 = _nouveau_graph_context_rd32,
+                .wr32 = _nouveau_graph_context_wr32,
+        },
+        .main = nvc0_grctx_generate_main,
+        .mods = nvc0_grctx_generate_mods,
+        .unkn = nvc0_grctx_generate_unkn,
+        .hub  = nvc0_grctx_init_hub,
+        .gpc  = nvc3_grctx_init_gpc,
+        .icmd = nvc0_grctx_init_icmd,
+        .mthd = nvc0_grctx_init_mthd,
+}.base;
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc8.c b/drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc8.c
new file mode 100644
index 000000000000..d0d4ce3c4892
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc8.c
@@ -0,0 +1,370 @@
+/*
+ * Copyright 2013 Red Hat Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Ben Skeggs <bskeggs@redhat.com>
+ */
+
+#include "nvc0.h"
+
+static struct nvc0_graph_init
+nvc8_grctx_init_icmd[] = {
+        { 0x001000,   1, 0x01, 0x00000004 },
+        { 0x0000a9,   1, 0x01, 0x0000ffff },
+        { 0x000038,   1, 0x01, 0x0fac6881 },
+        { 0x00003d,   1, 0x01, 0x00000001 },
+        { 0x0000e8,   8, 0x01, 0x00000400 },
+        { 0x000078,   8, 0x01, 0x00000300 },
+        { 0x000050,   1, 0x01, 0x00000011 },
+        { 0x000058,   8, 0x01, 0x00000008 },
+        { 0x000208,   8, 0x01, 0x00000001 },
+        { 0x000081,   1, 0x01, 0x00000001 },
+        { 0x000085,   1, 0x01, 0x00000004 },
+        { 0x000088,   1, 0x01, 0x00000400 },
+        { 0x000090,   1, 0x01, 0x00000300 },
+        { 0x000098,   1, 0x01, 0x00001001 },
+        { 0x0000e3,   1, 0x01, 0x00000001 },
+        { 0x0000da,   1, 0x01, 0x00000001 },
+        { 0x0000f8,   1, 0x01, 0x00000003 },
+        { 0x0000fa,   1, 0x01, 0x00000001 },
+        { 0x00009f,   4, 0x01, 0x0000ffff },
+        { 0x0000b1,   1, 0x01, 0x00000001 },
+        { 0x0000b2,  40, 0x01, 0x00000000 },
+        { 0x000210,   8, 0x01, 0x00000040 },
+        { 0x000218,   8, 0x01, 0x0000c080 },
+        { 0x0000ad,   1, 0x01, 0x0000013e },
+        { 0x0000e1,   1, 0x01, 0x00000010 },
+        { 0x000290,  16, 0x01, 0x00000000 },
+        { 0x0003b0,  16, 0x01, 0x00000000 },
+        { 0x0002a0,  16, 0x01, 0x00000000 },
+        { 0x000420,  16, 0x01, 0x00000000 },
+        { 0x0002b0,  16, 0x01, 0x00000000 },
+        { 0x000430,  16, 0x01, 0x00000000 },
+        { 0x0002c0,  16, 0x01, 0x00000000 },
+        { 0x0004d0,  16, 0x01, 0x00000000 },
+        { 0x000720,  16, 0x01, 0x00000000 },
+        { 0x0008c0,  16, 0x01, 0x00000000 },
+        { 0x000890,  16, 0x01, 0x00000000 },
+        { 0x0008e0,  16, 0x01, 0x00000000 },
+        { 0x0008a0,  16, 0x01, 0x00000000 },
+        { 0x0008f0,  16, 0x01, 0x00000000 },
+        { 0x00094c,   1, 0x01, 0x000000ff },
+        { 0x00094d,   1, 0x01, 0xffffffff },
+        { 0x00094e,   1, 0x01, 0x00000002 },
+        { 0x0002ec,   1, 0x01, 0x00000001 },
+        { 0x000303,   1, 0x01, 0x00000001 },
+        { 0x0002e6,   1, 0x01, 0x00000001 },
+        { 0x000466,   1, 0x01, 0x00000052 },
+        { 0x000301,   1, 0x01, 0x3f800000 },
+        { 0x000304,   1, 0x01, 0x30201000 },
+        { 0x000305,   1, 0x01, 0x70605040 },
+        { 0x000306,   1, 0x01, 0xb8a89888 },
+        { 0x000307,   1, 0x01, 0xf8e8d8c8 },
+        { 0x00030a,   1, 0x01, 0x00ffff00 },
+        { 0x00030b,   1, 0x01, 0x0000001a },
+        { 0x00030c,   1, 0x01, 0x00000001 },
+        { 0x000318,   1, 0x01, 0x00000001 },
+        { 0x000340,   1, 0x01, 0x00000000 },
+        { 0x000375,   1, 0x01, 0x00000001 },
+        { 0x000351,   1, 0x01, 0x00000100 },
+        { 0x00037d,   1, 0x01, 0x00000006 },
+        { 0x0003a0,   1, 0x01, 0x00000002 },
+        { 0x0003aa,   1, 0x01, 0x00000001 },
+        { 0x0003a9,   1, 0x01, 0x00000001 },
+        { 0x000380,   1, 0x01, 0x00000001 },
+        { 0x000360,   1, 0x01, 0x00000040 },
+        { 0x000366,   2, 0x01, 0x00000000 },
+        { 0x000368,   1, 0x01, 0x00001fff },
+        { 0x000370,   2, 0x01, 0x00000000 },
+        { 0x000372,   1, 0x01, 0x003fffff },
+        { 0x00037a,   1, 0x01, 0x00000012 },
+        { 0x0005e0,   5, 0x01, 0x00000022 },
+        { 0x000619,   1, 0x01, 0x00000003 },
+        { 0x000811,   1, 0x01, 0x00000003 },
+        { 0x000812,   1, 0x01, 0x00000004 },
+        { 0x000813,   1, 0x01, 0x00000006 },
+        { 0x000814,   1, 0x01, 0x00000008 },
+        { 0x000815,   1, 0x01, 0x0000000b },
+        { 0x000800,   6, 0x01, 0x00000001 },
+        { 0x000632,   1, 0x01, 0x00000001 },
+        { 0x000633,   1, 0x01, 0x00000002 },
+        { 0x000634,   1, 0x01, 0x00000003 },
+        { 0x000635,   1, 0x01, 0x00000004 },
+        { 0x000654,   1, 0x01, 0x3f800000 },
+        { 0x000657,   1, 0x01, 0x3f800000 },
+        { 0x000655,   2, 0x01, 0x3f800000 },
+        { 0x0006cd,   1, 0x01, 0x3f800000 },
+        { 0x0007f5,   1, 0x01, 0x3f800000 },
+        { 0x0007dc,   1, 0x01, 0x39291909 },
+        { 0x0007dd,   1, 0x01, 0x79695949 },
+        { 0x0007de,   1, 0x01, 0xb9a99989 },
+        { 0x0007df,   1, 0x01, 0xf9e9d9c9 },
+        { 0x0007e8,   1, 0x01, 0x00003210 },
+        { 0x0007e9,   1, 0x01, 0x00007654 },
+        { 0x0007ea,   1, 0x01, 0x00000098 },
+        { 0x0007ec,   1, 0x01, 0x39291909 },
+        { 0x0007ed,   1, 0x01, 0x79695949 },
+        { 0x0007ee,   1, 0x01, 0xb9a99989 },
+        { 0x0007ef,   1, 0x01, 0xf9e9d9c9 },
+        { 0x0007f0,   1, 0x01, 0x00003210 },
+        { 0x0007f1,   1, 0x01, 0x00007654 },
+        { 0x0007f2,   1, 0x01, 0x00000098 },
+        { 0x0005a5,   1, 0x01, 0x00000001 },
+        { 0x000980, 128, 0x01, 0x00000000 },
+        { 0x000468,   1, 0x01, 0x00000004 },
+        { 0x00046c,   1, 0x01, 0x00000001 },
+        { 0x000470,  96, 0x01, 0x00000000 },
+        { 0x000510,  16, 0x01, 0x3f800000 },
+        { 0x000520,   1, 0x01, 0x000002b6 },
+        { 0x000529,   1, 0x01, 0x00000001 },
+        { 0x000530,  16, 0x01, 0xffff0000 },
+        { 0x000585,   1, 0x01, 0x0000003f },
+        { 0x000576,   1, 0x01, 0x00000003 },
+        { 0x00057b,   1, 0x01, 0x00000059 },
+        { 0x000586,   1, 0x01, 0x00000040 },
+        { 0x000582,   2, 0x01, 0x00000080 },
+        { 0x0005c2,   1, 0x01, 0x00000001 },
+        { 0x000638,   1, 0x01, 0x00000001 },
+        { 0x000639,   1, 0x01, 0x00000001 },
+        { 0x00063a,   1, 0x01, 0x00000002 },
+        { 0x00063b,   2, 0x01, 0x00000001 },
+        { 0x00063d,   1, 0x01, 0x00000002 },
+        { 0x00063e,   1, 0x01, 0x00000001 },
+        { 0x0008b8,   8, 0x01, 0x00000001 },
+        { 0x000900,   8, 0x01, 0x00000001 },
+        { 0x000908,   8, 0x01, 0x00000002 },
+        { 0x000910,  16, 0x01, 0x00000001 },
+        { 0x000920,   8, 0x01, 0x00000002 },
+        { 0x000928,   8, 0x01, 0x00000001 },
+        { 0x000648,   9, 0x01, 0x00000001 },
+        { 0x000658,   1, 0x01, 0x0000000f },
+        { 0x0007ff,   1, 0x01, 0x0000000a },
+        { 0x00066a,   1, 0x01, 0x40000000 },
+        { 0x00066b,   1, 0x01, 0x10000000 },
+        { 0x00066c,   2, 0x01, 0xffff0000 },
+        { 0x0007af,   2, 0x01, 0x00000008 },
+        { 0x0007f6,   1, 0x01, 0x00000001 },
+        { 0x0006b2,   1, 0x01, 0x00000055 },
+        { 0x0007ad,   1, 0x01, 0x00000003 },
+        { 0x000937,   1, 0x01, 0x00000001 },
+        { 0x000971,   1, 0x01, 0x00000008 },
+        { 0x000972,   1, 0x01, 0x00000040 },
+        { 0x000973,   1, 0x01, 0x0000012c },
+        { 0x00097c,   1, 0x01, 0x00000040 },
+        { 0x000979,   1, 0x01, 0x00000003 },
+        { 0x000975,   1, 0x01, 0x00000020 },
+        { 0x000976,   1, 0x01, 0x00000001 },
+        { 0x000977,   1, 0x01, 0x00000020 },
+        { 0x000978,   1, 0x01, 0x00000001 },
+        { 0x000957,   1, 0x01, 0x00000003 },
+        { 0x00095e,   1, 0x01, 0x20164010 },
+        { 0x00095f,   1, 0x01, 0x00000020 },
+        { 0x00097d,   1, 0x01, 0x00000020 },
+        { 0x000683,   1, 0x01, 0x00000006 },
+        { 0x000685,   1, 0x01, 0x003fffff },
+        { 0x000687,   1, 0x01, 0x00000c48 },
+        { 0x0006a0,   1, 0x01, 0x00000005 },
+        { 0x000840,   1, 0x01, 0x00300008 },
+        { 0x000841,   1, 0x01, 0x04000080 },
+        { 0x000842,   1, 0x01, 0x00300008 },
+        { 0x000843,   1, 0x01, 0x04000080 },
+        { 0x000818,   8, 0x01, 0x00000000 },
+        { 0x000848,  16, 0x01, 0x00000000 },
+        { 0x000738,   1, 0x01, 0x00000000 },
+        { 0x0006aa,   1, 0x01, 0x00000001 },
+        { 0x0006ab,   1, 0x01, 0x00000002 },
+        { 0x0006ac,   1, 0x01, 0x00000080 },
+        { 0x0006ad,   2, 0x01, 0x00000100 },
+        { 0x0006b1,   1, 0x01, 0x00000011 },
+        { 0x0006bb,   1, 0x01, 0x000000cf },
+        { 0x0006ce,   1, 0x01, 0x2a712488 },
+        { 0x000739,   1, 0x01, 0x4085c000 },
+        { 0x00073a,   1, 0x01, 0x00000080 },
+        { 0x000786,   1, 0x01, 0x80000100 },
+        { 0x00073c,   1, 0x01, 0x00010100 },
+        { 0x00073d,   1, 0x01, 0x02800000 },
+        { 0x000787,   1, 0x01, 0x000000cf },
+        { 0x00078c,   1, 0x01, 0x00000008 },
+        { 0x000792,   1, 0x01, 0x00000001 },
+        { 0x000794,   1, 0x01, 0x00000001 },
+        { 0x000795,   2, 0x01, 0x00000001 },
+        { 0x000797,   1, 0x01, 0x000000cf },
+        { 0x000836,   1, 0x01, 0x00000001 },
+        { 0x00079a,   1, 0x01, 0x00000002 },
+        { 0x000833,   1, 0x01, 0x04444480 },
+        { 0x0007a1,   1, 0x01, 0x00000001 },
+        { 0x0007a3,   1, 0x01, 0x00000001 },
+        { 0x0007a4,   2, 0x01, 0x00000001 },
+        { 0x000831,   1, 0x01, 0x00000004 },
+        { 0x00080c,   1, 0x01, 0x00000002 },
+        { 0x00080d,   2, 0x01, 0x00000100 },
+        { 0x00080f,   1, 0x01, 0x00000001 },
+        { 0x000823,   1, 0x01, 0x00000002 },
+        { 0x000824,   2, 0x01, 0x00000100 },
+        { 0x000826,   1, 0x01, 0x00000001 },
+        { 0x00095d,   1, 0x01, 0x00000001 },
+        { 0x00082b,   1, 0x01, 0x00000004 },
+        { 0x000942,   1, 0x01, 0x00010001 },
+        { 0x000943,   1, 0x01, 0x00000001 },
+        { 0x000944,   1, 0x01, 0x00000022 },
+        { 0x0007c5,   1, 0x01, 0x00010001 },
+        { 0x000834,   1, 0x01, 0x00000001 },
+        { 0x0007c7,   1, 0x01, 0x00000001 },
+        { 0x00c1b0,   8, 0x01, 0x0000000f },
+        { 0x00c1b8,   1, 0x01, 0x0fac6881 },
+        { 0x00c1b9,   1, 0x01, 0x00fac688 },
+        { 0x01e100,   1, 0x01, 0x00000001 },
+        { 0x001000,   1, 0x01, 0x00000002 },
+        { 0x0006aa,   1, 0x01, 0x00000001 },
+        { 0x0006ad,   2, 0x01, 0x00000100 },
+        { 0x0006b1,   1, 0x01, 0x00000011 },
+        { 0x00078c,   1, 0x01, 0x00000008 },
+        { 0x000792,   1, 0x01, 0x00000001 },
+        { 0x000794,   1, 0x01, 0x00000001 },
+        { 0x000795,   2, 0x01, 0x00000001 },
+        { 0x000797,   1, 0x01, 0x000000cf },
+        { 0x00079a,   1, 0x01, 0x00000002 },
+        { 0x000833,   1, 0x01, 0x04444480 },
+        { 0x0007a1,   1, 0x01, 0x00000001 },
+        { 0x0007a3,   1, 0x01, 0x00000001 },
+        { 0x0007a4,   2, 0x01, 0x00000001 },
+        { 0x000831,   1, 0x01, 0x00000004 },
+        { 0x01e100,   1, 0x01, 0x00000001 },
+        { 0x001000,   1, 0x01, 0x00000014 },
+        { 0x000351,   1, 0x01, 0x00000100 },
+        { 0x000957,   1, 0x01, 0x00000003 },
+        { 0x00095d,   1, 0x01, 0x00000001 },
+        { 0x00082b,   1, 0x01, 0x00000004 },
+        { 0x000942,   1, 0x01, 0x00010001 },
+        { 0x000943,   1, 0x01, 0x00000001 },
+        { 0x0007c5,   1, 0x01, 0x00010001 },
+        { 0x000834,   1, 0x01, 0x00000001 },
+        { 0x0007c7,   1, 0x01, 0x00000001 },
+        { 0x01e100,   1, 0x01, 0x00000001 },
+        { 0x001000,   1, 0x01, 0x00000001 },
+        { 0x00080c,   1, 0x01, 0x00000002 },
+        { 0x00080d,   2, 0x01, 0x00000100 },
+        { 0x00080f,   1, 0x01, 0x00000001 },
+        { 0x000823,   1, 0x01, 0x00000002 },
+        { 0x000824,   2, 0x01, 0x00000100 },
+        { 0x000826,   1, 0x01, 0x00000001 },
+        { 0x01e100,   1, 0x01, 0x00000001 },
+        {}
+};
+
+static struct nvc0_graph_init
+nvc8_grctx_init_tpc[] = {
+        { 0x419818,   1, 0x04, 0x00000000 },
+        { 0x41983c,   1, 0x04, 0x00038bc7 },
+        { 0x419848,   1, 0x04, 0x00000000 },
+        { 0x419864,   1, 0x04, 0x0000012a },
+        { 0x419888,   1, 0x04, 0x00000000 },
+        { 0x419a00,   1, 0x04, 0x000001f0 },
+        { 0x419a04,   1, 0x04, 0x00000001 },
+        { 0x419a08,   1, 0x04, 0x00000023 },
+        { 0x419a0c,   1, 0x04, 0x00020000 },
+        { 0x419a10,   1, 0x04, 0x00000000 },
+        { 0x419a14,   1, 0x04, 0x00000200 },
+        { 0x419a1c,   1, 0x04, 0x00000000 },
+        { 0x419a20,   1, 0x04, 0x00000800 },
+        { 0x419b00,   1, 0x04, 0x0a418820 },
+        { 0x419b04,   1, 0x04, 0x062080e6 },
+        { 0x419b08,   1, 0x04, 0x020398a4 },
+        { 0x419b0c,   1, 0x04, 0x0e629062 },
+        { 0x419b10,   1, 0x04, 0x0a418820 },
+        { 0x419b14,   1, 0x04, 0x000000e6 },
+        { 0x419bd0,   1, 0x04, 0x00900103 },
+        { 0x419be0,   1, 0x04, 0x00000001 },
+        { 0x419be4,   1, 0x04, 0x00000000 },
+        { 0x419c00,   1, 0x04, 0x00000002 },
+        { 0x419c04,   1, 0x04, 0x00000006 },
+        { 0x419c08,   1, 0x04, 0x00000002 },
+        { 0x419c20,   1, 0x04, 0x00000000 },
+        { 0x419cb0,   1, 0x04, 0x00060048 },
+        { 0x419ce8,   1, 0x04, 0x00000000 },
+        { 0x419cf4,   1, 0x04, 0x00000183 },
+        { 0x419d20,   1, 0x04, 0x02180000 },
+        { 0x419d24,   1, 0x04, 0x00001fff },
+        { 0x419e04,   3, 0x04, 0x00000000 },
+        { 0x419e10,   1, 0x04, 0x00000002 },
+        { 0x419e44,   1, 0x04, 0x001beff2 },
+        { 0x419e48,   1, 0x04, 0x00000000 },
+        { 0x419e4c,   1, 0x04, 0x0000000f },
+        { 0x419e50,  17, 0x04, 0x00000000 },
+        { 0x419e98,   1, 0x04, 0x00000000 },
+        { 0x419f50,   2, 0x04, 0x00000000 },
+        {}
+};
+
+struct nvc0_graph_init
+nvc8_grctx_init_9197[] = {
+        { 0x0002e4,   1, 0x04, 0x0000b001 },
+        {}
+};
+
+struct nvc0_graph_init
+nvc8_grctx_init_9297[] = {
+        { 0x003400, 128, 0x04, 0x00000000 },
+        { 0x00036c,   2, 0x04, 0x00000000 },
+        { 0x0007a4,   2, 0x04, 0x00000000 },
+        { 0x000374,   1, 0x04, 0x00000000 },
+        { 0x000378,   1, 0x04, 0x00000020 },
+        {}
+};
+
+static struct nvc0_graph_mthd
+nvc8_grctx_init_mthd[] = {
+        { 0x9097, nvc1_grctx_init_9097, },
+        { 0x9197, nvc8_grctx_init_9197, },
+        { 0x9297, nvc8_grctx_init_9297, },
+        { 0x902d, nvc0_grctx_init_902d, },
+        { 0x9039, nvc0_grctx_init_9039, },
+        { 0x90c0, nvc0_grctx_init_90c0, },
+        { 0x902d, nvc0_grctx_init_mthd_magic, },
+        {}
+};
+
+static struct nvc0_graph_init *
+nvc8_grctx_init_gpc[] = {
+        nvc0_grctx_init_gpc_0,
+        nvc0_grctx_init_gpc_1,
+        nvc8_grctx_init_tpc,
+        NULL
+};
+
+struct nouveau_oclass *
+nvc8_grctx_oclass = &(struct nvc0_grctx_oclass) {
+        .base.handle = NV_ENGCTX(GR, 0xc8),
+        .base.ofuncs = &(struct nouveau_ofuncs) {
+                .ctor = nvc0_graph_context_ctor,
+                .dtor = nvc0_graph_context_dtor,
+                .init = _nouveau_graph_context_init,
+                .fini = _nouveau_graph_context_fini,
+                .rd32 = _nouveau_graph_context_rd32,
+                .wr32 = _nouveau_graph_context_wr32,
+        },
+        .main = nvc0_grctx_generate_main,
+        .mods = nvc0_grctx_generate_mods,
+        .unkn = nvc0_grctx_generate_unkn,
+        .hub  = nvc0_grctx_init_hub,
+        .gpc  = nvc8_grctx_init_gpc,
+        .icmd = nvc8_grctx_init_icmd,
+        .mthd = nvc8_grctx_init_mthd,
+}.base;
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/ctxnvd7.c b/drivers/gpu/drm/nouveau/core/engine/graph/ctxnvd7.c
new file mode 100644
index 000000000000..438e78410808
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/core/engine/graph/ctxnvd7.c
@@ -0,0 +1,290 @@
+/*
+ * Copyright 2013 Red Hat Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Ben Skeggs <bskeggs@redhat.com>
+ */
+
+#include "nvc0.h"
+
+struct nvc0_graph_init
+nvd7_grctx_init_unk40xx[] = {
+        { 0x404004,  10, 0x04, 0x00000000 },
+        { 0x404044,   1, 0x04, 0x00000000 },
+        { 0x404094,   1, 0x04, 0x00000000 },
+        { 0x404098,  12, 0x04, 0x00000000 },
+        { 0x4040c8,   1, 0x04, 0xf0000087 },
+        { 0x4040d0,   6, 0x04, 0x00000000 },
+        { 0x4040e8,   1, 0x04, 0x00001000 },
+        { 0x4040f8,   1, 0x04, 0x00000000 },
+        { 0x404130,   1, 0x04, 0x00000000 },
+        { 0x404134,   1, 0x04, 0x00000000 },
+        { 0x404138,   1, 0x04, 0x20000040 },
+        { 0x404150,   1, 0x04, 0x0000002e },
+        { 0x404154,   1, 0x04, 0x00000400 },
+        { 0x404158,   1, 0x04, 0x00000200 },
+        { 0x404164,   1, 0x04, 0x00000055 },
+        { 0x404168,   1, 0x04, 0x00000000 },
+        { 0x404178,   2, 0x04, 0x00000000 },
+        { 0x404200,   8, 0x04, 0x00000000 },
+        {}
+};
+
+static struct nvc0_graph_init
+nvd7_grctx_init_unk58xx[] = {
+        { 0x405800,   1, 0x04, 0x0f8000bf },
+        { 0x405830,   1, 0x04, 0x02180324 },
+        { 0x405834,   1, 0x04, 0x08000000 },
+        { 0x405838,   1, 0x04, 0x00000000 },
+        { 0x405854,   1, 0x04, 0x00000000 },
+        { 0x405870,   4, 0x04, 0x00000001 },
+        { 0x405a00,   2, 0x04, 0x00000000 },
+        { 0x405a18,   1, 0x04, 0x00000000 },
+        {}
+};
+
+static struct nvc0_graph_init
+nvd7_grctx_init_unk64xx[] = {
+        { 0x4064a8,   1, 0x04, 0x00000000 },
+        { 0x4064ac,   1, 0x04, 0x00003fff },
+        { 0x4064b4,   3, 0x04, 0x00000000 },
+        { 0x4064c0,   1, 0x04, 0x801a0078 },
+        { 0x4064c4,   1, 0x04, 0x00c9ffff },
+        { 0x4064d0,   8, 0x04, 0x00000000 },
+        {}
+};
+
+static struct nvc0_graph_init
+nvd7_grctx_init_gpc_0[] = {
+        { 0x418380,   1, 0x04, 0x00000016 },
+        { 0x418400,   1, 0x04, 0x38004e00 },
+        { 0x418404,   1, 0x04, 0x71e0ffff },
+        { 0x41840c,   1, 0x04, 0x00001008 },
+        { 0x418410,   1, 0x04, 0x0fff0fff },
+        { 0x418414,   1, 0x04, 0x02200fff },
+        { 0x418450,   6, 0x04, 0x00000000 },
+        { 0x418468,   1, 0x04, 0x00000001 },
+        { 0x41846c,   2, 0x04, 0x00000000 },
+        { 0x418600,   1, 0x04, 0x0000001f },
+        { 0x418684,   1, 0x04, 0x0000000f },
+        { 0x418700,   1, 0x04, 0x00000002 },
+        { 0x418704,   1, 0x04, 0x00000080 },
+        { 0x418708,   3, 0x04, 0x00000000 },
+        { 0x418800,   1, 0x04, 0x7006860a },
+        { 0x418808,   3, 0x04, 0x00000000 },
+        { 0x418828,   1, 0x04, 0x00008442 },
+        { 0x418830,   1, 0x04, 0x10000001 },
+        { 0x4188d8,   1, 0x04, 0x00000008 },
+        { 0x4188e0,   1, 0x04, 0x01000000 },
+        { 0x4188e8,   5, 0x04, 0x00000000 },
+        { 0x4188fc,   1, 0x04, 0x20100018 },
+        { 0x41891c,   1, 0x04, 0x00ff00ff },
+        { 0x418924,   1, 0x04, 0x00000000 },
+        { 0x418928,   1, 0x04, 0x00ffff00 },
+        { 0x41892c,   1, 0x04, 0x0000ff00 },
+        { 0x418b00,   1, 0x04, 0x00000006 },
+        { 0x418b08,   1, 0x04, 0x0a418820 },
+        { 0x418b0c,   1, 0x04, 0x062080e6 },
+        { 0x418b10,   1, 0x04, 0x020398a4 },
+        { 0x418b14,   1, 0x04, 0x0e629062 },
+        { 0x418b18,   1, 0x04, 0x0a418820 },
+        { 0x418b1c,   1, 0x04, 0x000000e6 },
+        { 0x418bb8,   1, 0x04, 0x00000103 },
+        { 0x418c08,   1, 0x04, 0x00000001 },
+        { 0x418c10,   8, 0x04, 0x00000000 },
+        { 0x418c6c,   1, 0x04, 0x00000001 },
+        { 0x418c80,   1, 0x04, 0x20200004 },
+        { 0x418c8c,   1, 0x04, 0x00000001 },
+        { 0x419000,   1, 0x04, 0x00000780 },
+        { 0x419004,   2, 0x04, 0x00000000 },
+        { 0x419014,   1, 0x04, 0x00000004 },
+        {}
+};
+
+static struct nvc0_graph_init
+nvd7_grctx_init_tpc[] = {
+        { 0x419848,   1, 0x04, 0x00000000 },
+        { 0x419864,   1, 0x04, 0x00000129 },
+        { 0x419888,   1, 0x04, 0x00000000 },
+        { 0x419a00,   1, 0x04, 0x000001f0 },
+        { 0x419a04,   1, 0x04, 0x00000001 },
+        { 0x419a08,   1, 0x04, 0x00000023 },
+        { 0x419a0c,   1, 0x04, 0x00020000 },
+        { 0x419a10,   1, 0x04, 0x00000000 },
+        { 0x419a14,   1, 0x04, 0x00000200 },
+        { 0x419a1c,   1, 0x04, 0x00008000 },
+        { 0x419a20,   1, 0x04, 0x00000800 },
+        { 0x419ac4,   1, 0x04, 0x0017f440 },
+        { 0x419c00,   1, 0x04, 0x0000000a },
+        { 0x419c04,   1, 0x04, 0x00000006 },
+        { 0x419c08,   1, 0x04, 0x00000002 },
+        { 0x419c20,   1, 0x04, 0x00000000 },
+        { 0x419c24,   1, 0x04, 0x00084210 },
+        { 0x419c28,   1, 0x04, 0x3efbefbe },
+        { 0x419cb0,   1, 0x04, 0x00020048 },
+        { 0x419ce8,   1, 0x04, 0x00000000 },
+        { 0x419cf4,   1, 0x04, 0x00000183 },
+        { 0x419e04,   3, 0x04, 0x00000000 },
+        { 0x419e10,   1, 0x04, 0x00000002 },
+        { 0x419e44,   1, 0x04, 0x001beff2 },
+        { 0x419e48,   1, 0x04, 0x00000000 },
+        { 0x419e4c,   1, 0x04, 0x0000000f },
+        { 0x419e50,  17, 0x04, 0x00000000 },
+        { 0x419e98,   1, 0x04, 0x00000000 },
+        { 0x419ee0,   1, 0x04, 0x00010110 },
+        { 0x419f30,  11, 0x04, 0x00000000 },
+        {}
+};
+
+static struct nvc0_graph_init
+nvd7_grctx_init_unk[] = {
+        { 0x41be24,   1, 0x04, 0x00000002 },
+        { 0x41bec0,   1, 0x04, 0x12180000 },
+        { 0x41bec4,   1, 0x04, 0x00003fff },
+        { 0x41bee4,   1, 0x04, 0x03240218 },
+        { 0x41bf00,   1, 0x04, 0x0a418820 },
+        { 0x41bf04,   1, 0x04, 0x062080e6 },
+        { 0x41bf08,   1, 0x04, 0x020398a4 },
+        { 0x41bf0c,   1, 0x04, 0x0e629062 },
+        { 0x41bf10,   1, 0x04, 0x0a418820 },
+        { 0x41bf14,   1, 0x04, 0x000000e6 },
+        { 0x41bfd0,   1, 0x04, 0x00900103 },
+        { 0x41bfe0,   1, 0x04, 0x00400001 },
+        { 0x41bfe4,   1, 0x04, 0x00000000 },
+        {}
+};
+
+static void
+nvd7_grctx_generate_mods(struct nvc0_graph_priv *priv, struct nvc0_grctx *info)
+{
+        u32 magic[GPC_MAX][2];
+        u32 offset;
+        int gpc;
+
+        mmio_data(0x003000, 0x0100, NV_MEM_ACCESS_RW | NV_MEM_ACCESS_SYS);
+        mmio_data(0x008000, 0x0100, NV_MEM_ACCESS_RW | NV_MEM_ACCESS_SYS);
+        mmio_data(0x060000, 0x1000, NV_MEM_ACCESS_RW);
+        mmio_list(0x40800c, 0x00000000,  8, 1);
+        mmio_list(0x408010, 0x80000000,  0, 0);
+        mmio_list(0x419004, 0x00000000,  8, 1);
+        mmio_list(0x419008, 0x00000000,  0, 0);
+        mmio_list(0x408004, 0x00000000,  8, 0);
+        mmio_list(0x408008, 0x80000018,  0, 0);
+        mmio_list(0x418808, 0x00000000,  8, 0);
+        mmio_list(0x41880c, 0x80000018,  0, 0);
+        mmio_list(0x418810, 0x80000000, 12, 2);
+        mmio_list(0x419848, 0x10000000, 12, 2);
+
+        mmio_list(0x405830, 0x02180324,  0, 0);
+        mmio_list(0x4064c4, 0x00c9ffff,  0, 0);
+
+        for (gpc = 0, offset = 0; gpc < priv->gpc_nr; gpc++) {
+                u16 magic0 = 0x0218 * priv->tpc_nr[gpc];
+                u16 magic1 = 0x0324 * priv->tpc_nr[gpc];
+                magic[gpc][0]  = 0x10000000 | (magic0 << 16) | offset;
+                magic[gpc][1]  = 0x00000000 | (magic1 << 16);
+                offset += 0x0324 * priv->tpc_nr[gpc];
+        }
+
+        for (gpc = 0; gpc < priv->gpc_nr; gpc++) {
+                mmio_list(GPC_UNIT(gpc, 0x30c0), magic[gpc][0], 0, 0);
+                mmio_list(GPC_UNIT(gpc, 0x30e4), magic[gpc][1] | offset, 0, 0);
+                offset += 0x07ff * priv->tpc_nr[gpc];
+        }
+        mmio_list(0x17e91c, 0x03060609, 0, 0); /* different from kepler */
+}
+
+void
+nvd7_grctx_generate_main(struct nvc0_graph_priv *priv, struct nvc0_grctx *info)
+{
+        struct nvc0_grctx_oclass *oclass = (void *)nv_engine(priv)->cclass;
+        int i;
+
+        nv_mask(priv, 0x000260, 0x00000001, 0x00000000);
+
+        for (i = 0; oclass->hub[i]; i++)
+                nvc0_graph_mmio(priv, oclass->hub[i]);
+        for (i = 0; oclass->gpc[i]; i++)
+                nvc0_graph_mmio(priv, oclass->gpc[i]);
+
+        nv_wr32(priv, 0x404154, 0x00000000);
+
+        oclass->mods(priv, info);
+        oclass->unkn(priv);
+
+        nvc0_grctx_generate_tpcid(priv);
+        nvc0_grctx_generate_r406028(priv);
+        nvc0_grctx_generate_r4060a8(priv);
+        nve4_grctx_generate_r418bb8(priv);
+        nvc0_grctx_generate_r406800(priv);
+
+        for (i = 0; i < 8; i++)
+                nv_wr32(priv, 0x4064d0 + (i * 0x04), 0x00000000);
+
+        nvc0_graph_icmd(priv, oclass->icmd);
+        nv_wr32(priv, 0x404154, 0x00000400);
+        nvc0_graph_mthd(priv, oclass->mthd);
+        nv_mask(priv, 0x000260, 0x00000001, 0x00000001);
+}
+
+
+static struct nvc0_graph_init *
+nvd7_grctx_init_hub[] = {
+        nvc0_grctx_init_base,
+        nvd7_grctx_init_unk40xx,
+        nvc0_grctx_init_unk44xx,
+        nvc0_grctx_init_unk46xx,
+        nvc0_grctx_init_unk47xx,
+        nvd7_grctx_init_unk58xx,
+        nvc0_grctx_init_unk60xx,
+        nvd7_grctx_init_unk64xx,
+        nvc0_grctx_init_unk78xx,
+        nvc0_grctx_init_unk80xx,
+        nvd9_grctx_init_rop,
+};
+
+struct nvc0_graph_init *
+nvd7_grctx_init_gpc[] = {
+        nvd7_grctx_init_gpc_0,
+        nvc0_grctx_init_gpc_1,
+        nvd7_grctx_init_tpc,
+        nvd7_grctx_init_unk,
+        NULL
+};
+
+struct nouveau_oclass *
+nvd7_grctx_oclass = &(struct nvc0_grctx_oclass) {
+        .base.handle = NV_ENGCTX(GR, 0xd7),
+        .base.ofuncs = &(struct nouveau_ofuncs) {
+                .ctor = nvc0_graph_context_ctor,
+                .dtor = nvc0_graph_context_dtor,
+                .init = _nouveau_graph_context_init,
+                .fini = _nouveau_graph_context_fini,
+                .rd32 = _nouveau_graph_context_rd32,
+                .wr32 = _nouveau_graph_context_wr32,
+        },
+        .main = nvd7_grctx_generate_main,
+        .mods = nvd7_grctx_generate_mods,
+        .unkn = nve4_grctx_generate_unkn,
+        .hub  = nvd7_grctx_init_hub,
+        .gpc  = nvd7_grctx_init_gpc,
+        .icmd = nvd9_grctx_init_icmd,
+        .mthd = nvd9_grctx_init_mthd,
+}.base;
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/ctxnvd9.c b/drivers/gpu/drm/nouveau/core/engine/graph/ctxnvd9.c
new file mode 100644
index 000000000000..818a4751df46
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/core/engine/graph/ctxnvd9.c
@@ -0,0 +1,515 @@
+/*
+ * Copyright 2013 Red Hat Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Ben Skeggs <bskeggs@redhat.com>
+ */
+
+#include "nvc0.h"
+
+struct nvc0_graph_init
+nvd9_grctx_init_90c0[] = {
+        { 0x002700,   4, 0x40, 0x00000000 },
+        { 0x002720,   4, 0x40, 0x00000000 },
+        { 0x002704,   4, 0x40, 0x00000000 },
+        { 0x002724,   4, 0x40, 0x00000000 },
+        { 0x002708,   4, 0x40, 0x00000000 },
+        { 0x002728,   4, 0x40, 0x00000000 },
+        { 0x00270c,   8, 0x20, 0x00000000 },
+        { 0x002710,   4, 0x40, 0x00014000 },
+        { 0x002730,   4, 0x40, 0x00014000 },
+        { 0x002714,   4, 0x40, 0x00000040 },
+        { 0x002734,   4, 0x40, 0x00000040 },
+        { 0x00030c,   1, 0x04, 0x00000001 },
+        { 0x001944,   1, 0x04, 0x00000000 },
+        { 0x000758,   1, 0x04, 0x00000100 },
+        { 0x0002c4,   1, 0x04, 0x00000000 },
+        { 0x000790,   5, 0x04, 0x00000000 },
+        { 0x00077c,   1, 0x04, 0x00000000 },
+        { 0x000204,   3, 0x04, 0x00000000 },
+        { 0x000214,   1, 0x04, 0x00000000 },
+        { 0x00024c,   1, 0x04, 0x00000000 },
+        { 0x000d94,   1, 0x04, 0x00000001 },
+        { 0x001608,   2, 0x04, 0x00000000 },
+        { 0x001664,   1, 0x04, 0x00000000 },
+        {}
+};
+
+struct nvc0_graph_init
+nvd9_grctx_init_icmd[] = {
+        { 0x001000,   1, 0x01, 0x00000004 },
+        { 0x0000a9,   1, 0x01, 0x0000ffff },
+        { 0x000038,   1, 0x01, 0x0fac6881 },
+        { 0x00003d,   1, 0x01, 0x00000001 },
+        { 0x0000e8,   8, 0x01, 0x00000400 },
+        { 0x000078,   8, 0x01, 0x00000300 },
+        { 0x000050,   1, 0x01, 0x00000011 },
+        { 0x000058,   8, 0x01, 0x00000008 },
+        { 0x000208,   8, 0x01, 0x00000001 },
+        { 0x000081,   1, 0x01, 0x00000001 },
+        { 0x000085,   1, 0x01, 0x00000004 },
+        { 0x000088,   1, 0x01, 0x00000400 },
+        { 0x000090,   1, 0x01, 0x00000300 },
+        { 0x000098,   1, 0x01, 0x00001001 },
+        { 0x0000e3,   1, 0x01, 0x00000001 },
+        { 0x0000da,   1, 0x01, 0x00000001 },
+        { 0x0000f8,   1, 0x01, 0x00000003 },
+        { 0x0000fa,   1, 0x01, 0x00000001 },
+        { 0x00009f,   4, 0x01, 0x0000ffff },
+        { 0x0000b1,   1, 0x01, 0x00000001 },
+        { 0x0000b2,  40, 0x01, 0x00000000 },
+        { 0x000210,   8, 0x01, 0x00000040 },
+        { 0x000400,  24, 0x01, 0x00000040 },
+        { 0x000218,   8, 0x01, 0x0000c080 },
+        { 0x000440,  24, 0x01, 0x0000c080 },
+        { 0x0000ad,   1, 0x01, 0x0000013e },
+        { 0x0000e1,   1, 0x01, 0x00000010 },
+        { 0x000290,  16, 0x01, 0x00000000 },
+        { 0x0003b0,  16, 0x01, 0x00000000 },
+        { 0x0002a0,  16, 0x01, 0x00000000 },
+        { 0x000420,  16, 0x01, 0x00000000 },
+        { 0x0002b0,  16, 0x01, 0x00000000 },
+        { 0x000430,  16, 0x01, 0x00000000 },
+        { 0x0002c0,  16, 0x01, 0x00000000 },
+        { 0x0004d0,  16, 0x01, 0x00000000 },
+        { 0x000720,  16, 0x01, 0x00000000 },
+        { 0x0008c0,  16, 0x01, 0x00000000 },
+        { 0x000890,  16, 0x01, 0x00000000 },
+        { 0x0008e0,  16, 0x01, 0x00000000 },
+        { 0x0008a0,  16, 0x01, 0x00000000 },
+        { 0x0008f0,  16, 0x01, 0x00000000 },
+        { 0x00094c,   1, 0x01, 0x000000ff },
+        { 0x00094d,   1, 0x01, 0xffffffff },
+        { 0x00094e,   1, 0x01, 0x00000002 },
+        { 0x0002ec,   1, 0x01, 0x00000001 },
+        { 0x000303,   1, 0x01, 0x00000001 },
+        { 0x0002e6,   1, 0x01, 0x00000001 },
+        { 0x000466,   1, 0x01, 0x00000052 },
+        { 0x000301,   1, 0x01, 0x3f800000 },
+        { 0x000304,   1, 0x01, 0x30201000 },
+        { 0x000305,   1, 0x01, 0x70605040 },
+        { 0x000306,   1, 0x01, 0xb8a89888 },
+        { 0x000307,   1, 0x01, 0xf8e8d8c8 },
+        { 0x00030a,   1, 0x01, 0x00ffff00 },
+        { 0x00030b,   1, 0x01, 0x0000001a },
+        { 0x00030c,   1, 0x01, 0x00000001 },
+        { 0x000318,   1, 0x01, 0x00000001 },
+        { 0x000340,   1, 0x01, 0x00000000 },
+        { 0x000375,   1, 0x01, 0x00000001 },
+        { 0x000351,   1, 0x01, 0x00000100 },
+        { 0x00037d,   1, 0x01, 0x00000006 },
+        { 0x0003a0,   1, 0x01, 0x00000002 },
+        { 0x0003aa,   1, 0x01, 0x00000001 },
+        { 0x0003a9,   1, 0x01, 0x00000001 },
+        { 0x000380,   1, 0x01, 0x00000001 },
+        { 0x000360,   1, 0x01, 0x00000040 },
+        { 0x000366,   2, 0x01, 0x00000000 },
+        { 0x000368,   1, 0x01, 0x00001fff },
+        { 0x000370,   2, 0x01, 0x00000000 },
+        { 0x000372,   1, 0x01, 0x003fffff },
+        { 0x00037a,   1, 0x01, 0x00000012 },
+        { 0x0005e0,   5, 0x01, 0x00000022 },
+        { 0x000619,   1, 0x01, 0x00000003 },
+        { 0x000811,   1, 0x01, 0x00000003 },
+        { 0x000812,   1, 0x01, 0x00000004 },
+        { 0x000813,   1, 0x01, 0x00000006 },
+        { 0x000814,   1, 0x01, 0x00000008 },
+        { 0x000815,   1, 0x01, 0x0000000b },
+        { 0x000800,   6, 0x01, 0x00000001 },
+        { 0x000632,   1, 0x01, 0x00000001 },
+        { 0x000633,   1, 0x01, 0x00000002 },
+        { 0x000634,   1, 0x01, 0x00000003 },
+        { 0x000635,   1, 0x01, 0x00000004 },
+        { 0x000654,   1, 0x01, 0x3f800000 },
+        { 0x000657,   1, 0x01, 0x3f800000 },
+        { 0x000655,   2, 0x01, 0x3f800000 },
+        { 0x0006cd,   1, 0x01, 0x3f800000 },
+        { 0x0007f5,   1, 0x01, 0x3f800000 },
+        { 0x0007dc,   1, 0x01, 0x39291909 },
+        { 0x0007dd,   1, 0x01, 0x79695949 },
+        { 0x0007de,   1, 0x01, 0xb9a99989 },
+        { 0x0007df,   1, 0x01, 0xf9e9d9c9 },
+        { 0x0007e8,   1, 0x01, 0x00003210 },
+        { 0x0007e9,   1, 0x01, 0x00007654 },
+        { 0x0007ea,   1, 0x01, 0x00000098 },
+        { 0x0007ec,   1, 0x01, 0x39291909 },
+        { 0x0007ed,   1, 0x01, 0x79695949 },
+        { 0x0007ee,   1, 0x01, 0xb9a99989 },
+        { 0x0007ef,   1, 0x01, 0xf9e9d9c9 },
+        { 0x0007f0,   1, 0x01, 0x00003210 },
+        { 0x0007f1,   1, 0x01, 0x00007654 },
+        { 0x0007f2,   1, 0x01, 0x00000098 },
+        { 0x0005a5,   1, 0x01, 0x00000001 },
+        { 0x000980, 128, 0x01, 0x00000000 },
+        { 0x000468,   1, 0x01, 0x00000004 },
+        { 0x00046c,   1, 0x01, 0x00000001 },
+        { 0x000470,  96, 0x01, 0x00000000 },
+        { 0x000510,  16, 0x01, 0x3f800000 },
+        { 0x000520,   1, 0x01, 0x000002b6 },
+        { 0x000529,   1, 0x01, 0x00000001 },
+        { 0x000530,  16, 0x01, 0xffff0000 },
+        { 0x000585,   1, 0x01, 0x0000003f },
+        { 0x000576,   1, 0x01, 0x00000003 },
+        { 0x00057b,   1, 0x01, 0x00000059 },
+        { 0x000586,   1, 0x01, 0x00000040 },
+        { 0x000582,   2, 0x01, 0x00000080 },
+        { 0x0005c2,   1, 0x01, 0x00000001 },
+        { 0x000638,   1, 0x01, 0x00000001 },
+        { 0x000639,   1, 0x01, 0x00000001 },
+        { 0x00063a,   1, 0x01, 0x00000002 },
+        { 0x00063b,   2, 0x01, 0x00000001 },
+        { 0x00063d,   1, 0x01, 0x00000002 },
+        { 0x00063e,   1, 0x01, 0x00000001 },
+        { 0x0008b8,   8, 0x01, 0x00000001 },
+        { 0x000900,   8, 0x01, 0x00000001 },
+        { 0x000908,   8, 0x01, 0x00000002 },
+        { 0x000910,  16, 0x01, 0x00000001 },
+        { 0x000920,   8, 0x01, 0x00000002 },
+        { 0x000928,   8, 0x01, 0x00000001 },
+        { 0x000648,   9, 0x01, 0x00000001 },
+        { 0x000658,   1, 0x01, 0x0000000f },
+        { 0x0007ff,   1, 0x01, 0x0000000a },
+        { 0x00066a,   1, 0x01, 0x40000000 },
+        { 0x00066b,   1, 0x01, 0x10000000 },
+        { 0x00066c,   2, 0x01, 0xffff0000 },
+        { 0x0007af,   2, 0x01, 0x00000008 },
+        { 0x0007f6,   1, 0x01, 0x00000001 },
+        { 0x0006b2,   1, 0x01, 0x00000055 },
+        { 0x0007ad,   1, 0x01, 0x00000003 },
+        { 0x000937,   1, 0x01, 0x00000001 },
+        { 0x000971,   1, 0x01, 0x00000008 },
+        { 0x000972,   1, 0x01, 0x00000040 },
+        { 0x000973,   1, 0x01, 0x0000012c },
+        { 0x00097c,   1, 0x01, 0x00000040 },
+        { 0x000979,   1, 0x01, 0x00000003 },
+        { 0x000975,   1, 0x01, 0x00000020 },
+        { 0x000976,   1, 0x01, 0x00000001 },
+        { 0x000977,   1, 0x01, 0x00000020 },
+        { 0x000978,   1, 0x01, 0x00000001 },
+        { 0x000957,   1, 0x01, 0x00000003 },
+        { 0x00095e,   1, 0x01, 0x20164010 },
+        { 0x00095f,   1, 0x01, 0x00000020 },
+        { 0x00097d,   1, 0x01, 0x00000020 },
+        { 0x000683,   1, 0x01, 0x00000006 },
+        { 0x000685,   1, 0x01, 0x003fffff },
+        { 0x000687,   1, 0x01, 0x00000c48 },
+        { 0x0006a0,   1, 0x01, 0x00000005 },
+        { 0x000840,   1, 0x01, 0x00300008 },
+        { 0x000841,   1, 0x01, 0x04000080 },
+        { 0x000842,   1, 0x01, 0x00300008 },
+        { 0x000843,   1, 0x01, 0x04000080 },
+        { 0x000818,   8, 0x01, 0x00000000 },
+        { 0x000848,  16, 0x01, 0x00000000 },
+        { 0x000738,   1, 0x01, 0x00000000 },
+        { 0x0006aa,   1, 0x01, 0x00000001 },
+        { 0x0006ab,   1, 0x01, 0x00000002 },
+        { 0x0006ac,   1, 0x01, 0x00000080 },
+        { 0x0006ad,   2, 0x01, 0x00000100 },
+        { 0x0006b1,   1, 0x01, 0x00000011 },
+        { 0x0006bb,   1, 0x01, 0x000000cf },
+        { 0x0006ce,   1, 0x01, 0x2a712488 },
+        { 0x000739,   1, 0x01, 0x4085c000 },
+        { 0x00073a,   1, 0x01, 0x00000080 },
+        { 0x000786,   1, 0x01, 0x80000100 },
+        { 0x00073c,   1, 0x01, 0x00010100 },
+        { 0x00073d,   1, 0x01, 0x02800000 },
+        { 0x000787,   1, 0x01, 0x000000cf },
+        { 0x00078c,   1, 0x01, 0x00000008 },
+        { 0x000792,   1, 0x01, 0x00000001 },
+        { 0x000794,   1, 0x01, 0x00000001 },
+        { 0x000795,   2, 0x01, 0x00000001 },
+        { 0x000797,   1, 0x01, 0x000000cf },
+        { 0x000836,   1, 0x01, 0x00000001 },
+        { 0x00079a,   1, 0x01, 0x00000002 },
+        { 0x000833,   1, 0x01, 0x04444480 },
+        { 0x0007a1,   1, 0x01, 0x00000001 },
+        { 0x0007a3,   1, 0x01, 0x00000001 },
+        { 0x0007a4,   2, 0x01, 0x00000001 },
+        { 0x000831,   1, 0x01, 0x00000004 },
+        { 0x00080c,   1, 0x01, 0x00000002 },
+        { 0x00080d,   2, 0x01, 0x00000100 },
+        { 0x00080f,   1, 0x01, 0x00000001 },
+        { 0x000823,   1, 0x01, 0x00000002 },
+        { 0x000824,   2, 0x01, 0x00000100 },
+        { 0x000826,   1, 0x01, 0x00000001 },
+        { 0x00095d,   1, 0x01, 0x00000001 },
+        { 0x00082b,   1, 0x01, 0x00000004 },
+        { 0x000942,   1, 0x01, 0x00010001 },
+        { 0x000943,   1, 0x01, 0x00000001 },
+        { 0x000944,   1, 0x01, 0x00000022 },
+        { 0x0007c5,   1, 0x01, 0x00010001 },
+        { 0x000834,   1, 0x01, 0x00000001 },
+        { 0x0007c7,   1, 0x01, 0x00000001 },
+        { 0x00c1b0,   8, 0x01, 0x0000000f },
+        { 0x00c1b8,   1, 0x01, 0x0fac6881 },
+        { 0x00c1b9,   1, 0x01, 0x00fac688 },
+        { 0x01e100,   1, 0x01, 0x00000001 },
+        { 0x001000,   1, 0x01, 0x00000002 },
+        { 0x0006aa,   1, 0x01, 0x00000001 },
+        { 0x0006ad,   2, 0x01, 0x00000100 },
+        { 0x0006b1,   1, 0x01, 0x00000011 },
+        { 0x00078c,   1, 0x01, 0x00000008 },
+        { 0x000792,   1, 0x01, 0x00000001 },
+        { 0x000794,   1, 0x01, 0x00000001 },
+        { 0x000795,   2, 0x01, 0x00000001 },
+        { 0x000797,   1, 0x01, 0x000000cf },
+        { 0x00079a,   1, 0x01, 0x00000002 },
+        { 0x000833,   1, 0x01, 0x04444480 },
+        { 0x0007a1,   1, 0x01, 0x00000001 },
+        { 0x0007a3,   1, 0x01, 0x00000001 },
+        { 0x0007a4,   2, 0x01, 0x00000001 },
+        { 0x000831,   1, 0x01, 0x00000004 },
+        { 0x01e100,   1, 0x01, 0x00000001 },
+        { 0x001000,   1, 0x01, 0x00000014 },
+        { 0x000351,   1, 0x01, 0x00000100 },
+        { 0x000957,   1, 0x01, 0x00000003 },
+        { 0x00095d,   1, 0x01, 0x00000001 },
+        { 0x00082b,   1, 0x01, 0x00000004 },
+        { 0x000942,   1, 0x01, 0x00010001 },
+        { 0x000943,   1, 0x01, 0x00000001 },
+        { 0x0007c5,   1, 0x01, 0x00010001 },
+        { 0x000834,   1, 0x01, 0x00000001 },
+        { 0x0007c7,   1, 0x01, 0x00000001 },
+        { 0x01e100,   1, 0x01, 0x00000001 },
+        { 0x001000,   1, 0x01, 0x00000001 },
+        { 0x00080c,   1, 0x01, 0x00000002 },
+        { 0x00080d,   2, 0x01, 0x00000100 },
+        { 0x00080f,   1, 0x01, 0x00000001 },
+        { 0x000823,   1, 0x01, 0x00000002 },
+        { 0x000824,   2, 0x01, 0x00000100 },
+        { 0x000826,   1, 0x01, 0x00000001 },
+        { 0x01e100,   1, 0x01, 0x00000001 },
+        {}
+};
+
+struct nvc0_graph_init
+nvd9_grctx_init_unk40xx[] = {
+        { 0x404004,  11, 0x04, 0x00000000 },
+        { 0x404044,   1, 0x04, 0x00000000 },
+        { 0x404094,   1, 0x04, 0x00000000 },
+        { 0x404098,  12, 0x04, 0x00000000 },
+        { 0x4040c8,   1, 0x04, 0xf0000087 },
+        { 0x4040d0,   6, 0x04, 0x00000000 },
+        { 0x4040e8,   1, 0x04, 0x00001000 },
+        { 0x4040f8,   1, 0x04, 0x00000000 },
+        { 0x404130,   1, 0x04, 0x00000000 },
+        { 0x404134,   1, 0x04, 0x00000000 },
+        { 0x404138,   1, 0x04, 0x20000040 },
+        { 0x404150,   1, 0x04, 0x0000002e },
+        { 0x404154,   1, 0x04, 0x00000400 },
+        { 0x404158,   1, 0x04, 0x00000200 },
+        { 0x404164,   1, 0x04, 0x00000055 },
+        { 0x404168,   1, 0x04, 0x00000000 },
+        { 0x404178,   2, 0x04, 0x00000000 },
+        { 0x404200,   8, 0x04, 0x00000000 },
+        {}
+};
+
+static struct nvc0_graph_init
+nvd9_grctx_init_unk58xx[] = {
+        { 0x405800,   1, 0x04, 0x0f8000bf },
+        { 0x405830,   1, 0x04, 0x02180218 },
+        { 0x405834,   1, 0x04, 0x08000000 },
+        { 0x405838,   1, 0x04, 0x00000000 },
+        { 0x405854,   1, 0x04, 0x00000000 },
+        { 0x405870,   4, 0x04, 0x00000001 },
+        { 0x405a00,   2, 0x04, 0x00000000 },
+        { 0x405a18,   1, 0x04, 0x00000000 },
+        {}
+};
+
+static struct nvc0_graph_init
+nvd9_grctx_init_unk64xx[] = {
+        { 0x4064a8,   1, 0x04, 0x00000000 },
+        { 0x4064ac,   1, 0x04, 0x00003fff },
+        { 0x4064b4,   3, 0x04, 0x00000000 },
+        { 0x4064c0,   1, 0x04, 0x80140078 },
+        { 0x4064c4,   1, 0x04, 0x0086ffff },
+        {}
+};
+
+struct nvc0_graph_init
+nvd9_grctx_init_rop[] = {
+        { 0x408800,   1, 0x04, 0x02802a3c },
+        { 0x408804,   1, 0x04, 0x00000040 },
+        { 0x408808,   1, 0x04, 0x1043e005 },
+        { 0x408900,   1, 0x04, 0x3080b801 },
+        { 0x408904,   1, 0x04, 0x1043e005 },
+        { 0x408908,   1, 0x04, 0x00c8102f },
+        { 0x408980,   1, 0x04, 0x0000011d },
+        {}
+};
+
+static struct nvc0_graph_init
+nvd9_grctx_init_gpc_0[] = {
+        { 0x418380,   1, 0x04, 0x00000016 },
+        { 0x418400,   1, 0x04, 0x38004e00 },
+        { 0x418404,   1, 0x04, 0x71e0ffff },
+        { 0x41840c,   1, 0x04, 0x00001008 },
+        { 0x418410,   1, 0x04, 0x0fff0fff },
+        { 0x418414,   1, 0x04, 0x02200fff },
+        { 0x418450,   6, 0x04, 0x00000000 },
+        { 0x418468,   1, 0x04, 0x00000001 },
+        { 0x41846c,   2, 0x04, 0x00000000 },
+        { 0x418600,   1, 0x04, 0x0000001f },
+        { 0x418684,   1, 0x04, 0x0000000f },
+        { 0x418700,   1, 0x04, 0x00000002 },
+        { 0x418704,   1, 0x04, 0x00000080 },
+        { 0x418708,   3, 0x04, 0x00000000 },
+        { 0x418800,   1, 0x04, 0x7006860a },
+        { 0x418808,   3, 0x04, 0x00000000 },
+        { 0x418828,   1, 0x04, 0x00008442 },
+        { 0x418830,   1, 0x04, 0x10000001 },
+        { 0x4188d8,   1, 0x04, 0x00000008 },
+        { 0x4188e0,   1, 0x04, 0x01000000 },
+        { 0x4188e8,   5, 0x04, 0x00000000 },
+        { 0x4188fc,   1, 0x04, 0x20100008 },
+        { 0x41891c,   1, 0x04, 0x00ff00ff },
+        { 0x418924,   1, 0x04, 0x00000000 },
+        { 0x418928,   1, 0x04, 0x00ffff00 },
+        { 0x41892c,   1, 0x04, 0x0000ff00 },
+        { 0x418b00,   1, 0x04, 0x00000006 },
+        { 0x418b08,   1, 0x04, 0x0a418820 },
+        { 0x418b0c,   1, 0x04, 0x062080e6 },
+        { 0x418b10,   1, 0x04, 0x020398a4 },
+        { 0x418b14,   1, 0x04, 0x0e629062 },
+        { 0x418b18,   1, 0x04, 0x0a418820 },
+        { 0x418b1c,   1, 0x04, 0x000000e6 },
+        { 0x418bb8,   1, 0x04, 0x00000103 },
+        { 0x418c08,   1, 0x04, 0x00000001 },
+        { 0x418c10,   8, 0x04, 0x00000000 },
+        { 0x418c6c,   1, 0x04, 0x00000001 },
+        { 0x418c80,   1, 0x04, 0x20200004 },
+        { 0x418c8c,   1, 0x04, 0x00000001 },
+        { 0x419000,   1, 0x04, 0x00000780 },
+        { 0x419004,   2, 0x04, 0x00000000 },
+        { 0x419014,   1, 0x04, 0x00000004 },
+        {}
+};
+
+static struct nvc0_graph_init
+nvd9_grctx_init_tpc[] = {
+        { 0x419818,   1, 0x04, 0x00000000 },
+        { 0x41983c,   1, 0x04, 0x00038bc7 },
+        { 0x419848,   1, 0x04, 0x00000000 },
+        { 0x419864,   1, 0x04, 0x00000129 },
+        { 0x419888,   1, 0x04, 0x00000000 },
+        { 0x419a00,   1, 0x04, 0x000001f0 },
+        { 0x419a04,   1, 0x04, 0x00000001 },
+        { 0x419a08,   1, 0x04, 0x00000023 },
+        { 0x419a0c,   1, 0x04, 0x00020000 },
+        { 0x419a10,   1, 0x04, 0x00000000 },
+        { 0x419a14,   1, 0x04, 0x00000200 },
+        { 0x419a1c,   1, 0x04, 0x00000000 },
+        { 0x419a20,   1, 0x04, 0x00000800 },
+        { 0x419ac4,   1, 0x04, 0x0017f440 },
+        { 0x419b00,   1, 0x04, 0x0a418820 },
+        { 0x419b04,   1, 0x04, 0x062080e6 },
+        { 0x419b08,   1, 0x04, 0x020398a4 },
+        { 0x419b0c,   1, 0x04, 0x0e629062 },
+        { 0x419b10,   1, 0x04, 0x0a418820 },
+        { 0x419b14,   1, 0x04, 0x000000e6 },
+        { 0x419bd0,   1, 0x04, 0x00900103 },
+        { 0x419be0,   1, 0x04, 0x00400001 },
+        { 0x419be4,   1, 0x04, 0x00000000 },
+        { 0x419c00,   1, 0x04, 0x0000000a },
+        { 0x419c04,   1, 0x04, 0x00000006 },
+        { 0x419c08,   1, 0x04, 0x00000002 },
+        { 0x419c20,   1, 0x04, 0x00000000 },
+        { 0x419c24,   1, 0x04, 0x00084210 },
+        { 0x419c28,   1, 0x04, 0x3cf3cf3c },
+        { 0x419cb0,   1, 0x04, 0x00020048 },
+        { 0x419ce8,   1, 0x04, 0x00000000 },
+        { 0x419cf4,   1, 0x04, 0x00000183 },
+        { 0x419d20,   1, 0x04, 0x12180000 },
+        { 0x419d24,   1, 0x04, 0x00001fff },
+        { 0x419d44,   1, 0x04, 0x02180218 },
+        { 0x419e04,   3, 0x04, 0x00000000 },
+        { 0x419e10,   1, 0x04, 0x00000002 },
+        { 0x419e44,   1, 0x04, 0x001beff2 },
+        { 0x419e48,   1, 0x04, 0x00000000 },
+        { 0x419e4c,   1, 0x04, 0x0000000f },
+        { 0x419e50,  17, 0x04, 0x00000000 },
+        { 0x419e98,   1, 0x04, 0x00000000 },
+        { 0x419ee0,   1, 0x04, 0x00010110 },
+        { 0x419f30,  11, 0x04, 0x00000000 },
+        {}
+};
+
+static struct nvc0_graph_init *
+nvd9_grctx_init_hub[] = {
+        nvc0_grctx_init_base,
+        nvd9_grctx_init_unk40xx,
+        nvc0_grctx_init_unk44xx,
+        nvc0_grctx_init_unk46xx,
+        nvc0_grctx_init_unk47xx,
+        nvd9_grctx_init_unk58xx,
+        nvc0_grctx_init_unk60xx,
+        nvd9_grctx_init_unk64xx,
+        nvc0_grctx_init_unk78xx,
+        nvc0_grctx_init_unk80xx,
+        nvd9_grctx_init_rop,
+};
+
+struct nvc0_graph_init *
+nvd9_grctx_init_gpc[] = {
+        nvd9_grctx_init_gpc_0,
+        nvc0_grctx_init_gpc_1,
+        nvd9_grctx_init_tpc,
+        NULL
+};
+
+struct nvc0_graph_init
+nvd9_grctx_init_mthd_magic[] = {
+        { 0x3410, 1, 0x04, 0x80002006 },
+        {}
+};
+
+struct nvc0_graph_mthd
+nvd9_grctx_init_mthd[] = {
+        { 0x9097, nvc1_grctx_init_9097, },
+        { 0x9197, nvc8_grctx_init_9197, },
+        { 0x9297, nvc8_grctx_init_9297, },
+        { 0x902d, nvc0_grctx_init_902d, },
+        { 0x9039, nvc0_grctx_init_9039, },
+        { 0x90c0, nvd9_grctx_init_90c0, },
+        { 0x902d, nvd9_grctx_init_mthd_magic, },
+        {}
+};
+
+struct nouveau_oclass *
+nvd9_grctx_oclass = &(struct nvc0_grctx_oclass) {
+        .base.handle = NV_ENGCTX(GR, 0xd9),
+        .base.ofuncs = &(struct nouveau_ofuncs) {
+                .ctor = nvc0_graph_context_ctor,
+                .dtor = nvc0_graph_context_dtor,
+                .init = _nouveau_graph_context_init,
+                .fini = _nouveau_graph_context_fini,
+                .rd32 = _nouveau_graph_context_rd32,
+                .wr32 = _nouveau_graph_context_wr32,
+        },
+        .main = nvc0_grctx_generate_main,
+        .mods = nvc1_grctx_generate_mods,
+        .unkn = nvc1_grctx_generate_unkn,
+        .hub  = nvd9_grctx_init_hub,
+        .gpc  = nvd9_grctx_init_gpc,
+        .icmd = nvd9_grctx_init_icmd,
+        .mthd = nvd9_grctx_init_mthd,
+}.base;
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/ctxnve0.c b/drivers/gpu/drm/nouveau/core/engine/graph/ctxnve0.c
deleted file mode 100644
index ae27dae3fe38..000000000000
--- a/drivers/gpu/drm/nouveau/core/engine/graph/ctxnve0.c
+++ /dev/null
@@ -1,2793 +0,0 @@
-/*
- * Copyright 2010 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-
-#include "nvc0.h"
-
-static void
-nve0_grctx_generate_icmd(struct nvc0_graph_priv *priv)
-{
-        nv_wr32(priv, 0x400208, 0x80000000);
-        nv_icmd(priv, 0x001000, 0x00000004);
-        nv_icmd(priv, 0x000039, 0x00000000);
-        nv_icmd(priv, 0x00003a, 0x00000000);
-        nv_icmd(priv, 0x00003b, 0x00000000);
-        nv_icmd(priv, 0x0000a9, 0x0000ffff);
-        nv_icmd(priv, 0x000038, 0x0fac6881);
-        nv_icmd(priv, 0x00003d, 0x00000001);
-        nv_icmd(priv, 0x0000e8, 0x00000400);
-        nv_icmd(priv, 0x0000e9, 0x00000400);
-        nv_icmd(priv, 0x0000ea, 0x00000400);
-        nv_icmd(priv, 0x0000eb, 0x00000400);
-        nv_icmd(priv, 0x0000ec, 0x00000400);
-        nv_icmd(priv, 0x0000ed, 0x00000400);
-        nv_icmd(priv, 0x0000ee, 0x00000400);
-        nv_icmd(priv, 0x0000ef, 0x00000400);
-        nv_icmd(priv, 0x000078, 0x00000300);
-        nv_icmd(priv, 0x000079, 0x00000300);
-        nv_icmd(priv, 0x00007a, 0x00000300);
-        nv_icmd(priv, 0x00007b, 0x00000300);
-        nv_icmd(priv, 0x00007c, 0x00000300);
-        nv_icmd(priv, 0x00007d, 0x00000300);
-        nv_icmd(priv, 0x00007e, 0x00000300);
-        nv_icmd(priv, 0x00007f, 0x00000300);
-        nv_icmd(priv, 0x000050, 0x00000011);
-        nv_icmd(priv, 0x000058, 0x00000008);
-        nv_icmd(priv, 0x000059, 0x00000008);
-        nv_icmd(priv, 0x00005a, 0x00000008);
-        nv_icmd(priv, 0x00005b, 0x00000008);
-        nv_icmd(priv, 0x00005c, 0x00000008);
-        nv_icmd(priv, 0x00005d, 0x00000008);
-        nv_icmd(priv, 0x00005e, 0x00000008);
-        nv_icmd(priv, 0x00005f, 0x00000008);
-        nv_icmd(priv, 0x000208, 0x00000001);
-        nv_icmd(priv, 0x000209, 0x00000001);
-        nv_icmd(priv, 0x00020a, 0x00000001);
-        nv_icmd(priv, 0x00020b, 0x00000001);
-        nv_icmd(priv, 0x00020c, 0x00000001);
-        nv_icmd(priv, 0x00020d, 0x00000001);
-        nv_icmd(priv, 0x00020e, 0x00000001);
-        nv_icmd(priv, 0x00020f, 0x00000001);
-        nv_icmd(priv, 0x000081, 0x00000001);
-        nv_icmd(priv, 0x000085, 0x00000004);
-        nv_icmd(priv, 0x000088, 0x00000400);
-        nv_icmd(priv, 0x000090, 0x00000300);
-        nv_icmd(priv, 0x000098, 0x00001001);
-        nv_icmd(priv, 0x0000e3, 0x00000001);
-        nv_icmd(priv, 0x0000da, 0x00000001);
-        nv_icmd(priv, 0x0000f8, 0x00000003);
-        nv_icmd(priv, 0x0000fa, 0x00000001);
-        nv_icmd(priv, 0x00009f, 0x0000ffff);
-        nv_icmd(priv, 0x0000a0, 0x0000ffff);
-        nv_icmd(priv, 0x0000a1, 0x0000ffff);
-        nv_icmd(priv, 0x0000a2, 0x0000ffff);
-        nv_icmd(priv, 0x0000b1, 0x00000001);
-        nv_icmd(priv, 0x0000ad, 0x0000013e);
-        nv_icmd(priv, 0x0000e1, 0x00000010);
-        nv_icmd(priv, 0x000290, 0x00000000);
-        nv_icmd(priv, 0x000291, 0x00000000);
-        nv_icmd(priv, 0x000292, 0x00000000);
-        nv_icmd(priv, 0x000293, 0x00000000);
-        nv_icmd(priv, 0x000294, 0x00000000);
-        nv_icmd(priv, 0x000295, 0x00000000);
-        nv_icmd(priv, 0x000296, 0x00000000);
-        nv_icmd(priv, 0x000297, 0x00000000);
-        nv_icmd(priv, 0x000298, 0x00000000);
-        nv_icmd(priv, 0x000299, 0x00000000);
-        nv_icmd(priv, 0x00029a, 0x00000000);
-        nv_icmd(priv, 0x00029b, 0x00000000);
-        nv_icmd(priv, 0x00029c, 0x00000000);
-        nv_icmd(priv, 0x00029d, 0x00000000);
-        nv_icmd(priv, 0x00029e, 0x00000000);
-        nv_icmd(priv, 0x00029f, 0x00000000);
-        nv_icmd(priv, 0x0003b0, 0x00000000);
-        nv_icmd(priv, 0x0003b1, 0x00000000);
-        nv_icmd(priv, 0x0003b2, 0x00000000);
-        nv_icmd(priv, 0x0003b3, 0x00000000);
-        nv_icmd(priv, 0x0003b4, 0x00000000);
-        nv_icmd(priv, 0x0003b5, 0x00000000);
-        nv_icmd(priv, 0x0003b6, 0x00000000);
-        nv_icmd(priv, 0x0003b7, 0x00000000);
-        nv_icmd(priv, 0x0003b8, 0x00000000);
-        nv_icmd(priv, 0x0003b9, 0x00000000);
-        nv_icmd(priv, 0x0003ba, 0x00000000);
-        nv_icmd(priv, 0x0003bb, 0x00000000);
-        nv_icmd(priv, 0x0003bc, 0x00000000);
-        nv_icmd(priv, 0x0003bd, 0x00000000);
-        nv_icmd(priv, 0x0003be, 0x00000000);
-        nv_icmd(priv, 0x0003bf, 0x00000000);
-        nv_icmd(priv, 0x0002a0, 0x00000000);
-        nv_icmd(priv, 0x0002a1, 0x00000000);
-        nv_icmd(priv, 0x0002a2, 0x00000000);
-        nv_icmd(priv, 0x0002a3, 0x00000000);
-        nv_icmd(priv, 0x0002a4, 0x00000000);
-        nv_icmd(priv, 0x0002a5, 0x00000000);
-        nv_icmd(priv, 0x0002a6, 0x00000000);
-        nv_icmd(priv, 0x0002a7, 0x00000000);
-        nv_icmd(priv, 0x0002a8, 0x00000000);
-        nv_icmd(priv, 0x0002a9, 0x00000000);
-        nv_icmd(priv, 0x0002aa, 0x00000000);
-        nv_icmd(priv, 0x0002ab, 0x00000000);
-        nv_icmd(priv, 0x0002ac, 0x00000000);
-        nv_icmd(priv, 0x0002ad, 0x00000000);
-        nv_icmd(priv, 0x0002ae, 0x00000000);
-        nv_icmd(priv, 0x0002af, 0x00000000);
-        nv_icmd(priv, 0x000420, 0x00000000);
-        nv_icmd(priv, 0x000421, 0x00000000);
-        nv_icmd(priv, 0x000422, 0x00000000);
-        nv_icmd(priv, 0x000423, 0x00000000);
-        nv_icmd(priv, 0x000424, 0x00000000);
-        nv_icmd(priv, 0x000425, 0x00000000);
-        nv_icmd(priv, 0x000426, 0x00000000);
-        nv_icmd(priv, 0x000427, 0x00000000);
-        nv_icmd(priv, 0x000428, 0x00000000);
-        nv_icmd(priv, 0x000429, 0x00000000);
-        nv_icmd(priv, 0x00042a, 0x00000000);
-        nv_icmd(priv, 0x00042b, 0x00000000);
-        nv_icmd(priv, 0x00042c, 0x00000000);
-        nv_icmd(priv, 0x00042d, 0x00000000);
-        nv_icmd(priv, 0x00042e, 0x00000000);
-        nv_icmd(priv, 0x00042f, 0x00000000);
-        nv_icmd(priv, 0x0002b0, 0x00000000);
-        nv_icmd(priv, 0x0002b1, 0x00000000);
-        nv_icmd(priv, 0x0002b2, 0x00000000);
-        nv_icmd(priv, 0x0002b3, 0x00000000);
-        nv_icmd(priv, 0x0002b4, 0x00000000);
-        nv_icmd(priv, 0x0002b5, 0x00000000);
-        nv_icmd(priv, 0x0002b6, 0x00000000);
-        nv_icmd(priv, 0x0002b7, 0x00000000);
-        nv_icmd(priv, 0x0002b8, 0x00000000);
-        nv_icmd(priv, 0x0002b9, 0x00000000);
-        nv_icmd(priv, 0x0002ba, 0x00000000);
-        nv_icmd(priv, 0x0002bb, 0x00000000);
-        nv_icmd(priv, 0x0002bc, 0x00000000);
-        nv_icmd(priv, 0x0002bd, 0x00000000);
-        nv_icmd(priv, 0x0002be, 0x00000000);
-        nv_icmd(priv, 0x0002bf, 0x00000000);
-        nv_icmd(priv, 0x000430, 0x00000000);
-        nv_icmd(priv, 0x000431, 0x00000000);
-        nv_icmd(priv, 0x000432, 0x00000000);
-        nv_icmd(priv, 0x000433, 0x00000000);
-        nv_icmd(priv, 0x000434, 0x00000000);
-        nv_icmd(priv, 0x000435, 0x00000000);
-        nv_icmd(priv, 0x000436, 0x00000000);
-        nv_icmd(priv, 0x000437, 0x00000000);
-        nv_icmd(priv, 0x000438, 0x00000000);
-        nv_icmd(priv, 0x000439, 0x00000000);
-        nv_icmd(priv, 0x00043a, 0x00000000);
-        nv_icmd(priv, 0x00043b, 0x00000000);
-        nv_icmd(priv, 0x00043c, 0x00000000);
-        nv_icmd(priv, 0x00043d, 0x00000000);
-        nv_icmd(priv, 0x00043e, 0x00000000);
-        nv_icmd(priv, 0x00043f, 0x00000000);
-        nv_icmd(priv, 0x0002c0, 0x00000000);
-        nv_icmd(priv, 0x0002c1, 0x00000000);
-        nv_icmd(priv, 0x0002c2, 0x00000000);
-        nv_icmd(priv, 0x0002c3, 0x00000000);
-        nv_icmd(priv, 0x0002c4, 0x00000000);
-        nv_icmd(priv, 0x0002c5, 0x00000000);
-        nv_icmd(priv, 0x0002c6, 0x00000000);
-        nv_icmd(priv, 0x0002c7, 0x00000000);
-        nv_icmd(priv, 0x0002c8, 0x00000000);
-        nv_icmd(priv, 0x0002c9, 0x00000000);
-        nv_icmd(priv, 0x0002ca, 0x00000000);
-        nv_icmd(priv, 0x0002cb, 0x00000000);
-        nv_icmd(priv, 0x0002cc, 0x00000000);
-        nv_icmd(priv, 0x0002cd, 0x00000000);
-        nv_icmd(priv, 0x0002ce, 0x00000000);
-        nv_icmd(priv, 0x0002cf, 0x00000000);
-        nv_icmd(priv, 0x0004d0, 0x00000000);
-        nv_icmd(priv, 0x0004d1, 0x00000000);
-        nv_icmd(priv, 0x0004d2, 0x00000000);
-        nv_icmd(priv, 0x0004d3, 0x00000000);
-        nv_icmd(priv, 0x0004d4, 0x00000000);
-        nv_icmd(priv, 0x0004d5, 0x00000000);
-        nv_icmd(priv, 0x0004d6, 0x00000000);
-        nv_icmd(priv, 0x0004d7, 0x00000000);
-        nv_icmd(priv, 0x0004d8, 0x00000000);
-        nv_icmd(priv, 0x0004d9, 0x00000000);
-        nv_icmd(priv, 0x0004da, 0x00000000);
-        nv_icmd(priv, 0x0004db, 0x00000000);
-        nv_icmd(priv, 0x0004dc, 0x00000000);
-        nv_icmd(priv, 0x0004dd, 0x00000000);
-        nv_icmd(priv, 0x0004de, 0x00000000);
-        nv_icmd(priv, 0x0004df, 0x00000000);
-        nv_icmd(priv, 0x000720, 0x00000000);
-        nv_icmd(priv, 0x000721, 0x00000000);
-        nv_icmd(priv, 0x000722, 0x00000000);
-        nv_icmd(priv, 0x000723, 0x00000000);
-        nv_icmd(priv, 0x000724, 0x00000000);
-        nv_icmd(priv, 0x000725, 0x00000000);
-        nv_icmd(priv, 0x000726, 0x00000000);
-        nv_icmd(priv, 0x000727, 0x00000000);
-        nv_icmd(priv, 0x000728, 0x00000000);
-        nv_icmd(priv, 0x000729, 0x00000000);
-        nv_icmd(priv, 0x00072a, 0x00000000);
-        nv_icmd(priv, 0x00072b, 0x00000000);
-        nv_icmd(priv, 0x00072c, 0x00000000);
-        nv_icmd(priv, 0x00072d, 0x00000000);
-        nv_icmd(priv, 0x00072e, 0x00000000);
-        nv_icmd(priv, 0x00072f, 0x00000000);
-        nv_icmd(priv, 0x0008c0, 0x00000000);
-        nv_icmd(priv, 0x0008c1, 0x00000000);
-        nv_icmd(priv, 0x0008c2, 0x00000000);
-        nv_icmd(priv, 0x0008c3, 0x00000000);
-        nv_icmd(priv, 0x0008c4, 0x00000000);
-        nv_icmd(priv, 0x0008c5, 0x00000000);
-        nv_icmd(priv, 0x0008c6, 0x00000000);
-        nv_icmd(priv, 0x0008c7, 0x00000000);
-        nv_icmd(priv, 0x0008c8, 0x00000000);
-        nv_icmd(priv, 0x0008c9, 0x00000000);
-        nv_icmd(priv, 0x0008ca, 0x00000000);
-        nv_icmd(priv, 0x0008cb, 0x00000000);
-        nv_icmd(priv, 0x0008cc, 0x00000000);
-        nv_icmd(priv, 0x0008cd, 0x00000000);
-        nv_icmd(priv, 0x0008ce, 0x00000000);
-        nv_icmd(priv, 0x0008cf, 0x00000000);
-        nv_icmd(priv, 0x000890, 0x00000000);
-        nv_icmd(priv, 0x000891, 0x00000000);
-        nv_icmd(priv, 0x000892, 0x00000000);
-        nv_icmd(priv, 0x000893, 0x00000000);
-        nv_icmd(priv, 0x000894, 0x00000000);
-        nv_icmd(priv, 0x000895, 0x00000000);
-        nv_icmd(priv, 0x000896, 0x00000000);
-        nv_icmd(priv, 0x000897, 0x00000000);
-        nv_icmd(priv, 0x000898, 0x00000000);
-        nv_icmd(priv, 0x000899, 0x00000000);
-        nv_icmd(priv, 0x00089a, 0x00000000);
-        nv_icmd(priv, 0x00089b, 0x00000000);
-        nv_icmd(priv, 0x00089c, 0x00000000);
-        nv_icmd(priv, 0x00089d, 0x00000000);
-        nv_icmd(priv, 0x00089e, 0x00000000);
-        nv_icmd(priv, 0x00089f, 0x00000000);
-        nv_icmd(priv, 0x0008e0, 0x00000000);
-        nv_icmd(priv, 0x0008e1, 0x00000000);
-        nv_icmd(priv, 0x0008e2, 0x00000000);
-        nv_icmd(priv, 0x0008e3, 0x00000000);
-        nv_icmd(priv, 0x0008e4, 0x00000000);
-        nv_icmd(priv, 0x0008e5, 0x00000000);
-        nv_icmd(priv, 0x0008e6, 0x00000000);
-        nv_icmd(priv, 0x0008e7, 0x00000000);
-        nv_icmd(priv, 0x0008e8, 0x00000000);
-        nv_icmd(priv, 0x0008e9, 0x00000000);
-        nv_icmd(priv, 0x0008ea, 0x00000000);
-        nv_icmd(priv, 0x0008eb, 0x00000000);
-        nv_icmd(priv, 0x0008ec, 0x00000000);
-        nv_icmd(priv, 0x0008ed, 0x00000000);
-        nv_icmd(priv, 0x0008ee, 0x00000000);
-        nv_icmd(priv, 0x0008ef, 0x00000000);
-        nv_icmd(priv, 0x0008a0, 0x00000000);
-        nv_icmd(priv, 0x0008a1, 0x00000000);
-        nv_icmd(priv, 0x0008a2, 0x00000000);
-        nv_icmd(priv, 0x0008a3, 0x00000000);
-        nv_icmd(priv, 0x0008a4, 0x00000000);
-        nv_icmd(priv, 0x0008a5, 0x00000000);
-        nv_icmd(priv, 0x0008a6, 0x00000000);
-        nv_icmd(priv, 0x0008a7, 0x00000000);
-        nv_icmd(priv, 0x0008a8, 0x00000000);
-        nv_icmd(priv, 0x0008a9, 0x00000000);
-        nv_icmd(priv, 0x0008aa, 0x00000000);
-        nv_icmd(priv, 0x0008ab, 0x00000000);
-        nv_icmd(priv, 0x0008ac, 0x00000000);
-        nv_icmd(priv, 0x0008ad, 0x00000000);
-        nv_icmd(priv, 0x0008ae, 0x00000000);
-        nv_icmd(priv, 0x0008af, 0x00000000);
-        nv_icmd(priv, 0x0008f0, 0x00000000);
-        nv_icmd(priv, 0x0008f1, 0x00000000);
-        nv_icmd(priv, 0x0008f2, 0x00000000);
-        nv_icmd(priv, 0x0008f3, 0x00000000);
-        nv_icmd(priv, 0x0008f4, 0x00000000);
-        nv_icmd(priv, 0x0008f5, 0x00000000);
-        nv_icmd(priv, 0x0008f6, 0x00000000);
-        nv_icmd(priv, 0x0008f7, 0x00000000);
-        nv_icmd(priv, 0x0008f8, 0x00000000);
-        nv_icmd(priv, 0x0008f9, 0x00000000);
-        nv_icmd(priv, 0x0008fa, 0x00000000);
-        nv_icmd(priv, 0x0008fb, 0x00000000);
-        nv_icmd(priv, 0x0008fc, 0x00000000);
-        nv_icmd(priv, 0x0008fd, 0x00000000);
-        nv_icmd(priv, 0x0008fe, 0x00000000);
-        nv_icmd(priv, 0x0008ff, 0x00000000);
-        nv_icmd(priv, 0x00094c, 0x000000ff);
-        nv_icmd(priv, 0x00094d, 0xffffffff);
-        nv_icmd(priv, 0x00094e, 0x00000002);
-        nv_icmd(priv, 0x0002ec, 0x00000001);
-        nv_icmd(priv, 0x000303, 0x00000001);
-        nv_icmd(priv, 0x0002e6, 0x00000001);
-        nv_icmd(priv, 0x000466, 0x00000052);
-        nv_icmd(priv, 0x000301, 0x3f800000);
-        nv_icmd(priv, 0x000304, 0x30201000);
-        nv_icmd(priv, 0x000305, 0x70605040);
-        nv_icmd(priv, 0x000306, 0xb8a89888);
-        nv_icmd(priv, 0x000307, 0xf8e8d8c8);
-        nv_icmd(priv, 0x00030a, 0x00ffff00);
-        nv_icmd(priv, 0x00030b, 0x0000001a);
-        nv_icmd(priv, 0x00030c, 0x00000001);
-        nv_icmd(priv, 0x000318, 0x00000001);
-        nv_icmd(priv, 0x000340, 0x00000000);
-        nv_icmd(priv, 0x000375, 0x00000001);
-        nv_icmd(priv, 0x00037d, 0x00000006);
-        nv_icmd(priv, 0x0003a0, 0x00000002);
-        nv_icmd(priv, 0x0003aa, 0x00000001);
-        nv_icmd(priv, 0x0003a9, 0x00000001);
-        nv_icmd(priv, 0x000380, 0x00000001);
-        nv_icmd(priv, 0x000383, 0x00000011);
-        nv_icmd(priv, 0x000360, 0x00000040);
-        nv_icmd(priv, 0x000366, 0x00000000);
-        nv_icmd(priv, 0x000367, 0x00000000);
-        nv_icmd(priv, 0x000368, 0x00000fff);
-        nv_icmd(priv, 0x000370, 0x00000000);
-        nv_icmd(priv, 0x000371, 0x00000000);
-        nv_icmd(priv, 0x000372, 0x000fffff);
-        nv_icmd(priv, 0x00037a, 0x00000012);
-        nv_icmd(priv, 0x000619, 0x00000003);
-        nv_icmd(priv, 0x000811, 0x00000003);
-        nv_icmd(priv, 0x000812, 0x00000004);
-        nv_icmd(priv, 0x000813, 0x00000006);
-        nv_icmd(priv, 0x000814, 0x00000008);
-        nv_icmd(priv, 0x000815, 0x0000000b);
-        nv_icmd(priv, 0x000800, 0x00000001);
-        nv_icmd(priv, 0x000801, 0x00000001);
-        nv_icmd(priv, 0x000802, 0x00000001);
-        nv_icmd(priv, 0x000803, 0x00000001);
-        nv_icmd(priv, 0x000804, 0x00000001);
-        nv_icmd(priv, 0x000805, 0x00000001);
-        nv_icmd(priv, 0x000632, 0x00000001);
-        nv_icmd(priv, 0x000633, 0x00000002);
-        nv_icmd(priv, 0x000634, 0x00000003);
-        nv_icmd(priv, 0x000635, 0x00000004);
-        nv_icmd(priv, 0x000654, 0x3f800000);
-        nv_icmd(priv, 0x000657, 0x3f800000);
-        nv_icmd(priv, 0x000655, 0x3f800000);
-        nv_icmd(priv, 0x000656, 0x3f800000);
-        nv_icmd(priv, 0x0006cd, 0x3f800000);
-        nv_icmd(priv, 0x0007f5, 0x3f800000);
-        nv_icmd(priv, 0x0007dc, 0x39291909);
-        nv_icmd(priv, 0x0007dd, 0x79695949);
-        nv_icmd(priv, 0x0007de, 0xb9a99989);
-        nv_icmd(priv, 0x0007df, 0xf9e9d9c9);
-        nv_icmd(priv, 0x0007e8, 0x00003210);
-        nv_icmd(priv, 0x0007e9, 0x00007654);
-        nv_icmd(priv, 0x0007ea, 0x00000098);
-        nv_icmd(priv, 0x0007ec, 0x39291909);
-        nv_icmd(priv, 0x0007ed, 0x79695949);
-        nv_icmd(priv, 0x0007ee, 0xb9a99989);
-        nv_icmd(priv, 0x0007ef, 0xf9e9d9c9);
-        nv_icmd(priv, 0x0007f0, 0x00003210);
-        nv_icmd(priv, 0x0007f1, 0x00007654);
-        nv_icmd(priv, 0x0007f2, 0x00000098);
-        nv_icmd(priv, 0x0005a5, 0x00000001);
-        nv_icmd(priv, 0x000980, 0x00000000);
-        nv_icmd(priv, 0x000981, 0x00000000);
-        nv_icmd(priv, 0x000982, 0x00000000);
-        nv_icmd(priv, 0x000983, 0x00000000);
-        nv_icmd(priv, 0x000984, 0x00000000);
-        nv_icmd(priv, 0x000985, 0x00000000);
-        nv_icmd(priv, 0x000986, 0x00000000);
-        nv_icmd(priv, 0x000987, 0x00000000);
-        nv_icmd(priv, 0x000988, 0x00000000);
-        nv_icmd(priv, 0x000989, 0x00000000);
-        nv_icmd(priv, 0x00098a, 0x00000000);
-        nv_icmd(priv, 0x00098b, 0x00000000);
-        nv_icmd(priv, 0x00098c, 0x00000000);
-        nv_icmd(priv, 0x00098d, 0x00000000);
-        nv_icmd(priv, 0x00098e, 0x00000000);
-        nv_icmd(priv, 0x00098f, 0x00000000);
-        nv_icmd(priv, 0x000990, 0x00000000);
-        nv_icmd(priv, 0x000991, 0x00000000);
-        nv_icmd(priv, 0x000992, 0x00000000);
-        nv_icmd(priv, 0x000993, 0x00000000);
-        nv_icmd(priv, 0x000994, 0x00000000);
-        nv_icmd(priv, 0x000995, 0x00000000);
-        nv_icmd(priv, 0x000996, 0x00000000);
-        nv_icmd(priv, 0x000997, 0x00000000);
-        nv_icmd(priv, 0x000998, 0x00000000);
-        nv_icmd(priv, 0x000999, 0x00000000);
-        nv_icmd(priv, 0x00099a, 0x00000000);
-        nv_icmd(priv, 0x00099b, 0x00000000);
-        nv_icmd(priv, 0x00099c, 0x00000000);
-        nv_icmd(priv, 0x00099d, 0x00000000);
-        nv_icmd(priv, 0x00099e, 0x00000000);
-        nv_icmd(priv, 0x00099f, 0x00000000);
-        nv_icmd(priv, 0x0009a0, 0x00000000);
-        nv_icmd(priv, 0x0009a1, 0x00000000);
-        nv_icmd(priv, 0x0009a2, 0x00000000);
-        nv_icmd(priv, 0x0009a3, 0x00000000);
-        nv_icmd(priv, 0x0009a4, 0x00000000);
-        nv_icmd(priv, 0x0009a5, 0x00000000);
-        nv_icmd(priv, 0x0009a6, 0x00000000);
-        nv_icmd(priv, 0x0009a7, 0x00000000);
-        nv_icmd(priv, 0x0009a8, 0x00000000);
-        nv_icmd(priv, 0x0009a9, 0x00000000);
-        nv_icmd(priv, 0x0009aa, 0x00000000);
-        nv_icmd(priv, 0x0009ab, 0x00000000);
-        nv_icmd(priv, 0x0009ac, 0x00000000);
-        nv_icmd(priv, 0x0009ad, 0x00000000);
-        nv_icmd(priv, 0x0009ae, 0x00000000);
-        nv_icmd(priv, 0x0009af, 0x00000000);
-        nv_icmd(priv, 0x0009b0, 0x00000000);
-        nv_icmd(priv, 0x0009b1, 0x00000000);
-        nv_icmd(priv, 0x0009b2, 0x00000000);
-        nv_icmd(priv, 0x0009b3, 0x00000000);
-        nv_icmd(priv, 0x0009b4, 0x00000000);
-        nv_icmd(priv, 0x0009b5, 0x00000000);
-        nv_icmd(priv, 0x0009b6, 0x00000000);
-        nv_icmd(priv, 0x0009b7, 0x00000000);
-        nv_icmd(priv, 0x0009b8, 0x00000000);
-        nv_icmd(priv, 0x0009b9, 0x00000000);
-        nv_icmd(priv, 0x0009ba, 0x00000000);
-        nv_icmd(priv, 0x0009bb, 0x00000000);
-        nv_icmd(priv, 0x0009bc, 0x00000000);
-        nv_icmd(priv, 0x0009bd, 0x00000000);
-        nv_icmd(priv, 0x0009be, 0x00000000);
-        nv_icmd(priv, 0x0009bf, 0x00000000);
-        nv_icmd(priv, 0x0009c0, 0x00000000);
-        nv_icmd(priv, 0x0009c1, 0x00000000);
-        nv_icmd(priv, 0x0009c2, 0x00000000);
-        nv_icmd(priv, 0x0009c3, 0x00000000);
-        nv_icmd(priv, 0x0009c4, 0x00000000);
-        nv_icmd(priv, 0x0009c5, 0x00000000);
-        nv_icmd(priv, 0x0009c6, 0x00000000);
-        nv_icmd(priv, 0x0009c7, 0x00000000);
-        nv_icmd(priv, 0x0009c8, 0x00000000);
-        nv_icmd(priv, 0x0009c9, 0x00000000);
-        nv_icmd(priv, 0x0009ca, 0x00000000);
-        nv_icmd(priv, 0x0009cb, 0x00000000);
-        nv_icmd(priv, 0x0009cc, 0x00000000);
-        nv_icmd(priv, 0x0009cd, 0x00000000);
-        nv_icmd(priv, 0x0009ce, 0x00000000);
-        nv_icmd(priv, 0x0009cf, 0x00000000);
-        nv_icmd(priv, 0x0009d0, 0x00000000);
-        nv_icmd(priv, 0x0009d1, 0x00000000);
-        nv_icmd(priv, 0x0009d2, 0x00000000);
-        nv_icmd(priv, 0x0009d3, 0x00000000);
-        nv_icmd(priv, 0x0009d4, 0x00000000);
-        nv_icmd(priv, 0x0009d5, 0x00000000);
-        nv_icmd(priv, 0x0009d6, 0x00000000);
-        nv_icmd(priv, 0x0009d7, 0x00000000);
-        nv_icmd(priv, 0x0009d8, 0x00000000);
-        nv_icmd(priv, 0x0009d9, 0x00000000);
-        nv_icmd(priv, 0x0009da, 0x00000000);
-        nv_icmd(priv, 0x0009db, 0x00000000);
-        nv_icmd(priv, 0x0009dc, 0x00000000);
-        nv_icmd(priv, 0x0009dd, 0x00000000);
-        nv_icmd(priv, 0x0009de, 0x00000000);
-        nv_icmd(priv, 0x0009df, 0x00000000);
-        nv_icmd(priv, 0x0009e0, 0x00000000);
-        nv_icmd(priv, 0x0009e1, 0x00000000);
-        nv_icmd(priv, 0x0009e2, 0x00000000);
-        nv_icmd(priv, 0x0009e3, 0x00000000);
-        nv_icmd(priv, 0x0009e4, 0x00000000);
-        nv_icmd(priv, 0x0009e5, 0x00000000);
-        nv_icmd(priv, 0x0009e6, 0x00000000);
-        nv_icmd(priv, 0x0009e7, 0x00000000);
-        nv_icmd(priv, 0x0009e8, 0x00000000);
-        nv_icmd(priv, 0x0009e9, 0x00000000);
-        nv_icmd(priv, 0x0009ea, 0x00000000);
-        nv_icmd(priv, 0x0009eb, 0x00000000);
-        nv_icmd(priv, 0x0009ec, 0x00000000);
-        nv_icmd(priv, 0x0009ed, 0x00000000);
-        nv_icmd(priv, 0x0009ee, 0x00000000);
-        nv_icmd(priv, 0x0009ef, 0x00000000);
-        nv_icmd(priv, 0x0009f0, 0x00000000);
-        nv_icmd(priv, 0x0009f1, 0x00000000);
-        nv_icmd(priv, 0x0009f2, 0x00000000);
-        nv_icmd(priv, 0x0009f3, 0x00000000);
-        nv_icmd(priv, 0x0009f4, 0x00000000);
-        nv_icmd(priv, 0x0009f5, 0x00000000);
-        nv_icmd(priv, 0x0009f6, 0x00000000);
-        nv_icmd(priv, 0x0009f7, 0x00000000);
-        nv_icmd(priv, 0x0009f8, 0x00000000);
-        nv_icmd(priv, 0x0009f9, 0x00000000);
-        nv_icmd(priv, 0x0009fa, 0x00000000);
-        nv_icmd(priv, 0x0009fb, 0x00000000);
-        nv_icmd(priv, 0x0009fc, 0x00000000);
-        nv_icmd(priv, 0x0009fd, 0x00000000);
-        nv_icmd(priv, 0x0009fe, 0x00000000);
-        nv_icmd(priv, 0x0009ff, 0x00000000);
-        nv_icmd(priv, 0x000468, 0x00000004);
-        nv_icmd(priv, 0x00046c, 0x00000001);
-        nv_icmd(priv, 0x000470, 0x00000000);
-        nv_icmd(priv, 0x000471, 0x00000000);
-        nv_icmd(priv, 0x000472, 0x00000000);
-        nv_icmd(priv, 0x000473, 0x00000000);
-        nv_icmd(priv, 0x000474, 0x00000000);
-        nv_icmd(priv, 0x000475, 0x00000000);
-        nv_icmd(priv, 0x000476, 0x00000000);
-        nv_icmd(priv, 0x000477, 0x00000000);
-        nv_icmd(priv, 0x000478, 0x00000000);
-        nv_icmd(priv, 0x000479, 0x00000000);
-        nv_icmd(priv, 0x00047a, 0x00000000);
-        nv_icmd(priv, 0x00047b, 0x00000000);
-        nv_icmd(priv, 0x00047c, 0x00000000);
-        nv_icmd(priv, 0x00047d, 0x00000000);
-        nv_icmd(priv, 0x00047e, 0x00000000);
-        nv_icmd(priv, 0x00047f, 0x00000000);
-        nv_icmd(priv, 0x000480, 0x00000000);
-        nv_icmd(priv, 0x000481, 0x00000000);
-        nv_icmd(priv, 0x000482, 0x00000000);
-        nv_icmd(priv, 0x000483, 0x00000000);
-        nv_icmd(priv, 0x000484, 0x00000000);
-        nv_icmd(priv, 0x000485, 0x00000000);
-        nv_icmd(priv, 0x000486, 0x00000000);
-        nv_icmd(priv, 0x000487, 0x00000000);
-        nv_icmd(priv, 0x000488, 0x00000000);
-        nv_icmd(priv, 0x000489, 0x00000000);
-        nv_icmd(priv, 0x00048a, 0x00000000);
-        nv_icmd(priv, 0x00048b, 0x00000000);
-        nv_icmd(priv, 0x00048c, 0x00000000);
-        nv_icmd(priv, 0x00048d, 0x00000000);
-        nv_icmd(priv, 0x00048e, 0x00000000);
-        nv_icmd(priv, 0x00048f, 0x00000000);
-        nv_icmd(priv, 0x000490, 0x00000000);
-        nv_icmd(priv, 0x000491, 0x00000000);
-        nv_icmd(priv, 0x000492, 0x00000000);
-        nv_icmd(priv, 0x000493, 0x00000000);
-        nv_icmd(priv, 0x000494, 0x00000000);
-        nv_icmd(priv, 0x000495, 0x00000000);
-        nv_icmd(priv, 0x000496, 0x00000000);
-        nv_icmd(priv, 0x000497, 0x00000000);
-        nv_icmd(priv, 0x000498, 0x00000000);
-        nv_icmd(priv, 0x000499, 0x00000000);
-        nv_icmd(priv, 0x00049a, 0x00000000);
-        nv_icmd(priv, 0x00049b, 0x00000000);
-        nv_icmd(priv, 0x00049c, 0x00000000);
-        nv_icmd(priv, 0x00049d, 0x00000000);
-        nv_icmd(priv, 0x00049e, 0x00000000);
-        nv_icmd(priv, 0x00049f, 0x00000000);
-        nv_icmd(priv, 0x0004a0, 0x00000000);
-        nv_icmd(priv, 0x0004a1, 0x00000000);
-        nv_icmd(priv, 0x0004a2, 0x00000000);
-        nv_icmd(priv, 0x0004a3, 0x00000000);
-        nv_icmd(priv, 0x0004a4, 0x00000000);
-        nv_icmd(priv, 0x0004a5, 0x00000000);
-        nv_icmd(priv, 0x0004a6, 0x00000000);
-        nv_icmd(priv, 0x0004a7, 0x00000000);
-        nv_icmd(priv, 0x0004a8, 0x00000000);
-        nv_icmd(priv, 0x0004a9, 0x00000000);
-        nv_icmd(priv, 0x0004aa, 0x00000000);
-        nv_icmd(priv, 0x0004ab, 0x00000000);
-        nv_icmd(priv, 0x0004ac, 0x00000000);
-        nv_icmd(priv, 0x0004ad, 0x00000000);
-        nv_icmd(priv, 0x0004ae, 0x00000000);
-        nv_icmd(priv, 0x0004af, 0x00000000);
-        nv_icmd(priv, 0x0004b0, 0x00000000);
-        nv_icmd(priv, 0x0004b1, 0x00000000);
-        nv_icmd(priv, 0x0004b2, 0x00000000);
-        nv_icmd(priv, 0x0004b3, 0x00000000);
-        nv_icmd(priv, 0x0004b4, 0x00000000);
-        nv_icmd(priv, 0x0004b5, 0x00000000);
-        nv_icmd(priv, 0x0004b6, 0x00000000);
-        nv_icmd(priv, 0x0004b7, 0x00000000);
-        nv_icmd(priv, 0x0004b8, 0x00000000);
-        nv_icmd(priv, 0x0004b9, 0x00000000);
-        nv_icmd(priv, 0x0004ba, 0x00000000);
-        nv_icmd(priv, 0x0004bb, 0x00000000);
-        nv_icmd(priv, 0x0004bc, 0x00000000);
-        nv_icmd(priv, 0x0004bd, 0x00000000);
-        nv_icmd(priv, 0x0004be, 0x00000000);
-        nv_icmd(priv, 0x0004bf, 0x00000000);
-        nv_icmd(priv, 0x0004c0, 0x00000000);
-        nv_icmd(priv, 0x0004c1, 0x00000000);
-        nv_icmd(priv, 0x0004c2, 0x00000000);
-        nv_icmd(priv, 0x0004c3, 0x00000000);
-        nv_icmd(priv, 0x0004c4, 0x00000000);
-        nv_icmd(priv, 0x0004c5, 0x00000000);
-        nv_icmd(priv, 0x0004c6, 0x00000000);
-        nv_icmd(priv, 0x0004c7, 0x00000000);
-        nv_icmd(priv, 0x0004c8, 0x00000000);
-        nv_icmd(priv, 0x0004c9, 0x00000000);
-        nv_icmd(priv, 0x0004ca, 0x00000000);
-        nv_icmd(priv, 0x0004cb, 0x00000000);
-        nv_icmd(priv, 0x0004cc, 0x00000000);
-        nv_icmd(priv, 0x0004cd, 0x00000000);
-        nv_icmd(priv, 0x0004ce, 0x00000000);
-        nv_icmd(priv, 0x0004cf, 0x00000000);
-        nv_icmd(priv, 0x000510, 0x3f800000);
-        nv_icmd(priv, 0x000511, 0x3f800000);
-        nv_icmd(priv, 0x000512, 0x3f800000);
-        nv_icmd(priv, 0x000513, 0x3f800000);
-        nv_icmd(priv, 0x000514, 0x3f800000);
-        nv_icmd(priv, 0x000515, 0x3f800000);
-        nv_icmd(priv, 0x000516, 0x3f800000);
-        nv_icmd(priv, 0x000517, 0x3f800000);
-        nv_icmd(priv, 0x000518, 0x3f800000);
-        nv_icmd(priv, 0x000519, 0x3f800000);
-        nv_icmd(priv, 0x00051a, 0x3f800000);
-        nv_icmd(priv, 0x00051b, 0x3f800000);
-        nv_icmd(priv, 0x00051c, 0x3f800000);
-        nv_icmd(priv, 0x00051d, 0x3f800000);
-        nv_icmd(priv, 0x00051e, 0x3f800000);
-        nv_icmd(priv, 0x00051f, 0x3f800000);
-        nv_icmd(priv, 0x000520, 0x000002b6);
-        nv_icmd(priv, 0x000529, 0x00000001);
-        nv_icmd(priv, 0x000530, 0xffff0000);
-        nv_icmd(priv, 0x000531, 0xffff0000);
-        nv_icmd(priv, 0x000532, 0xffff0000);
-        nv_icmd(priv, 0x000533, 0xffff0000);
-        nv_icmd(priv, 0x000534, 0xffff0000);
-        nv_icmd(priv, 0x000535, 0xffff0000);
-        nv_icmd(priv, 0x000536, 0xffff0000);
-        nv_icmd(priv, 0x000537, 0xffff0000);
-        nv_icmd(priv, 0x000538, 0xffff0000);
-        nv_icmd(priv, 0x000539, 0xffff0000);
-        nv_icmd(priv, 0x00053a, 0xffff0000);
-        nv_icmd(priv, 0x00053b, 0xffff0000);
-        nv_icmd(priv, 0x00053c, 0xffff0000);
-        nv_icmd(priv, 0x00053d, 0xffff0000);
-        nv_icmd(priv, 0x00053e, 0xffff0000);
-        nv_icmd(priv, 0x00053f, 0xffff0000);
-        nv_icmd(priv, 0x000585, 0x0000003f);
-        nv_icmd(priv, 0x000576, 0x00000003);
-        nv_icmd(priv, 0x00057b, 0x00000059);
-        nv_icmd(priv, 0x000586, 0x00000040);
-        nv_icmd(priv, 0x000582, 0x00000080);
-        nv_icmd(priv, 0x000583, 0x00000080);
-        nv_icmd(priv, 0x0005c2, 0x00000001);
-        nv_icmd(priv, 0x000638, 0x00000001);
-        nv_icmd(priv, 0x000639, 0x00000001);
-        nv_icmd(priv, 0x00063a, 0x00000002);
-        nv_icmd(priv, 0x00063b, 0x00000001);
-        nv_icmd(priv, 0x00063c, 0x00000001);
-        nv_icmd(priv, 0x00063d, 0x00000002);
-        nv_icmd(priv, 0x00063e, 0x00000001);
-        nv_icmd(priv, 0x0008b8, 0x00000001);
-        nv_icmd(priv, 0x0008b9, 0x00000001);
-        nv_icmd(priv, 0x0008ba, 0x00000001);
-        nv_icmd(priv, 0x0008bb, 0x00000001);
-        nv_icmd(priv, 0x0008bc, 0x00000001);
-        nv_icmd(priv, 0x0008bd, 0x00000001);
-        nv_icmd(priv, 0x0008be, 0x00000001);
-        nv_icmd(priv, 0x0008bf, 0x00000001);
-        nv_icmd(priv, 0x000900, 0x00000001);
-        nv_icmd(priv, 0x000901, 0x00000001);
-        nv_icmd(priv, 0x000902, 0x00000001);
-        nv_icmd(priv, 0x000903, 0x00000001);
-        nv_icmd(priv, 0x000904, 0x00000001);
-        nv_icmd(priv, 0x000905, 0x00000001);
-        nv_icmd(priv, 0x000906, 0x00000001);
-        nv_icmd(priv, 0x000907, 0x00000001);
-        nv_icmd(priv, 0x000908, 0x00000002);
-        nv_icmd(priv, 0x000909, 0x00000002);
-        nv_icmd(priv, 0x00090a, 0x00000002);
-        nv_icmd(priv, 0x00090b, 0x00000002);
-        nv_icmd(priv, 0x00090c, 0x00000002);
-        nv_icmd(priv, 0x00090d, 0x00000002);
-        nv_icmd(priv, 0x00090e, 0x00000002);
-        nv_icmd(priv, 0x00090f, 0x00000002);
-        nv_icmd(priv, 0x000910, 0x00000001);
-        nv_icmd(priv, 0x000911, 0x00000001);
-        nv_icmd(priv, 0x000912, 0x00000001);
-        nv_icmd(priv, 0x000913, 0x00000001);
-        nv_icmd(priv, 0x000914, 0x00000001);
-        nv_icmd(priv, 0x000915, 0x00000001);
-        nv_icmd(priv, 0x000916, 0x00000001);
-        nv_icmd(priv, 0x000917, 0x00000001);
-        nv_icmd(priv, 0x000918, 0x00000001);
-        nv_icmd(priv, 0x000919, 0x00000001);
-        nv_icmd(priv, 0x00091a, 0x00000001);
-        nv_icmd(priv, 0x00091b, 0x00000001);
-        nv_icmd(priv, 0x00091c, 0x00000001);
-        nv_icmd(priv, 0x00091d, 0x00000001);
-        nv_icmd(priv, 0x00091e, 0x00000001);
-        nv_icmd(priv, 0x00091f, 0x00000001);
-        nv_icmd(priv, 0x000920, 0x00000002);
-        nv_icmd(priv, 0x000921, 0x00000002);
-        nv_icmd(priv, 0x000922, 0x00000002);
-        nv_icmd(priv, 0x000923, 0x00000002);
-        nv_icmd(priv, 0x000924, 0x00000002);
-        nv_icmd(priv, 0x000925, 0x00000002);
-        nv_icmd(priv, 0x000926, 0x00000002);
-        nv_icmd(priv, 0x000927, 0x00000002);
-        nv_icmd(priv, 0x000928, 0x00000001);
-        nv_icmd(priv, 0x000929, 0x00000001);
-        nv_icmd(priv, 0x00092a, 0x00000001);
-        nv_icmd(priv, 0x00092b, 0x00000001);
-        nv_icmd(priv, 0x00092c, 0x00000001);
-        nv_icmd(priv, 0x00092d, 0x00000001);
-        nv_icmd(priv, 0x00092e, 0x00000001);
-        nv_icmd(priv, 0x00092f, 0x00000001);
-        nv_icmd(priv, 0x000648, 0x00000001);
-        nv_icmd(priv, 0x000649, 0x00000001);
-        nv_icmd(priv, 0x00064a, 0x00000001);
-        nv_icmd(priv, 0x00064b, 0x00000001);
-        nv_icmd(priv, 0x00064c, 0x00000001);
-        nv_icmd(priv, 0x00064d, 0x00000001);
-        nv_icmd(priv, 0x00064e, 0x00000001);
-        nv_icmd(priv, 0x00064f, 0x00000001);
-        nv_icmd(priv, 0x000650, 0x00000001);
-        nv_icmd(priv, 0x000658, 0x0000000f);
-        nv_icmd(priv, 0x0007ff, 0x0000000a);
-        nv_icmd(priv, 0x00066a, 0x40000000);
-        nv_icmd(priv, 0x00066b, 0x10000000);
-        nv_icmd(priv, 0x00066c, 0xffff0000);
-        nv_icmd(priv, 0x00066d, 0xffff0000);
-        nv_icmd(priv, 0x0007af, 0x00000008);
-        nv_icmd(priv, 0x0007b0, 0x00000008);
-        nv_icmd(priv, 0x0007f6, 0x00000001);
-        nv_icmd(priv, 0x0006b2, 0x00000055);
-        nv_icmd(priv, 0x0007ad, 0x00000003);
-        nv_icmd(priv, 0x000937, 0x00000001);
-        nv_icmd(priv, 0x000971, 0x00000008);
-        nv_icmd(priv, 0x000972, 0x00000040);
-        nv_icmd(priv, 0x000973, 0x0000012c);
-        nv_icmd(priv, 0x00097c, 0x00000040);
-        nv_icmd(priv, 0x000979, 0x00000003);
-        nv_icmd(priv, 0x000975, 0x00000020);
-        nv_icmd(priv, 0x000976, 0x00000001);
-        nv_icmd(priv, 0x000977, 0x00000020);
-        nv_icmd(priv, 0x000978, 0x00000001);
-        nv_icmd(priv, 0x000957, 0x00000003);
-        nv_icmd(priv, 0x00095e, 0x20164010);
-        nv_icmd(priv, 0x00095f, 0x00000020);
-        nv_icmd(priv, 0x00097d, 0x00000020);
-        nv_icmd(priv, 0x000683, 0x00000006);
-        nv_icmd(priv, 0x000685, 0x003fffff);
-        nv_icmd(priv, 0x000687, 0x003fffff);
-        nv_icmd(priv, 0x0006a0, 0x00000005);
-        nv_icmd(priv, 0x000840, 0x00400008);
-        nv_icmd(priv, 0x000841, 0x08000080);
-        nv_icmd(priv, 0x000842, 0x00400008);
-        nv_icmd(priv, 0x000843, 0x08000080);
-        nv_icmd(priv, 0x000818, 0x00000000);
-        nv_icmd(priv, 0x000819, 0x00000000);
-        nv_icmd(priv, 0x00081a, 0x00000000);
-        nv_icmd(priv, 0x00081b, 0x00000000);
-        nv_icmd(priv, 0x00081c, 0x00000000);
-        nv_icmd(priv, 0x00081d, 0x00000000);
-        nv_icmd(priv, 0x00081e, 0x00000000);
-        nv_icmd(priv, 0x00081f, 0x00000000);
-        nv_icmd(priv, 0x000848, 0x00000000);
-        nv_icmd(priv, 0x000849, 0x00000000);
-        nv_icmd(priv, 0x00084a, 0x00000000);
-        nv_icmd(priv, 0x00084b, 0x00000000);
-        nv_icmd(priv, 0x00084c, 0x00000000);
-        nv_icmd(priv, 0x00084d, 0x00000000);
-        nv_icmd(priv, 0x00084e, 0x00000000);
-        nv_icmd(priv, 0x00084f, 0x00000000);
-        nv_icmd(priv, 0x000850, 0x00000000);
-        nv_icmd(priv, 0x000851, 0x00000000);
-        nv_icmd(priv, 0x000852, 0x00000000);
-        nv_icmd(priv, 0x000853, 0x00000000);
-        nv_icmd(priv, 0x000854, 0x00000000);
-        nv_icmd(priv, 0x000855, 0x00000000);
-        nv_icmd(priv, 0x000856, 0x00000000);
-        nv_icmd(priv, 0x000857, 0x00000000);
-        nv_icmd(priv, 0x000738, 0x00000000);
-        nv_icmd(priv, 0x0006aa, 0x00000001);
-        nv_icmd(priv, 0x0006ab, 0x00000002);
-        nv_icmd(priv, 0x0006ac, 0x00000080);
-        nv_icmd(priv, 0x0006ad, 0x00000100);
-        nv_icmd(priv, 0x0006ae, 0x00000100);
-        nv_icmd(priv, 0x0006b1, 0x00000011);
-        nv_icmd(priv, 0x0006bb, 0x000000cf);
-        nv_icmd(priv, 0x0006ce, 0x2a712488);
-        nv_icmd(priv, 0x000739, 0x4085c000);
-        nv_icmd(priv, 0x00073a, 0x00000080);
-        nv_icmd(priv, 0x000786, 0x80000100);
-        nv_icmd(priv, 0x00073c, 0x00010100);
-        nv_icmd(priv, 0x00073d, 0x02800000);
-        nv_icmd(priv, 0x000787, 0x000000cf);
-        nv_icmd(priv, 0x00078c, 0x00000008);
-        nv_icmd(priv, 0x000792, 0x00000001);
-        nv_icmd(priv, 0x000794, 0x00000001);
-        nv_icmd(priv, 0x000795, 0x00000001);
-        nv_icmd(priv, 0x000796, 0x00000001);
-        nv_icmd(priv, 0x000797, 0x000000cf);
-        nv_icmd(priv, 0x000836, 0x00000001);
-        nv_icmd(priv, 0x00079a, 0x00000002);
-        nv_icmd(priv, 0x000833, 0x04444480);
-        nv_icmd(priv, 0x0007a1, 0x00000001);
-        nv_icmd(priv, 0x0007a3, 0x00000001);
-        nv_icmd(priv, 0x0007a4, 0x00000001);
-        nv_icmd(priv, 0x0007a5, 0x00000001);
-        nv_icmd(priv, 0x000831, 0x00000004);
-        nv_icmd(priv, 0x000b07, 0x00000002);
-        nv_icmd(priv, 0x000b08, 0x00000100);
-        nv_icmd(priv, 0x000b09, 0x00000100);
-        nv_icmd(priv, 0x000b0a, 0x00000001);
-        nv_icmd(priv, 0x000a04, 0x000000ff);
-        nv_icmd(priv, 0x000a0b, 0x00000040);
-        nv_icmd(priv, 0x00097f, 0x00000100);
-        nv_icmd(priv, 0x000a02, 0x00000001);
-        nv_icmd(priv, 0x000809, 0x00000007);
-        nv_icmd(priv, 0x00c221, 0x00000040);
-        nv_icmd(priv, 0x00c1b0, 0x0000000f);
-        nv_icmd(priv, 0x00c1b1, 0x0000000f);
-        nv_icmd(priv, 0x00c1b2, 0x0000000f);
-        nv_icmd(priv, 0x00c1b3, 0x0000000f);
-        nv_icmd(priv, 0x00c1b4, 0x0000000f);
-        nv_icmd(priv, 0x00c1b5, 0x0000000f);
-        nv_icmd(priv, 0x00c1b6, 0x0000000f);
-        nv_icmd(priv, 0x00c1b7, 0x0000000f);
-        nv_icmd(priv, 0x00c1b8, 0x0fac6881);
-        nv_icmd(priv, 0x00c1b9, 0x00fac688);
-        nv_icmd(priv, 0x00c401, 0x00000001);
-        nv_icmd(priv, 0x00c402, 0x00010001);
-        nv_icmd(priv, 0x00c403, 0x00000001);
-        nv_icmd(priv, 0x00c404, 0x00000001);
-        nv_icmd(priv, 0x00c40e, 0x00000020);
-        nv_icmd(priv, 0x00c500, 0x00000003);
-        nv_icmd(priv, 0x01e100, 0x00000001);
-        nv_icmd(priv, 0x001000, 0x00000002);
-        nv_icmd(priv, 0x0006aa, 0x00000001);
-        nv_icmd(priv, 0x0006ad, 0x00000100);
-        nv_icmd(priv, 0x0006ae, 0x00000100);
-        nv_icmd(priv, 0x0006b1, 0x00000011);
-        nv_icmd(priv, 0x00078c, 0x00000008);
-        nv_icmd(priv, 0x000792, 0x00000001);
-        nv_icmd(priv, 0x000794, 0x00000001);
-        nv_icmd(priv, 0x000795, 0x00000001);
-        nv_icmd(priv, 0x000796, 0x00000001);
-        nv_icmd(priv, 0x000797, 0x000000cf);
-        nv_icmd(priv, 0x00079a, 0x00000002);
-        nv_icmd(priv, 0x000833, 0x04444480);
-        nv_icmd(priv, 0x0007a1, 0x00000001);
-        nv_icmd(priv, 0x0007a3, 0x00000001);
-        nv_icmd(priv, 0x0007a4, 0x00000001);
-        nv_icmd(priv, 0x0007a5, 0x00000001);
-        nv_icmd(priv, 0x000831, 0x00000004);
-        nv_icmd(priv, 0x01e100, 0x00000001);
-        nv_icmd(priv, 0x001000, 0x00000008);
-        nv_icmd(priv, 0x000039, 0x00000000);
-        nv_icmd(priv, 0x00003a, 0x00000000);
-        nv_icmd(priv, 0x00003b, 0x00000000);
-        nv_icmd(priv, 0x000380, 0x00000001);
-        nv_icmd(priv, 0x000366, 0x00000000);
-        nv_icmd(priv, 0x000367, 0x00000000);
-        nv_icmd(priv, 0x000368, 0x00000fff);
-        nv_icmd(priv, 0x000370, 0x00000000);
-        nv_icmd(priv, 0x000371, 0x00000000);
-        nv_icmd(priv, 0x000372, 0x000fffff);
-        nv_icmd(priv, 0x000813, 0x00000006);
-        nv_icmd(priv, 0x000814, 0x00000008);
-        nv_icmd(priv, 0x000957, 0x00000003);
-        nv_icmd(priv, 0x000818, 0x00000000);
-        nv_icmd(priv, 0x000819, 0x00000000);
-        nv_icmd(priv, 0x00081a, 0x00000000);
-        nv_icmd(priv, 0x00081b, 0x00000000);
-        nv_icmd(priv, 0x00081c, 0x00000000);
-        nv_icmd(priv, 0x00081d, 0x00000000);
-        nv_icmd(priv, 0x00081e, 0x00000000);
-        nv_icmd(priv, 0x00081f, 0x00000000);
-        nv_icmd(priv, 0x000848, 0x00000000);
-        nv_icmd(priv, 0x000849, 0x00000000);
-        nv_icmd(priv, 0x00084a, 0x00000000);
-        nv_icmd(priv, 0x00084b, 0x00000000);
-        nv_icmd(priv, 0x00084c, 0x00000000);
-        nv_icmd(priv, 0x00084d, 0x00000000);
-        nv_icmd(priv, 0x00084e, 0x00000000);
-        nv_icmd(priv, 0x00084f, 0x00000000);
-        nv_icmd(priv, 0x000850, 0x00000000);
-        nv_icmd(priv, 0x000851, 0x00000000);
-        nv_icmd(priv, 0x000852, 0x00000000);
-        nv_icmd(priv, 0x000853, 0x00000000);
-        nv_icmd(priv, 0x000854, 0x00000000);
-        nv_icmd(priv, 0x000855, 0x00000000);
-        nv_icmd(priv, 0x000856, 0x00000000);
-        nv_icmd(priv, 0x000857, 0x00000000);
-        nv_icmd(priv, 0x000738, 0x00000000);
-        nv_icmd(priv, 0x000b07, 0x00000002);
-        nv_icmd(priv, 0x000b08, 0x00000100);
-        nv_icmd(priv, 0x000b09, 0x00000100);
-        nv_icmd(priv, 0x000b0a, 0x00000001);
-        nv_icmd(priv, 0x000a04, 0x000000ff);
-        nv_icmd(priv, 0x00097f, 0x00000100);
-        nv_icmd(priv, 0x000a02, 0x00000001);
-        nv_icmd(priv, 0x000809, 0x00000007);
-        nv_icmd(priv, 0x00c221, 0x00000040);
-        nv_icmd(priv, 0x00c401, 0x00000001);
-        nv_icmd(priv, 0x00c402, 0x00010001);
-        nv_icmd(priv, 0x00c403, 0x00000001);
-        nv_icmd(priv, 0x00c404, 0x00000001);
-        nv_icmd(priv, 0x00c40e, 0x00000020);
-        nv_icmd(priv, 0x00c500, 0x00000003);
-        nv_icmd(priv, 0x01e100, 0x00000001);
-        nv_icmd(priv, 0x001000, 0x00000001);
-        nv_icmd(priv, 0x000b07, 0x00000002);
-        nv_icmd(priv, 0x000b08, 0x00000100);
-        nv_icmd(priv, 0x000b09, 0x00000100);
-        nv_icmd(priv, 0x000b0a, 0x00000001);
-        nv_icmd(priv, 0x01e100, 0x00000001);
-        nv_wr32(priv, 0x400208, 0x00000000);
-}
-
-static void
-nve0_grctx_generate_a097(struct nvc0_graph_priv *priv)
-{
-        nv_mthd(priv, 0xa097, 0x0800, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x0840, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x0880, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x08c0, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x0900, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x0940, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x0980, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x09c0, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x0804, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x0844, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x0884, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x08c4, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x0904, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x0944, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x0984, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x09c4, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x0808, 0x00000400);
-        nv_mthd(priv, 0xa097, 0x0848, 0x00000400);
-        nv_mthd(priv, 0xa097, 0x0888, 0x00000400);
-        nv_mthd(priv, 0xa097, 0x08c8, 0x00000400);
-        nv_mthd(priv, 0xa097, 0x0908, 0x00000400);
-        nv_mthd(priv, 0xa097, 0x0948, 0x00000400);
-        nv_mthd(priv, 0xa097, 0x0988, 0x00000400);
-        nv_mthd(priv, 0xa097, 0x09c8, 0x00000400);
-        nv_mthd(priv, 0xa097, 0x080c, 0x00000300);
-        nv_mthd(priv, 0xa097, 0x084c, 0x00000300);
-        nv_mthd(priv, 0xa097, 0x088c, 0x00000300);
-        nv_mthd(priv, 0xa097, 0x08cc, 0x00000300);
-        nv_mthd(priv, 0xa097, 0x090c, 0x00000300);
-        nv_mthd(priv, 0xa097, 0x094c, 0x00000300);
-        nv_mthd(priv, 0xa097, 0x098c, 0x00000300);
-        nv_mthd(priv, 0xa097, 0x09cc, 0x00000300);
-        nv_mthd(priv, 0xa097, 0x0810, 0x000000cf);
-        nv_mthd(priv, 0xa097, 0x0850, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x0890, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x08d0, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x0910, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x0950, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x0990, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x09d0, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x0814, 0x00000040);
-        nv_mthd(priv, 0xa097, 0x0854, 0x00000040);
-        nv_mthd(priv, 0xa097, 0x0894, 0x00000040);
-        nv_mthd(priv, 0xa097, 0x08d4, 0x00000040);
-        nv_mthd(priv, 0xa097, 0x0914, 0x00000040);
-        nv_mthd(priv, 0xa097, 0x0954, 0x00000040);
-        nv_mthd(priv, 0xa097, 0x0994, 0x00000040);
-        nv_mthd(priv, 0xa097, 0x09d4, 0x00000040);
-        nv_mthd(priv, 0xa097, 0x0818, 0x00000001);
-        nv_mthd(priv, 0xa097, 0x0858, 0x00000001);
-        nv_mthd(priv, 0xa097, 0x0898, 0x00000001);
-        nv_mthd(priv, 0xa097, 0x08d8, 0x00000001);
-        nv_mthd(priv, 0xa097, 0x0918, 0x00000001);
-        nv_mthd(priv, 0xa097, 0x0958, 0x00000001);
-        nv_mthd(priv, 0xa097, 0x0998, 0x00000001);
-        nv_mthd(priv, 0xa097, 0x09d8, 0x00000001);
-        nv_mthd(priv, 0xa097, 0x081c, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x085c, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x089c, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x08dc, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x091c, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x095c, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x099c, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x09dc, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x0820, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x0860, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x08a0, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x08e0, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x0920, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x0960, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x09a0, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x09e0, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x1c00, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x1c10, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x1c20, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x1c30, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x1c40, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x1c50, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x1c60, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x1c70, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x1c80, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x1c90, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x1ca0, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x1cb0, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x1cc0, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x1cd0, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x1ce0, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x1cf0, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x1c04, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x1c14, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x1c24, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x1c34, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x1c44, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x1c54, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x1c64, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x1c74, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x1c84, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x1c94, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x1ca4, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x1cb4, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x1cc4, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x1cd4, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x1ce4, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x1cf4, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x1c08, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x1c18, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x1c28, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x1c38, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x1c48, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x1c58, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x1c68, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x1c78, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x1c88, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x1c98, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x1ca8, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x1cb8, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x1cc8, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x1cd8, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x1ce8, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x1cf8, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x1c0c, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x1c1c, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x1c2c, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x1c3c, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x1c4c, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x1c5c, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x1c6c, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x1c7c, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x1c8c, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x1c9c, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x1cac, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x1cbc, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x1ccc, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x1cdc, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x1cec, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x1cfc, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x1d00, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x1d10, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x1d20, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x1d30, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x1d40, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x1d50, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x1d60, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x1d70, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x1d80, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x1d90, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x1da0, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x1db0, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x1dc0, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x1dd0, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x1de0, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x1df0, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x1d04, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x1d14, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x1d24, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x1d34, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x1d44, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x1d54, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x1d64, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x1d74, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x1d84, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x1d94, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x1da4, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x1db4, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x1dc4, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x1dd4, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x1de4, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x1df4, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x1d08, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x1d18, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x1d28, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x1d38, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x1d48, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x1d58, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x1d68, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x1d78, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x1d88, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x1d98, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x1da8, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x1db8, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x1dc8, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x1dd8, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x1de8, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x1df8, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x1d0c, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x1d1c, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x1d2c, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x1d3c, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x1d4c, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x1d5c, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x1d6c, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x1d7c, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x1d8c, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x1d9c, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x1dac, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x1dbc, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x1dcc, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x1ddc, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x1dec, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x1dfc, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x1f00, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x1f08, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x1f10, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x1f18, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x1f20, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x1f28, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x1f30, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x1f38, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x1f40, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x1f48, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x1f50, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x1f58, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x1f60, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x1f68, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x1f70, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x1f78, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x1f04, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x1f0c, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x1f14, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x1f1c, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x1f24, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x1f2c, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x1f34, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x1f3c, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x1f44, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x1f4c, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x1f54, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x1f5c, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x1f64, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x1f6c, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x1f74, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x1f7c, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x1f80, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x1f88, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x1f90, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x1f98, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x1fa0, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x1fa8, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x1fb0, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x1fb8, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x1fc0, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x1fc8, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x1fd0, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x1fd8, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x1fe0, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x1fe8, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x1ff0, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x1ff8, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x1f84, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x1f8c, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x1f94, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x1f9c, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x1fa4, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x1fac, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x1fb4, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x1fbc, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x1fc4, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x1fcc, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x1fd4, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x1fdc, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x1fe4, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x1fec, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x1ff4, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x1ffc, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x2000, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x2040, 0x00000011);
-        nv_mthd(priv, 0xa097, 0x2080, 0x00000020);
-        nv_mthd(priv, 0xa097, 0x20c0, 0x00000030);
-        nv_mthd(priv, 0xa097, 0x2100, 0x00000040);
-        nv_mthd(priv, 0xa097, 0x2140, 0x00000051);
-        nv_mthd(priv, 0xa097, 0x200c, 0x00000001);
-        nv_mthd(priv, 0xa097, 0x204c, 0x00000001);
-        nv_mthd(priv, 0xa097, 0x208c, 0x00000001);
-        nv_mthd(priv, 0xa097, 0x20cc, 0x00000001);
-        nv_mthd(priv, 0xa097, 0x210c, 0x00000001);
-        nv_mthd(priv, 0xa097, 0x214c, 0x00000001);
-        nv_mthd(priv, 0xa097, 0x2010, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x2050, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x2090, 0x00000001);
-        nv_mthd(priv, 0xa097, 0x20d0, 0x00000002);
-        nv_mthd(priv, 0xa097, 0x2110, 0x00000003);
-        nv_mthd(priv, 0xa097, 0x2150, 0x00000004);
-        nv_mthd(priv, 0xa097, 0x0380, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x03a0, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x03c0, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x03e0, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x0384, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x03a4, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x03c4, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x03e4, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x0388, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x03a8, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x03c8, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x03e8, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x038c, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x03ac, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x03cc, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x03ec, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x0700, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x0710, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x0720, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x0730, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x0704, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x0714, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x0724, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x0734, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x0708, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x0718, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x0728, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x0738, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x2800, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x2804, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x2808, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x280c, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x2810, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x2814, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x2818, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x281c, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x2820, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x2824, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x2828, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x282c, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x2830, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x2834, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x2838, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x283c, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x2840, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x2844, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x2848, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x284c, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x2850, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x2854, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x2858, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x285c, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x2860, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x2864, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x2868, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x286c, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x2870, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x2874, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x2878, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x287c, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x2880, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x2884, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x2888, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x288c, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x2890, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x2894, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x2898, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x289c, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x28a0, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x28a4, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x28a8, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x28ac, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x28b0, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x28b4, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x28b8, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x28bc, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x28c0, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x28c4, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x28c8, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x28cc, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x28d0, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x28d4, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x28d8, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x28dc, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x28e0, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x28e4, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x28e8, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x28ec, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x28f0, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x28f4, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x28f8, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x28fc, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x2900, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x2904, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x2908, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x290c, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x2910, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x2914, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x2918, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x291c, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x2920, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x2924, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x2928, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x292c, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x2930, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x2934, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x2938, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x293c, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x2940, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x2944, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x2948, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x294c, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x2950, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x2954, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x2958, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x295c, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x2960, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x2964, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x2968, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x296c, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x2970, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x2974, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x2978, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x297c, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x2980, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x2984, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x2988, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x298c, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x2990, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x2994, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x2998, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x299c, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x29a0, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x29a4, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x29a8, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x29ac, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x29b0, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x29b4, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x29b8, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x29bc, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x29c0, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x29c4, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x29c8, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x29cc, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x29d0, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x29d4, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x29d8, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x29dc, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x29e0, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x29e4, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x29e8, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x29ec, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x29f0, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x29f4, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x29f8, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x29fc, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x0a00, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x0a20, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x0a40, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x0a60, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x0a80, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x0aa0, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x0ac0, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x0ae0, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x0b00, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x0b20, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x0b40, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x0b60, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x0b80, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x0ba0, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x0bc0, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x0be0, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x0a04, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x0a24, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x0a44, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x0a64, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x0a84, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x0aa4, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x0ac4, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x0ae4, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x0b04, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x0b24, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x0b44, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x0b64, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x0b84, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x0ba4, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x0bc4, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x0be4, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x0a08, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x0a28, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x0a48, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x0a68, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x0a88, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x0aa8, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x0ac8, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x0ae8, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x0b08, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x0b28, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x0b48, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x0b68, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x0b88, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x0ba8, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x0bc8, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x0be8, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x0a0c, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x0a2c, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x0a4c, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x0a6c, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x0a8c, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x0aac, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x0acc, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x0aec, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x0b0c, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x0b2c, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x0b4c, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x0b6c, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x0b8c, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x0bac, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x0bcc, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x0bec, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x0a10, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x0a30, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x0a50, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x0a70, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x0a90, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x0ab0, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x0ad0, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x0af0, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x0b10, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x0b30, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x0b50, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x0b70, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x0b90, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x0bb0, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x0bd0, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x0bf0, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x0a14, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x0a34, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x0a54, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x0a74, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x0a94, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x0ab4, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x0ad4, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x0af4, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x0b14, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x0b34, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x0b54, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x0b74, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x0b94, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x0bb4, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x0bd4, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x0bf4, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x0c00, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x0c10, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x0c20, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x0c30, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x0c40, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x0c50, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x0c60, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x0c70, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x0c80, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x0c90, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x0ca0, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x0cb0, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x0cc0, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x0cd0, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x0ce0, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x0cf0, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x0c04, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x0c14, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x0c24, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x0c34, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x0c44, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x0c54, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x0c64, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x0c74, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x0c84, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x0c94, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x0ca4, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x0cb4, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x0cc4, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x0cd4, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x0ce4, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x0cf4, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x0c08, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x0c18, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x0c28, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x0c38, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x0c48, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x0c58, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x0c68, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x0c78, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x0c88, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x0c98, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x0ca8, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x0cb8, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x0cc8, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x0cd8, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x0ce8, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x0cf8, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x0c0c, 0x3f800000);
-        nv_mthd(priv, 0xa097, 0x0c1c, 0x3f800000);
-        nv_mthd(priv, 0xa097, 0x0c2c, 0x3f800000);
-        nv_mthd(priv, 0xa097, 0x0c3c, 0x3f800000);
-        nv_mthd(priv, 0xa097, 0x0c4c, 0x3f800000);
-        nv_mthd(priv, 0xa097, 0x0c5c, 0x3f800000);
-        nv_mthd(priv, 0xa097, 0x0c6c, 0x3f800000);
-        nv_mthd(priv, 0xa097, 0x0c7c, 0x3f800000);
-        nv_mthd(priv, 0xa097, 0x0c8c, 0x3f800000);
-        nv_mthd(priv, 0xa097, 0x0c9c, 0x3f800000);
-        nv_mthd(priv, 0xa097, 0x0cac, 0x3f800000);
-        nv_mthd(priv, 0xa097, 0x0cbc, 0x3f800000);
-        nv_mthd(priv, 0xa097, 0x0ccc, 0x3f800000);
-        nv_mthd(priv, 0xa097, 0x0cdc, 0x3f800000);
-        nv_mthd(priv, 0xa097, 0x0cec, 0x3f800000);
-        nv_mthd(priv, 0xa097, 0x0cfc, 0x3f800000);
-        nv_mthd(priv, 0xa097, 0x0d00, 0xffff0000);
-        nv_mthd(priv, 0xa097, 0x0d08, 0xffff0000);
-        nv_mthd(priv, 0xa097, 0x0d10, 0xffff0000);
-        nv_mthd(priv, 0xa097, 0x0d18, 0xffff0000);
-        nv_mthd(priv, 0xa097, 0x0d20, 0xffff0000);
-        nv_mthd(priv, 0xa097, 0x0d28, 0xffff0000);
-        nv_mthd(priv, 0xa097, 0x0d30, 0xffff0000);
-        nv_mthd(priv, 0xa097, 0x0d38, 0xffff0000);
-        nv_mthd(priv, 0xa097, 0x0d04, 0xffff0000);
-        nv_mthd(priv, 0xa097, 0x0d0c, 0xffff0000);
-        nv_mthd(priv, 0xa097, 0x0d14, 0xffff0000);
-        nv_mthd(priv, 0xa097, 0x0d1c, 0xffff0000);
-        nv_mthd(priv, 0xa097, 0x0d24, 0xffff0000);
-        nv_mthd(priv, 0xa097, 0x0d2c, 0xffff0000);
-        nv_mthd(priv, 0xa097, 0x0d34, 0xffff0000);
-        nv_mthd(priv, 0xa097, 0x0d3c, 0xffff0000);
-        nv_mthd(priv, 0xa097, 0x0e00, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x0e10, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x0e20, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x0e30, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x0e40, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x0e50, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x0e60, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x0e70, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x0e80, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x0e90, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x0ea0, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x0eb0, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x0ec0, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x0ed0, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x0ee0, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x0ef0, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x0e04, 0xffff0000);
-        nv_mthd(priv, 0xa097, 0x0e14, 0xffff0000);
-        nv_mthd(priv, 0xa097, 0x0e24, 0xffff0000);
-        nv_mthd(priv, 0xa097, 0x0e34, 0xffff0000);
-        nv_mthd(priv, 0xa097, 0x0e44, 0xffff0000);
-        nv_mthd(priv, 0xa097, 0x0e54, 0xffff0000);
-        nv_mthd(priv, 0xa097, 0x0e64, 0xffff0000);
-        nv_mthd(priv, 0xa097, 0x0e74, 0xffff0000);
-        nv_mthd(priv, 0xa097, 0x0e84, 0xffff0000);
-        nv_mthd(priv, 0xa097, 0x0e94, 0xffff0000);
-        nv_mthd(priv, 0xa097, 0x0ea4, 0xffff0000);
-        nv_mthd(priv, 0xa097, 0x0eb4, 0xffff0000);
-        nv_mthd(priv, 0xa097, 0x0ec4, 0xffff0000);
-        nv_mthd(priv, 0xa097, 0x0ed4, 0xffff0000);
-        nv_mthd(priv, 0xa097, 0x0ee4, 0xffff0000);
-        nv_mthd(priv, 0xa097, 0x0ef4, 0xffff0000);
-        nv_mthd(priv, 0xa097, 0x0e08, 0xffff0000);
-        nv_mthd(priv, 0xa097, 0x0e18, 0xffff0000);
-        nv_mthd(priv, 0xa097, 0x0e28, 0xffff0000);
-        nv_mthd(priv, 0xa097, 0x0e38, 0xffff0000);
-        nv_mthd(priv, 0xa097, 0x0e48, 0xffff0000);
-        nv_mthd(priv, 0xa097, 0x0e58, 0xffff0000);
-        nv_mthd(priv, 0xa097, 0x0e68, 0xffff0000);
-        nv_mthd(priv, 0xa097, 0x0e78, 0xffff0000);
-        nv_mthd(priv, 0xa097, 0x0e88, 0xffff0000);
-        nv_mthd(priv, 0xa097, 0x0e98, 0xffff0000);
-        nv_mthd(priv, 0xa097, 0x0ea8, 0xffff0000);
-        nv_mthd(priv, 0xa097, 0x0eb8, 0xffff0000);
-        nv_mthd(priv, 0xa097, 0x0ec8, 0xffff0000);
-        nv_mthd(priv, 0xa097, 0x0ed8, 0xffff0000);
-        nv_mthd(priv, 0xa097, 0x0ee8, 0xffff0000);
-        nv_mthd(priv, 0xa097, 0x0ef8, 0xffff0000);
-        nv_mthd(priv, 0xa097, 0x0d40, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x0d48, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x0d50, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x0d58, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x0d44, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x0d4c, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x0d54, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x0d5c, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x1e00, 0x00000001);
-        nv_mthd(priv, 0xa097, 0x1e20, 0x00000001);
-        nv_mthd(priv, 0xa097, 0x1e40, 0x00000001);
-        nv_mthd(priv, 0xa097, 0x1e60, 0x00000001);
-        nv_mthd(priv, 0xa097, 0x1e80, 0x00000001);
-        nv_mthd(priv, 0xa097, 0x1ea0, 0x00000001);
-        nv_mthd(priv, 0xa097, 0x1ec0, 0x00000001);
-        nv_mthd(priv, 0xa097, 0x1ee0, 0x00000001);
-        nv_mthd(priv, 0xa097, 0x1e04, 0x00000001);
-        nv_mthd(priv, 0xa097, 0x1e24, 0x00000001);
-        nv_mthd(priv, 0xa097, 0x1e44, 0x00000001);
-        nv_mthd(priv, 0xa097, 0x1e64, 0x00000001);
-        nv_mthd(priv, 0xa097, 0x1e84, 0x00000001);
-        nv_mthd(priv, 0xa097, 0x1ea4, 0x00000001);
-        nv_mthd(priv, 0xa097, 0x1ec4, 0x00000001);
-        nv_mthd(priv, 0xa097, 0x1ee4, 0x00000001);
-        nv_mthd(priv, 0xa097, 0x1e08, 0x00000002);
-        nv_mthd(priv, 0xa097, 0x1e28, 0x00000002);
-        nv_mthd(priv, 0xa097, 0x1e48, 0x00000002);
-        nv_mthd(priv, 0xa097, 0x1e68, 0x00000002);
-        nv_mthd(priv, 0xa097, 0x1e88, 0x00000002);
-        nv_mthd(priv, 0xa097, 0x1ea8, 0x00000002);
-        nv_mthd(priv, 0xa097, 0x1ec8, 0x00000002);
-        nv_mthd(priv, 0xa097, 0x1ee8, 0x00000002);
-        nv_mthd(priv, 0xa097, 0x1e0c, 0x00000001);
-        nv_mthd(priv, 0xa097, 0x1e2c, 0x00000001);
-        nv_mthd(priv, 0xa097, 0x1e4c, 0x00000001);
-        nv_mthd(priv, 0xa097, 0x1e6c, 0x00000001);
-        nv_mthd(priv, 0xa097, 0x1e8c, 0x00000001);
-        nv_mthd(priv, 0xa097, 0x1eac, 0x00000001);
-        nv_mthd(priv, 0xa097, 0x1ecc, 0x00000001);
-        nv_mthd(priv, 0xa097, 0x1eec, 0x00000001);
-        nv_mthd(priv, 0xa097, 0x1e10, 0x00000001);
-        nv_mthd(priv, 0xa097, 0x1e30, 0x00000001);
-        nv_mthd(priv, 0xa097, 0x1e50, 0x00000001);
-        nv_mthd(priv, 0xa097, 0x1e70, 0x00000001);
-        nv_mthd(priv, 0xa097, 0x1e90, 0x00000001);
-        nv_mthd(priv, 0xa097, 0x1eb0, 0x00000001);
-        nv_mthd(priv, 0xa097, 0x1ed0, 0x00000001);
-        nv_mthd(priv, 0xa097, 0x1ef0, 0x00000001);
-        nv_mthd(priv, 0xa097, 0x1e14, 0x00000002);
-        nv_mthd(priv, 0xa097, 0x1e34, 0x00000002);
-        nv_mthd(priv, 0xa097, 0x1e54, 0x00000002);
-        nv_mthd(priv, 0xa097, 0x1e74, 0x00000002);
-        nv_mthd(priv, 0xa097, 0x1e94, 0x00000002);
-        nv_mthd(priv, 0xa097, 0x1eb4, 0x00000002);
-        nv_mthd(priv, 0xa097, 0x1ed4, 0x00000002);
-        nv_mthd(priv, 0xa097, 0x1ef4, 0x00000002);
-        nv_mthd(priv, 0xa097, 0x1e18, 0x00000001);
-        nv_mthd(priv, 0xa097, 0x1e38, 0x00000001);
-        nv_mthd(priv, 0xa097, 0x1e58, 0x00000001);
-        nv_mthd(priv, 0xa097, 0x1e78, 0x00000001);
-        nv_mthd(priv, 0xa097, 0x1e98, 0x00000001);
-        nv_mthd(priv, 0xa097, 0x1eb8, 0x00000001);
-        nv_mthd(priv, 0xa097, 0x1ed8, 0x00000001);
-        nv_mthd(priv, 0xa097, 0x1ef8, 0x00000001);
-        nv_mthd(priv, 0xa097, 0x3400, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x3404, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x3408, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x340c, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x3410, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x3414, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x3418, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x341c, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x3420, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x3424, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x3428, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x342c, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x3430, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x3434, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x3438, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x343c, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x3440, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x3444, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x3448, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x344c, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x3450, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x3454, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x3458, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x345c, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x3460, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x3464, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x3468, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x346c, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x3470, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x3474, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x3478, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x347c, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x3480, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x3484, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x3488, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x348c, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x3490, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x3494, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x3498, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x349c, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x34a0, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x34a4, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x34a8, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x34ac, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x34b0, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x34b4, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x34b8, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x34bc, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x34c0, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x34c4, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x34c8, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x34cc, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x34d0, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x34d4, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x34d8, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x34dc, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x34e0, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x34e4, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x34e8, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x34ec, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x34f0, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x34f4, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x34f8, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x34fc, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x3500, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x3504, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x3508, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x350c, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x3510, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x3514, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x3518, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x351c, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x3520, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x3524, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x3528, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x352c, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x3530, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x3534, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x3538, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x353c, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x3540, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x3544, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x3548, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x354c, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x3550, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x3554, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x3558, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x355c, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x3560, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x3564, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x3568, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x356c, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x3570, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x3574, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x3578, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x357c, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x3580, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x3584, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x3588, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x358c, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x3590, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x3594, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x3598, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x359c, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x35a0, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x35a4, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x35a8, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x35ac, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x35b0, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x35b4, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x35b8, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x35bc, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x35c0, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x35c4, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x35c8, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x35cc, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x35d0, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x35d4, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x35d8, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x35dc, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x35e0, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x35e4, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x35e8, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x35ec, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x35f0, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x35f4, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x35f8, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x35fc, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x030c, 0x00000001);
-        nv_mthd(priv, 0xa097, 0x1944, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x1514, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x0d68, 0x0000ffff);
-        nv_mthd(priv, 0xa097, 0x121c, 0x0fac6881);
-        nv_mthd(priv, 0xa097, 0x0fac, 0x00000001);
-        nv_mthd(priv, 0xa097, 0x1538, 0x00000001);
-        nv_mthd(priv, 0xa097, 0x0fe0, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x0fe4, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x0fe8, 0x00000014);
-        nv_mthd(priv, 0xa097, 0x0fec, 0x00000040);
-        nv_mthd(priv, 0xa097, 0x0ff0, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x179c, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x1228, 0x00000400);
-        nv_mthd(priv, 0xa097, 0x122c, 0x00000300);
-        nv_mthd(priv, 0xa097, 0x1230, 0x00010001);
-        nv_mthd(priv, 0xa097, 0x07f8, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x15b4, 0x00000001);
-        nv_mthd(priv, 0xa097, 0x15cc, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x1534, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x0fb0, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x15d0, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x153c, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x16b4, 0x00000003);
-        nv_mthd(priv, 0xa097, 0x0fbc, 0x0000ffff);
-        nv_mthd(priv, 0xa097, 0x0fc0, 0x0000ffff);
-        nv_mthd(priv, 0xa097, 0x0fc4, 0x0000ffff);
-        nv_mthd(priv, 0xa097, 0x0fc8, 0x0000ffff);
-        nv_mthd(priv, 0xa097, 0x0df8, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x0dfc, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x1948, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x1970, 0x00000001);
-        nv_mthd(priv, 0xa097, 0x161c, 0x000009f0);
-        nv_mthd(priv, 0xa097, 0x0dcc, 0x00000010);
-        nv_mthd(priv, 0xa097, 0x163c, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x15e4, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x1160, 0x25e00040);
-        nv_mthd(priv, 0xa097, 0x1164, 0x25e00040);
-        nv_mthd(priv, 0xa097, 0x1168, 0x25e00040);
-        nv_mthd(priv, 0xa097, 0x116c, 0x25e00040);
-        nv_mthd(priv, 0xa097, 0x1170, 0x25e00040);
-        nv_mthd(priv, 0xa097, 0x1174, 0x25e00040);
-        nv_mthd(priv, 0xa097, 0x1178, 0x25e00040);
-        nv_mthd(priv, 0xa097, 0x117c, 0x25e00040);
-        nv_mthd(priv, 0xa097, 0x1180, 0x25e00040);
-        nv_mthd(priv, 0xa097, 0x1184, 0x25e00040);
-        nv_mthd(priv, 0xa097, 0x1188, 0x25e00040);
-        nv_mthd(priv, 0xa097, 0x118c, 0x25e00040);
-        nv_mthd(priv, 0xa097, 0x1190, 0x25e00040);
-        nv_mthd(priv, 0xa097, 0x1194, 0x25e00040);
-        nv_mthd(priv, 0xa097, 0x1198, 0x25e00040);
-        nv_mthd(priv, 0xa097, 0x119c, 0x25e00040);
-        nv_mthd(priv, 0xa097, 0x11a0, 0x25e00040);
-        nv_mthd(priv, 0xa097, 0x11a4, 0x25e00040);
-        nv_mthd(priv, 0xa097, 0x11a8, 0x25e00040);
-        nv_mthd(priv, 0xa097, 0x11ac, 0x25e00040);
-        nv_mthd(priv, 0xa097, 0x11b0, 0x25e00040);
-        nv_mthd(priv, 0xa097, 0x11b4, 0x25e00040);
-        nv_mthd(priv, 0xa097, 0x11b8, 0x25e00040);
-        nv_mthd(priv, 0xa097, 0x11bc, 0x25e00040);
-        nv_mthd(priv, 0xa097, 0x11c0, 0x25e00040);
-        nv_mthd(priv, 0xa097, 0x11c4, 0x25e00040);
-        nv_mthd(priv, 0xa097, 0x11c8, 0x25e00040);
-        nv_mthd(priv, 0xa097, 0x11cc, 0x25e00040);
-        nv_mthd(priv, 0xa097, 0x11d0, 0x25e00040);
-        nv_mthd(priv, 0xa097, 0x11d4, 0x25e00040);
-        nv_mthd(priv, 0xa097, 0x11d8, 0x25e00040);
-        nv_mthd(priv, 0xa097, 0x11dc, 0x25e00040);
-        nv_mthd(priv, 0xa097, 0x1880, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x1884, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x1888, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x188c, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x1890, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x1894, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x1898, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x189c, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x18a0, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x18a4, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x18a8, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x18ac, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x18b0, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x18b4, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x18b8, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x18bc, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x18c0, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x18c4, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x18c8, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x18cc, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x18d0, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x18d4, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x18d8, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x18dc, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x18e0, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x18e4, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x18e8, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x18ec, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x18f0, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x18f4, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x18f8, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x18fc, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x0f84, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x0f88, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x17c8, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x17cc, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x17d0, 0x000000ff);
-        nv_mthd(priv, 0xa097, 0x17d4, 0xffffffff);
-        nv_mthd(priv, 0xa097, 0x17d8, 0x00000002);
-        nv_mthd(priv, 0xa097, 0x17dc, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x15f4, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x15f8, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x1434, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x1438, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x0d74, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x0dec, 0x00000001);
-        nv_mthd(priv, 0xa097, 0x13a4, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x1318, 0x00000001);
-        nv_mthd(priv, 0xa097, 0x1644, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x0748, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x0de8, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x1648, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x12a4, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x1120, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x1124, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x1128, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x112c, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x1118, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x164c, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x1658, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x1910, 0x00000290);
-        nv_mthd(priv, 0xa097, 0x1518, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x165c, 0x00000001);
-        nv_mthd(priv, 0xa097, 0x1520, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x1604, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x1570, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x13b0, 0x3f800000);
-        nv_mthd(priv, 0xa097, 0x13b4, 0x3f800000);
-        nv_mthd(priv, 0xa097, 0x020c, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x1670, 0x30201000);
-        nv_mthd(priv, 0xa097, 0x1674, 0x70605040);
-        nv_mthd(priv, 0xa097, 0x1678, 0xb8a89888);
-        nv_mthd(priv, 0xa097, 0x167c, 0xf8e8d8c8);
-        nv_mthd(priv, 0xa097, 0x166c, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x1680, 0x00ffff00);
-        nv_mthd(priv, 0xa097, 0x12d0, 0x00000003);
-        nv_mthd(priv, 0xa097, 0x12d4, 0x00000002);
-        nv_mthd(priv, 0xa097, 0x1684, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x1688, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x0dac, 0x00001b02);
-        nv_mthd(priv, 0xa097, 0x0db0, 0x00001b02);
-        nv_mthd(priv, 0xa097, 0x0db4, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x168c, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x15bc, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x156c, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x187c, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x1110, 0x00000001);
-        nv_mthd(priv, 0xa097, 0x0dc0, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x0dc4, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x0dc8, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x1234, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x1690, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x12ac, 0x00000001);
-        nv_mthd(priv, 0xa097, 0x0790, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x0794, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x0798, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x079c, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x07a0, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x077c, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x1000, 0x00000010);
-        nv_mthd(priv, 0xa097, 0x10fc, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x1290, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x0218, 0x00000010);
-        nv_mthd(priv, 0xa097, 0x12d8, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x12dc, 0x00000010);
-        nv_mthd(priv, 0xa097, 0x0d94, 0x00000001);
-        nv_mthd(priv, 0xa097, 0x155c, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x1560, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x1564, 0x00000fff);
-        nv_mthd(priv, 0xa097, 0x1574, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x1578, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x157c, 0x000fffff);
-        nv_mthd(priv, 0xa097, 0x1354, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x1610, 0x00000012);
-        nv_mthd(priv, 0xa097, 0x1608, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x160c, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x260c, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x07ac, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x162c, 0x00000003);
-        nv_mthd(priv, 0xa097, 0x0210, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x0320, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x0324, 0x3f800000);
-        nv_mthd(priv, 0xa097, 0x0328, 0x3f800000);
-        nv_mthd(priv, 0xa097, 0x032c, 0x3f800000);
-        nv_mthd(priv, 0xa097, 0x0330, 0x3f800000);
-        nv_mthd(priv, 0xa097, 0x0334, 0x3f800000);
-        nv_mthd(priv, 0xa097, 0x0338, 0x3f800000);
-        nv_mthd(priv, 0xa097, 0x0750, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x0760, 0x39291909);
-        nv_mthd(priv, 0xa097, 0x0764, 0x79695949);
-        nv_mthd(priv, 0xa097, 0x0768, 0xb9a99989);
-        nv_mthd(priv, 0xa097, 0x076c, 0xf9e9d9c9);
-        nv_mthd(priv, 0xa097, 0x0770, 0x30201000);
-        nv_mthd(priv, 0xa097, 0x0774, 0x70605040);
-        nv_mthd(priv, 0xa097, 0x0778, 0x00009080);
-        nv_mthd(priv, 0xa097, 0x0780, 0x39291909);
-        nv_mthd(priv, 0xa097, 0x0784, 0x79695949);
-        nv_mthd(priv, 0xa097, 0x0788, 0xb9a99989);
-        nv_mthd(priv, 0xa097, 0x078c, 0xf9e9d9c9);
-        nv_mthd(priv, 0xa097, 0x07d0, 0x30201000);
-        nv_mthd(priv, 0xa097, 0x07d4, 0x70605040);
-        nv_mthd(priv, 0xa097, 0x07d8, 0x00009080);
-        nv_mthd(priv, 0xa097, 0x037c, 0x00000001);
-        nv_mthd(priv, 0xa097, 0x0740, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x0744, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x2600, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x1918, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x191c, 0x00000900);
-        nv_mthd(priv, 0xa097, 0x1920, 0x00000405);
-        nv_mthd(priv, 0xa097, 0x1308, 0x00000001);
-        nv_mthd(priv, 0xa097, 0x1924, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x13ac, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x192c, 0x00000001);
-        nv_mthd(priv, 0xa097, 0x193c, 0x00002c1c);
-        nv_mthd(priv, 0xa097, 0x0d7c, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x0f8c, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x02c0, 0x00000001);
-        nv_mthd(priv, 0xa097, 0x1510, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x1940, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x0ff4, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x0ff8, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x194c, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x1950, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x1968, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x1590, 0x0000003f);
-        nv_mthd(priv, 0xa097, 0x07e8, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x07ec, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x07f0, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x07f4, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x196c, 0x00000011);
-        nv_mthd(priv, 0xa097, 0x02e4, 0x0000b001);
-        nv_mthd(priv, 0xa097, 0x036c, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x0370, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x197c, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x0fcc, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x0fd0, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x02d8, 0x00000040);
-        nv_mthd(priv, 0xa097, 0x1980, 0x00000080);
-        nv_mthd(priv, 0xa097, 0x1504, 0x00000080);
-        nv_mthd(priv, 0xa097, 0x1984, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x0300, 0x00000001);
-        nv_mthd(priv, 0xa097, 0x13a8, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x12ec, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x1310, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x1314, 0x00000001);
-        nv_mthd(priv, 0xa097, 0x1380, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x1384, 0x00000001);
-        nv_mthd(priv, 0xa097, 0x1388, 0x00000001);
-        nv_mthd(priv, 0xa097, 0x138c, 0x00000001);
-        nv_mthd(priv, 0xa097, 0x1390, 0x00000001);
-        nv_mthd(priv, 0xa097, 0x1394, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x139c, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x1398, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x1594, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x1598, 0x00000001);
-        nv_mthd(priv, 0xa097, 0x159c, 0x00000001);
-        nv_mthd(priv, 0xa097, 0x15a0, 0x00000001);
-        nv_mthd(priv, 0xa097, 0x15a4, 0x00000001);
-        nv_mthd(priv, 0xa097, 0x0f54, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x0f58, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x0f5c, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x19bc, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x0f9c, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x0fa0, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x12cc, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x12e8, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x130c, 0x00000001);
-        nv_mthd(priv, 0xa097, 0x1360, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x1364, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x1368, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x136c, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x1370, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x1374, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x1378, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x137c, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x133c, 0x00000001);
-        nv_mthd(priv, 0xa097, 0x1340, 0x00000001);
-        nv_mthd(priv, 0xa097, 0x1344, 0x00000002);
-        nv_mthd(priv, 0xa097, 0x1348, 0x00000001);
-        nv_mthd(priv, 0xa097, 0x134c, 0x00000001);
-        nv_mthd(priv, 0xa097, 0x1350, 0x00000002);
-        nv_mthd(priv, 0xa097, 0x1358, 0x00000001);
-        nv_mthd(priv, 0xa097, 0x12e4, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x131c, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x1320, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x1324, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x1328, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x19c0, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x1140, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x19c4, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x19c8, 0x00001500);
-        nv_mthd(priv, 0xa097, 0x135c, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x0f90, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x19e0, 0x00000001);
-        nv_mthd(priv, 0xa097, 0x19e4, 0x00000001);
-        nv_mthd(priv, 0xa097, 0x19e8, 0x00000001);
-        nv_mthd(priv, 0xa097, 0x19ec, 0x00000001);
-        nv_mthd(priv, 0xa097, 0x19f0, 0x00000001);
-        nv_mthd(priv, 0xa097, 0x19f4, 0x00000001);
-        nv_mthd(priv, 0xa097, 0x19f8, 0x00000001);
-        nv_mthd(priv, 0xa097, 0x19fc, 0x00000001);
-        nv_mthd(priv, 0xa097, 0x19cc, 0x00000001);
-        nv_mthd(priv, 0xa097, 0x15b8, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x1a00, 0x00001111);
-        nv_mthd(priv, 0xa097, 0x1a04, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x1a08, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x1a0c, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x1a10, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x1a14, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x1a18, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x1a1c, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x0d6c, 0xffff0000);
-        nv_mthd(priv, 0xa097, 0x0d70, 0xffff0000);
-        nv_mthd(priv, 0xa097, 0x10f8, 0x00001010);
-        nv_mthd(priv, 0xa097, 0x0d80, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x0d84, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x0d88, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x0d8c, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x0d90, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x0da0, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x07a4, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x07a8, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x1508, 0x80000000);
-        nv_mthd(priv, 0xa097, 0x150c, 0x40000000);
-        nv_mthd(priv, 0xa097, 0x1668, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x0318, 0x00000008);
-        nv_mthd(priv, 0xa097, 0x031c, 0x00000008);
-        nv_mthd(priv, 0xa097, 0x0d9c, 0x00000001);
-        nv_mthd(priv, 0xa097, 0x0374, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x0378, 0x00000020);
-        nv_mthd(priv, 0xa097, 0x07dc, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x074c, 0x00000055);
-        nv_mthd(priv, 0xa097, 0x1420, 0x00000003);
-        nv_mthd(priv, 0xa097, 0x17bc, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x17c0, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x17c4, 0x00000001);
-        nv_mthd(priv, 0xa097, 0x1008, 0x00000008);
-        nv_mthd(priv, 0xa097, 0x100c, 0x00000040);
-        nv_mthd(priv, 0xa097, 0x1010, 0x0000012c);
-        nv_mthd(priv, 0xa097, 0x0d60, 0x00000040);
-        nv_mthd(priv, 0xa097, 0x075c, 0x00000003);
-        nv_mthd(priv, 0xa097, 0x1018, 0x00000020);
-        nv_mthd(priv, 0xa097, 0x101c, 0x00000001);
-        nv_mthd(priv, 0xa097, 0x1020, 0x00000020);
-        nv_mthd(priv, 0xa097, 0x1024, 0x00000001);
-        nv_mthd(priv, 0xa097, 0x1444, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x1448, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x144c, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x0360, 0x20164010);
-        nv_mthd(priv, 0xa097, 0x0364, 0x00000020);
-        nv_mthd(priv, 0xa097, 0x0368, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x0de4, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x0204, 0x00000006);
-        nv_mthd(priv, 0xa097, 0x0208, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x02cc, 0x003fffff);
-        nv_mthd(priv, 0xa097, 0x02d0, 0x003fffff);
-        nv_mthd(priv, 0xa097, 0x1220, 0x00000005);
-        nv_mthd(priv, 0xa097, 0x0fdc, 0x00000000);
-        nv_mthd(priv, 0xa097, 0x0f98, 0x00400008);
-        nv_mthd(priv, 0xa097, 0x1284, 0x08000080);
-        nv_mthd(priv, 0xa097, 0x1450, 0x00400008);
-        nv_mthd(priv, 0xa097, 0x1454, 0x08000080);
-        nv_mthd(priv, 0xa097, 0x0214, 0x00000000);
-}
-
-static void
-nve0_grctx_generate_902d(struct nvc0_graph_priv *priv)
-{
-        nv_mthd(priv, 0x902d, 0x0200, 0x000000cf);
-        nv_mthd(priv, 0x902d, 0x0204, 0x00000001);
-        nv_mthd(priv, 0x902d, 0x0208, 0x00000020);
-        nv_mthd(priv, 0x902d, 0x020c, 0x00000001);
-        nv_mthd(priv, 0x902d, 0x0210, 0x00000000);
-        nv_mthd(priv, 0x902d, 0x0214, 0x00000080);
-        nv_mthd(priv, 0x902d, 0x0218, 0x00000100);
-        nv_mthd(priv, 0x902d, 0x021c, 0x00000100);
-        nv_mthd(priv, 0x902d, 0x0220, 0x00000000);
-        nv_mthd(priv, 0x902d, 0x0224, 0x00000000);
-        nv_mthd(priv, 0x902d, 0x0230, 0x000000cf);
-        nv_mthd(priv, 0x902d, 0x0234, 0x00000001);
-        nv_mthd(priv, 0x902d, 0x0238, 0x00000020);
-        nv_mthd(priv, 0x902d, 0x023c, 0x00000001);
-        nv_mthd(priv, 0x902d, 0x0244, 0x00000080);
-        nv_mthd(priv, 0x902d, 0x0248, 0x00000100);
-        nv_mthd(priv, 0x902d, 0x024c, 0x00000100);
-        nv_mthd(priv, 0x902d, 0x3410, 0x00000000);
-}
-
-static void
-nve0_graph_generate_unk40xx(struct nvc0_graph_priv *priv)
-{
-        nv_wr32(priv, 0x404010, 0x0);
-        nv_wr32(priv, 0x404014, 0x0);
-        nv_wr32(priv, 0x404018, 0x0);
-        nv_wr32(priv, 0x40401c, 0x0);
-        nv_wr32(priv, 0x404020, 0x0);
-        nv_wr32(priv, 0x404024, 0xe000);
-        nv_wr32(priv, 0x404028, 0x0);
-        nv_wr32(priv, 0x4040a8, 0x0);
-        nv_wr32(priv, 0x4040ac, 0x0);
-        nv_wr32(priv, 0x4040b0, 0x0);
-        nv_wr32(priv, 0x4040b4, 0x0);
-        nv_wr32(priv, 0x4040b8, 0x0);
-        nv_wr32(priv, 0x4040bc, 0x0);
-        nv_wr32(priv, 0x4040c0, 0x0);
-        nv_wr32(priv, 0x4040c4, 0x0);
-        nv_wr32(priv, 0x4040c8, 0xf800008f);
-        nv_wr32(priv, 0x4040d0, 0x0);
-        nv_wr32(priv, 0x4040d4, 0x0);
-        nv_wr32(priv, 0x4040d8, 0x0);
-        nv_wr32(priv, 0x4040dc, 0x0);
-        nv_wr32(priv, 0x4040e0, 0x0);
-        nv_wr32(priv, 0x4040e4, 0x0);
-        nv_wr32(priv, 0x4040e8, 0x1000);
-        nv_wr32(priv, 0x4040f8, 0x0);
-        nv_wr32(priv, 0x404130, 0x0);
-        nv_wr32(priv, 0x404134, 0x0);
-        nv_wr32(priv, 0x404138, 0x20000040);
-        nv_wr32(priv, 0x404150, 0x2e);
-        nv_wr32(priv, 0x404154, 0x400);
-        nv_wr32(priv, 0x404158, 0x200);
-        nv_wr32(priv, 0x404164, 0x55);
-        nv_wr32(priv, 0x4041a0, 0x0);
-        nv_wr32(priv, 0x4041a4, 0x0);
-        nv_wr32(priv, 0x4041a8, 0x0);
-        nv_wr32(priv, 0x4041ac, 0x0);
-        nv_wr32(priv, 0x404200, 0x0);
-        nv_wr32(priv, 0x404204, 0x0);
-        nv_wr32(priv, 0x404208, 0x0);
-        nv_wr32(priv, 0x40420c, 0x0);
-}
-
-static void
-nve0_graph_generate_unk44xx(struct nvc0_graph_priv *priv)
-{
-        nv_wr32(priv, 0x404404, 0x0);
-        nv_wr32(priv, 0x404408, 0x0);
-        nv_wr32(priv, 0x40440c, 0x0);
-        nv_wr32(priv, 0x404410, 0x0);
-        nv_wr32(priv, 0x404414, 0x0);
-        nv_wr32(priv, 0x404418, 0x0);
-        nv_wr32(priv, 0x40441c, 0x0);
-        nv_wr32(priv, 0x404420, 0x0);
-        nv_wr32(priv, 0x404424, 0x0);
-        nv_wr32(priv, 0x404428, 0x0);
-        nv_wr32(priv, 0x40442c, 0x0);
-        nv_wr32(priv, 0x404430, 0x0);
-        nv_wr32(priv, 0x404434, 0x0);
-        nv_wr32(priv, 0x404438, 0x0);
-        nv_wr32(priv, 0x404460, 0x0);
-        nv_wr32(priv, 0x404464, 0x0);
-        nv_wr32(priv, 0x404468, 0xffffff);
-        nv_wr32(priv, 0x40446c, 0x0);
-        nv_wr32(priv, 0x404480, 0x1);
-        nv_wr32(priv, 0x404498, 0x1);
-}
-
-static void
-nve0_graph_generate_unk46xx(struct nvc0_graph_priv *priv)
-{
-        nv_wr32(priv, 0x404604, 0x14);
-        nv_wr32(priv, 0x404608, 0x0);
-        nv_wr32(priv, 0x40460c, 0x3fff);
-        nv_wr32(priv, 0x404610, 0x100);
-        nv_wr32(priv, 0x404618, 0x0);
-        nv_wr32(priv, 0x40461c, 0x0);
-        nv_wr32(priv, 0x404620, 0x0);
-        nv_wr32(priv, 0x404624, 0x0);
-        nv_wr32(priv, 0x40462c, 0x0);
-        nv_wr32(priv, 0x404630, 0x0);
-        nv_wr32(priv, 0x404640, 0x0);
-        nv_wr32(priv, 0x404654, 0x0);
-        nv_wr32(priv, 0x404660, 0x0);
-        nv_wr32(priv, 0x404678, 0x0);
-        nv_wr32(priv, 0x40467c, 0x2);
-        nv_wr32(priv, 0x404680, 0x0);
-        nv_wr32(priv, 0x404684, 0x0);
-        nv_wr32(priv, 0x404688, 0x0);
-        nv_wr32(priv, 0x40468c, 0x0);
-        nv_wr32(priv, 0x404690, 0x0);
-        nv_wr32(priv, 0x404694, 0x0);
-        nv_wr32(priv, 0x404698, 0x0);
-        nv_wr32(priv, 0x40469c, 0x0);
-        nv_wr32(priv, 0x4046a0, 0x7f0080);
-        nv_wr32(priv, 0x4046a4, 0x0);
-        nv_wr32(priv, 0x4046a8, 0x0);
-        nv_wr32(priv, 0x4046ac, 0x0);
-        nv_wr32(priv, 0x4046b0, 0x0);
-        nv_wr32(priv, 0x4046b4, 0x0);
-        nv_wr32(priv, 0x4046b8, 0x0);
-        nv_wr32(priv, 0x4046bc, 0x0);
-        nv_wr32(priv, 0x4046c0, 0x0);
-        nv_wr32(priv, 0x4046c8, 0x0);
-        nv_wr32(priv, 0x4046cc, 0x0);
-        nv_wr32(priv, 0x4046d0, 0x0);
-}
-
-static void
-nve0_graph_generate_unk47xx(struct nvc0_graph_priv *priv)
-{
-        nv_wr32(priv, 0x404700, 0x0);
-        nv_wr32(priv, 0x404704, 0x0);
-        nv_wr32(priv, 0x404708, 0x0);
-        nv_wr32(priv, 0x404718, 0x0);
-        nv_wr32(priv, 0x40471c, 0x0);
-        nv_wr32(priv, 0x404720, 0x0);
-        nv_wr32(priv, 0x404724, 0x0);
-        nv_wr32(priv, 0x404728, 0x0);
-        nv_wr32(priv, 0x40472c, 0x0);
-        nv_wr32(priv, 0x404730, 0x0);
-        nv_wr32(priv, 0x404734, 0x100);
-        nv_wr32(priv, 0x404738, 0x0);
-        nv_wr32(priv, 0x40473c, 0x0);
-        nv_wr32(priv, 0x404744, 0x0);
-        nv_wr32(priv, 0x404748, 0x0);
-        nv_wr32(priv, 0x404754, 0x0);
-}
-
-static void
-nve0_graph_generate_unk58xx(struct nvc0_graph_priv *priv)
-{
-        nv_wr32(priv, 0x405800, 0xf8000bf);
-        nv_wr32(priv, 0x405830, 0x2180648);
-        nv_wr32(priv, 0x405834, 0x8000000);
-        nv_wr32(priv, 0x405838, 0x0);
-        nv_wr32(priv, 0x405854, 0x0);
-        nv_wr32(priv, 0x405870, 0x1);
-        nv_wr32(priv, 0x405874, 0x1);
-        nv_wr32(priv, 0x405878, 0x1);
-        nv_wr32(priv, 0x40587c, 0x1);
-        nv_wr32(priv, 0x405a00, 0x0);
-        nv_wr32(priv, 0x405a04, 0x0);
-        nv_wr32(priv, 0x405a18, 0x0);
-        nv_wr32(priv, 0x405b00, 0x0);
-        nv_wr32(priv, 0x405b10, 0x1000);
-}
-
-static void
-nve0_graph_generate_unk60xx(struct nvc0_graph_priv *priv)
-{
-        nv_wr32(priv, 0x406020, 0x4103c1);
-        nv_wr32(priv, 0x406028, 0x1);
-        nv_wr32(priv, 0x40602c, 0x1);
-        nv_wr32(priv, 0x406030, 0x1);
-        nv_wr32(priv, 0x406034, 0x1);
-}
-
-static void
-nve0_graph_generate_unk64xx(struct nvc0_graph_priv *priv)
-{
-        nv_wr32(priv, 0x4064a8, 0x0);
-        nv_wr32(priv, 0x4064ac, 0x3fff);
-        nv_wr32(priv, 0x4064b4, 0x0);
-        nv_wr32(priv, 0x4064b8, 0x0);
-        nv_wr32(priv, 0x4064c0, 0x801a00f0);
-        nv_wr32(priv, 0x4064c4, 0x192ffff);
-        nv_wr32(priv, 0x4064c8, 0x1800600);
-        nv_wr32(priv, 0x4064cc, 0x0);
-        nv_wr32(priv, 0x4064d0, 0x0);
-        nv_wr32(priv, 0x4064d4, 0x0);
-        nv_wr32(priv, 0x4064d8, 0x0);
-        nv_wr32(priv, 0x4064dc, 0x0);
-        nv_wr32(priv, 0x4064e0, 0x0);
-        nv_wr32(priv, 0x4064e4, 0x0);
-        nv_wr32(priv, 0x4064e8, 0x0);
-        nv_wr32(priv, 0x4064ec, 0x0);
-        nv_wr32(priv, 0x4064fc, 0x22a);
-}
-
-static void
-nve0_graph_generate_unk70xx(struct nvc0_graph_priv *priv)
-{
-        nv_wr32(priv, 0x407040, 0x0);
-}
-
-static void
-nve0_graph_generate_unk78xx(struct nvc0_graph_priv *priv)
-{
-        nv_wr32(priv, 0x407804, 0x23);
-        nv_wr32(priv, 0x40780c, 0xa418820);
-        nv_wr32(priv, 0x407810, 0x62080e6);
-        nv_wr32(priv, 0x407814, 0x20398a4);
-        nv_wr32(priv, 0x407818, 0xe629062);
-        nv_wr32(priv, 0x40781c, 0xa418820);
-        nv_wr32(priv, 0x407820, 0xe6);
-        nv_wr32(priv, 0x4078bc, 0x103);
-}
-
-static void
-nve0_graph_generate_unk80xx(struct nvc0_graph_priv *priv)
-{
-        nv_wr32(priv, 0x408000, 0x0);
-        nv_wr32(priv, 0x408004, 0x0);
-        nv_wr32(priv, 0x408008, 0x30);
-        nv_wr32(priv, 0x40800c, 0x0);
-        nv_wr32(priv, 0x408010, 0x0);
-        nv_wr32(priv, 0x408014, 0x69);
-        nv_wr32(priv, 0x408018, 0xe100e100);
-        nv_wr32(priv, 0x408064, 0x0);
-}
-
-static void
-nve0_graph_generate_unk88xx(struct nvc0_graph_priv *priv)
-{
-        nv_wr32(priv, 0x408800, 0x2802a3c);
-        nv_wr32(priv, 0x408804, 0x40);
-        nv_wr32(priv, 0x408808, 0x1043e005);
-        nv_wr32(priv, 0x408840, 0xb);
-        nv_wr32(priv, 0x408900, 0x3080b801);
-        nv_wr32(priv, 0x408904, 0x62000001);
-        nv_wr32(priv, 0x408908, 0xc8102f);
-        nv_wr32(priv, 0x408980, 0x11d);
-}
-
-static void
-nve0_graph_generate_gpc(struct nvc0_graph_priv *priv)
-{
-        nv_wr32(priv, 0x418380, 0x16);
-        nv_wr32(priv, 0x418400, 0x38004e00);
-        nv_wr32(priv, 0x418404, 0x71e0ffff);
-        nv_wr32(priv, 0x41840c, 0x1008);
-        nv_wr32(priv, 0x418410, 0xfff0fff);
-        nv_wr32(priv, 0x418414, 0x2200fff);
-        nv_wr32(priv, 0x418450, 0x0);
-        nv_wr32(priv, 0x418454, 0x0);
-        nv_wr32(priv, 0x418458, 0x0);
-        nv_wr32(priv, 0x41845c, 0x0);
-        nv_wr32(priv, 0x418460, 0x0);
-        nv_wr32(priv, 0x418464, 0x0);
-        nv_wr32(priv, 0x418468, 0x1);
-        nv_wr32(priv, 0x41846c, 0x0);
-        nv_wr32(priv, 0x418470, 0x0);
-        nv_wr32(priv, 0x418600, 0x1f);
-        nv_wr32(priv, 0x418684, 0xf);
-        nv_wr32(priv, 0x418700, 0x2);
-        nv_wr32(priv, 0x418704, 0x80);
-        nv_wr32(priv, 0x418708, 0x0);
-        nv_wr32(priv, 0x41870c, 0x0);
-        nv_wr32(priv, 0x418710, 0x0);
-        nv_wr32(priv, 0x418800, 0x7006860a);
-        nv_wr32(priv, 0x418808, 0x0);
-        nv_wr32(priv, 0x41880c, 0x0);
-        nv_wr32(priv, 0x418810, 0x0);
-        nv_wr32(priv, 0x418828, 0x44);
-        nv_wr32(priv, 0x418830, 0x10000001);
-        nv_wr32(priv, 0x4188d8, 0x8);
-        nv_wr32(priv, 0x4188e0, 0x1000000);
-        nv_wr32(priv, 0x4188e8, 0x0);
-        nv_wr32(priv, 0x4188ec, 0x0);
-        nv_wr32(priv, 0x4188f0, 0x0);
-        nv_wr32(priv, 0x4188f4, 0x0);
-        nv_wr32(priv, 0x4188f8, 0x0);
-        nv_wr32(priv, 0x4188fc, 0x20100018);
-        nv_wr32(priv, 0x41891c, 0xff00ff);
-        nv_wr32(priv, 0x418924, 0x0);
-        nv_wr32(priv, 0x418928, 0xffff00);
-        nv_wr32(priv, 0x41892c, 0xff00);
-        nv_wr32(priv, 0x418a00, 0x0);
-        nv_wr32(priv, 0x418a04, 0x0);
-        nv_wr32(priv, 0x418a08, 0x0);
-        nv_wr32(priv, 0x418a0c, 0x10000);
-        nv_wr32(priv, 0x418a10, 0x0);
-        nv_wr32(priv, 0x418a14, 0x0);
-        nv_wr32(priv, 0x418a18, 0x0);
-        nv_wr32(priv, 0x418a20, 0x0);
-        nv_wr32(priv, 0x418a24, 0x0);
-        nv_wr32(priv, 0x418a28, 0x0);
-        nv_wr32(priv, 0x418a2c, 0x10000);
-        nv_wr32(priv, 0x418a30, 0x0);
-        nv_wr32(priv, 0x418a34, 0x0);
-        nv_wr32(priv, 0x418a38, 0x0);
-        nv_wr32(priv, 0x418a40, 0x0);
-        nv_wr32(priv, 0x418a44, 0x0);
-        nv_wr32(priv, 0x418a48, 0x0);
-        nv_wr32(priv, 0x418a4c, 0x10000);
-        nv_wr32(priv, 0x418a50, 0x0);
-        nv_wr32(priv, 0x418a54, 0x0);
-        nv_wr32(priv, 0x418a58, 0x0);
-        nv_wr32(priv, 0x418a60, 0x0);
-        nv_wr32(priv, 0x418a64, 0x0);
-        nv_wr32(priv, 0x418a68, 0x0);
-        nv_wr32(priv, 0x418a6c, 0x10000);
-        nv_wr32(priv, 0x418a70, 0x0);
-        nv_wr32(priv, 0x418a74, 0x0);
-        nv_wr32(priv, 0x418a78, 0x0);
-        nv_wr32(priv, 0x418a80, 0x0);
-        nv_wr32(priv, 0x418a84, 0x0);
-        nv_wr32(priv, 0x418a88, 0x0);
-        nv_wr32(priv, 0x418a8c, 0x10000);
-        nv_wr32(priv, 0x418a90, 0x0);
-        nv_wr32(priv, 0x418a94, 0x0);
-        nv_wr32(priv, 0x418a98, 0x0);
-        nv_wr32(priv, 0x418aa0, 0x0);
-        nv_wr32(priv, 0x418aa4, 0x0);
-        nv_wr32(priv, 0x418aa8, 0x0);
-        nv_wr32(priv, 0x418aac, 0x10000);
-        nv_wr32(priv, 0x418ab0, 0x0);
-        nv_wr32(priv, 0x418ab4, 0x0);
-        nv_wr32(priv, 0x418ab8, 0x0);
-        nv_wr32(priv, 0x418ac0, 0x0);
-        nv_wr32(priv, 0x418ac4, 0x0);
-        nv_wr32(priv, 0x418ac8, 0x0);
-        nv_wr32(priv, 0x418acc, 0x10000);
-        nv_wr32(priv, 0x418ad0, 0x0);
-        nv_wr32(priv, 0x418ad4, 0x0);
-        nv_wr32(priv, 0x418ad8, 0x0);
-        nv_wr32(priv, 0x418ae0, 0x0);
-        nv_wr32(priv, 0x418ae4, 0x0);
-        nv_wr32(priv, 0x418ae8, 0x0);
-        nv_wr32(priv, 0x418aec, 0x10000);
-        nv_wr32(priv, 0x418af0, 0x0);
-        nv_wr32(priv, 0x418af4, 0x0);
-        nv_wr32(priv, 0x418af8, 0x0);
-        nv_wr32(priv, 0x418b00, 0x6);
-        nv_wr32(priv, 0x418b08, 0xa418820);
-        nv_wr32(priv, 0x418b0c, 0x62080e6);
-        nv_wr32(priv, 0x418b10, 0x20398a4);
-        nv_wr32(priv, 0x418b14, 0xe629062);
-        nv_wr32(priv, 0x418b18, 0xa418820);
-        nv_wr32(priv, 0x418b1c, 0xe6);
-        nv_wr32(priv, 0x418bb8, 0x103);
-        nv_wr32(priv, 0x418c08, 0x1);
-        nv_wr32(priv, 0x418c10, 0x0);
-        nv_wr32(priv, 0x418c14, 0x0);
-        nv_wr32(priv, 0x418c18, 0x0);
-        nv_wr32(priv, 0x418c1c, 0x0);
-        nv_wr32(priv, 0x418c20, 0x0);
-        nv_wr32(priv, 0x418c24, 0x0);
-        nv_wr32(priv, 0x418c28, 0x0);
-        nv_wr32(priv, 0x418c2c, 0x0);
-        nv_wr32(priv, 0x418c40, 0xffffffff);
-        nv_wr32(priv, 0x418c6c, 0x1);
-        nv_wr32(priv, 0x418c80, 0x20200004);
-        nv_wr32(priv, 0x418c8c, 0x1);
-        nv_wr32(priv, 0x419000, 0x780);
-        nv_wr32(priv, 0x419004, 0x0);
-        nv_wr32(priv, 0x419008, 0x0);
-        nv_wr32(priv, 0x419014, 0x4);
-}
-
-static void
-nve0_graph_generate_tpc(struct nvc0_graph_priv *priv)
-{
-        nv_wr32(priv, 0x419848, 0x0);
-        nv_wr32(priv, 0x419864, 0x129);
-        nv_wr32(priv, 0x419888, 0x0);
-        nv_wr32(priv, 0x419a00, 0xf0);
-        nv_wr32(priv, 0x419a04, 0x1);
-        nv_wr32(priv, 0x419a08, 0x21);
-        nv_wr32(priv, 0x419a0c, 0x20000);
-        nv_wr32(priv, 0x419a10, 0x0);
-        nv_wr32(priv, 0x419a14, 0x200);
-        nv_wr32(priv, 0x419a1c, 0xc000);
-        nv_wr32(priv, 0x419a20, 0x800);
-        nv_wr32(priv, 0x419a30, 0x1);
-        nv_wr32(priv, 0x419ac4, 0x37f440);
-        nv_wr32(priv, 0x419c00, 0xa);
-        nv_wr32(priv, 0x419c04, 0x80000006);
-        nv_wr32(priv, 0x419c08, 0x2);
-        nv_wr32(priv, 0x419c20, 0x0);
-        nv_wr32(priv, 0x419c24, 0x84210);
-        nv_wr32(priv, 0x419c28, 0x3efbefbe);
-        nv_wr32(priv, 0x419ce8, 0x0);
-        nv_wr32(priv, 0x419cf4, 0x3203);
-        nv_wr32(priv, 0x419e04, 0x0);
-        nv_wr32(priv, 0x419e08, 0x0);
-        nv_wr32(priv, 0x419e0c, 0x0);
-        nv_wr32(priv, 0x419e10, 0x402);
-        nv_wr32(priv, 0x419e44, 0x13eff2);
-        nv_wr32(priv, 0x419e48, 0x0);
-        nv_wr32(priv, 0x419e4c, 0x7f);
-        nv_wr32(priv, 0x419e50, 0x0);
-        nv_wr32(priv, 0x419e54, 0x0);
-        nv_wr32(priv, 0x419e58, 0x0);
-        nv_wr32(priv, 0x419e5c, 0x0);
-        nv_wr32(priv, 0x419e60, 0x0);
-        nv_wr32(priv, 0x419e64, 0x0);
-        nv_wr32(priv, 0x419e68, 0x0);
-        nv_wr32(priv, 0x419e6c, 0x0);
-        nv_wr32(priv, 0x419e70, 0x0);
-        nv_wr32(priv, 0x419e74, 0x0);
-        nv_wr32(priv, 0x419e78, 0x0);
-        nv_wr32(priv, 0x419e7c, 0x0);
-        nv_wr32(priv, 0x419e80, 0x0);
-        nv_wr32(priv, 0x419e84, 0x0);
-        nv_wr32(priv, 0x419e88, 0x0);
-        nv_wr32(priv, 0x419e8c, 0x0);
-        nv_wr32(priv, 0x419e90, 0x0);
-        nv_wr32(priv, 0x419e94, 0x0);
-        nv_wr32(priv, 0x419e98, 0x0);
-        nv_wr32(priv, 0x419eac, 0x1fcf);
-        nv_wr32(priv, 0x419eb0, 0xd3f);
-        nv_wr32(priv, 0x419ec8, 0x1304f);
-        nv_wr32(priv, 0x419f30, 0x0);
-        nv_wr32(priv, 0x419f34, 0x0);
-        nv_wr32(priv, 0x419f38, 0x0);
-        nv_wr32(priv, 0x419f3c, 0x0);
-        nv_wr32(priv, 0x419f40, 0x0);
-        nv_wr32(priv, 0x419f44, 0x0);
-        nv_wr32(priv, 0x419f48, 0x0);
-        nv_wr32(priv, 0x419f4c, 0x0);
-        nv_wr32(priv, 0x419f58, 0x0);
-        nv_wr32(priv, 0x419f78, 0xb);
-}
-
-static void
-nve0_graph_generate_tpcunk(struct nvc0_graph_priv *priv)
-{
-        nv_wr32(priv, 0x41be24, 0x6);
-        nv_wr32(priv, 0x41bec0, 0x12180000);
-        nv_wr32(priv, 0x41bec4, 0x37f7f);
-        nv_wr32(priv, 0x41bee4, 0x6480430);
-        nv_wr32(priv, 0x41bf00, 0xa418820);
-        nv_wr32(priv, 0x41bf04, 0x62080e6);
-        nv_wr32(priv, 0x41bf08, 0x20398a4);
-        nv_wr32(priv, 0x41bf0c, 0xe629062);
-        nv_wr32(priv, 0x41bf10, 0xa418820);
-        nv_wr32(priv, 0x41bf14, 0xe6);
-        nv_wr32(priv, 0x41bfd0, 0x900103);
-        nv_wr32(priv, 0x41bfe0, 0x400001);
-        nv_wr32(priv, 0x41bfe4, 0x0);
-}
-
-int
-nve0_grctx_generate(struct nvc0_graph_priv *priv)
-{
-        struct nvc0_grctx info;
-        int ret, i, gpc, tpc, id;
-        u32 data[6] = {}, data2[2] = {}, tmp;
-        u32 tpc_set = 0, tpc_mask = 0;
-        u32 magic[GPC_MAX][2], offset;
-        u8 tpcnr[GPC_MAX], a, b;
-        u8 shift, ntpcv;
-
-        ret = nvc0_grctx_init(priv, &info);
-        if (ret)
-                return ret;
-
-        nv_mask(priv, 0x000260, 0x00000001, 0x00000000);
-        nv_wr32(priv, 0x400204, 0x00000000);
-        nv_wr32(priv, 0x400208, 0x00000000);
-
-        nve0_graph_generate_unk40xx(priv);
-        nve0_graph_generate_unk44xx(priv);
-        nve0_graph_generate_unk46xx(priv);
-        nve0_graph_generate_unk47xx(priv);
-        nve0_graph_generate_unk58xx(priv);
-        nve0_graph_generate_unk60xx(priv);
-        nve0_graph_generate_unk64xx(priv);
-        nve0_graph_generate_unk70xx(priv);
-        nve0_graph_generate_unk78xx(priv);
-        nve0_graph_generate_unk80xx(priv);
-        nve0_graph_generate_unk88xx(priv);
-        nve0_graph_generate_gpc(priv);
-        nve0_graph_generate_tpc(priv);
-        nve0_graph_generate_tpcunk(priv);
-
-        nv_wr32(priv, 0x404154, 0x0);
-
-        mmio_data(0x003000, 0x0100, NV_MEM_ACCESS_RW | NV_MEM_ACCESS_SYS);
-        mmio_data(0x008000, 0x0100, NV_MEM_ACCESS_RW | NV_MEM_ACCESS_SYS);
-        mmio_data(0x060000, 0x1000, NV_MEM_ACCESS_RW);
-        mmio_list(0x40800c, 0x00000000,  8, 1);
-        mmio_list(0x408010, 0x80000000,  0, 0);
-        mmio_list(0x419004, 0x00000000,  8, 1);
-        mmio_list(0x419008, 0x00000000,  0, 0);
-        mmio_list(0x4064cc, 0x80000000,  0, 0);
-        mmio_list(0x408004, 0x00000000,  8, 0);
-        mmio_list(0x408008, 0x80000030,  0, 0);
-        mmio_list(0x418808, 0x00000000,  8, 0);
-        mmio_list(0x41880c, 0x80000030,  0, 0);
-        mmio_list(0x4064c8, 0x01800600,  0, 0);
-        mmio_list(0x418810, 0x80000000, 12, 2);
-        mmio_list(0x419848, 0x10000000, 12, 2);
-        mmio_list(0x405830, 0x02180648,  0, 0);
-        mmio_list(0x4064c4, 0x0192ffff,  0, 0);
-        for (gpc = 0, offset = 0; gpc < priv->gpc_nr; gpc++) {
-                u16 magic0 = 0x0218 * priv->tpc_nr[gpc];
-                u16 magic1 = 0x0648 * priv->tpc_nr[gpc];
-                magic[gpc][0]  = 0x10000000 | (magic0 << 16) | offset;
-                magic[gpc][1]  = 0x00000000 | (magic1 << 16);
-                offset += 0x0324 * priv->tpc_nr[gpc];
-        }
-        for (gpc = 0; gpc < priv->gpc_nr; gpc++) {
-                mmio_list(GPC_UNIT(gpc, 0x30c0), magic[gpc][0], 0, 0);
-                mmio_list(GPC_UNIT(gpc, 0x30e4), magic[gpc][1] | offset, 0, 0);
-                offset += 0x07ff * priv->tpc_nr[gpc];
-        }
-        mmio_list(0x17e91c, 0x06060609, 0, 0);
-        mmio_list(0x17e920, 0x00090a05, 0, 0);
-
-        nv_wr32(priv, 0x418c6c, 0x1);
-        nv_wr32(priv, 0x41980c, 0x10);
-        nv_wr32(priv, 0x41be08, 0x4);
-        nv_wr32(priv, 0x4064c0, 0x801a00f0);
-        nv_wr32(priv, 0x405800, 0xf8000bf);
-        nv_wr32(priv, 0x419c00, 0xa);
-
-        for (tpc = 0, id = 0; tpc < 4; tpc++) {
-                for (gpc = 0; gpc < priv->gpc_nr; gpc++) {
-                        if (tpc < priv->tpc_nr[gpc]) {
-                                nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x0698), id);
-                                nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x04e8), id);
-                                nv_wr32(priv, GPC_UNIT(gpc, 0x0c10 + tpc * 4), id);
-                                nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x0088), id++);
-                        }
-
-                        nv_wr32(priv, GPC_UNIT(gpc, 0x0c08), priv->tpc_nr[gpc]);
-                        nv_wr32(priv, GPC_UNIT(gpc, 0x0c8c), priv->tpc_nr[gpc]);
-                }
-        }
-
-        tmp = 0;
-        for (i = 0; i < priv->gpc_nr; i++)
-                tmp |= priv->tpc_nr[i] << (i * 4);
-        nv_wr32(priv, 0x406028, tmp);
-        nv_wr32(priv, 0x405870, tmp);
-
-        nv_wr32(priv, 0x40602c, 0x0);
-        nv_wr32(priv, 0x405874, 0x0);
-        nv_wr32(priv, 0x406030, 0x0);
-        nv_wr32(priv, 0x405878, 0x0);
-        nv_wr32(priv, 0x406034, 0x0);
-        nv_wr32(priv, 0x40587c, 0x0);
-
-        /* calculate first set of magics */
-        memcpy(tpcnr, priv->tpc_nr, sizeof(priv->tpc_nr));
-
-        gpc = -1;
-        for (tpc = 0; tpc < priv->tpc_total; tpc++) {
-                do {
-                        gpc = (gpc + 1) % priv->gpc_nr;
-                } while (!tpcnr[gpc]);
-                tpcnr[gpc]--;
-
-                data[tpc / 6] |= gpc << ((tpc % 6) * 5);
-        }
-
-        for (; tpc < 32; tpc++)
-                data[tpc / 6] |= 7 << ((tpc % 6) * 5);
-
-        /* and the second... */
-        shift = 0;
-        ntpcv = priv->tpc_total;
-        while (!(ntpcv & (1 << 4))) {
-                ntpcv <<= 1;
-                shift++;
-        }
-
-        data2[0]  = ntpcv << 16;
-        data2[0] |= shift << 21;
-        data2[0] |= (((1 << (0 + 5)) % ntpcv) << 24);
-        data2[0] |= priv->tpc_total << 8;
-        data2[0] |= priv->magic_not_rop_nr;
-        for (i = 1; i < 7; i++)
-                data2[1] |= ((1 << (i + 5)) % ntpcv) << ((i - 1) * 5);
-
-        /* and write it all the various parts of PGRAPH */
-        nv_wr32(priv, 0x418bb8, (priv->tpc_total << 8) | priv->magic_not_rop_nr);
-        for (i = 0; i < 6; i++)
-                nv_wr32(priv, 0x418b08 + (i * 4), data[i]);
-
-        nv_wr32(priv, 0x41bfd0, data2[0]);
-        nv_wr32(priv, 0x41bfe4, data2[1]);
-        for (i = 0; i < 6; i++)
-                nv_wr32(priv, 0x41bf00 + (i * 4), data[i]);
-
-        nv_wr32(priv, 0x4078bc, (priv->tpc_total << 8) | priv->magic_not_rop_nr);
-        for (i = 0; i < 6; i++)
-                nv_wr32(priv, 0x40780c + (i * 4), data[i]);
-
-
-        memcpy(tpcnr, priv->tpc_nr, sizeof(priv->tpc_nr));
-        for (gpc = 0; gpc < priv->gpc_nr; gpc++)
-                tpc_mask |= ((1 << priv->tpc_nr[gpc]) - 1) << (gpc * 8);
-
-        for (i = 0, gpc = -1, b = -1; i < 32; i++) {
-                a = (i * (priv->tpc_total - 1)) / 32;
-                if (a != b) {
-                        b = a;
-                        do {
-                                gpc = (gpc + 1) % priv->gpc_nr;
-                        } while (!tpcnr[gpc]);
-                        tpc = priv->tpc_nr[gpc] - tpcnr[gpc]--;
-
-                        tpc_set |= 1 << ((gpc * 8) + tpc);
-                }
-
-                nv_wr32(priv, 0x406800 + (i * 0x20), tpc_set);
-                nv_wr32(priv, 0x406c00 + (i * 0x20), tpc_set ^ tpc_mask);
-        }
-
-        for (i = 0; i < 8; i++)
-                nv_wr32(priv, 0x4064d0 + (i * 0x04), 0x00000000);
-
-        nv_wr32(priv, 0x405b00, (priv->tpc_total << 8) | priv->gpc_nr);
-        if (priv->gpc_nr == 1) {
-                nv_mask(priv, 0x408850, 0x0000000f, priv->tpc_nr[0]);
-                nv_mask(priv, 0x408958, 0x0000000f, priv->tpc_nr[0]);
-        } else {
-                nv_mask(priv, 0x408850, 0x0000000f, priv->gpc_nr);
-                nv_mask(priv, 0x408958, 0x0000000f, priv->gpc_nr);
-        }
-        nv_mask(priv, 0x419f78, 0x00000001, 0x00000000);
-
-        nve0_grctx_generate_icmd(priv);
-        nve0_grctx_generate_a097(priv);
-        nve0_grctx_generate_902d(priv);
-
-        nv_mask(priv, 0x000260, 0x00000001, 0x00000001);
-        nv_wr32(priv, 0x418800, 0x7026860a); //XXX
-        nv_wr32(priv, 0x41be10, 0x00bb8bc7); //XXX
-        return nvc0_grctx_fini(&info);
-}
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/ctxnve4.c b/drivers/gpu/drm/nouveau/core/engine/graph/ctxnve4.c
new file mode 100644
index 000000000000..e2de73ee5eee
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/core/engine/graph/ctxnve4.c
@@ -0,0 +1,1018 @@
+/*
+ * Copyright 2013 Red Hat Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Ben Skeggs <bskeggs@redhat.com>
+ */
+
+#include "nvc0.h"
+
+struct nvc0_graph_init
+nve4_grctx_init_icmd[] = {
+        { 0x001000,   1, 0x01, 0x00000004 },
+        { 0x000039,   3, 0x01, 0x00000000 },
+        { 0x0000a9,   1, 0x01, 0x0000ffff },
+        { 0x000038,   1, 0x01, 0x0fac6881 },
+        { 0x00003d,   1, 0x01, 0x00000001 },
+        { 0x0000e8,   8, 0x01, 0x00000400 },
+        { 0x000078,   8, 0x01, 0x00000300 },
+        { 0x000050,   1, 0x01, 0x00000011 },
+        { 0x000058,   8, 0x01, 0x00000008 },
+        { 0x000208,   8, 0x01, 0x00000001 },
+        { 0x000081,   1, 0x01, 0x00000001 },
+        { 0x000085,   1, 0x01, 0x00000004 },
+        { 0x000088,   1, 0x01, 0x00000400 },
+        { 0x000090,   1, 0x01, 0x00000300 },
+        { 0x000098,   1, 0x01, 0x00001001 },
+        { 0x0000e3,   1, 0x01, 0x00000001 },
+        { 0x0000da,   1, 0x01, 0x00000001 },
+        { 0x0000f8,   1, 0x01, 0x00000003 },
+        { 0x0000fa,   1, 0x01, 0x00000001 },
+        { 0x00009f,   4, 0x01, 0x0000ffff },
+        { 0x0000b1,   1, 0x01, 0x00000001 },
+        { 0x0000ad,   1, 0x01, 0x0000013e },
+        { 0x0000e1,   1, 0x01, 0x00000010 },
+        { 0x000290,  16, 0x01, 0x00000000 },
+        { 0x0003b0,  16, 0x01, 0x00000000 },
+        { 0x0002a0,  16, 0x01, 0x00000000 },
+        { 0x000420,  16, 0x01, 0x00000000 },
+        { 0x0002b0,  16, 0x01, 0x00000000 },
+        { 0x000430,  16, 0x01, 0x00000000 },
+        { 0x0002c0,  16, 0x01, 0x00000000 },
+        { 0x0004d0,  16, 0x01, 0x00000000 },
+        { 0x000720,  16, 0x01, 0x00000000 },
+        { 0x0008c0,  16, 0x01, 0x00000000 },
+        { 0x000890,  16, 0x01, 0x00000000 },
+        { 0x0008e0,  16, 0x01, 0x00000000 },
+        { 0x0008a0,  16, 0x01, 0x00000000 },
+        { 0x0008f0,  16, 0x01, 0x00000000 },
+        { 0x00094c,   1, 0x01, 0x000000ff },
+        { 0x00094d,   1, 0x01, 0xffffffff },
+        { 0x00094e,   1, 0x01, 0x00000002 },
+        { 0x0002ec,   1, 0x01, 0x00000001 },
+        { 0x000303,   1, 0x01, 0x00000001 },
+        { 0x0002e6,   1, 0x01, 0x00000001 },
+        { 0x000466,   1, 0x01, 0x00000052 },
+        { 0x000301,   1, 0x01, 0x3f800000 },
+        { 0x000304,   1, 0x01, 0x30201000 },
+        { 0x000305,   1, 0x01, 0x70605040 },
+        { 0x000306,   1, 0x01, 0xb8a89888 },
+        { 0x000307,   1, 0x01, 0xf8e8d8c8 },
+        { 0x00030a,   1, 0x01, 0x00ffff00 },
+        { 0x00030b,   1, 0x01, 0x0000001a },
+        { 0x00030c,   1, 0x01, 0x00000001 },
+        { 0x000318,   1, 0x01, 0x00000001 },
+        { 0x000340,   1, 0x01, 0x00000000 },
+        { 0x000375,   1, 0x01, 0x00000001 },
+        { 0x00037d,   1, 0x01, 0x00000006 },
+        { 0x0003a0,   1, 0x01, 0x00000002 },
+        { 0x0003aa,   1, 0x01, 0x00000001 },
+        { 0x0003a9,   1, 0x01, 0x00000001 },
+        { 0x000380,   1, 0x01, 0x00000001 },
+        { 0x000383,   1, 0x01, 0x00000011 },
+        { 0x000360,   1, 0x01, 0x00000040 },
+        { 0x000366,   2, 0x01, 0x00000000 },
+        { 0x000368,   1, 0x01, 0x00000fff },
+        { 0x000370,   2, 0x01, 0x00000000 },
+        { 0x000372,   1, 0x01, 0x000fffff },
+        { 0x00037a,   1, 0x01, 0x00000012 },
+        { 0x000619,   1, 0x01, 0x00000003 },
+        { 0x000811,   1, 0x01, 0x00000003 },
+        { 0x000812,   1, 0x01, 0x00000004 },
+        { 0x000813,   1, 0x01, 0x00000006 },
+        { 0x000814,   1, 0x01, 0x00000008 },
+        { 0x000815,   1, 0x01, 0x0000000b },
+        { 0x000800,   6, 0x01, 0x00000001 },
+        { 0x000632,   1, 0x01, 0x00000001 },
+        { 0x000633,   1, 0x01, 0x00000002 },
+        { 0x000634,   1, 0x01, 0x00000003 },
+        { 0x000635,   1, 0x01, 0x00000004 },
+        { 0x000654,   1, 0x01, 0x3f800000 },
+        { 0x000657,   1, 0x01, 0x3f800000 },
+        { 0x000655,   2, 0x01, 0x3f800000 },
+        { 0x0006cd,   1, 0x01, 0x3f800000 },
+        { 0x0007f5,   1, 0x01, 0x3f800000 },
+        { 0x0007dc,   1, 0x01, 0x39291909 },
+        { 0x0007dd,   1, 0x01, 0x79695949 },
+        { 0x0007de,   1, 0x01, 0xb9a99989 },
+        { 0x0007df,   1, 0x01, 0xf9e9d9c9 },
+        { 0x0007e8,   1, 0x01, 0x00003210 },
+        { 0x0007e9,   1, 0x01, 0x00007654 },
+        { 0x0007ea,   1, 0x01, 0x00000098 },
+        { 0x0007ec,   1, 0x01, 0x39291909 },
+        { 0x0007ed,   1, 0x01, 0x79695949 },
+        { 0x0007ee,   1, 0x01, 0xb9a99989 },
+        { 0x0007ef,   1, 0x01, 0xf9e9d9c9 },
+        { 0x0007f0,   1, 0x01, 0x00003210 },
+        { 0x0007f1,   1, 0x01, 0x00007654 },
+        { 0x0007f2,   1, 0x01, 0x00000098 },
+        { 0x0005a5,   1, 0x01, 0x00000001 },
+        { 0x000980, 128, 0x01, 0x00000000 },
+        { 0x000468,   1, 0x01, 0x00000004 },
+        { 0x00046c,   1, 0x01, 0x00000001 },
+        { 0x000470,  96, 0x01, 0x00000000 },
+        { 0x000510,  16, 0x01, 0x3f800000 },
+        { 0x000520,   1, 0x01, 0x000002b6 },
+        { 0x000529,   1, 0x01, 0x00000001 },
+        { 0x000530,  16, 0x01, 0xffff0000 },
+        { 0x000585,   1, 0x01, 0x0000003f },
+        { 0x000576,   1, 0x01, 0x00000003 },
+        { 0x00057b,   1, 0x01, 0x00000059 },
+        { 0x000586,   1, 0x01, 0x00000040 },
+        { 0x000582,   2, 0x01, 0x00000080 },
+        { 0x0005c2,   1, 0x01, 0x00000001 },
+        { 0x000638,   1, 0x01, 0x00000001 },
+        { 0x000639,   1, 0x01, 0x00000001 },
+        { 0x00063a,   1, 0x01, 0x00000002 },
+        { 0x00063b,   2, 0x01, 0x00000001 },
+        { 0x00063d,   1, 0x01, 0x00000002 },
+        { 0x00063e,   1, 0x01, 0x00000001 },
+        { 0x0008b8,   8, 0x01, 0x00000001 },
+        { 0x000900,   8, 0x01, 0x00000001 },
+        { 0x000908,   8, 0x01, 0x00000002 },
+        { 0x000910,  16, 0x01, 0x00000001 },
+        { 0x000920,   8, 0x01, 0x00000002 },
+        { 0x000928,   8, 0x01, 0x00000001 },
+        { 0x000648,   9, 0x01, 0x00000001 },
+        { 0x000658,   1, 0x01, 0x0000000f },
+        { 0x0007ff,   1, 0x01, 0x0000000a },
+        { 0x00066a,   1, 0x01, 0x40000000 },
+        { 0x00066b,   1, 0x01, 0x10000000 },
+        { 0x00066c,   2, 0x01, 0xffff0000 },
+        { 0x0007af,   2, 0x01, 0x00000008 },
+        { 0x0007f6,   1, 0x01, 0x00000001 },
+        { 0x0006b2,   1, 0x01, 0x00000055 },
+        { 0x0007ad,   1, 0x01, 0x00000003 },
+        { 0x000937,   1, 0x01, 0x00000001 },
+        { 0x000971,   1, 0x01, 0x00000008 },
+        { 0x000972,   1, 0x01, 0x00000040 },
+        { 0x000973,   1, 0x01, 0x0000012c },
+        { 0x00097c,   1, 0x01, 0x00000040 },
+        { 0x000979,   1, 0x01, 0x00000003 },
+        { 0x000975,   1, 0x01, 0x00000020 },
+        { 0x000976,   1, 0x01, 0x00000001 },
+        { 0x000977,   1, 0x01, 0x00000020 },
+        { 0x000978,   1, 0x01, 0x00000001 },
+        { 0x000957,   1, 0x01, 0x00000003 },
+        { 0x00095e,   1, 0x01, 0x20164010 },
+        { 0x00095f,   1, 0x01, 0x00000020 },
+        { 0x00097d,   1, 0x01, 0x00000020 },
+        { 0x000683,   1, 0x01, 0x00000006 },
+        { 0x000685,   1, 0x01, 0x003fffff },
+        { 0x000687,   1, 0x01, 0x003fffff },
+        { 0x0006a0,   1, 0x01, 0x00000005 },
+        { 0x000840,   1, 0x01, 0x00400008 },
+        { 0x000841,   1, 0x01, 0x08000080 },
+        { 0x000842,   1, 0x01, 0x00400008 },
+        { 0x000843,   1, 0x01, 0x08000080 },
+        { 0x0006aa,   1, 0x01, 0x00000001 },
+        { 0x0006ab,   1, 0x01, 0x00000002 },
+        { 0x0006ac,   1, 0x01, 0x00000080 },
+        { 0x0006ad,   2, 0x01, 0x00000100 },
+        { 0x0006b1,   1, 0x01, 0x00000011 },
+        { 0x0006bb,   1, 0x01, 0x000000cf },
+        { 0x0006ce,   1, 0x01, 0x2a712488 },
+        { 0x000739,   1, 0x01, 0x4085c000 },
+        { 0x00073a,   1, 0x01, 0x00000080 },
+        { 0x000786,   1, 0x01, 0x80000100 },
+        { 0x00073c,   1, 0x01, 0x00010100 },
+        { 0x00073d,   1, 0x01, 0x02800000 },
+        { 0x000787,   1, 0x01, 0x000000cf },
+        { 0x00078c,   1, 0x01, 0x00000008 },
+        { 0x000792,   1, 0x01, 0x00000001 },
+        { 0x000794,   1, 0x01, 0x00000001 },
+        { 0x000795,   2, 0x01, 0x00000001 },
+        { 0x000797,   1, 0x01, 0x000000cf },
+        { 0x000836,   1, 0x01, 0x00000001 },
+        { 0x00079a,   1, 0x01, 0x00000002 },
+        { 0x000833,   1, 0x01, 0x04444480 },
+        { 0x0007a1,   1, 0x01, 0x00000001 },
+        { 0x0007a3,   1, 0x01, 0x00000001 },
+        { 0x0007a4,   2, 0x01, 0x00000001 },
+        { 0x000831,   1, 0x01, 0x00000004 },
+        { 0x000b07,   1, 0x01, 0x00000002 },
+        { 0x000b08,   2, 0x01, 0x00000100 },
+        { 0x000b0a,   1, 0x01, 0x00000001 },
+        { 0x000a04,   1, 0x01, 0x000000ff },
+        { 0x000a0b,   1, 0x01, 0x00000040 },
+        { 0x00097f,   1, 0x01, 0x00000100 },
+        { 0x000a02,   1, 0x01, 0x00000001 },
+        { 0x000809,   1, 0x01, 0x00000007 },
+        { 0x00c221,   1, 0x01, 0x00000040 },
+        { 0x00c1b0,   8, 0x01, 0x0000000f },
+        { 0x00c1b8,   1, 0x01, 0x0fac6881 },
+        { 0x00c1b9,   1, 0x01, 0x00fac688 },
+        { 0x00c401,   1, 0x01, 0x00000001 },
+        { 0x00c402,   1, 0x01, 0x00010001 },
+        { 0x00c403,   2, 0x01, 0x00000001 },
+        { 0x00c40e,   1, 0x01, 0x00000020 },
+        { 0x00c500,   1, 0x01, 0x00000003 },
+        { 0x01e100,   1, 0x01, 0x00000001 },
+        { 0x001000,   1, 0x01, 0x00000002 },
+        { 0x0006aa,   1, 0x01, 0x00000001 },
+        { 0x0006ad,   2, 0x01, 0x00000100 },
+        { 0x0006b1,   1, 0x01, 0x00000011 },
+        { 0x00078c,   1, 0x01, 0x00000008 },
+        { 0x000792,   1, 0x01, 0x00000001 },
+        { 0x000794,   1, 0x01, 0x00000001 },
+        { 0x000795,   2, 0x01, 0x00000001 },
+        { 0x000797,   1, 0x01, 0x000000cf },
+        { 0x00079a,   1, 0x01, 0x00000002 },
+        { 0x000833,   1, 0x01, 0x04444480 },
+        { 0x0007a1,   1, 0x01, 0x00000001 },
+        { 0x0007a3,   1, 0x01, 0x00000001 },
+        { 0x0007a4,   2, 0x01, 0x00000001 },
+        { 0x000831,   1, 0x01, 0x00000004 },
+        { 0x01e100,   1, 0x01, 0x00000001 },
+        { 0x001000,   1, 0x01, 0x00000008 },
+        { 0x000039,   3, 0x01, 0x00000000 },
+        { 0x000380,   1, 0x01, 0x00000001 },
+        { 0x000366,   2, 0x01, 0x00000000 },
+        { 0x000368,   1, 0x01, 0x00000fff },
+        { 0x000370,   2, 0x01, 0x00000000 },
+        { 0x000372,   1, 0x01, 0x000fffff },
+        { 0x000813,   1, 0x01, 0x00000006 },
+        { 0x000814,   1, 0x01, 0x00000008 },
+        { 0x000957,   1, 0x01, 0x00000003 },
+        { 0x000b07,   1, 0x01, 0x00000002 },
+        { 0x000b08,   2, 0x01, 0x00000100 },
+        { 0x000b0a,   1, 0x01, 0x00000001 },
+        { 0x000a04,   1, 0x01, 0x000000ff },
+        { 0x00097f,   1, 0x01, 0x00000100 },
+        { 0x000a02,   1, 0x01, 0x00000001 },
+        { 0x000809,   1, 0x01, 0x00000007 },
+        { 0x00c221,   1, 0x01, 0x00000040 },
+        { 0x00c401,   1, 0x01, 0x00000001 },
+        { 0x00c402,   1, 0x01, 0x00010001 },
+        { 0x00c403,   2, 0x01, 0x00000001 },
+        { 0x00c40e,   1, 0x01, 0x00000020 },
+        { 0x00c500,   1, 0x01, 0x00000003 },
+        { 0x01e100,   1, 0x01, 0x00000001 },
+        { 0x001000,   1, 0x01, 0x00000001 },
+        { 0x000b07,   1, 0x01, 0x00000002 },
+        { 0x000b08,   2, 0x01, 0x00000100 },
+        { 0x000b0a,   1, 0x01, 0x00000001 },
+        { 0x01e100,   1, 0x01, 0x00000001 },
+        {}
+};
+
+struct nvc0_graph_init
+nve4_grctx_init_a097[] = {
+        { 0x000800,   8, 0x40, 0x00000000 },
+        { 0x000804,   8, 0x40, 0x00000000 },
+        { 0x000808,   8, 0x40, 0x00000400 },
+        { 0x00080c,   8, 0x40, 0x00000300 },
+        { 0x000810,   1, 0x04, 0x000000cf },
+        { 0x000850,   7, 0x40, 0x00000000 },
+        { 0x000814,   8, 0x40, 0x00000040 },
+        { 0x000818,   8, 0x40, 0x00000001 },
+        { 0x00081c,   8, 0x40, 0x00000000 },
+        { 0x000820,   8, 0x40, 0x00000000 },
+        { 0x001c00,  16, 0x10, 0x00000000 },
+        { 0x001c04,  16, 0x10, 0x00000000 },
+        { 0x001c08,  16, 0x10, 0x00000000 },
+        { 0x001c0c,  16, 0x10, 0x00000000 },
+        { 0x001d00,  16, 0x10, 0x00000000 },
+        { 0x001d04,  16, 0x10, 0x00000000 },
+        { 0x001d08,  16, 0x10, 0x00000000 },
+        { 0x001d0c,  16, 0x10, 0x00000000 },
+        { 0x001f00,  16, 0x08, 0x00000000 },
+        { 0x001f04,  16, 0x08, 0x00000000 },
+        { 0x001f80,  16, 0x08, 0x00000000 },
+        { 0x001f84,  16, 0x08, 0x00000000 },
+        { 0x002000,   1, 0x04, 0x00000000 },
+        { 0x002040,   1, 0x04, 0x00000011 },
+        { 0x002080,   1, 0x04, 0x00000020 },
+        { 0x0020c0,   1, 0x04, 0x00000030 },
+        { 0x002100,   1, 0x04, 0x00000040 },
+        { 0x002140,   1, 0x04, 0x00000051 },
+        { 0x00200c,   6, 0x40, 0x00000001 },
+        { 0x002010,   1, 0x04, 0x00000000 },
+        { 0x002050,   1, 0x04, 0x00000000 },
+        { 0x002090,   1, 0x04, 0x00000001 },
+        { 0x0020d0,   1, 0x04, 0x00000002 },
+        { 0x002110,   1, 0x04, 0x00000003 },
+        { 0x002150,   1, 0x04, 0x00000004 },
+        { 0x000380,   4, 0x20, 0x00000000 },
+        { 0x000384,   4, 0x20, 0x00000000 },
+        { 0x000388,   4, 0x20, 0x00000000 },
+        { 0x00038c,   4, 0x20, 0x00000000 },
+        { 0x000700,   4, 0x10, 0x00000000 },
+        { 0x000704,   4, 0x10, 0x00000000 },
+        { 0x000708,   4, 0x10, 0x00000000 },
+        { 0x002800, 128, 0x04, 0x00000000 },
+        { 0x000a00,  16, 0x20, 0x00000000 },
+        { 0x000a04,  16, 0x20, 0x00000000 },
+        { 0x000a08,  16, 0x20, 0x00000000 },
+        { 0x000a0c,  16, 0x20, 0x00000000 },
+        { 0x000a10,  16, 0x20, 0x00000000 },
+        { 0x000a14,  16, 0x20, 0x00000000 },
+        { 0x000c00,  16, 0x10, 0x00000000 },
+        { 0x000c04,  16, 0x10, 0x00000000 },
+        { 0x000c08,  16, 0x10, 0x00000000 },
+        { 0x000c0c,  16, 0x10, 0x3f800000 },
+        { 0x000d00,   8, 0x08, 0xffff0000 },
+        { 0x000d04,   8, 0x08, 0xffff0000 },
+        { 0x000e00,  16, 0x10, 0x00000000 },
+        { 0x000e04,  16, 0x10, 0xffff0000 },
+        { 0x000e08,  16, 0x10, 0xffff0000 },
+        { 0x000d40,   4, 0x08, 0x00000000 },
+        { 0x000d44,   4, 0x08, 0x00000000 },
+        { 0x001e00,   8, 0x20, 0x00000001 },
+        { 0x001e04,   8, 0x20, 0x00000001 },
+        { 0x001e08,   8, 0x20, 0x00000002 },
+        { 0x001e0c,   8, 0x20, 0x00000001 },
+        { 0x001e10,   8, 0x20, 0x00000001 },
+        { 0x001e14,   8, 0x20, 0x00000002 },
+        { 0x001e18,   8, 0x20, 0x00000001 },
+        { 0x003400, 128, 0x04, 0x00000000 },
+        { 0x00030c,   1, 0x04, 0x00000001 },
+        { 0x001944,   1, 0x04, 0x00000000 },
+        { 0x001514,   1, 0x04, 0x00000000 },
+        { 0x000d68,   1, 0x04, 0x0000ffff },
+        { 0x00121c,   1, 0x04, 0x0fac6881 },
+        { 0x000fac,   1, 0x04, 0x00000001 },
+        { 0x001538,   1, 0x04, 0x00000001 },
+        { 0x000fe0,   2, 0x04, 0x00000000 },
+        { 0x000fe8,   1, 0x04, 0x00000014 },
+        { 0x000fec,   1, 0x04, 0x00000040 },
+        { 0x000ff0,   1, 0x04, 0x00000000 },
+        { 0x00179c,   1, 0x04, 0x00000000 },
+        { 0x001228,   1, 0x04, 0x00000400 },
+        { 0x00122c,   1, 0x04, 0x00000300 },
+        { 0x001230,   1, 0x04, 0x00010001 },
+        { 0x0007f8,   1, 0x04, 0x00000000 },
+        { 0x0015b4,   1, 0x04, 0x00000001 },
+        { 0x0015cc,   1, 0x04, 0x00000000 },
+        { 0x001534,   1, 0x04, 0x00000000 },
+        { 0x000fb0,   1, 0x04, 0x00000000 },
+        { 0x0015d0,   1, 0x04, 0x00000000 },
+        { 0x00153c,   1, 0x04, 0x00000000 },
+        { 0x0016b4,   1, 0x04, 0x00000003 },
+        { 0x000fbc,   4, 0x04, 0x0000ffff },
+        { 0x000df8,   2, 0x04, 0x00000000 },
+        { 0x001948,   1, 0x04, 0x00000000 },
+        { 0x001970,   1, 0x04, 0x00000001 },
+        { 0x00161c,   1, 0x04, 0x000009f0 },
+        { 0x000dcc,   1, 0x04, 0x00000010 },
+        { 0x00163c,   1, 0x04, 0x00000000 },
+        { 0x0015e4,   1, 0x04, 0x00000000 },
+        { 0x001160,  32, 0x04, 0x25e00040 },
+        { 0x001880,  32, 0x04, 0x00000000 },
+        { 0x000f84,   2, 0x04, 0x00000000 },
+        { 0x0017c8,   2, 0x04, 0x00000000 },
+        { 0x0017d0,   1, 0x04, 0x000000ff },
+        { 0x0017d4,   1, 0x04, 0xffffffff },
+        { 0x0017d8,   1, 0x04, 0x00000002 },
+        { 0x0017dc,   1, 0x04, 0x00000000 },
+        { 0x0015f4,   2, 0x04, 0x00000000 },
+        { 0x001434,   2, 0x04, 0x00000000 },
+        { 0x000d74,   1, 0x04, 0x00000000 },
+        { 0x000dec,   1, 0x04, 0x00000001 },
+        { 0x0013a4,   1, 0x04, 0x00000000 },
+        { 0x001318,   1, 0x04, 0x00000001 },
+        { 0x001644,   1, 0x04, 0x00000000 },
+        { 0x000748,   1, 0x04, 0x00000000 },
+        { 0x000de8,   1, 0x04, 0x00000000 },
+        { 0x001648,   1, 0x04, 0x00000000 },
+        { 0x0012a4,   1, 0x04, 0x00000000 },
+        { 0x001120,   4, 0x04, 0x00000000 },
+        { 0x001118,   1, 0x04, 0x00000000 },
+        { 0x00164c,   1, 0x04, 0x00000000 },
+        { 0x001658,   1, 0x04, 0x00000000 },
+        { 0x001910,   1, 0x04, 0x00000290 },
+        { 0x001518,   1, 0x04, 0x00000000 },
+        { 0x00165c,   1, 0x04, 0x00000001 },
+        { 0x001520,   1, 0x04, 0x00000000 },
+        { 0x001604,   1, 0x04, 0x00000000 },
+        { 0x001570,   1, 0x04, 0x00000000 },
+        { 0x0013b0,   2, 0x04, 0x3f800000 },
+        { 0x00020c,   1, 0x04, 0x00000000 },
+        { 0x001670,   1, 0x04, 0x30201000 },
+        { 0x001674,   1, 0x04, 0x70605040 },
+        { 0x001678,   1, 0x04, 0xb8a89888 },
+        { 0x00167c,   1, 0x04, 0xf8e8d8c8 },
+        { 0x00166c,   1, 0x04, 0x00000000 },
+        { 0x001680,   1, 0x04, 0x00ffff00 },
+        { 0x0012d0,   1, 0x04, 0x00000003 },
+        { 0x0012d4,   1, 0x04, 0x00000002 },
+        { 0x001684,   2, 0x04, 0x00000000 },
+        { 0x000dac,   2, 0x04, 0x00001b02 },
+        { 0x000db4,   1, 0x04, 0x00000000 },
+        { 0x00168c,   1, 0x04, 0x00000000 },
+        { 0x0015bc,   1, 0x04, 0x00000000 },
+        { 0x00156c,   1, 0x04, 0x00000000 },
+        { 0x00187c,   1, 0x04, 0x00000000 },
+        { 0x001110,   1, 0x04, 0x00000001 },
+        { 0x000dc0,   3, 0x04, 0x00000000 },
+        { 0x001234,   1, 0x04, 0x00000000 },
+        { 0x001690,   1, 0x04, 0x00000000 },
+        { 0x0012ac,   1, 0x04, 0x00000001 },
+        { 0x000790,   5, 0x04, 0x00000000 },
+        { 0x00077c,   1, 0x04, 0x00000000 },
+        { 0x001000,   1, 0x04, 0x00000010 },
+        { 0x0010fc,   1, 0x04, 0x00000000 },
+        { 0x001290,   1, 0x04, 0x00000000 },
+        { 0x000218,   1, 0x04, 0x00000010 },
+        { 0x0012d8,   1, 0x04, 0x00000000 },
+        { 0x0012dc,   1, 0x04, 0x00000010 },
+        { 0x000d94,   1, 0x04, 0x00000001 },
+        { 0x00155c,   2, 0x04, 0x00000000 },
+        { 0x001564,   1, 0x04, 0x00000fff },
+        { 0x001574,   2, 0x04, 0x00000000 },
+        { 0x00157c,   1, 0x04, 0x000fffff },
+        { 0x001354,   1, 0x04, 0x00000000 },
+        { 0x001610,   1, 0x04, 0x00000012 },
+        { 0x001608,   2, 0x04, 0x00000000 },
+        { 0x00260c,   1, 0x04, 0x00000000 },
+        { 0x0007ac,   1, 0x04, 0x00000000 },
+        { 0x00162c,   1, 0x04, 0x00000003 },
+        { 0x000210,   1, 0x04, 0x00000000 },
+        { 0x000320,   1, 0x04, 0x00000000 },
+        { 0x000324,   6, 0x04, 0x3f800000 },
+        { 0x000750,   1, 0x04, 0x00000000 },
+        { 0x000760,   1, 0x04, 0x39291909 },
+        { 0x000764,   1, 0x04, 0x79695949 },
+        { 0x000768,   1, 0x04, 0xb9a99989 },
+        { 0x00076c,   1, 0x04, 0xf9e9d9c9 },
+        { 0x000770,   1, 0x04, 0x30201000 },
+        { 0x000774,   1, 0x04, 0x70605040 },
+        { 0x000778,   1, 0x04, 0x00009080 },
+        { 0x000780,   1, 0x04, 0x39291909 },
+        { 0x000784,   1, 0x04, 0x79695949 },
+        { 0x000788,   1, 0x04, 0xb9a99989 },
+        { 0x00078c,   1, 0x04, 0xf9e9d9c9 },
+        { 0x0007d0,   1, 0x04, 0x30201000 },
+        { 0x0007d4,   1, 0x04, 0x70605040 },
+        { 0x0007d8,   1, 0x04, 0x00009080 },
+        { 0x00037c,   1, 0x04, 0x00000001 },
+        { 0x000740,   2, 0x04, 0x00000000 },
+        { 0x002600,   1, 0x04, 0x00000000 },
+        { 0x001918,   1, 0x04, 0x00000000 },
+        { 0x00191c,   1, 0x04, 0x00000900 },
+        { 0x001920,   1, 0x04, 0x00000405 },
+        { 0x001308,   1, 0x04, 0x00000001 },
+        { 0x001924,   1, 0x04, 0x00000000 },
+        { 0x0013ac,   1, 0x04, 0x00000000 },
+        { 0x00192c,   1, 0x04, 0x00000001 },
+        { 0x00193c,   1, 0x04, 0x00002c1c },
+        { 0x000d7c,   1, 0x04, 0x00000000 },
+        { 0x000f8c,   1, 0x04, 0x00000000 },
+        { 0x0002c0,   1, 0x04, 0x00000001 },
+        { 0x001510,   1, 0x04, 0x00000000 },
+        { 0x001940,   1, 0x04, 0x00000000 },
+        { 0x000ff4,   2, 0x04, 0x00000000 },
+        { 0x00194c,   2, 0x04, 0x00000000 },
+        { 0x001968,   1, 0x04, 0x00000000 },
+        { 0x001590,   1, 0x04, 0x0000003f },
+        { 0x0007e8,   4, 0x04, 0x00000000 },
+        { 0x00196c,   1, 0x04, 0x00000011 },
+        { 0x0002e4,   1, 0x04, 0x0000b001 },
+        { 0x00036c,   2, 0x04, 0x00000000 },
+        { 0x00197c,   1, 0x04, 0x00000000 },
+        { 0x000fcc,   2, 0x04, 0x00000000 },
+        { 0x0002d8,   1, 0x04, 0x00000040 },
+        { 0x001980,   1, 0x04, 0x00000080 },
+        { 0x001504,   1, 0x04, 0x00000080 },
+        { 0x001984,   1, 0x04, 0x00000000 },
+        { 0x000300,   1, 0x04, 0x00000001 },
+        { 0x0013a8,   1, 0x04, 0x00000000 },
+        { 0x0012ec,   1, 0x04, 0x00000000 },
+        { 0x001310,   1, 0x04, 0x00000000 },
+        { 0x001314,   1, 0x04, 0x00000001 },
+        { 0x001380,   1, 0x04, 0x00000000 },
+        { 0x001384,   4, 0x04, 0x00000001 },
+        { 0x001394,   1, 0x04, 0x00000000 },
+        { 0x00139c,   1, 0x04, 0x00000000 },
+        { 0x001398,   1, 0x04, 0x00000000 },
+        { 0x001594,   1, 0x04, 0x00000000 },
+        { 0x001598,   4, 0x04, 0x00000001 },
+        { 0x000f54,   3, 0x04, 0x00000000 },
+        { 0x0019bc,   1, 0x04, 0x00000000 },
+        { 0x000f9c,   2, 0x04, 0x00000000 },
+        { 0x0012cc,   1, 0x04, 0x00000000 },
+        { 0x0012e8,   1, 0x04, 0x00000000 },
+        { 0x00130c,   1, 0x04, 0x00000001 },
+        { 0x001360,   8, 0x04, 0x00000000 },
+        { 0x00133c,   2, 0x04, 0x00000001 },
+        { 0x001344,   1, 0x04, 0x00000002 },
+        { 0x001348,   2, 0x04, 0x00000001 },
+        { 0x001350,   1, 0x04, 0x00000002 },
+        { 0x001358,   1, 0x04, 0x00000001 },
+        { 0x0012e4,   1, 0x04, 0x00000000 },
+        { 0x00131c,   1, 0x04, 0x00000000 },
+        { 0x001320,   3, 0x04, 0x00000000 },
+        { 0x0019c0,   1, 0x04, 0x00000000 },
+        { 0x001140,   1, 0x04, 0x00000000 },
+        { 0x0019c4,   1, 0x04, 0x00000000 },
+        { 0x0019c8,   1, 0x04, 0x00001500 },
+        { 0x00135c,   1, 0x04, 0x00000000 },
+        { 0x000f90,   1, 0x04, 0x00000000 },
+        { 0x0019e0,   8, 0x04, 0x00000001 },
+        { 0x0019cc,   1, 0x04, 0x00000001 },
+        { 0x0015b8,   1, 0x04, 0x00000000 },
+        { 0x001a00,   1, 0x04, 0x00001111 },
+        { 0x001a04,   7, 0x04, 0x00000000 },
+        { 0x000d6c,   2, 0x04, 0xffff0000 },
+        { 0x0010f8,   1, 0x04, 0x00001010 },
+        { 0x000d80,   5, 0x04, 0x00000000 },
+        { 0x000da0,   1, 0x04, 0x00000000 },
+        { 0x0007a4,   2, 0x04, 0x00000000 },
+        { 0x001508,   1, 0x04, 0x80000000 },
+        { 0x00150c,   1, 0x04, 0x40000000 },
+        { 0x001668,   1, 0x04, 0x00000000 },
+        { 0x000318,   2, 0x04, 0x00000008 },
+        { 0x000d9c,   1, 0x04, 0x00000001 },
+        { 0x000374,   1, 0x04, 0x00000000 },
+        { 0x000378,   1, 0x04, 0x00000020 },
+        { 0x0007dc,   1, 0x04, 0x00000000 },
+        { 0x00074c,   1, 0x04, 0x00000055 },
+        { 0x001420,   1, 0x04, 0x00000003 },
+        { 0x0017bc,   2, 0x04, 0x00000000 },
+        { 0x0017c4,   1, 0x04, 0x00000001 },
+        { 0x001008,   1, 0x04, 0x00000008 },
+        { 0x00100c,   1, 0x04, 0x00000040 },
+        { 0x001010,   1, 0x04, 0x0000012c },
+        { 0x000d60,   1, 0x04, 0x00000040 },
+        { 0x00075c,   1, 0x04, 0x00000003 },
+        { 0x001018,   1, 0x04, 0x00000020 },
+        { 0x00101c,   1, 0x04, 0x00000001 },
+        { 0x001020,   1, 0x04, 0x00000020 },
+        { 0x001024,   1, 0x04, 0x00000001 },
+        { 0x001444,   3, 0x04, 0x00000000 },
+        { 0x000360,   1, 0x04, 0x20164010 },
+        { 0x000364,   1, 0x04, 0x00000020 },
+        { 0x000368,   1, 0x04, 0x00000000 },
+        { 0x000de4,   1, 0x04, 0x00000000 },
+        { 0x000204,   1, 0x04, 0x00000006 },
+        { 0x000208,   1, 0x04, 0x00000000 },
+        { 0x0002cc,   2, 0x04, 0x003fffff },
+        { 0x001220,   1, 0x04, 0x00000005 },
+        { 0x000fdc,   1, 0x04, 0x00000000 },
+        { 0x000f98,   1, 0x04, 0x00400008 },
+        { 0x001284,   1, 0x04, 0x08000080 },
+        { 0x001450,   1, 0x04, 0x00400008 },
+        { 0x001454,   1, 0x04, 0x08000080 },
+        { 0x000214,   1, 0x04, 0x00000000 },
+        {}
+};
+
+static struct nvc0_graph_init
+nve4_grctx_init_unk40xx[] = {
+        { 0x404010,   5, 0x04, 0x00000000 },
+        { 0x404024,   1, 0x04, 0x0000e000 },
+        { 0x404028,   1, 0x04, 0x00000000 },
+        { 0x4040a8,   1, 0x04, 0x00000000 },
+        { 0x4040ac,   7, 0x04, 0x00000000 },
+        { 0x4040c8,   1, 0x04, 0xf800008f },
+        { 0x4040d0,   6, 0x04, 0x00000000 },
+        { 0x4040e8,   1, 0x04, 0x00001000 },
+        { 0x4040f8,   1, 0x04, 0x00000000 },
+        { 0x404130,   1, 0x04, 0x00000000 },
+        { 0x404134,   1, 0x04, 0x00000000 },
+        { 0x404138,   1, 0x04, 0x20000040 },
+        { 0x404150,   1, 0x04, 0x0000002e },
+        { 0x404154,   1, 0x04, 0x00000400 },
+        { 0x404158,   1, 0x04, 0x00000200 },
+        { 0x404164,   1, 0x04, 0x00000055 },
+        { 0x4041a0,   4, 0x04, 0x00000000 },
+        { 0x404200,   4, 0x04, 0x00000000 },
+        {}
+};
+
+struct nvc0_graph_init
+nve4_grctx_init_unk46xx[] = {
+        { 0x404604,   1, 0x04, 0x00000014 },
+        { 0x404608,   1, 0x04, 0x00000000 },
+        { 0x40460c,   1, 0x04, 0x00003fff },
+        { 0x404610,   1, 0x04, 0x00000100 },
+        { 0x404618,   4, 0x04, 0x00000000 },
+        { 0x40462c,   2, 0x04, 0x00000000 },
+        { 0x404640,   1, 0x04, 0x00000000 },
+        { 0x404654,   1, 0x04, 0x00000000 },
+        { 0x404660,   1, 0x04, 0x00000000 },
+        { 0x404678,   1, 0x04, 0x00000000 },
+        { 0x40467c,   1, 0x04, 0x00000002 },
+        { 0x404680,   8, 0x04, 0x00000000 },
+        { 0x4046a0,   1, 0x04, 0x007f0080 },
+        { 0x4046a4,   8, 0x04, 0x00000000 },
+        { 0x4046c8,   3, 0x04, 0x00000000 },
+        {}
+};
+
+struct nvc0_graph_init
+nve4_grctx_init_unk47xx[] = {
+        { 0x404700,   3, 0x04, 0x00000000 },
+        { 0x404718,   7, 0x04, 0x00000000 },
+        { 0x404734,   1, 0x04, 0x00000100 },
+        { 0x404738,   2, 0x04, 0x00000000 },
+        { 0x404744,   2, 0x04, 0x00000000 },
+        { 0x404754,   1, 0x04, 0x00000000 },
+        {}
+};
+
+struct nvc0_graph_init
+nve4_grctx_init_unk58xx[] = {
+        { 0x405800,   1, 0x04, 0x0f8000bf },
+        { 0x405830,   1, 0x04, 0x02180648 },
+        { 0x405834,   1, 0x04, 0x08000000 },
+        { 0x405838,   1, 0x04, 0x00000000 },
+        { 0x405854,   1, 0x04, 0x00000000 },
+        { 0x405870,   4, 0x04, 0x00000001 },
+        { 0x405a00,   2, 0x04, 0x00000000 },
+        { 0x405a18,   1, 0x04, 0x00000000 },
+        {}
+};
+
+static struct nvc0_graph_init
+nve4_grctx_init_unk5bxx[] = {
+        { 0x405b00,   1, 0x04, 0x00000000 },
+        { 0x405b10,   1, 0x04, 0x00001000 },
+        {}
+};
+
+static struct nvc0_graph_init
+nve4_grctx_init_unk60xx[] = {
+        { 0x406020,   1, 0x04, 0x004103c1 },
+        { 0x406028,   4, 0x04, 0x00000001 },
+        {}
+};
+
+static struct nvc0_graph_init
+nve4_grctx_init_unk64xx[] = {
+        { 0x4064a8,   1, 0x04, 0x00000000 },
+        { 0x4064ac,   1, 0x04, 0x00003fff },
+        { 0x4064b4,   2, 0x04, 0x00000000 },
+        { 0x4064c0,   1, 0x04, 0x801a00f0 },
+        { 0x4064c4,   1, 0x04, 0x0192ffff },
+        { 0x4064c8,   1, 0x04, 0x01800600 },
+        { 0x4064cc,   9, 0x04, 0x00000000 },
+        { 0x4064fc,   1, 0x04, 0x0000022a },
+        {}
+};
+
+static struct nvc0_graph_init
+nve4_grctx_init_unk70xx[] = {
+        { 0x407040,   1, 0x04, 0x00000000 },
+        {}
+};
+
+struct nvc0_graph_init
+nve4_grctx_init_unk80xx[] = {
+        { 0x408000,   2, 0x04, 0x00000000 },
+        { 0x408008,   1, 0x04, 0x00000030 },
+        { 0x40800c,   2, 0x04, 0x00000000 },
+        { 0x408014,   1, 0x04, 0x00000069 },
+        { 0x408018,   1, 0x04, 0xe100e100 },
+        { 0x408064,   1, 0x04, 0x00000000 },
+        {}
+};
+
+static struct nvc0_graph_init
+nve4_grctx_init_rop[] = {
+        { 0x408800,   1, 0x04, 0x02802a3c },
+        { 0x408804,   1, 0x04, 0x00000040 },
+        { 0x408808,   1, 0x04, 0x1043e005 },
+        { 0x408840,   1, 0x04, 0x0000000b },
+        { 0x408900,   1, 0x04, 0x3080b801 },
+        { 0x408904,   1, 0x04, 0x62000001 },
+        { 0x408908,   1, 0x04, 0x00c8102f },
+        { 0x408980,   1, 0x04, 0x0000011d },
+        {}
+};
+
+static struct nvc0_graph_init
+nve4_grctx_init_gpc_0[] = {
+        { 0x418380,   1, 0x04, 0x00000016 },
+        { 0x418400,   1, 0x04, 0x38004e00 },
+        { 0x418404,   1, 0x04, 0x71e0ffff },
+        { 0x41840c,   1, 0x04, 0x00001008 },
+        { 0x418410,   1, 0x04, 0x0fff0fff },
+        { 0x418414,   1, 0x04, 0x02200fff },
+        { 0x418450,   6, 0x04, 0x00000000 },
+        { 0x418468,   1, 0x04, 0x00000001 },
+        { 0x41846c,   2, 0x04, 0x00000000 },
+        { 0x418600,   1, 0x04, 0x0000001f },
+        { 0x418684,   1, 0x04, 0x0000000f },
+        { 0x418700,   1, 0x04, 0x00000002 },
+        { 0x418704,   1, 0x04, 0x00000080 },
+        { 0x418708,   3, 0x04, 0x00000000 },
+        { 0x418800,   1, 0x04, 0x7006860a },
+        { 0x418808,   3, 0x04, 0x00000000 },
+        { 0x418828,   1, 0x04, 0x00000044 },
+        { 0x418830,   1, 0x04, 0x10000001 },
+        { 0x4188d8,   1, 0x04, 0x00000008 },
+        { 0x4188e0,   1, 0x04, 0x01000000 },
+        { 0x4188e8,   5, 0x04, 0x00000000 },
+        { 0x4188fc,   1, 0x04, 0x20100018 },
+        { 0x41891c,   1, 0x04, 0x00ff00ff },
+        { 0x418924,   1, 0x04, 0x00000000 },
+        { 0x418928,   1, 0x04, 0x00ffff00 },
+        { 0x41892c,   1, 0x04, 0x0000ff00 },
+        { 0x418b00,   1, 0x04, 0x00000006 },
+        { 0x418b08,   1, 0x04, 0x0a418820 },
+        { 0x418b0c,   1, 0x04, 0x062080e6 },
+        { 0x418b10,   1, 0x04, 0x020398a4 },
+        { 0x418b14,   1, 0x04, 0x0e629062 },
+        { 0x418b18,   1, 0x04, 0x0a418820 },
+        { 0x418b1c,   1, 0x04, 0x000000e6 },
+        { 0x418bb8,   1, 0x04, 0x00000103 },
+        { 0x418c08,   1, 0x04, 0x00000001 },
+        { 0x418c10,   8, 0x04, 0x00000000 },
+        { 0x418c40,   1, 0x04, 0xffffffff },
+        { 0x418c6c,   1, 0x04, 0x00000001 },
+        { 0x418c80,   1, 0x04, 0x20200004 },
+        { 0x418c8c,   1, 0x04, 0x00000001 },
+        { 0x419000,   1, 0x04, 0x00000780 },
+        { 0x419004,   2, 0x04, 0x00000000 },
+        { 0x419014,   1, 0x04, 0x00000004 },
+        {}
+};
+
+static struct nvc0_graph_init
+nve4_grctx_init_tpc[] = {
+        { 0x419848,   1, 0x04, 0x00000000 },
+        { 0x419864,   1, 0x04, 0x00000129 },
+        { 0x419888,   1, 0x04, 0x00000000 },
+        { 0x419a00,   1, 0x04, 0x000000f0 },
+        { 0x419a04,   1, 0x04, 0x00000001 },
+        { 0x419a08,   1, 0x04, 0x00000021 },
+        { 0x419a0c,   1, 0x04, 0x00020000 },
+        { 0x419a10,   1, 0x04, 0x00000000 },
+        { 0x419a14,   1, 0x04, 0x00000200 },
+        { 0x419a1c,   1, 0x04, 0x0000c000 },
+        { 0x419a20,   1, 0x04, 0x00000800 },
+        { 0x419a30,   1, 0x04, 0x00000001 },
+        { 0x419ac4,   1, 0x04, 0x0037f440 },
+        { 0x419c00,   1, 0x04, 0x0000000a },
+        { 0x419c04,   1, 0x04, 0x80000006 },
+        { 0x419c08,   1, 0x04, 0x00000002 },
+        { 0x419c20,   1, 0x04, 0x00000000 },
+        { 0x419c24,   1, 0x04, 0x00084210 },
+        { 0x419c28,   1, 0x04, 0x3efbefbe },
+        { 0x419ce8,   1, 0x04, 0x00000000 },
+        { 0x419cf4,   1, 0x04, 0x00003203 },
+        { 0x419e04,   3, 0x04, 0x00000000 },
+        { 0x419e10,   1, 0x04, 0x00000402 },
+        { 0x419e44,   1, 0x04, 0x0013eff2 },
+        { 0x419e48,   1, 0x04, 0x00000000 },
+        { 0x419e4c,   1, 0x04, 0x0000007f },
+        { 0x419e50,  19, 0x04, 0x00000000 },
+        { 0x419eac,   1, 0x04, 0x00001f8f },
+        { 0x419eb0,   1, 0x04, 0x00000d3f },
+        { 0x419ec8,   1, 0x04, 0x0001304f },
+        { 0x419f30,   8, 0x04, 0x00000000 },
+        { 0x419f58,   1, 0x04, 0x00000000 },
+        { 0x419f70,   1, 0x04, 0x00000000 },
+        { 0x419f78,   1, 0x04, 0x0000000b },
+        { 0x419f7c,   1, 0x04, 0x0000027a },
+        {}
+};
+
+static struct nvc0_graph_init
+nve4_grctx_init_unk[] = {
+        { 0x41be24,   1, 0x04, 0x00000006 },
+        { 0x41bec0,   1, 0x04, 0x12180000 },
+        { 0x41bec4,   1, 0x04, 0x00037f7f },
+        { 0x41bee4,   1, 0x04, 0x06480430 },
+        { 0x41bf00,   1, 0x04, 0x0a418820 },
+        { 0x41bf04,   1, 0x04, 0x062080e6 },
+        { 0x41bf08,   1, 0x04, 0x020398a4 },
+        { 0x41bf0c,   1, 0x04, 0x0e629062 },
+        { 0x41bf10,   1, 0x04, 0x0a418820 },
+        { 0x41bf14,   1, 0x04, 0x000000e6 },
+        { 0x41bfd0,   1, 0x04, 0x00900103 },
+        { 0x41bfe0,   1, 0x04, 0x00400001 },
+        { 0x41bfe4,   1, 0x04, 0x00000000 },
+        {}
+};
+
+static void
+nve4_grctx_generate_mods(struct nvc0_graph_priv *priv, struct nvc0_grctx *info)
+{
+        u32 magic[GPC_MAX][2];
+        u32 offset;
+        int gpc;
+
+        mmio_data(0x003000, 0x0100, NV_MEM_ACCESS_RW | NV_MEM_ACCESS_SYS);
+        mmio_data(0x008000, 0x0100, NV_MEM_ACCESS_RW | NV_MEM_ACCESS_SYS);
+        mmio_data(0x060000, 0x1000, NV_MEM_ACCESS_RW);
+        mmio_list(0x40800c, 0x00000000,  8, 1);
+        mmio_list(0x408010, 0x80000000,  0, 0);
+        mmio_list(0x419004, 0x00000000,  8, 1);
+        mmio_list(0x419008, 0x00000000,  0, 0);
+        mmio_list(0x4064cc, 0x80000000,  0, 0);
+        mmio_list(0x408004, 0x00000000,  8, 0);
+        mmio_list(0x408008, 0x80000030,  0, 0);
+        mmio_list(0x418808, 0x00000000,  8, 0);
+        mmio_list(0x41880c, 0x80000030,  0, 0);
+        mmio_list(0x4064c8, 0x01800600,  0, 0);
+        mmio_list(0x418810, 0x80000000, 12, 2);
+        mmio_list(0x419848, 0x10000000, 12, 2);
+
+        mmio_list(0x405830, 0x02180648,  0, 0);
+        mmio_list(0x4064c4, 0x0192ffff,  0, 0);
+
+        for (gpc = 0, offset = 0; gpc < priv->gpc_nr; gpc++) {
+                u16 magic0 = 0x0218 * priv->tpc_nr[gpc];
+                u16 magic1 = 0x0648 * priv->tpc_nr[gpc];
+                magic[gpc][0]  = 0x10000000 | (magic0 << 16) | offset;
+                magic[gpc][1]  = 0x00000000 | (magic1 << 16);
+                offset += 0x0324 * priv->tpc_nr[gpc];
+        }
+
+        for (gpc = 0; gpc < priv->gpc_nr; gpc++) {
+                mmio_list(GPC_UNIT(gpc, 0x30c0), magic[gpc][0], 0, 0);
+                mmio_list(GPC_UNIT(gpc, 0x30e4), magic[gpc][1] | offset, 0, 0);
+                offset += 0x07ff * priv->tpc_nr[gpc];
+        }
+
+        mmio_list(0x17e91c, 0x06060609, 0, 0);
+        mmio_list(0x17e920, 0x00090a05, 0, 0);
+}
+
+void
+nve4_grctx_generate_unkn(struct nvc0_graph_priv *priv)
+{
+        nv_mask(priv, 0x418c6c, 0x00000001, 0x00000001);
+        nv_mask(priv, 0x41980c, 0x00000010, 0x00000010);
+        nv_mask(priv, 0x41be08, 0x00000004, 0x00000004);
+        nv_mask(priv, 0x4064c0, 0x80000000, 0x80000000);
+        nv_mask(priv, 0x405800, 0x08000000, 0x08000000);
+        nv_mask(priv, 0x419c00, 0x00000008, 0x00000008);
+}
+
+void
+nve4_grctx_generate_r418bb8(struct nvc0_graph_priv *priv)
+{
+        u32 data[6] = {}, data2[2] = {};
+        u8  tpcnr[GPC_MAX];
+        u8  shift, ntpcv;
+        int gpc, tpc, i;
+
+        /* calculate first set of magics */
+        memcpy(tpcnr, priv->tpc_nr, sizeof(priv->tpc_nr));
+
+        gpc = -1;
+        for (tpc = 0; tpc < priv->tpc_total; tpc++) {
+                do {
+                        gpc = (gpc + 1) % priv->gpc_nr;
+                } while (!tpcnr[gpc]);
+                tpcnr[gpc]--;
+
+                data[tpc / 6] |= gpc << ((tpc % 6) * 5);
+        }
+
+        for (; tpc < 32; tpc++)
+                data[tpc / 6] |= 7 << ((tpc % 6) * 5);
+
+        /* and the second... */
+        shift = 0;
+        ntpcv = priv->tpc_total;
+        while (!(ntpcv & (1 << 4))) {
+                ntpcv <<= 1;
+                shift++;
+        }
+
+        data2[0]  = (ntpcv << 16);
+        data2[0] |= (shift << 21);
+        data2[0] |= (((1 << (0 + 5)) % ntpcv) << 24);
+        for (i = 1; i < 7; i++)
+                data2[1] |= ((1 << (i + 5)) % ntpcv) << ((i - 1) * 5);
+
+        /* GPC_BROADCAST */
+        nv_wr32(priv, 0x418bb8, (priv->tpc_total << 8) |
+                                 priv->magic_not_rop_nr);
+        for (i = 0; i < 6; i++)
+                nv_wr32(priv, 0x418b08 + (i * 4), data[i]);
+
+        /* GPC_BROADCAST.TP_BROADCAST */
+        nv_wr32(priv, 0x41bfd0, (priv->tpc_total << 8) |
+                                 priv->magic_not_rop_nr | data2[0]);
+        nv_wr32(priv, 0x41bfe4, data2[1]);
+        for (i = 0; i < 6; i++)
+                nv_wr32(priv, 0x41bf00 + (i * 4), data[i]);
+
+        /* UNK78xx */
+        nv_wr32(priv, 0x4078bc, (priv->tpc_total << 8) |
+                                 priv->magic_not_rop_nr);
+        for (i = 0; i < 6; i++)
+                nv_wr32(priv, 0x40780c + (i * 4), data[i]);
+}
+
+void
+nve4_grctx_generate_main(struct nvc0_graph_priv *priv, struct nvc0_grctx *info)
+{
+        struct nvc0_grctx_oclass *oclass = (void *)nv_engine(priv)->cclass;
+        int i;
+
+        nv_mask(priv, 0x000260, 0x00000001, 0x00000000);
+
+        for (i = 0; oclass->hub[i]; i++)
+                nvc0_graph_mmio(priv, oclass->hub[i]);
+        for (i = 0; oclass->gpc[i]; i++)
+                nvc0_graph_mmio(priv, oclass->gpc[i]);
+
+        nv_wr32(priv, 0x404154, 0x00000000);
+
+        oclass->mods(priv, info);
+        oclass->unkn(priv);
+
+        nvc0_grctx_generate_tpcid(priv);
+        nvc0_grctx_generate_r406028(priv);
+        nve4_grctx_generate_r418bb8(priv);
+        nvc0_grctx_generate_r406800(priv);
+
+        for (i = 0; i < 8; i++)
+                nv_wr32(priv, 0x4064d0 + (i * 0x04), 0x00000000);
+
+        nv_wr32(priv, 0x405b00, (priv->tpc_total << 8) | priv->gpc_nr);
+        if (priv->gpc_nr == 1) {
+                nv_mask(priv, 0x408850, 0x0000000f, priv->tpc_nr[0]);
+                nv_mask(priv, 0x408958, 0x0000000f, priv->tpc_nr[0]);
+        } else {
+                nv_mask(priv, 0x408850, 0x0000000f, priv->gpc_nr);
+                nv_mask(priv, 0x408958, 0x0000000f, priv->gpc_nr);
+        }
+        nv_mask(priv, 0x419f78, 0x00000001, 0x00000000);
+
+        nvc0_graph_icmd(priv, oclass->icmd);
+        nv_wr32(priv, 0x404154, 0x00000400);
+        nvc0_graph_mthd(priv, oclass->mthd);
+        nv_mask(priv, 0x000260, 0x00000001, 0x00000001);
+
+        nv_mask(priv, 0x418800, 0x00200000, 0x00200000);
+        nv_mask(priv, 0x41be10, 0x00800000, 0x00800000);
+}
+
+static struct nvc0_graph_init *
+nve4_grctx_init_hub[] = {
+        nvc0_grctx_init_base,
+        nve4_grctx_init_unk40xx,
+        nvc0_grctx_init_unk44xx,
+        nve4_grctx_init_unk46xx,
+        nve4_grctx_init_unk47xx,
+        nve4_grctx_init_unk58xx,
+        nve4_grctx_init_unk5bxx,
+        nve4_grctx_init_unk60xx,
+        nve4_grctx_init_unk64xx,
+        nve4_grctx_init_unk70xx,
+        nvc0_grctx_init_unk78xx,
+        nve4_grctx_init_unk80xx,
+        nve4_grctx_init_rop,
+        NULL
+};
+
+struct nvc0_graph_init *
+nve4_grctx_init_gpc[] = {
+        nve4_grctx_init_gpc_0,
+        nvc0_grctx_init_gpc_1,
+        nve4_grctx_init_tpc,
+        nve4_grctx_init_unk,
+        NULL
+};
+
+static struct nvc0_graph_mthd
+nve4_grctx_init_mthd[] = {
+        { 0xa097, nve4_grctx_init_a097, },
+        { 0x902d, nvc0_grctx_init_902d, },
+        { 0x902d, nvc0_grctx_init_mthd_magic, },
+        {}
+};
+
+struct nouveau_oclass *
+nve4_grctx_oclass = &(struct nvc0_grctx_oclass) {
+        .base.handle = NV_ENGCTX(GR, 0xe4),
+        .base.ofuncs = &(struct nouveau_ofuncs) {
+                .ctor = nvc0_graph_context_ctor,
+                .dtor = nvc0_graph_context_dtor,
+                .init = _nouveau_graph_context_init,
+                .fini = _nouveau_graph_context_fini,
+                .rd32 = _nouveau_graph_context_rd32,
+                .wr32 = _nouveau_graph_context_wr32,
+        },
+        .main = nve4_grctx_generate_main,
+        .mods = nve4_grctx_generate_mods,
+        .unkn = nve4_grctx_generate_unkn,
+        .hub  = nve4_grctx_init_hub,
+        .gpc  = nve4_grctx_init_gpc,
+        .icmd = nve4_grctx_init_icmd,
+        .mthd = nve4_grctx_init_mthd,
+}.base;
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/ctxnvf0.c b/drivers/gpu/drm/nouveau/core/engine/graph/ctxnvf0.c
new file mode 100644
index 000000000000..dcb2ebb8c29d
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/core/engine/graph/ctxnvf0.c
@@ -0,0 +1,328 @@
+/*
+ * Copyright 2013 Red Hat Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Ben Skeggs <bskeggs@redhat.com>
+ */
+
+#include "nvc0.h"
+
+static struct nvc0_graph_init
+nvf0_grctx_init_unk40xx[] = {
+        { 0x404004,   8, 0x04, 0x00000000 },
+        { 0x404024,   1, 0x04, 0x0000e000 },
+        { 0x404028,   8, 0x04, 0x00000000 },
+        { 0x4040a8,   8, 0x04, 0x00000000 },
+        { 0x4040c8,   1, 0x04, 0xf800008f },
+        { 0x4040d0,   6, 0x04, 0x00000000 },
+        { 0x4040e8,   1, 0x04, 0x00001000 },
+        { 0x4040f8,   1, 0x04, 0x00000000 },
+        { 0x404100,  10, 0x04, 0x00000000 },
+        { 0x404130,   2, 0x04, 0x00000000 },
+        { 0x404138,   1, 0x04, 0x20000040 },
+        { 0x404150,   1, 0x04, 0x0000002e },
+        { 0x404154,   1, 0x04, 0x00000400 },
+        { 0x404158,   1, 0x04, 0x00000200 },
+        { 0x404164,   1, 0x04, 0x00000055 },
+        { 0x40417c,   2, 0x04, 0x00000000 },
+        { 0x4041a0,   4, 0x04, 0x00000000 },
+        { 0x404200,   1, 0x04, 0x0000a197 },
+        { 0x404204,   1, 0x04, 0x0000a1c0 },
+        { 0x404208,   1, 0x04, 0x0000a140 },
+        { 0x40420c,   1, 0x04, 0x0000902d },
+        {}
+};
+
+static struct nvc0_graph_init
+nvf0_grctx_init_unk44xx[] = {
+        { 0x404404,  12, 0x04, 0x00000000 },
+        { 0x404438,   1, 0x04, 0x00000000 },
+        { 0x404460,   2, 0x04, 0x00000000 },
+        { 0x404468,   1, 0x04, 0x00ffffff },
+        { 0x40446c,   1, 0x04, 0x00000000 },
+        { 0x404480,   1, 0x04, 0x00000001 },
+        { 0x404498,   1, 0x04, 0x00000001 },
+        {}
+};
+
+static struct nvc0_graph_init
+nvf0_grctx_init_unk5bxx[] = {
+        { 0x405b00,   1, 0x04, 0x00000000 },
+        { 0x405b10,   1, 0x04, 0x00001000 },
+        { 0x405b20,   1, 0x04, 0x04000000 },
+        {}
+};
+
+static struct nvc0_graph_init
+nvf0_grctx_init_unk60xx[] = {
+        { 0x406020,   1, 0x04, 0x034103c1 },
+        { 0x406028,   4, 0x04, 0x00000001 },
+        {}
+};
+
+static struct nvc0_graph_init
+nvf0_grctx_init_unk64xx[] = {
+        { 0x4064a8,   1, 0x04, 0x00000000 },
+        { 0x4064ac,   1, 0x04, 0x00003fff },
+        { 0x4064b0,   3, 0x04, 0x00000000 },
+        { 0x4064c0,   1, 0x04, 0x802000f0 },
+        { 0x4064c4,   1, 0x04, 0x0192ffff },
+        { 0x4064c8,   1, 0x04, 0x018007c0 },
+        { 0x4064cc,   9, 0x04, 0x00000000 },
+        { 0x4064fc,   1, 0x04, 0x0000022a },
+        {}
+};
+
+static struct nvc0_graph_init
+nvf0_grctx_init_unk88xx[] = {
+        { 0x408800,   1, 0x04, 0x12802a3c },
+        { 0x408804,   1, 0x04, 0x00000040 },
+        { 0x408808,   1, 0x04, 0x1003e005 },
+        { 0x408840,   1, 0x04, 0x0000000b },
+        { 0x408900,   1, 0x04, 0x3080b801 },
+        { 0x408904,   1, 0x04, 0x62000001 },
+        { 0x408908,   1, 0x04, 0x00c8102f },
+        { 0x408980,   1, 0x04, 0x0000011d },
+        {}
+};
+
+static struct nvc0_graph_init
+nvf0_grctx_init_gpc_0[] = {
+        { 0x418380,   1, 0x04, 0x00000016 },
+        { 0x418400,   1, 0x04, 0x38004e00 },
+        { 0x418404,   1, 0x04, 0x71e0ffff },
+        { 0x41840c,   1, 0x04, 0x00001008 },
+        { 0x418410,   1, 0x04, 0x0fff0fff },
+        { 0x418414,   1, 0x04, 0x02200fff },
+        { 0x418450,   6, 0x04, 0x00000000 },
+        { 0x418468,   1, 0x04, 0x00000001 },
+        { 0x41846c,   2, 0x04, 0x00000000 },
+        { 0x418600,   1, 0x04, 0x0000001f },
+        { 0x418684,   1, 0x04, 0x0000000f },
+        { 0x418700,   1, 0x04, 0x00000002 },
+        { 0x418704,   1, 0x04, 0x00000080 },
+        { 0x418708,   3, 0x04, 0x00000000 },
+        { 0x418800,   1, 0x04, 0x7006860a },
+        { 0x418808,   1, 0x04, 0x00000000 },
+        { 0x41880c,   1, 0x04, 0x00000030 },
+        { 0x418810,   1, 0x04, 0x00000000 },
+        { 0x418828,   1, 0x04, 0x00000044 },
+        { 0x418830,   1, 0x04, 0x10000001 },
+        { 0x4188d8,   1, 0x04, 0x00000008 },
+        { 0x4188e0,   1, 0x04, 0x01000000 },
+        { 0x4188e8,   5, 0x04, 0x00000000 },
+        { 0x4188fc,   1, 0x04, 0x20100018 },
+        { 0x41891c,   1, 0x04, 0x00ff00ff },
+        { 0x418924,   1, 0x04, 0x00000000 },
+        { 0x418928,   1, 0x04, 0x00ffff00 },
+        { 0x41892c,   1, 0x04, 0x0000ff00 },
+        { 0x418b00,   1, 0x04, 0x00000006 },
+        { 0x418b08,   1, 0x04, 0x0a418820 },
+        { 0x418b0c,   1, 0x04, 0x062080e6 },
+        { 0x418b10,   1, 0x04, 0x020398a4 },
+        { 0x418b14,   1, 0x04, 0x0e629062 },
+        { 0x418b18,   1, 0x04, 0x0a418820 },
+        { 0x418b1c,   1, 0x04, 0x000000e6 },
+        { 0x418bb8,   1, 0x04, 0x00000103 },
+        { 0x418c08,   1, 0x04, 0x00000001 },
+        { 0x418c10,   8, 0x04, 0x00000000 },
+        { 0x418c40,   1, 0x04, 0xffffffff },
+        { 0x418c6c,   1, 0x04, 0x00000001 },
+        { 0x418c80,   1, 0x04, 0x20200004 },
+        { 0x418c8c,   1, 0x04, 0x00000001 },
+        { 0x418d24,   1, 0x04, 0x00000000 },
+        { 0x419000,   1, 0x04, 0x00000780 },
+        { 0x419004,   2, 0x04, 0x00000000 },
+        { 0x419014,   1, 0x04, 0x00000004 },
+        {}
+};
+
+static struct nvc0_graph_init
+nvf0_grctx_init_tpc[] = {
+        { 0x419848,   1, 0x04, 0x00000000 },
+        { 0x419864,   1, 0x04, 0x00000129 },
+        { 0x419888,   1, 0x04, 0x00000000 },
+        { 0x419a00,   1, 0x04, 0x000000f0 },
+        { 0x419a04,   1, 0x04, 0x00000001 },
+        { 0x419a08,   1, 0x04, 0x00000021 },
+        { 0x419a0c,   1, 0x04, 0x00020000 },
+        { 0x419a10,   1, 0x04, 0x00000000 },
+        { 0x419a14,   1, 0x04, 0x00000200 },
+        { 0x419a1c,   1, 0x04, 0x0000c000 },
+        { 0x419a20,   1, 0x04, 0x00020800 },
+        { 0x419a30,   1, 0x04, 0x00000001 },
+        { 0x419ac4,   1, 0x04, 0x0037f440 },
+        { 0x419c00,   1, 0x04, 0x0000001a },
+        { 0x419c04,   1, 0x04, 0x80000006 },
+        { 0x419c08,   1, 0x04, 0x00000002 },
+        { 0x419c20,   1, 0x04, 0x00000000 },
+        { 0x419c24,   1, 0x04, 0x00084210 },
+        { 0x419c28,   1, 0x04, 0x3efbefbe },
+        { 0x419ce8,   1, 0x04, 0x00000000 },
+        { 0x419cf4,   1, 0x04, 0x00000203 },
+        { 0x419e04,   1, 0x04, 0x00000000 },
+        { 0x419e08,   1, 0x04, 0x0000001d },
+        { 0x419e0c,   1, 0x04, 0x00000000 },
+        { 0x419e10,   1, 0x04, 0x00001c02 },
+        { 0x419e44,   1, 0x04, 0x0013eff2 },
+        { 0x419e48,   1, 0x04, 0x00000000 },
+        { 0x419e4c,   1, 0x04, 0x0000007f },
+        { 0x419e50,   2, 0x04, 0x00000000 },
+        { 0x419e58,   1, 0x04, 0x00000001 },
+        { 0x419e5c,   3, 0x04, 0x00000000 },
+        { 0x419e68,   1, 0x04, 0x00000002 },
+        { 0x419e6c,  12, 0x04, 0x00000000 },
+        { 0x419eac,   1, 0x04, 0x00001fcf },
+        { 0x419eb0,   1, 0x04, 0x0db00da0 },
+        { 0x419eb8,   1, 0x04, 0x00000000 },
+        { 0x419ec8,   1, 0x04, 0x0001304f },
+        { 0x419f30,   4, 0x04, 0x00000000 },
+        { 0x419f40,   1, 0x04, 0x00000018 },
+        { 0x419f44,   3, 0x04, 0x00000000 },
+        { 0x419f58,   1, 0x04, 0x00000000 },
+        { 0x419f70,   1, 0x04, 0x00007300 },
+        { 0x419f78,   1, 0x04, 0x000000eb },
+        { 0x419f7c,   1, 0x04, 0x00000404 },
+        {}
+};
+
+static struct nvc0_graph_init
+nvf0_grctx_init_unk[] = {
+        { 0x41be24,   1, 0x04, 0x00000006 },
+        { 0x41bec0,   1, 0x04, 0x10000000 },
+        { 0x41bec4,   1, 0x04, 0x00037f7f },
+        { 0x41bee4,   1, 0x04, 0x00000000 },
+        { 0x41bf00,   1, 0x04, 0x0a418820 },
+        { 0x41bf04,   1, 0x04, 0x062080e6 },
+        { 0x41bf08,   1, 0x04, 0x020398a4 },
+        { 0x41bf0c,   1, 0x04, 0x0e629062 },
+        { 0x41bf10,   1, 0x04, 0x0a418820 },
+        { 0x41bf14,   1, 0x04, 0x000000e6 },
+        { 0x41bfd0,   1, 0x04, 0x00900103 },
+        { 0x41bfe0,   1, 0x04, 0x00400001 },
+        { 0x41bfe4,   1, 0x04, 0x00000000 },
+        {}
+};
+
+static void
+nvf0_grctx_generate_mods(struct nvc0_graph_priv *priv, struct nvc0_grctx *info)
+{
+        u32 magic[GPC_MAX][4];
+        u32 offset;
+        int gpc;
+
+        mmio_data(0x003000, 0x0100, NV_MEM_ACCESS_RW | NV_MEM_ACCESS_SYS);
+        mmio_data(0x008000, 0x0100, NV_MEM_ACCESS_RW | NV_MEM_ACCESS_SYS);
+        mmio_data(0x060000, 0x1000, NV_MEM_ACCESS_RW);
+        mmio_list(0x40800c, 0x00000000,  8, 1);
+        mmio_list(0x408010, 0x80000000,  0, 0);
+        mmio_list(0x419004, 0x00000000,  8, 1);
+        mmio_list(0x419008, 0x00000000,  0, 0);
+        mmio_list(0x4064cc, 0x80000000,  0, 0);
+        mmio_list(0x408004, 0x00000000,  8, 0);
+        mmio_list(0x408008, 0x80000030,  0, 0);
+        mmio_list(0x418808, 0x00000000,  8, 0);
+        mmio_list(0x41880c, 0x80000030,  0, 0);
+        mmio_list(0x4064c8, 0x01800600,  0, 0);
+        mmio_list(0x418810, 0x80000000, 12, 2);
+        mmio_list(0x419848, 0x10000000, 12, 2);
+
+        mmio_list(0x405830, 0x02180648,  0, 0);
+        mmio_list(0x4064c4, 0x0192ffff,  0, 0);
+
+        for (gpc = 0, offset = 0; gpc < priv->gpc_nr; gpc++) {
+                u16 magic0 = 0x0218 * (priv->tpc_nr[gpc] - 1);
+                u16 magic1 = 0x0648 * (priv->tpc_nr[gpc] - 1);
+                u16 magic2 = 0x0218;
+                u16 magic3 = 0x0648;
+                magic[gpc][0]  = 0x10000000 | (magic0 << 16) | offset;
+                magic[gpc][1]  = 0x00000000 | (magic1 << 16);
+                offset += 0x0324 * (priv->tpc_nr[gpc] - 1);;
+                magic[gpc][2]  = 0x10000000 | (magic2 << 16) | offset;
+                magic[gpc][3]  = 0x00000000 | (magic3 << 16);
+                offset += 0x0324;
+        }
+
+        for (gpc = 0; gpc < priv->gpc_nr; gpc++) {
+                mmio_list(GPC_UNIT(gpc, 0x30c0), magic[gpc][0], 0, 0);
+                mmio_list(GPC_UNIT(gpc, 0x30e4), magic[gpc][1] | offset, 0, 0);
+                offset += 0x07ff * (priv->tpc_nr[gpc] - 1);
+                mmio_list(GPC_UNIT(gpc, 0x32c0), magic[gpc][2], 0, 0);
+                mmio_list(GPC_UNIT(gpc, 0x32e4), magic[gpc][3] | offset, 0, 0);
+                offset += 0x07ff;
+        }
+
+        mmio_list(0x17e91c, 0x06060609, 0, 0);
+        mmio_list(0x17e920, 0x00090a05, 0, 0);
+}
+
+static struct nvc0_graph_init *
+nvf0_grctx_init_hub[] = {
+        nvc0_grctx_init_base,
+        nvf0_grctx_init_unk40xx,
+        nvf0_grctx_init_unk44xx,
+        nve4_grctx_init_unk46xx,
+        nve4_grctx_init_unk47xx,
+        nve4_grctx_init_unk58xx,
+        nvf0_grctx_init_unk5bxx,
+        nvf0_grctx_init_unk60xx,
+        nvf0_grctx_init_unk64xx,
+        nve4_grctx_init_unk80xx,
+        nvf0_grctx_init_unk88xx,
+        nvd9_grctx_init_rop,
+        NULL
+};
+
+struct nvc0_graph_init *
+nvf0_grctx_init_gpc[] = {
+        nvf0_grctx_init_gpc_0,
+        nvc0_grctx_init_gpc_1,
+        nvf0_grctx_init_tpc,
+        nvf0_grctx_init_unk,
+        NULL
+};
+
+static struct nvc0_graph_mthd
+nvf0_grctx_init_mthd[] = {
+        { 0xa197, nvc1_grctx_init_9097, },
+        { 0x902d, nvc0_grctx_init_902d, },
+        { 0x902d, nvc0_grctx_init_mthd_magic, },
+        {}
+};
+
+struct nouveau_oclass *
+nvf0_grctx_oclass = &(struct nvc0_grctx_oclass) {
+        .base.handle = NV_ENGCTX(GR, 0xf0),
+        .base.ofuncs = &(struct nouveau_ofuncs) {
+                .ctor = nvc0_graph_context_ctor,
+                .dtor = nvc0_graph_context_dtor,
+                .init = _nouveau_graph_context_init,
+                .fini = _nouveau_graph_context_fini,
+                .rd32 = _nouveau_graph_context_rd32,
+                .wr32 = _nouveau_graph_context_wr32,
+        },
+        .main = nve4_grctx_generate_main,
+        .mods = nvf0_grctx_generate_mods,
+        .unkn = nve4_grctx_generate_unkn,
+        .hub  = nvf0_grctx_init_hub,
+        .gpc  = nvf0_grctx_init_gpc,
+        .icmd = nvc0_grctx_init_icmd,
+        .mthd = nvf0_grctx_init_mthd,
+}.base;
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/nvc0.fuc b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/com.fuc
index e6b228844a32..5d24b6de16cc 100644
--- a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/nvc0.fuc
+++ b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/com.fuc
@@ -23,42 +23,7 @@
  * Authors: Ben Skeggs
  */
 
-define(`mmctx_data', `.b32 eval((($2 - 1) << 26) | $1)')
-define(`queue_init', `.skip eval((2 * 4) + ((8 * 4) * 2))')
-
-ifdef(`include_code', `
-// Error codes
-define(`E_BAD_COMMAND', 0x01)
-define(`E_CMD_OVERFLOW', 0x02)
-
-// Util macros to help with debugging ucode hangs etc
-define(`T_WAIT', 0)
-define(`T_MMCTX', 1)
-define(`T_STRWAIT', 2)
-define(`T_STRINIT', 3)
-define(`T_AUTO', 4)
-define(`T_CHAN', 5)
-define(`T_LOAD', 6)
-define(`T_SAVE', 7)
-define(`T_LCHAN', 8)
-define(`T_LCTXH', 9)
-
-define(`trace_set', `
-        mov $r8 0x83c
-        shl b32 $r8 6
-        clear b32 $r9
-        bset $r9 $1
-        iowr I[$r8 + 0x000] $r9         // CC_SCRATCH[7]
-')
-
-define(`trace_clr', `
-        mov $r8 0x85c
-        shl b32 $r8 6
-        clear b32 $r9
-        bset $r9 $1
-        iowr I[$r8 + 0x000] $r9         // CC_SCRATCH[7]
-')
-
+#ifdef INCLUDE_CODE
 // queue_put - add request to queue
 //
 // In : $r13 queue pointer
@@ -178,27 +143,37 @@ watchdog_clear:
         iowr I[$r8 + 0x000] $r0
         ret
 
-// wait_done{z,o} - wait on FUC_DONE bit to become clear/set
+// wait_donez - wait on FUC_DONE bit to become clear
+//
+// In : $r10 bit to wait on
+//
+wait_donez:
+        trace_set(T_WAIT);
+        nv_iowr(NV_PGRAPH_FECS_CC_SCRATCH_VAL(6), 0, $r10)
+        wait_donez_ne:
+                nv_iord($r8, NV_PGRAPH_FECS_SIGNAL, 0)
+                xbit $r8 $r8 $r10
+                bra ne #wait_donez_ne
+        trace_clr(T_WAIT)
+        ret
+
+// wait_doneo - wait on FUC_DONE bit to become set
 //
 // In : $r10 bit to wait on
 //
-define(`wait_done', `
-$1:
+wait_doneo:
         trace_set(T_WAIT);
         mov $r8 0x818
         shl b32 $r8 6
-        iowr I[$r8 + 0x000] $r10        // CC_SCRATCH[6] = wait bit
-        wait_done_$1:
+        iowr I[$r8 + 0x000] $r10
+        wait_doneo_e:
                 mov $r8 0x400
                 shl b32 $r8 6
-                iord $r8 I[$r8 + 0x000] // DONE
+                iord $r8 I[$r8 + 0x000]
                 xbit $r8 $r8 $r10
-                bra $2 #wait_done_$1
+                bra e #wait_doneo_e
         trace_clr(T_WAIT)
         ret
-')
-wait_done(wait_donez, ne)
-wait_done(wait_doneo, e)
 
 // mmctx_size - determine size of a mmio list transfer
 //
@@ -397,4 +372,4 @@ strand_ctx_init:
         sub b32 $r15 $r14 $r15
         trace_clr(T_STRINIT)
         ret
-')
+#endif
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpc.fuc b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpc.fuc
new file mode 100644
index 000000000000..5547c1b3f4f2
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpc.fuc
@@ -0,0 +1,404 @@
+/* fuc microcode for nvc0 PGRAPH/GPC
+ *
+ * Copyright 2011 Red Hat Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Ben Skeggs
+ */
+
+/* TODO
+ * - bracket certain functions with scratch writes, useful for debugging
+ * - watchdog timer around ctx operations
+ */
+
+#ifdef INCLUDE_DATA
+gpc_mmio_list_head:     .b32 #mmio_list_base
+gpc_mmio_list_tail:
+tpc_mmio_list_head:     .b32 #mmio_list_base
+tpc_mmio_list_tail:
+unk_mmio_list_head:     .b32 #mmio_list_base
+unk_mmio_list_tail:     .b32 #mmio_list_base
+
+gpc_id:                 .b32 0
+
+tpc_count:              .b32 0
+tpc_mask:               .b32 0
+
+#if NV_PGRAPH_GPCX_UNK__SIZE > 0
+unk_count:              .b32 0
+unk_mask:               .b32 0
+#endif
+
+cmd_queue:              queue_init
+
+mmio_list_base:
+#endif
+
+#ifdef INCLUDE_CODE
+// reports an exception to the host
+//
+// In: $r15 error code (see nvc0.fuc)
+//
+error:
+        push $r14
+        mov $r14 -0x67ec        // 0x9814
+        sethi $r14 0x400000
+        call #nv_wr32           // HUB_CTXCTL_CC_SCRATCH[5] = error code
+        add b32 $r14 0x41c
+        mov $r15 1
+        call #nv_wr32           // HUB_CTXCTL_INTR_UP_SET
+        pop $r14
+        ret
+
+// GPC fuc initialisation, executed by triggering ucode start, will
+// fall through to main loop after completion.
+//
+// Input:
+//   CC_SCRATCH[1]: context base
+//
+// Output:
+//   CC_SCRATCH[0]:
+//           31:31: set to signal completion
+//   CC_SCRATCH[1]:
+//            31:0: GPC context size
+//
+init:
+        clear b32 $r0
+        mov $sp $r0
+
+        // enable fifo access
+        mov $r1 0x1200
+        mov $r2 2
+        iowr I[$r1 + 0x000] $r2         // FIFO_ENABLE
+
+        // setup i0 handler, and route all interrupts to it
+        mov $r1 #ih
+        mov $iv0 $r1
+        mov $r1 0x400
+        iowr I[$r1 + 0x300] $r0         // INTR_DISPATCH
+
+        // enable fifo interrupt
+        mov $r2 4
+        iowr I[$r1 + 0x000] $r2         // INTR_EN_SET
+
+        // enable interrupts
+        bset $flags ie0
+
+        // figure out which GPC we are, and how many TPCs we have
+        mov $r1 0x608
+        shl b32 $r1 6
+        iord $r2 I[$r1 + 0x000]         // UNITS
+        mov $r3 1
+        and $r2 0x1f
+        shl b32 $r3 $r2
+        sub b32 $r3 1
+        st b32 D[$r0 + #tpc_count] $r2
+        st b32 D[$r0 + #tpc_mask] $r3
+        add b32 $r1 0x400
+        iord $r2 I[$r1 + 0x000]         // MYINDEX
+        st b32 D[$r0 + #gpc_id] $r2
+
+#if NV_PGRAPH_GPCX_UNK__SIZE > 0
+        // figure out which, and how many, UNKs are actually present
+        mov $r14 0x0c30
+        sethi $r14 0x500000
+        clear b32 $r2
+        clear b32 $r3
+        clear b32 $r4
+        init_unk_loop:
+                call #nv_rd32
+                cmp b32 $r15 0
+                bra z #init_unk_next
+                        mov $r15 1
+                        shl b32 $r15 $r2
+                        or $r4 $r15
+                        add b32 $r3 1
+                init_unk_next:
+                add b32 $r2 1
+                add b32 $r14 4
+                cmp b32 $r2 NV_PGRAPH_GPCX_UNK__SIZE
+                bra ne #init_unk_loop
+        init_unk_done:
+        st b32 D[$r0 + #unk_count] $r3
+        st b32 D[$r0 + #unk_mask] $r4
+#endif
+
+        // initialise context base, and size tracking
+        nv_iord($r2, NV_PGRAPH_GPCX_GPCCS_CC_SCRATCH_VAL(1), 0)
+        clear b32 $r3           // track GPC context size here
+
+        // set mmctx base addresses now so we don't have to do it later,
+        // they don't currently ever change
+        mov $r4 0x700
+        shl b32 $r4 6
+        shr b32 $r5 $r2 8
+        iowr I[$r4 + 0x000] $r5         // MMCTX_SAVE_SWBASE
+        iowr I[$r4 + 0x100] $r5         // MMCTX_LOAD_SWBASE
+
+        // calculate GPC mmio context size
+        ld b32 $r14 D[$r0 + #gpc_mmio_list_head]
+        ld b32 $r15 D[$r0 + #gpc_mmio_list_tail]
+        call #mmctx_size
+        add b32 $r2 $r15
+        add b32 $r3 $r15
+
+        // calculate per-TPC mmio context size
+        ld b32 $r14 D[$r0 + #tpc_mmio_list_head]
+        ld b32 $r15 D[$r0 + #tpc_mmio_list_tail]
+        call #mmctx_size
+        ld b32 $r14 D[$r0 + #tpc_count]
+        mulu $r14 $r15
+        add b32 $r2 $r14
+        add b32 $r3 $r14
+
+#if NV_PGRAPH_GPCX_UNK__SIZE > 0
+        // calculate per-UNK mmio context size
+        ld b32 $r14 D[$r0 + #unk_mmio_list_head]
+        ld b32 $r15 D[$r0 + #unk_mmio_list_tail]
+        call #mmctx_size
+        ld b32 $r14 D[$r0 + #unk_count]
+        mulu $r14 $r15
+        add b32 $r2 $r14
+        add b32 $r3 $r14
+#endif
+
+        // round up base/size to 256 byte boundary (for strand SWBASE)
+        add b32 $r4 0x1300
+        shr b32 $r3 2
+        iowr I[$r4 + 0x000] $r3         // MMCTX_LOAD_COUNT, wtf for?!?
+        shr b32 $r2 8
+        shr b32 $r3 6
+        add b32 $r2 1
+        add b32 $r3 1
+        shl b32 $r2 8
+        shl b32 $r3 8
+
+        // calculate size of strand context data
+        mov b32 $r15 $r2
+        call #strand_ctx_init
+        add b32 $r3 $r15
+
+        // save context size, and tell HUB we're done
+        nv_iowr(NV_PGRAPH_GPCX_GPCCS_CC_SCRATCH_VAL(1), 0, $r3)
+        clear b32 $r2
+        bset $r2 31
+        nv_iowr(NV_PGRAPH_GPCX_GPCCS_CC_SCRATCH_SET(0), 0, $r2)
+
+// Main program loop, very simple, sleeps until woken up by the interrupt
+// handler, pulls a command from the queue and executes its handler
+//
+main:
+        bset $flags $p0
+        sleep $p0
+        mov $r13 #cmd_queue
+        call #queue_get
+        bra $p1 #main
+
+        // 0x0000-0x0003 are all context transfers
+        cmpu b32 $r14 0x04
+        bra nc #main_not_ctx_xfer
+                // fetch $flags and mask off $p1/$p2
+                mov $r1 $flags
+                mov $r2 0x0006
+                not b32 $r2
+                and $r1 $r2
+                // set $p1/$p2 according to transfer type
+                shl b32 $r14 1
+                or $r1 $r14
+                mov $flags $r1
+                // transfer context data
+                call #ctx_xfer
+                bra #main
+
+        main_not_ctx_xfer:
+        shl b32 $r15 $r14 16
+        or $r15 E_BAD_COMMAND
+        call #error
+        bra #main
+
+// interrupt handler
+ih:
+        push $r8
+        mov $r8 $flags
+        push $r8
+        push $r9
+        push $r10
+        push $r11
+        push $r13
+        push $r14
+        push $r15
+        clear b32 $r0
+
+        // incoming fifo command?
+        iord $r10 I[$r0 + 0x200]        // INTR
+        and $r11 $r10 0x00000004
+        bra e #ih_no_fifo
+                // queue incoming fifo command for later processing
+                mov $r11 0x1900
+                mov $r13 #cmd_queue
+                iord $r14 I[$r11 + 0x100]       // FIFO_CMD
+                iord $r15 I[$r11 + 0x000]       // FIFO_DATA
+                call #queue_put
+                add b32 $r11 0x400
+                mov $r14 1
+                iowr I[$r11 + 0x000] $r14       // FIFO_ACK
+
+        // ack, and wake up main()
+        ih_no_fifo:
+        iowr I[$r0 + 0x100] $r10        // INTR_ACK
+
+        pop $r15
+        pop $r14
+        pop $r13
+        pop $r11
+        pop $r10
+        pop $r9
+        pop $r8
+        mov $flags $r8
+        pop $r8
+        bclr $flags $p0
+        iret
+
+// Set this GPC's bit in HUB_BAR, used to signal completion of various
+// activities to the HUB fuc
+//
+hub_barrier_done:
+        mov $r15 1
+        ld b32 $r14 D[$r0 + #gpc_id]
+        shl b32 $r15 $r14
+        mov $r14 -0x6be8        // 0x409418 - HUB_BAR_SET
+        sethi $r14 0x400000
+        call #nv_wr32
+        ret
+
+// Disables various things, waits a bit, and re-enables them..
+//
+// Not sure how exactly this helps, perhaps "ENABLE" is not such a
+// good description for the bits we turn off?  Anyways, without this,
+// funny things happen.
+//
+ctx_redswitch:
+        mov $r14 0x614
+        shl b32 $r14 6
+        mov $r15 0x020
+        iowr I[$r14] $r15       // GPC_RED_SWITCH = POWER
+        mov $r15 8
+        ctx_redswitch_delay:
+                sub b32 $r15 1
+                bra ne #ctx_redswitch_delay
+        mov $r15 0xa20
+        iowr I[$r14] $r15       // GPC_RED_SWITCH = UNK11, ENABLE, POWER
+        ret
+
+// Transfer GPC context data between GPU and storage area
+//
+// In: $r15 context base address
+//     $p1 clear on save, set on load
+//     $p2 set if opposite direction done/will be done, so:
+//              on save it means: "a load will follow this save"
+//              on load it means: "a save preceeded this load"
+//
+ctx_xfer:
+        // set context base address
+        mov $r1 0xa04
+        shl b32 $r1 6
+        iowr I[$r1 + 0x000] $r15// MEM_BASE
+        bra not $p1 #ctx_xfer_not_load
+                call #ctx_redswitch
+        ctx_xfer_not_load:
+
+        // strands
+        mov $r1 0x4afc
+        sethi $r1 0x20000
+        mov $r2 0xc
+        iowr I[$r1] $r2         // STRAND_CMD(0x3f) = 0x0c
+        call #strand_wait
+        mov $r2 0x47fc
+        sethi $r2 0x20000
+        iowr I[$r2] $r0         // STRAND_FIRST_GENE(0x3f) = 0x00
+        xbit $r2 $flags $p1
+        add b32 $r2 3
+        iowr I[$r1] $r2         // STRAND_CMD(0x3f) = 0x03/0x04 (SAVE/LOAD)
+
+        // mmio context
+        xbit $r10 $flags $p1    // direction
+        or $r10 2               // first
+        mov $r11 0x0000
+        sethi $r11 0x500000
+        ld b32 $r12 D[$r0 + #gpc_id]
+        shl b32 $r12 15
+        add b32 $r11 $r12       // base = NV_PGRAPH_GPCn
+        ld b32 $r12 D[$r0 + #gpc_mmio_list_head]
+        ld b32 $r13 D[$r0 + #gpc_mmio_list_tail]
+        mov $r14 0              // not multi
+        call #mmctx_xfer
+
+        // per-TPC mmio context
+        xbit $r10 $flags $p1    // direction
+#if !NV_PGRAPH_GPCX_UNK__SIZE
+        or $r10 4               // last
+#endif
+        mov $r11 0x4000
+        sethi $r11 0x500000     // base = NV_PGRAPH_GPC0_TPC0
+        ld b32 $r12 D[$r0 + #gpc_id]
+        shl b32 $r12 15
+        add b32 $r11 $r12       // base = NV_PGRAPH_GPCn_TPC0
+        ld b32 $r12 D[$r0 + #tpc_mmio_list_head]
+        ld b32 $r13 D[$r0 + #tpc_mmio_list_tail]
+        ld b32 $r15 D[$r0 + #tpc_mask]
+        mov $r14 0x800          // stride = 0x800
+        call #mmctx_xfer
+
+#if NV_PGRAPH_GPCX_UNK__SIZE > 0
+        // per-UNK mmio context
+        xbit $r10 $flags $p1    // direction
+        or $r10 4               // last
+        mov $r11 0x3000
+        sethi $r11 0x500000     // base = NV_PGRAPH_GPC0_UNK0
+        ld b32 $r12 D[$r0 + #gpc_id]
+        shl b32 $r12 15
+        add b32 $r11 $r12       // base = NV_PGRAPH_GPCn_UNK0
+        ld b32 $r12 D[$r0 + #unk_mmio_list_head]
+        ld b32 $r13 D[$r0 + #unk_mmio_list_tail]
+        ld b32 $r15 D[$r0 + #unk_mask]
+        mov $r14 0x200          // stride = 0x200
+        call #mmctx_xfer
+#endif
+
+        // wait for strands to finish
+        call #strand_wait
+
+        // if load, or a save without a load following, do some
+        // unknown stuff that's done after finishing a block of
+        // strand commands
+        bra $p1 #ctx_xfer_post
+        bra not $p2 #ctx_xfer_done
+        ctx_xfer_post:
+                mov $r1 0x4afc
+                sethi $r1 0x20000
+                mov $r2 0xd
+                iowr I[$r1] $r2         // STRAND_CMD(0x3f) = 0x0d
+                call #strand_wait
+
+        // mark completion in HUB's barrier
+        ctx_xfer_done:
+        call #hub_barrier_done
+        ret
+#endif
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvc0.fuc b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvc0.fuc
index f7055af0f2a6..5ae06a2d64c9 100644
--- a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvc0.fuc
+++ b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvc0.fuc
@@ -1,6 +1,5 @@
-/* fuc microcode for nvc0 PGRAPH/GPC
- *
- * Copyright 2011 Red Hat Inc.
+/*
+ * Copyright 2013 Red Hat Inc.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -20,525 +19,24 @@
  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  * OTHER DEALINGS IN THE SOFTWARE.
  *
- * Authors: Ben Skeggs
+ * Authors: Ben Skeggs <bskeggs@redhat.com>
  */
 
-/* To build:
- *    m4 gpcnvc0.fuc | envyas -a -w -m fuc -V fuc3 -o gpcnvc0.fuc.h
- */
+#define NV_PGRAPH_GPCX_UNK__SIZE                                     0x00000000
 
-/* TODO
- * - bracket certain functions with scratch writes, useful for debugging
- * - watchdog timer around ctx operations
- */
+#define CHIPSET GF100
+#include "macros.fuc"
 
 .section #nvc0_grgpc_data
-include(`nvc0.fuc')
-gpc_id:                 .b32 0
-gpc_mmio_list_head:     .b32 0
-gpc_mmio_list_tail:     .b32 0
-
-tpc_count:              .b32 0
-tpc_mask:               .b32 0
-tpc_mmio_list_head:     .b32 0
-tpc_mmio_list_tail:     .b32 0
-
-cmd_queue:              queue_init
-
-// chipset descriptions
-chipsets:
-.b8  0xc0 0 0 0
-.b16 #nvc0_gpc_mmio_head
-.b16 #nvc0_gpc_mmio_tail
-.b16 #nvc0_tpc_mmio_head
-.b16 #nvc0_tpc_mmio_tail
-.b8  0xc1 0 0 0
-.b16 #nvc0_gpc_mmio_head
-.b16 #nvc1_gpc_mmio_tail
-.b16 #nvc0_tpc_mmio_head
-.b16 #nvc1_tpc_mmio_tail
-.b8  0xc3 0 0 0
-.b16 #nvc0_gpc_mmio_head
-.b16 #nvc0_gpc_mmio_tail
-.b16 #nvc0_tpc_mmio_head
-.b16 #nvc3_tpc_mmio_tail
-.b8  0xc4 0 0 0
-.b16 #nvc0_gpc_mmio_head
-.b16 #nvc0_gpc_mmio_tail
-.b16 #nvc0_tpc_mmio_head
-.b16 #nvc3_tpc_mmio_tail
-.b8  0xc8 0 0 0
-.b16 #nvc0_gpc_mmio_head
-.b16 #nvc0_gpc_mmio_tail
-.b16 #nvc0_tpc_mmio_head
-.b16 #nvc0_tpc_mmio_tail
-.b8  0xce 0 0 0
-.b16 #nvc0_gpc_mmio_head
-.b16 #nvc0_gpc_mmio_tail
-.b16 #nvc0_tpc_mmio_head
-.b16 #nvc3_tpc_mmio_tail
-.b8  0xcf 0 0 0
-.b16 #nvc0_gpc_mmio_head
-.b16 #nvc0_gpc_mmio_tail
-.b16 #nvc0_tpc_mmio_head
-.b16 #nvcf_tpc_mmio_tail
-.b8  0xd9 0 0 0
-.b16 #nvd9_gpc_mmio_head
-.b16 #nvd9_gpc_mmio_tail
-.b16 #nvd9_tpc_mmio_head
-.b16 #nvd9_tpc_mmio_tail
-.b8  0xd7 0 0 0
-.b16 #nvd9_gpc_mmio_head
-.b16 #nvd9_gpc_mmio_tail
-.b16 #nvd9_tpc_mmio_head
-.b16 #nvd9_tpc_mmio_tail
-.b8  0 0 0 0
-
-// GPC mmio lists
-nvc0_gpc_mmio_head:
-mmctx_data(0x000380, 1)
-mmctx_data(0x000400, 6)
-mmctx_data(0x000450, 9)
-mmctx_data(0x000600, 1)
-mmctx_data(0x000684, 1)
-mmctx_data(0x000700, 5)
-mmctx_data(0x000800, 1)
-mmctx_data(0x000808, 3)
-mmctx_data(0x000828, 1)
-mmctx_data(0x000830, 1)
-mmctx_data(0x0008d8, 1)
-mmctx_data(0x0008e0, 1)
-mmctx_data(0x0008e8, 6)
-mmctx_data(0x00091c, 1)
-mmctx_data(0x000924, 3)
-mmctx_data(0x000b00, 1)
-mmctx_data(0x000b08, 6)
-mmctx_data(0x000bb8, 1)
-mmctx_data(0x000c08, 1)
-mmctx_data(0x000c10, 8)
-mmctx_data(0x000c80, 1)
-mmctx_data(0x000c8c, 1)
-mmctx_data(0x001000, 3)
-mmctx_data(0x001014, 1)
-nvc0_gpc_mmio_tail:
-mmctx_data(0x000c6c, 1);
-nvc1_gpc_mmio_tail:
-
-nvd9_gpc_mmio_head:
-mmctx_data(0x000380, 1)
-mmctx_data(0x000400, 2)
-mmctx_data(0x00040c, 3)
-mmctx_data(0x000450, 9)
-mmctx_data(0x000600, 1)
-mmctx_data(0x000684, 1)
-mmctx_data(0x000700, 5)
-mmctx_data(0x000800, 1)
-mmctx_data(0x000808, 3)
-mmctx_data(0x000828, 1)
-mmctx_data(0x000830, 1)
-mmctx_data(0x0008d8, 1)
-mmctx_data(0x0008e0, 1)
-mmctx_data(0x0008e8, 6)
-mmctx_data(0x00091c, 1)
-mmctx_data(0x000924, 3)
-mmctx_data(0x000b00, 1)
-mmctx_data(0x000b08, 6)
-mmctx_data(0x000bb8, 1)
-mmctx_data(0x000c08, 1)
-mmctx_data(0x000c10, 8)
-mmctx_data(0x000c6c, 1)
-mmctx_data(0x000c80, 1)
-mmctx_data(0x000c8c, 1)
-mmctx_data(0x001000, 3)
-mmctx_data(0x001014, 1)
-nvd9_gpc_mmio_tail:
-
-// TPC mmio lists
-nvc0_tpc_mmio_head:
-mmctx_data(0x000018, 1)
-mmctx_data(0x00003c, 1)
-mmctx_data(0x000048, 1)
-mmctx_data(0x000064, 1)
-mmctx_data(0x000088, 1)
-mmctx_data(0x000200, 6)
-mmctx_data(0x00021c, 2)
-mmctx_data(0x000300, 6)
-mmctx_data(0x0003d0, 1)
-mmctx_data(0x0003e0, 2)
-mmctx_data(0x000400, 3)
-mmctx_data(0x000420, 1)
-mmctx_data(0x0004b0, 1)
-mmctx_data(0x0004e8, 1)
-mmctx_data(0x0004f4, 1)
-mmctx_data(0x000520, 2)
-mmctx_data(0x000604, 4)
-mmctx_data(0x000644, 20)
-mmctx_data(0x000698, 1)
-mmctx_data(0x000750, 2)
-nvc0_tpc_mmio_tail:
-mmctx_data(0x000758, 1)
-mmctx_data(0x0002c4, 1)
-mmctx_data(0x0006e0, 1)
-nvcf_tpc_mmio_tail:
-mmctx_data(0x0004bc, 1)
-nvc3_tpc_mmio_tail:
-mmctx_data(0x000544, 1)
-nvc1_tpc_mmio_tail:
-
-nvd9_tpc_mmio_head:
-mmctx_data(0x000018, 1)
-mmctx_data(0x00003c, 1)
-mmctx_data(0x000048, 1)
-mmctx_data(0x000064, 1)
-mmctx_data(0x000088, 1)
-mmctx_data(0x000200, 6)
-mmctx_data(0x00021c, 2)
-mmctx_data(0x0002c4, 1)
-mmctx_data(0x000300, 6)
-mmctx_data(0x0003d0, 1)
-mmctx_data(0x0003e0, 2)
-mmctx_data(0x000400, 3)
-mmctx_data(0x000420, 3)
-mmctx_data(0x0004b0, 1)
-mmctx_data(0x0004e8, 1)
-mmctx_data(0x0004f4, 1)
-mmctx_data(0x000520, 2)
-mmctx_data(0x000544, 1)
-mmctx_data(0x000604, 4)
-mmctx_data(0x000644, 20)
-mmctx_data(0x000698, 1)
-mmctx_data(0x0006e0, 1)
-mmctx_data(0x000750, 3)
-nvd9_tpc_mmio_tail:
+#define INCLUDE_DATA
+#include "com.fuc"
+#include "gpc.fuc"
+#undef INCLUDE_DATA
 
 .section #nvc0_grgpc_code
+#define INCLUDE_CODE
 bra #init
-define(`include_code')
-include(`nvc0.fuc')
-
-// reports an exception to the host
-//
-// In: $r15 error code (see nvc0.fuc)
-//
-error:
-        push $r14
-        mov $r14 -0x67ec        // 0x9814
-        sethi $r14 0x400000
-        call #nv_wr32           // HUB_CTXCTL_CC_SCRATCH[5] = error code
-        add b32 $r14 0x41c
-        mov $r15 1
-        call #nv_wr32           // HUB_CTXCTL_INTR_UP_SET
-        pop $r14
-        ret
-
-// GPC fuc initialisation, executed by triggering ucode start, will
-// fall through to main loop after completion.
-//
-// Input:
-//   CC_SCRATCH[0]: chipset (PMC_BOOT_0 read returns 0x0bad0bad... sigh)
-//   CC_SCRATCH[1]: context base
-//
-// Output:
-//   CC_SCRATCH[0]:
-//           31:31: set to signal completion
-//   CC_SCRATCH[1]:
-//            31:0: GPC context size
-//
-init:
-        clear b32 $r0
-        mov $sp $r0
-
-        // enable fifo access
-        mov $r1 0x1200
-        mov $r2 2
-        iowr I[$r1 + 0x000] $r2         // FIFO_ENABLE
-
-        // setup i0 handler, and route all interrupts to it
-        mov $r1 #ih
-        mov $iv0 $r1
-        mov $r1 0x400
-        iowr I[$r1 + 0x300] $r0         // INTR_DISPATCH
-
-        // enable fifo interrupt
-        mov $r2 4
-        iowr I[$r1 + 0x000] $r2         // INTR_EN_SET
-
-        // enable interrupts
-        bset $flags ie0
-
-        // figure out which GPC we are, and how many TPCs we have
-        mov $r1 0x608
-        shl b32 $r1 6
-        iord $r2 I[$r1 + 0x000]         // UNITS
-        mov $r3 1
-        and $r2 0x1f
-        shl b32 $r3 $r2
-        sub b32 $r3 1
-        st b32 D[$r0 + #tpc_count] $r2
-        st b32 D[$r0 + #tpc_mask] $r3
-        add b32 $r1 0x400
-        iord $r2 I[$r1 + 0x000]         // MYINDEX
-        st b32 D[$r0 + #gpc_id] $r2
-
-        // find context data for this chipset
-        mov $r2 0x800
-        shl b32 $r2 6
-        iord $r2 I[$r2 + 0x000]         // CC_SCRATCH[0]
-        mov $r1 #chipsets - 12
-        init_find_chipset:
-                add b32 $r1 12
-                ld b32 $r3 D[$r1 + 0x00]
-                cmpu b32 $r3 $r2
-                bra e #init_context
-                cmpu b32 $r3 0
-                bra ne #init_find_chipset
-                // unknown chipset
-                ret
-
-        // initialise context base, and size tracking
-        init_context:
-        mov $r2 0x800
-        shl b32 $r2 6
-        iord $r2 I[$r2 + 0x100] // CC_SCRATCH[1], initial base
-        clear b32 $r3           // track GPC context size here
-
-        // set mmctx base addresses now so we don't have to do it later,
-        // they don't currently ever change
-        mov $r4 0x700
-        shl b32 $r4 6
-        shr b32 $r5 $r2 8
-        iowr I[$r4 + 0x000] $r5         // MMCTX_SAVE_SWBASE
-        iowr I[$r4 + 0x100] $r5         // MMCTX_LOAD_SWBASE
-
-        // calculate GPC mmio context size, store the chipset-specific
-        // mmio list pointers somewhere we can get at them later without
-        // re-parsing the chipset list
-        clear b32 $r14
-        clear b32 $r15
-        ld b16 $r14 D[$r1 + 4]
-        ld b16 $r15 D[$r1 + 6]
-        st b16 D[$r0 + #gpc_mmio_list_head] $r14
-        st b16 D[$r0 + #gpc_mmio_list_tail] $r15
-        call #mmctx_size
-        add b32 $r2 $r15
-        add b32 $r3 $r15
-
-        // calculate per-TPC mmio context size, store the list pointers
-        ld b16 $r14 D[$r1 + 8]
-        ld b16 $r15 D[$r1 + 10]
-        st b16 D[$r0 + #tpc_mmio_list_head] $r14
-        st b16 D[$r0 + #tpc_mmio_list_tail] $r15
-        call #mmctx_size
-        ld b32 $r14 D[$r0 + #tpc_count]
-        mulu $r14 $r15
-        add b32 $r2 $r14
-        add b32 $r3 $r14
-
-        // round up base/size to 256 byte boundary (for strand SWBASE)
-        add b32 $r4 0x1300
-        shr b32 $r3 2
-        iowr I[$r4 + 0x000] $r3         // MMCTX_LOAD_COUNT, wtf for?!?
-        shr b32 $r2 8
-        shr b32 $r3 6
-        add b32 $r2 1
-        add b32 $r3 1
-        shl b32 $r2 8
-        shl b32 $r3 8
-
-        // calculate size of strand context data
-        mov b32 $r15 $r2
-        call #strand_ctx_init
-        add b32 $r3 $r15
-
-        // save context size, and tell HUB we're done
-        mov $r1 0x800
-        shl b32 $r1 6
-        iowr I[$r1 + 0x100] $r3         // CC_SCRATCH[1]  = context size
-        add b32 $r1 0x800
-        clear b32 $r2
-        bset $r2 31
-        iowr I[$r1 + 0x000] $r2         // CC_SCRATCH[0] |= 0x80000000
-
-// Main program loop, very simple, sleeps until woken up by the interrupt
-// handler, pulls a command from the queue and executes its handler
-//
-main:
-        bset $flags $p0
-        sleep $p0
-        mov $r13 #cmd_queue
-        call #queue_get
-        bra $p1 #main
-
-        // 0x0000-0x0003 are all context transfers
-        cmpu b32 $r14 0x04
-        bra nc #main_not_ctx_xfer
-                // fetch $flags and mask off $p1/$p2
-                mov $r1 $flags
-                mov $r2 0x0006
-                not b32 $r2
-                and $r1 $r2
-                // set $p1/$p2 according to transfer type
-                shl b32 $r14 1
-                or $r1 $r14
-                mov $flags $r1
-                // transfer context data
-                call #ctx_xfer
-                bra #main
-
-        main_not_ctx_xfer:
-        shl b32 $r15 $r14 16
-        or $r15 E_BAD_COMMAND
-        call #error
-        bra #main
-
-// interrupt handler
-ih:
-        push $r8
-        mov $r8 $flags
-        push $r8
-        push $r9
-        push $r10
-        push $r11
-        push $r13
-        push $r14
-        push $r15
-
-        // incoming fifo command?
-        iord $r10 I[$r0 + 0x200]        // INTR
-        and $r11 $r10 0x00000004
-        bra e #ih_no_fifo
-                // queue incoming fifo command for later processing
-                mov $r11 0x1900
-                mov $r13 #cmd_queue
-                iord $r14 I[$r11 + 0x100]       // FIFO_CMD
-                iord $r15 I[$r11 + 0x000]       // FIFO_DATA
-                call #queue_put
-                add b32 $r11 0x400
-                mov $r14 1
-                iowr I[$r11 + 0x000] $r14       // FIFO_ACK
-
-        // ack, and wake up main()
-        ih_no_fifo:
-        iowr I[$r0 + 0x100] $r10        // INTR_ACK
-
-        pop $r15
-        pop $r14
-        pop $r13
-        pop $r11
-        pop $r10
-        pop $r9
-        pop $r8
-        mov $flags $r8
-        pop $r8
-        bclr $flags $p0
-        iret
-
-// Set this GPC's bit in HUB_BAR, used to signal completion of various
-// activities to the HUB fuc
-//
-hub_barrier_done:
-        mov $r15 1
-        ld b32 $r14 D[$r0 + #gpc_id]
-        shl b32 $r15 $r14
-        mov $r14 -0x6be8        // 0x409418 - HUB_BAR_SET
-        sethi $r14 0x400000
-        call #nv_wr32
-        ret
-
-// Disables various things, waits a bit, and re-enables them..
-//
-// Not sure how exactly this helps, perhaps "ENABLE" is not such a
-// good description for the bits we turn off?  Anyways, without this,
-// funny things happen.
-//
-ctx_redswitch:
-        mov $r14 0x614
-        shl b32 $r14 6
-        mov $r15 0x020
-        iowr I[$r14] $r15       // GPC_RED_SWITCH = POWER
-        mov $r15 8
-        ctx_redswitch_delay:
-                sub b32 $r15 1
-                bra ne #ctx_redswitch_delay
-        mov $r15 0xa20
-        iowr I[$r14] $r15       // GPC_RED_SWITCH = UNK11, ENABLE, POWER
-        ret
-
-// Transfer GPC context data between GPU and storage area
-//
-// In: $r15 context base address
-//     $p1 clear on save, set on load
-//     $p2 set if opposite direction done/will be done, so:
-//              on save it means: "a load will follow this save"
-//              on load it means: "a save preceeded this load"
-//
-ctx_xfer:
-        // set context base address
-        mov $r1 0xa04
-        shl b32 $r1 6
-        iowr I[$r1 + 0x000] $r15// MEM_BASE
-        bra not $p1 #ctx_xfer_not_load
-                call #ctx_redswitch
-        ctx_xfer_not_load:
-
-        // strands
-        mov $r1 0x4afc
-        sethi $r1 0x20000
-        mov $r2 0xc
-        iowr I[$r1] $r2         // STRAND_CMD(0x3f) = 0x0c
-        call #strand_wait
-        mov $r2 0x47fc
-        sethi $r2 0x20000
-        iowr I[$r2] $r0         // STRAND_FIRST_GENE(0x3f) = 0x00
-        xbit $r2 $flags $p1
-        add b32 $r2 3
-        iowr I[$r1] $r2         // STRAND_CMD(0x3f) = 0x03/0x04 (SAVE/LOAD)
-
-        // mmio context
-        xbit $r10 $flags $p1    // direction
-        or $r10 2               // first
-        mov $r11 0x0000
-        sethi $r11 0x500000
-        ld b32 $r12 D[$r0 + #gpc_id]
-        shl b32 $r12 15
-        add b32 $r11 $r12       // base = NV_PGRAPH_GPCn
-        ld b32 $r12 D[$r0 + #gpc_mmio_list_head]
-        ld b32 $r13 D[$r0 + #gpc_mmio_list_tail]
-        mov $r14 0              // not multi
-        call #mmctx_xfer
-
-        // per-TPC mmio context
-        xbit $r10 $flags $p1    // direction
-        or $r10 4               // last
-        mov $r11 0x4000
-        sethi $r11 0x500000     // base = NV_PGRAPH_GPC0_TPC0
-        ld b32 $r12 D[$r0 + #gpc_id]
-        shl b32 $r12 15
-        add b32 $r11 $r12       // base = NV_PGRAPH_GPCn_TPC0
-        ld b32 $r12 D[$r0 + #tpc_mmio_list_head]
-        ld b32 $r13 D[$r0 + #tpc_mmio_list_tail]
-        ld b32 $r15 D[$r0 + #tpc_mask]
-        mov $r14 0x800          // stride = 0x800
-        call #mmctx_xfer
-
-        // wait for strands to finish
-        call #strand_wait
-
-        // if load, or a save without a load following, do some
-        // unknown stuff that's done after finishing a block of
-        // strand commands
-        bra $p1 #ctx_xfer_post
-        bra not $p2 #ctx_xfer_done
-        ctx_xfer_post:
-                mov $r1 0x4afc
-                sethi $r1 0x20000
-                mov $r2 0xd
-                iowr I[$r1] $r2         // STRAND_CMD(0x3f) = 0x0d
-                call #strand_wait
-
-        // mark completion in HUB's barrier
-        ctx_xfer_done:
-        call #hub_barrier_done
-        ret
-
+#include "com.fuc"
+#include "gpc.fuc"
 .align 256
+#undef INCLUDE_CODE
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvc0.fuc.h b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvc0.fuc.h
index 96050ddb22ca..f2b0dea80116 100644
--- a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvc0.fuc.h
+++ b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvc0.fuc.h
@@ -1,17 +1,19 @@
 uint32_t nvc0_grgpc_data[] = {
-/* 0x0000: gpc_id */
-        0x00000000,
-/* 0x0004: gpc_mmio_list_head */
-        0x00000000,
-/* 0x0008: gpc_mmio_list_tail */
-        0x00000000,
-/* 0x000c: tpc_count */
-        0x00000000,
-/* 0x0010: tpc_mask */
+/* 0x0000: gpc_mmio_list_head */
+        0x00000064,
+/* 0x0004: gpc_mmio_list_tail */
+/* 0x0004: tpc_mmio_list_head */
+        0x00000064,
+/* 0x0008: tpc_mmio_list_tail */
+/* 0x0008: unk_mmio_list_head */
+        0x00000064,
+/* 0x000c: unk_mmio_list_tail */
+        0x00000064,
+/* 0x0010: gpc_id */
         0x00000000,
-/* 0x0014: tpc_mmio_list_head */
+/* 0x0014: tpc_count */
         0x00000000,
-/* 0x0018: tpc_mmio_list_tail */
+/* 0x0018: tpc_mask */
         0x00000000,
 /* 0x001c: cmd_queue */
         0x00000000,
@@ -32,153 +34,17 @@ uint32_t nvc0_grgpc_data[] = {
         0x00000000,
         0x00000000,
         0x00000000,
-/* 0x0064: chipsets */
-        0x000000c0,
-        0x012800c8,
-        0x01e40194,
-        0x000000c1,
-        0x012c00c8,
-        0x01f80194,
-        0x000000c3,
-        0x012800c8,
-        0x01f40194,
-        0x000000c4,
-        0x012800c8,
-        0x01f40194,
-        0x000000c8,
-        0x012800c8,
-        0x01e40194,
-        0x000000ce,
-        0x012800c8,
-        0x01f40194,
-        0x000000cf,
-        0x012800c8,
-        0x01f00194,
-        0x000000d9,
-        0x0194012c,
-        0x025401f8,
-        0x00000000,
-/* 0x00c8: nvc0_gpc_mmio_head */
-        0x00000380,
-        0x14000400,
-        0x20000450,
-        0x00000600,
-        0x00000684,
-        0x10000700,
-        0x00000800,
-        0x08000808,
-        0x00000828,
-        0x00000830,
-        0x000008d8,
-        0x000008e0,
-        0x140008e8,
-        0x0000091c,
-        0x08000924,
-        0x00000b00,
-        0x14000b08,
-        0x00000bb8,
-        0x00000c08,
-        0x1c000c10,
-        0x00000c80,
-        0x00000c8c,
-        0x08001000,
-        0x00001014,
-/* 0x0128: nvc0_gpc_mmio_tail */
-        0x00000c6c,
-/* 0x012c: nvc1_gpc_mmio_tail */
-/* 0x012c: nvd9_gpc_mmio_head */
-        0x00000380,
-        0x04000400,
-        0x0800040c,
-        0x20000450,
-        0x00000600,
-        0x00000684,
-        0x10000700,
-        0x00000800,
-        0x08000808,
-        0x00000828,
-        0x00000830,
-        0x000008d8,
-        0x000008e0,
-        0x140008e8,
-        0x0000091c,
-        0x08000924,
-        0x00000b00,
-        0x14000b08,
-        0x00000bb8,
-        0x00000c08,
-        0x1c000c10,
-        0x00000c6c,
-        0x00000c80,
-        0x00000c8c,
-        0x08001000,
-        0x00001014,
-/* 0x0194: nvd9_gpc_mmio_tail */
-/* 0x0194: nvc0_tpc_mmio_head */
-        0x00000018,
-        0x0000003c,
-        0x00000048,
-        0x00000064,
-        0x00000088,
-        0x14000200,
-        0x0400021c,
-        0x14000300,
-        0x000003d0,
-        0x040003e0,
-        0x08000400,
-        0x00000420,
-        0x000004b0,
-        0x000004e8,
-        0x000004f4,
-        0x04000520,
-        0x0c000604,
-        0x4c000644,
-        0x00000698,
-        0x04000750,
-/* 0x01e4: nvc0_tpc_mmio_tail */
-        0x00000758,
-        0x000002c4,
-        0x000006e0,
-/* 0x01f0: nvcf_tpc_mmio_tail */
-        0x000004bc,
-/* 0x01f4: nvc3_tpc_mmio_tail */
-        0x00000544,
-/* 0x01f8: nvc1_tpc_mmio_tail */
-/* 0x01f8: nvd9_tpc_mmio_head */
-        0x00000018,
-        0x0000003c,
-        0x00000048,
-        0x00000064,
-        0x00000088,
-        0x14000200,
-        0x0400021c,
-        0x000002c4,
-        0x14000300,
-        0x000003d0,
-        0x040003e0,
-        0x08000400,
-        0x08000420,
-        0x000004b0,
-        0x000004e8,
-        0x000004f4,
-        0x04000520,
-        0x00000544,
-        0x0c000604,
-        0x4c000644,
-        0x00000698,
-        0x000006e0,
-        0x08000750,
 };
 
 uint32_t nvc0_grgpc_code[] = {
-        0x03060ef5,
+        0x03180ef5,
 /* 0x0004: queue_put */
         0x9800d898,
         0x86f001d9,
         0x0489b808,
         0xf00c1bf4,
         0x21f502f7,
-        0x00f802ec,
+        0x00f802fe,
 /* 0x001c: queue_put_next */
         0xb60798c4,
         0x8dbb0384,
@@ -210,7 +76,7 @@ uint32_t nvc0_grgpc_code[] = {
         0xc800bccf,
         0x1bf41fcc,
         0x06a7f0fa,
-        0x010321f5,
+        0x010921f5,
         0xf840bfcf,
 /* 0x008d: nv_wr32 */
         0x28b7f100,
@@ -232,63 +98,66 @@ uint32_t nvc0_grgpc_code[] = {
         0x0684b604,
         0xf80080d0,
 /* 0x00c9: wait_donez */
-        0x3c87f100,
-        0x0684b608,
-        0x99f094bd,
-        0x0089d000,
-        0x081887f1,
-        0xd00684b6,
-/* 0x00e2: wait_done_wait_donez */
-        0x87f1008a,
-        0x84b60400,
-        0x0088cf06,
+        0xf094bd00,
+        0x07f10099,
+        0x03f00f00,
+        0x0009d002,
+        0x07f104bd,
+        0x03f00600,
+        0x000ad002,
+/* 0x00e6: wait_donez_ne */
+        0x87f104bd,
+        0x83f00000,
+        0x0088cf01,
         0xf4888aff,
-        0x87f1f31b,
-        0x84b6085c,
-        0xf094bd06,
-        0x89d00099,
-/* 0x0103: wait_doneo */
-        0xf100f800,
-        0xb6083c87,
-        0x94bd0684,
-        0xd00099f0,
-        0x87f10089,
+        0x94bdf31b,
+        0xf10099f0,
+        0xf0170007,
+        0x09d00203,
+        0xf804bd00,
+/* 0x0109: wait_doneo */
+        0xf094bd00,
+        0x07f10099,
+        0x03f00f00,
+        0x0009d002,
+        0x87f104bd,
         0x84b60818,
         0x008ad006,
-/* 0x011c: wait_done_wait_doneo */
+/* 0x0124: wait_doneo_e */
         0x040087f1,
         0xcf0684b6,
         0x8aff0088,
         0xf30bf488,
-        0x085c87f1,
-        0xbd0684b6,
-        0x0099f094,
-        0xf80089d0,
-/* 0x013d: mmctx_size */
-/* 0x013f: nv_mmctx_size_loop */
-        0x9894bd00,
-        0x85b600e8,
-        0x0180b61a,
-        0xbb0284b6,
-        0xe0b60098,
-        0x04efb804,
-        0xb9eb1bf4,
-        0x00f8029f,
-/* 0x015c: mmctx_xfer */
-        0x083c87f1,
-        0xbd0684b6,
-        0x0199f094,
-        0xf10089d0,
+        0x99f094bd,
+        0x0007f100,
+        0x0203f017,
+        0xbd0009d0,
+/* 0x0147: mmctx_size */
+        0xbd00f804,
+/* 0x0149: nv_mmctx_size_loop */
+        0x00e89894,
+        0xb61a85b6,
+        0x84b60180,
+        0x0098bb02,
+        0xb804e0b6,
+        0x1bf404ef,
+        0x029fb9eb,
+/* 0x0166: mmctx_xfer */
+        0x94bd00f8,
+        0xf10199f0,
+        0xf00f0007,
+        0x09d00203,
+        0xf104bd00,
         0xb6071087,
         0x94bd0684,
         0xf405bbfd,
         0x8bd0090b,
         0x0099f000,
-/* 0x0180: mmctx_base_disabled */
+/* 0x018c: mmctx_base_disabled */
         0xf405eefd,
         0x8ed00c0b,
         0xc08fd080,
-/* 0x018f: mmctx_multi_disabled */
+/* 0x019b: mmctx_multi_disabled */
         0xb70199f0,
         0xc8010080,
         0xb4b600ab,
@@ -296,8 +165,8 @@ uint32_t nvc0_grgpc_code[] = {
         0xb601aec8,
         0xbefd11e4,
         0x008bd005,
-/* 0x01a8: mmctx_exec_loop */
-/* 0x01a8: mmctx_wait_free */
+/* 0x01b4: mmctx_exec_loop */
+/* 0x01b4: mmctx_wait_free */
         0xf0008ecf,
         0x0bf41fe4,
         0x00ce98fa,
@@ -306,76 +175,77 @@ uint32_t nvc0_grgpc_code[] = {
         0x04cdb804,
         0xc8e81bf4,
         0x1bf402ab,
-/* 0x01c9: mmctx_fini_wait */
+/* 0x01d5: mmctx_fini_wait */
         0x008bcf18,
         0xb01fb4f0,
         0x1bf410b4,
         0x02a7f0f7,
         0xf4c921f4,
-/* 0x01de: mmctx_stop */
+/* 0x01ea: mmctx_stop */
         0xabc81b0e,
         0x10b4b600,
         0xf00cb9f0,
         0x8bd012b9,
-/* 0x01ed: mmctx_stop_wait */
+/* 0x01f9: mmctx_stop_wait */
         0x008bcf00,
         0xf412bbc8,
-/* 0x01f6: mmctx_done */
-        0x87f1fa1b,
-        0x84b6085c,
-        0xf094bd06,
-        0x89d00199,
-/* 0x0207: strand_wait */
-        0xf900f800,
-        0x02a7f0a0,
-        0xfcc921f4,
-/* 0x0213: strand_pre */
-        0xf100f8a0,
-        0xf04afc87,
-        0x97f00283,
-        0x0089d00c,
-        0x020721f5,
-/* 0x0226: strand_post */
-        0x87f100f8,
-        0x83f04afc,
-        0x0d97f002,
-        0xf50089d0,
-        0xf8020721,
-/* 0x0239: strand_set */
-        0xfca7f100,
-        0x02a3f04f,
-        0x0500aba2,
-        0xd00fc7f0,
-        0xc7f000ac,
-        0x00bcd00b,
-        0x020721f5,
-        0xf000aed0,
-        0xbcd00ac7,
-        0x0721f500,
-/* 0x0263: strand_ctx_init */
-        0xf100f802,
-        0xb6083c87,
-        0x94bd0684,
-        0xd00399f0,
+/* 0x0202: mmctx_done */
+        0x94bdfa1b,
+        0xf10199f0,
+        0xf0170007,
+        0x09d00203,
+        0xf804bd00,
+/* 0x0215: strand_wait */
+        0xf0a0f900,
+        0x21f402a7,
+        0xf8a0fcc9,
+/* 0x0221: strand_pre */
+        0xfc87f100,
+        0x0283f04a,
+        0xd00c97f0,
         0x21f50089,
-        0xe7f00213,
-        0x3921f503,
+        0x00f80215,
+/* 0x0234: strand_post */
+        0x4afc87f1,
+        0xf00283f0,
+        0x89d00d97,
+        0x1521f500,
+/* 0x0247: strand_set */
+        0xf100f802,
+        0xf04ffca7,
+        0xaba202a3,
+        0xc7f00500,
+        0x00acd00f,
+        0xd00bc7f0,
+        0x21f500bc,
+        0xaed00215,
+        0x0ac7f000,
+        0xf500bcd0,
+        0xf8021521,
+/* 0x0271: strand_ctx_init */
+        0xf094bd00,
+        0x07f10399,
+        0x03f00f00,
+        0x0009d002,
+        0x21f504bd,
+        0xe7f00221,
+        0x4721f503,
         0xfca7f102,
         0x02a3f046,
         0x0400aba0,
         0xf040a0d0,
         0xbcd001c7,
-        0x0721f500,
+        0x1521f500,
         0x010c9202,
         0xf000acd0,
         0xbcd002c7,
-        0x0721f500,
-        0x2621f502,
+        0x1521f500,
+        0x3421f502,
         0x8087f102,
         0x0684b608,
         0xb70089cf,
         0x95220080,
-/* 0x02ba: ctx_init_strand_loop */
+/* 0x02ca: ctx_init_strand_loop */
         0x8ed008fe,
         0x408ed000,
         0xb6808acf,
@@ -384,86 +254,74 @@ uint32_t nvc0_grgpc_code[] = {
         0xb60480b6,
         0x1bf40192,
         0x08e4b6e8,
-        0xf1f2efbc,
-        0xb6085c87,
-        0x94bd0684,
-        0xd00399f0,
-        0x00f80089,
-/* 0x02ec: error */
-        0xe7f1e0f9,
-        0xe3f09814,
-        0x8d21f440,
-        0x041ce0b7,
-        0xf401f7f0,
-        0xe0fc8d21,
-/* 0x0306: init */
-        0x04bd00f8,
-        0xf10004fe,
-        0xf0120017,
-        0x12d00227,
-        0x3e17f100,
-        0x0010fe04,
-        0x040017f1,
-        0xf0c010d0,
-        0x12d00427,
-        0x1031f400,
-        0x060817f1,
-        0xcf0614b6,
-        0x37f00012,
-        0x1f24f001,
-        0xb60432bb,
-        0x02800132,
-        0x04038003,
-        0x040010b7,
-        0x800012cf,
-        0x27f10002,
-        0x24b60800,
-        0x0022cf06,
-/* 0x035f: init_find_chipset */
-        0xb65817f0,
-        0x13980c10,
-        0x0432b800,
-        0xb00b0bf4,
-        0x1bf40034,
-/* 0x0373: init_context */
-        0xf100f8f1,
-        0xb6080027,
-        0x22cf0624,
-        0xf134bd40,
-        0xb6070047,
-        0x25950644,
-        0x0045d008,
-        0xbd4045d0,
-        0x58f4bde4,
-        0x1f58021e,
-        0x020e4003,
-        0xf5040f40,
-        0xbb013d21,
-        0x3fbb002f,
-        0x041e5800,
-        0x40051f58,
-        0x0f400a0e,
-        0x3d21f50c,
-        0x030e9801,
-        0xbb00effd,
-        0x3ebb002e,
-        0x0040b700,
-        0x0235b613,
-        0xb60043d0,
-        0x35b60825,
-        0x0120b606,
-        0xb60130b6,
-        0x34b60824,
-        0x022fb908,
-        0x026321f5,
-        0xf1003fbb,
-        0xb6080017,
-        0x13d00614,
-        0x0010b740,
-        0xf024bd08,
-        0x12d01f29,
-/* 0x0401: main */
-        0x0031f400,
+        0xbdf2efbc,
+        0x0399f094,
+        0x170007f1,
+        0xd00203f0,
+        0x04bd0009,
+/* 0x02fe: error */
+        0xe0f900f8,
+        0x9814e7f1,
+        0xf440e3f0,
+        0xe0b78d21,
+        0xf7f0041c,
+        0x8d21f401,
+        0x00f8e0fc,
+/* 0x0318: init */
+        0x04fe04bd,
+        0x0017f100,
+        0x0227f012,
+        0xf10012d0,
+        0xfe042617,
+        0x17f10010,
+        0x10d00400,
+        0x0427f0c0,
+        0xf40012d0,
+        0x17f11031,
+        0x14b60608,
+        0x0012cf06,
+        0xf00137f0,
+        0x32bb1f24,
+        0x0132b604,
+        0x80050280,
+        0x10b70603,
+        0x12cf0400,
+        0x04028000,
+        0x010027f1,
+        0xcf0223f0,
+        0x34bd0022,
+        0x070047f1,
+        0x950644b6,
+        0x45d00825,
+        0x4045d000,
+        0x98000e98,
+        0x21f5010f,
+        0x2fbb0147,
+        0x003fbb00,
+        0x98010e98,
+        0x21f5020f,
+        0x0e980147,
+        0x00effd05,
+        0xbb002ebb,
+        0x40b7003e,
+        0x35b61300,
+        0x0043d002,
+        0xb60825b6,
+        0x20b60635,
+        0x0130b601,
+        0xb60824b6,
+        0x2fb90834,
+        0x7121f502,
+        0x003fbb02,
+        0x010007f1,
+        0xd00203f0,
+        0x04bd0003,
+        0x29f024bd,
+        0x0007f11f,
+        0x0203f008,
+        0xbd0002d0,
+/* 0x03e9: main */
+        0x0031f404,
         0xf00028f4,
         0x21f41cd7,
         0xf401f439,
@@ -474,94 +332,100 @@ uint32_t nvc0_grgpc_code[] = {
         0x01e4b604,
         0xfe051efd,
         0x21f50018,
-        0x0ef404c3,
-/* 0x0431: main_not_ctx_xfer */
+        0x0ef404ad,
+/* 0x0419: main_not_ctx_xfer */
         0x10ef94d3,
         0xf501f5f0,
-        0xf402ec21,
-/* 0x043e: ih */
+        0xf402fe21,
+/* 0x0426: ih */
         0x80f9c60e,
         0xf90188fe,
         0xf990f980,
         0xf9b0f9a0,
         0xf9e0f9d0,
-        0x800acff0,
-        0xf404abc4,
-        0xb7f11d0b,
-        0xd7f01900,
-        0x40becf1c,
-        0xf400bfcf,
-        0xb0b70421,
-        0xe7f00400,
-        0x00bed001,
-/* 0x0474: ih_no_fifo */
-        0xfc400ad0,
-        0xfce0fcf0,
-        0xfcb0fcd0,
-        0xfc90fca0,
-        0x0088fe80,
-        0x32f480fc,
-/* 0x048f: hub_barrier_done */
-        0xf001f800,
-        0x0e9801f7,
-        0x04febb00,
-        0x9418e7f1,
-        0xf440e3f0,
-        0x00f88d21,
-/* 0x04a4: ctx_redswitch */
-        0x0614e7f1,
-        0xf006e4b6,
-        0xefd020f7,
-        0x08f7f000,
-/* 0x04b4: ctx_redswitch_delay */
-        0xf401f2b6,
-        0xf7f1fd1b,
-        0xefd00a20,
-/* 0x04c3: ctx_xfer */
-        0xf100f800,
-        0xb60a0417,
-        0x1fd00614,
-        0x0711f400,
-        0x04a421f5,
-/* 0x04d4: ctx_xfer_not_load */
-        0x4afc17f1,
-        0xf00213f0,
-        0x12d00c27,
-        0x0721f500,
-        0xfc27f102,
-        0x0223f047,
-        0xf00020d0,
-        0x20b6012c,
-        0x0012d003,
+        0xcf04bdf0,
+        0xabc4800a,
+        0x1d0bf404,
+        0x1900b7f1,
+        0xcf1cd7f0,
+        0xbfcf40be,
+        0x0421f400,
+        0x0400b0b7,
+        0xd001e7f0,
+/* 0x045e: ih_no_fifo */
+        0x0ad000be,
+        0xfcf0fc40,
+        0xfcd0fce0,
+        0xfca0fcb0,
+        0xfe80fc90,
+        0x80fc0088,
+        0xf80032f4,
+/* 0x0479: hub_barrier_done */
+        0x01f7f001,
+        0xbb040e98,
+        0xe7f104fe,
+        0xe3f09418,
+        0x8d21f440,
+/* 0x048e: ctx_redswitch */
+        0xe7f100f8,
+        0xe4b60614,
+        0x20f7f006,
+        0xf000efd0,
+/* 0x049e: ctx_redswitch_delay */
+        0xf2b608f7,
+        0xfd1bf401,
+        0x0a20f7f1,
+        0xf800efd0,
+/* 0x04ad: ctx_xfer */
+        0x0417f100,
+        0x0614b60a,
+        0xf4001fd0,
+        0x21f50711,
+/* 0x04be: ctx_xfer_not_load */
+        0x17f1048e,
+        0x13f04afc,
+        0x0c27f002,
+        0xf50012d0,
+        0xf1021521,
+        0xf047fc27,
+        0x20d00223,
+        0x012cf000,
+        0xd00320b6,
+        0xacf00012,
+        0x02a5f001,
+        0xf000b7f0,
+        0x0c9850b3,
+        0x0fc4b604,
+        0x9800bcbb,
+        0x0d98000c,
+        0x00e7f001,
+        0x016621f5,
         0xf001acf0,
-        0xb7f002a5,
-        0x50b3f000,
-        0xb6000c98,
-        0xbcbb0fc4,
-        0x010c9800,
-        0xf0020d98,
-        0x21f500e7,
-        0xacf0015c,
-        0x04a5f001,
-        0x4000b7f1,
-        0x9850b3f0,
-        0xc4b6000c,
-        0x00bcbb0f,
-        0x98050c98,
-        0x0f98060d,
-        0x00e7f104,
-        0x5c21f508,
-        0x0721f501,
-        0x0601f402,
-/* 0x054b: ctx_xfer_post */
-        0xf11412f4,
-        0xf04afc17,
-        0x27f00213,
-        0x0012d00d,
-        0x020721f5,
-/* 0x055c: ctx_xfer_done */
-        0x048f21f5,
-        0x000000f8,
+        0xb7f104a5,
+        0xb3f04000,
+        0x040c9850,
+        0xbb0fc4b6,
+        0x0c9800bc,
+        0x020d9801,
+        0xf1060f98,
+        0xf50800e7,
+        0xf5016621,
+        0xf4021521,
+        0x12f40601,
+/* 0x0535: ctx_xfer_post */
+        0xfc17f114,
+        0x0213f04a,
+        0xd00d27f0,
+        0x21f50012,
+/* 0x0546: ctx_xfer_done */
+        0x21f50215,
+        0x00f80479,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
         0x00000000,
         0x00000000,
         0x00000000,
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvd7.fuc b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvd7.fuc
new file mode 100644
index 000000000000..c2f754edbd7d
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvd7.fuc
@@ -0,0 +1,42 @@
+/*
+ * Copyright 2013 Red Hat Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Ben Skeggs <bskeggs@redhat.com>
+ */
+
+#define NV_PGRAPH_GPCX_UNK__SIZE                                     0x00000001
+
+#define CHIPSET GF117
+#include "macros.fuc"
+
+.section #nvd7_grgpc_data
+#define INCLUDE_DATA
+#include "com.fuc"
+#include "gpc.fuc"
+#undef INCLUDE_DATA
+
+.section #nvd7_grgpc_code
+#define INCLUDE_CODE
+bra #init
+#include "com.fuc"
+#include "gpc.fuc"
+.align 256
+#undef INCLUDE_CODE
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvd7.fuc.h b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvd7.fuc.h
new file mode 100644
index 000000000000..dd346c2a1624
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvd7.fuc.h
@@ -0,0 +1,475 @@
+uint32_t nvd7_grgpc_data[] = {
+/* 0x0000: gpc_mmio_list_head */
+        0x0000006c,
+/* 0x0004: gpc_mmio_list_tail */
+/* 0x0004: tpc_mmio_list_head */
+        0x0000006c,
+/* 0x0008: tpc_mmio_list_tail */
+/* 0x0008: unk_mmio_list_head */
+        0x0000006c,
+/* 0x000c: unk_mmio_list_tail */
+        0x0000006c,
+/* 0x0010: gpc_id */
+        0x00000000,
+/* 0x0014: tpc_count */
+        0x00000000,
+/* 0x0018: tpc_mask */
+        0x00000000,
+/* 0x001c: unk_count */
+        0x00000000,
+/* 0x0020: unk_mask */
+        0x00000000,
+/* 0x0024: cmd_queue */
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+};
+
+uint32_t nvd7_grgpc_code[] = {
+        0x03180ef5,
+/* 0x0004: queue_put */
+        0x9800d898,
+        0x86f001d9,
+        0x0489b808,
+        0xf00c1bf4,
+        0x21f502f7,
+        0x00f802fe,
+/* 0x001c: queue_put_next */
+        0xb60798c4,
+        0x8dbb0384,
+        0x0880b600,
+        0x80008e80,
+        0x90b6018f,
+        0x0f94f001,
+        0xf801d980,
+/* 0x0039: queue_get */
+        0x0131f400,
+        0x9800d898,
+        0x89b801d9,
+        0x210bf404,
+        0xb60789c4,
+        0x9dbb0394,
+        0x0890b600,
+        0x98009e98,
+        0x80b6019f,
+        0x0f84f001,
+        0xf400d880,
+/* 0x0066: queue_get_done */
+        0x00f80132,
+/* 0x0068: nv_rd32 */
+        0x0728b7f1,
+        0xb906b4b6,
+        0xc9f002ec,
+        0x00bcd01f,
+/* 0x0078: nv_rd32_wait */
+        0xc800bccf,
+        0x1bf41fcc,
+        0x06a7f0fa,
+        0x010921f5,
+        0xf840bfcf,
+/* 0x008d: nv_wr32 */
+        0x28b7f100,
+        0x06b4b607,
+        0xb980bfd0,
+        0xc9f002ec,
+        0x1ec9f01f,
+/* 0x00a3: nv_wr32_wait */
+        0xcf00bcd0,
+        0xccc800bc,
+        0xfa1bf41f,
+/* 0x00ae: watchdog_reset */
+        0x87f100f8,
+        0x84b60430,
+        0x1ff9f006,
+        0xf8008fd0,
+/* 0x00bd: watchdog_clear */
+        0x3087f100,
+        0x0684b604,
+        0xf80080d0,
+/* 0x00c9: wait_donez */
+        0xf094bd00,
+        0x07f10099,
+        0x03f00f00,
+        0x0009d002,
+        0x07f104bd,
+        0x03f00600,
+        0x000ad002,
+/* 0x00e6: wait_donez_ne */
+        0x87f104bd,
+        0x83f00000,
+        0x0088cf01,
+        0xf4888aff,
+        0x94bdf31b,
+        0xf10099f0,
+        0xf0170007,
+        0x09d00203,
+        0xf804bd00,
+/* 0x0109: wait_doneo */
+        0xf094bd00,
+        0x07f10099,
+        0x03f00f00,
+        0x0009d002,
+        0x87f104bd,
+        0x84b60818,
+        0x008ad006,
+/* 0x0124: wait_doneo_e */
+        0x040087f1,
+        0xcf0684b6,
+        0x8aff0088,
+        0xf30bf488,
+        0x99f094bd,
+        0x0007f100,
+        0x0203f017,
+        0xbd0009d0,
+/* 0x0147: mmctx_size */
+        0xbd00f804,
+/* 0x0149: nv_mmctx_size_loop */
+        0x00e89894,
+        0xb61a85b6,
+        0x84b60180,
+        0x0098bb02,
+        0xb804e0b6,
+        0x1bf404ef,
+        0x029fb9eb,
+/* 0x0166: mmctx_xfer */
+        0x94bd00f8,
+        0xf10199f0,
+        0xf00f0007,
+        0x09d00203,
+        0xf104bd00,
+        0xb6071087,
+        0x94bd0684,
+        0xf405bbfd,
+        0x8bd0090b,
+        0x0099f000,
+/* 0x018c: mmctx_base_disabled */
+        0xf405eefd,
+        0x8ed00c0b,
+        0xc08fd080,
+/* 0x019b: mmctx_multi_disabled */
+        0xb70199f0,
+        0xc8010080,
+        0xb4b600ab,
+        0x0cb9f010,
+        0xb601aec8,
+        0xbefd11e4,
+        0x008bd005,
+/* 0x01b4: mmctx_exec_loop */
+/* 0x01b4: mmctx_wait_free */
+        0xf0008ecf,
+        0x0bf41fe4,
+        0x00ce98fa,
+        0xd005e9fd,
+        0xc0b6c08e,
+        0x04cdb804,
+        0xc8e81bf4,
+        0x1bf402ab,
+/* 0x01d5: mmctx_fini_wait */
+        0x008bcf18,
+        0xb01fb4f0,
+        0x1bf410b4,
+        0x02a7f0f7,
+        0xf4c921f4,
+/* 0x01ea: mmctx_stop */
+        0xabc81b0e,
+        0x10b4b600,
+        0xf00cb9f0,
+        0x8bd012b9,
+/* 0x01f9: mmctx_stop_wait */
+        0x008bcf00,
+        0xf412bbc8,
+/* 0x0202: mmctx_done */
+        0x94bdfa1b,
+        0xf10199f0,
+        0xf0170007,
+        0x09d00203,
+        0xf804bd00,
+/* 0x0215: strand_wait */
+        0xf0a0f900,
+        0x21f402a7,
+        0xf8a0fcc9,
+/* 0x0221: strand_pre */
+        0xfc87f100,
+        0x0283f04a,
+        0xd00c97f0,
+        0x21f50089,
+        0x00f80215,
+/* 0x0234: strand_post */
+        0x4afc87f1,
+        0xf00283f0,
+        0x89d00d97,
+        0x1521f500,
+/* 0x0247: strand_set */
+        0xf100f802,
+        0xf04ffca7,
+        0xaba202a3,
+        0xc7f00500,
+        0x00acd00f,
+        0xd00bc7f0,
+        0x21f500bc,
+        0xaed00215,
+        0x0ac7f000,
+        0xf500bcd0,
+        0xf8021521,
+/* 0x0271: strand_ctx_init */
+        0xf094bd00,
+        0x07f10399,
+        0x03f00f00,
+        0x0009d002,
+        0x21f504bd,
+        0xe7f00221,
+        0x4721f503,
+        0xfca7f102,
+        0x02a3f046,
+        0x0400aba0,
+        0xf040a0d0,
+        0xbcd001c7,
+        0x1521f500,
+        0x010c9202,
+        0xf000acd0,
+        0xbcd002c7,
+        0x1521f500,
+        0x3421f502,
+        0x8087f102,
+        0x0684b608,
+        0xb70089cf,
+        0x95220080,
+/* 0x02ca: ctx_init_strand_loop */
+        0x8ed008fe,
+        0x408ed000,
+        0xb6808acf,
+        0xa0b606a5,
+        0x00eabb01,
+        0xb60480b6,
+        0x1bf40192,
+        0x08e4b6e8,
+        0xbdf2efbc,
+        0x0399f094,
+        0x170007f1,
+        0xd00203f0,
+        0x04bd0009,
+/* 0x02fe: error */
+        0xe0f900f8,
+        0x9814e7f1,
+        0xf440e3f0,
+        0xe0b78d21,
+        0xf7f0041c,
+        0x8d21f401,
+        0x00f8e0fc,
+/* 0x0318: init */
+        0x04fe04bd,
+        0x0017f100,
+        0x0227f012,
+        0xf10012d0,
+        0xfe047017,
+        0x17f10010,
+        0x10d00400,
+        0x0427f0c0,
+        0xf40012d0,
+        0x17f11031,
+        0x14b60608,
+        0x0012cf06,
+        0xf00137f0,
+        0x32bb1f24,
+        0x0132b604,
+        0x80050280,
+        0x10b70603,
+        0x12cf0400,
+        0x04028000,
+        0x0c30e7f1,
+        0xbd50e3f0,
+        0xbd34bd24,
+/* 0x0371: init_unk_loop */
+        0x6821f444,
+        0xf400f6b0,
+        0xf7f00f0b,
+        0x04f2bb01,
+        0xb6054ffd,
+/* 0x0386: init_unk_next */
+        0x20b60130,
+        0x04e0b601,
+        0xf40126b0,
+/* 0x0392: init_unk_done */
+        0x0380e21b,
+        0x08048007,
+        0x010027f1,
+        0xcf0223f0,
+        0x34bd0022,
+        0x070047f1,
+        0x950644b6,
+        0x45d00825,
+        0x4045d000,
+        0x98000e98,
+        0x21f5010f,
+        0x2fbb0147,
+        0x003fbb00,
+        0x98010e98,
+        0x21f5020f,
+        0x0e980147,
+        0x00effd05,
+        0xbb002ebb,
+        0x0e98003e,
+        0x030f9802,
+        0x014721f5,
+        0xfd070e98,
+        0x2ebb00ef,
+        0x003ebb00,
+        0x130040b7,
+        0xd00235b6,
+        0x25b60043,
+        0x0635b608,
+        0xb60120b6,
+        0x24b60130,
+        0x0834b608,
+        0xf5022fb9,
+        0xbb027121,
+        0x07f1003f,
+        0x03f00100,
+        0x0003d002,
+        0x24bd04bd,
+        0xf11f29f0,
+        0xf0080007,
+        0x02d00203,
+/* 0x0433: main */
+        0xf404bd00,
+        0x28f40031,
+        0x24d7f000,
+        0xf43921f4,
+        0xe4b0f401,
+        0x1e18f404,
+        0xf00181fe,
+        0x20bd0627,
+        0xb60412fd,
+        0x1efd01e4,
+        0x0018fe05,
+        0x04f721f5,
+/* 0x0463: main_not_ctx_xfer */
+        0x94d30ef4,
+        0xf5f010ef,
+        0xfe21f501,
+        0xc60ef402,
+/* 0x0470: ih */
+        0x88fe80f9,
+        0xf980f901,
+        0xf9a0f990,
+        0xf9d0f9b0,
+        0xbdf0f9e0,
+        0x800acf04,
+        0xf404abc4,
+        0xb7f11d0b,
+        0xd7f01900,
+        0x40becf24,
+        0xf400bfcf,
+        0xb0b70421,
+        0xe7f00400,
+        0x00bed001,
+/* 0x04a8: ih_no_fifo */
+        0xfc400ad0,
+        0xfce0fcf0,
+        0xfcb0fcd0,
+        0xfc90fca0,
+        0x0088fe80,
+        0x32f480fc,
+/* 0x04c3: hub_barrier_done */
+        0xf001f800,
+        0x0e9801f7,
+        0x04febb04,
+        0x9418e7f1,
+        0xf440e3f0,
+        0x00f88d21,
+/* 0x04d8: ctx_redswitch */
+        0x0614e7f1,
+        0xf006e4b6,
+        0xefd020f7,
+        0x08f7f000,
+/* 0x04e8: ctx_redswitch_delay */
+        0xf401f2b6,
+        0xf7f1fd1b,
+        0xefd00a20,
+/* 0x04f7: ctx_xfer */
+        0xf100f800,
+        0xb60a0417,
+        0x1fd00614,
+        0x0711f400,
+        0x04d821f5,
+/* 0x0508: ctx_xfer_not_load */
+        0x4afc17f1,
+        0xf00213f0,
+        0x12d00c27,
+        0x1521f500,
+        0xfc27f102,
+        0x0223f047,
+        0xf00020d0,
+        0x20b6012c,
+        0x0012d003,
+        0xf001acf0,
+        0xb7f002a5,
+        0x50b3f000,
+        0xb6040c98,
+        0xbcbb0fc4,
+        0x000c9800,
+        0xf0010d98,
+        0x21f500e7,
+        0xacf00166,
+        0x00b7f101,
+        0x50b3f040,
+        0xb6040c98,
+        0xbcbb0fc4,
+        0x010c9800,
+        0x98020d98,
+        0xe7f1060f,
+        0x21f50800,
+        0xacf00166,
+        0x04a5f001,
+        0x3000b7f1,
+        0x9850b3f0,
+        0xc4b6040c,
+        0x00bcbb0f,
+        0x98020c98,
+        0x0f98030d,
+        0x00e7f108,
+        0x6621f502,
+        0x1521f501,
+        0x0601f402,
+/* 0x05a3: ctx_xfer_post */
+        0xf11412f4,
+        0xf04afc17,
+        0x27f00213,
+        0x0012d00d,
+        0x021521f5,
+/* 0x05b4: ctx_xfer_done */
+        0x04c321f5,
+        0x000000f8,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+};
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnve0.fuc b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnve0.fuc
index 62ab231cd6b6..6b906cd2a31f 100644
--- a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnve0.fuc
+++ b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnve0.fuc
@@ -1,6 +1,5 @@
-/* fuc microcode for nve0 PGRAPH/GPC
- *
- * Copyright 2011 Red Hat Inc.
+/*
+ * Copyright 2013 Red Hat Inc.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -20,437 +19,24 @@
  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  * OTHER DEALINGS IN THE SOFTWARE.
  *
- * Authors: Ben Skeggs
+ * Authors: Ben Skeggs <bskeggs@redhat.com>
  */
 
-/* To build:
- *    m4 nve0_grgpc.fuc | envyas -a -w -m fuc -V nva3 -o nve0_grgpc.fuc.h
- */
+#define NV_PGRAPH_GPCX_UNK__SIZE                                     0x00000001
 
-/* TODO
- * - bracket certain functions with scratch writes, useful for debugging
- * - watchdog timer around ctx operations
- */
+#define CHIPSET GK100
+#include "macros.fuc"
 
 .section #nve0_grgpc_data
-include(`nve0.fuc')
-gpc_id:                 .b32 0
-gpc_mmio_list_head:     .b32 0
-gpc_mmio_list_tail:     .b32 0
-
-tpc_count:              .b32 0
-tpc_mask:               .b32 0
-tpc_mmio_list_head:     .b32 0
-tpc_mmio_list_tail:     .b32 0
-
-cmd_queue:              queue_init
-
-// chipset descriptions
-chipsets:
-.b8  0xe4 0 0 0
-.b16 #nve4_gpc_mmio_head
-.b16 #nve4_gpc_mmio_tail
-.b16 #nve4_tpc_mmio_head
-.b16 #nve4_tpc_mmio_tail
-.b8  0xe7 0 0 0
-.b16 #nve4_gpc_mmio_head
-.b16 #nve4_gpc_mmio_tail
-.b16 #nve4_tpc_mmio_head
-.b16 #nve4_tpc_mmio_tail
-.b8  0xe6 0 0 0
-.b16 #nve4_gpc_mmio_head
-.b16 #nve4_gpc_mmio_tail
-.b16 #nve4_tpc_mmio_head
-.b16 #nve4_tpc_mmio_tail
-.b8  0 0 0 0
-
-// GPC mmio lists
-nve4_gpc_mmio_head:
-mmctx_data(0x000380, 1)
-mmctx_data(0x000400, 2)
-mmctx_data(0x00040c, 3)
-mmctx_data(0x000450, 9)
-mmctx_data(0x000600, 1)
-mmctx_data(0x000684, 1)
-mmctx_data(0x000700, 5)
-mmctx_data(0x000800, 1)
-mmctx_data(0x000808, 3)
-mmctx_data(0x000828, 1)
-mmctx_data(0x000830, 1)
-mmctx_data(0x0008d8, 1)
-mmctx_data(0x0008e0, 1)
-mmctx_data(0x0008e8, 6)
-mmctx_data(0x00091c, 1)
-mmctx_data(0x000924, 3)
-mmctx_data(0x000b00, 1)
-mmctx_data(0x000b08, 6)
-mmctx_data(0x000bb8, 1)
-mmctx_data(0x000c08, 1)
-mmctx_data(0x000c10, 8)
-mmctx_data(0x000c40, 1)
-mmctx_data(0x000c6c, 1)
-mmctx_data(0x000c80, 1)
-mmctx_data(0x000c8c, 1)
-mmctx_data(0x001000, 3)
-mmctx_data(0x001014, 1)
-mmctx_data(0x003024, 1)
-mmctx_data(0x0030c0, 2)
-mmctx_data(0x0030e4, 1)
-mmctx_data(0x003100, 6)
-mmctx_data(0x0031d0, 1)
-mmctx_data(0x0031e0, 2)
-nve4_gpc_mmio_tail:
-
-// TPC mmio lists
-nve4_tpc_mmio_head:
-mmctx_data(0x000048, 1)
-mmctx_data(0x000064, 1)
-mmctx_data(0x000088, 1)
-mmctx_data(0x000200, 6)
-mmctx_data(0x00021c, 2)
-mmctx_data(0x000230, 1)
-mmctx_data(0x0002c4, 1)
-mmctx_data(0x000400, 3)
-mmctx_data(0x000420, 3)
-mmctx_data(0x0004e8, 1)
-mmctx_data(0x0004f4, 1)
-mmctx_data(0x000604, 4)
-mmctx_data(0x000644, 22)
-mmctx_data(0x0006ac, 2)
-mmctx_data(0x0006c8, 1)
-mmctx_data(0x000730, 8)
-mmctx_data(0x000758, 1)
-mmctx_data(0x000778, 1)
-nve4_tpc_mmio_tail:
+#define INCLUDE_DATA
+#include "com.fuc"
+#include "gpc.fuc"
+#undef INCLUDE_DATA
 
 .section #nve0_grgpc_code
+#define INCLUDE_CODE
 bra #init
-define(`include_code')
-include(`nve0.fuc')
-
-// reports an exception to the host
-//
-// In: $r15 error code (see nve0.fuc)
-//
-error:
-        push $r14
-        mov $r14 -0x67ec        // 0x9814
-        sethi $r14 0x400000
-        call #nv_wr32           // HUB_CTXCTL_CC_SCRATCH[5] = error code
-        add b32 $r14 0x41c
-        mov $r15 1
-        call #nv_wr32           // HUB_CTXCTL_INTR_UP_SET
-        pop $r14
-        ret
-
-// GPC fuc initialisation, executed by triggering ucode start, will
-// fall through to main loop after completion.
-//
-// Input:
-//   CC_SCRATCH[0]: chipset (PMC_BOOT_0 read returns 0x0bad0bad... sigh)
-//   CC_SCRATCH[1]: context base
-//
-// Output:
-//   CC_SCRATCH[0]:
-//           31:31: set to signal completion
-//   CC_SCRATCH[1]:
-//            31:0: GPC context size
-//
-init:
-        clear b32 $r0
-        mov $sp $r0
-
-        // enable fifo access
-        mov $r1 0x1200
-        mov $r2 2
-        iowr I[$r1 + 0x000] $r2         // FIFO_ENABLE
-
-        // setup i0 handler, and route all interrupts to it
-        mov $r1 #ih
-        mov $iv0 $r1
-        mov $r1 0x400
-        iowr I[$r1 + 0x300] $r0         // INTR_DISPATCH
-
-        // enable fifo interrupt
-        mov $r2 4
-        iowr I[$r1 + 0x000] $r2         // INTR_EN_SET
-
-        // enable interrupts
-        bset $flags ie0
-
-        // figure out which GPC we are, and how many TPCs we have
-        mov $r1 0x608
-        shl b32 $r1 6
-        iord $r2 I[$r1 + 0x000]         // UNITS
-        mov $r3 1
-        and $r2 0x1f
-        shl b32 $r3 $r2
-        sub b32 $r3 1
-        st b32 D[$r0 + #tpc_count] $r2
-        st b32 D[$r0 + #tpc_mask] $r3
-        add b32 $r1 0x400
-        iord $r2 I[$r1 + 0x000]         // MYINDEX
-        st b32 D[$r0 + #gpc_id] $r2
-
-        // find context data for this chipset
-        mov $r2 0x800
-        shl b32 $r2 6
-        iord $r2 I[$r2 + 0x000]         // CC_SCRATCH[0]
-        mov $r1 #chipsets - 12
-        init_find_chipset:
-                add b32 $r1 12
-                ld b32 $r3 D[$r1 + 0x00]
-                cmpu b32 $r3 $r2
-                bra e #init_context
-                cmpu b32 $r3 0
-                bra ne #init_find_chipset
-                // unknown chipset
-                ret
-
-        // initialise context base, and size tracking
-        init_context:
-        mov $r2 0x800
-        shl b32 $r2 6
-        iord $r2 I[$r2 + 0x100] // CC_SCRATCH[1], initial base
-        clear b32 $r3           // track GPC context size here
-
-        // set mmctx base addresses now so we don't have to do it later,
-        // they don't currently ever change
-        mov $r4 0x700
-        shl b32 $r4 6
-        shr b32 $r5 $r2 8
-        iowr I[$r4 + 0x000] $r5         // MMCTX_SAVE_SWBASE
-        iowr I[$r4 + 0x100] $r5         // MMCTX_LOAD_SWBASE
-
-        // calculate GPC mmio context size, store the chipset-specific
-        // mmio list pointers somewhere we can get at them later without
-        // re-parsing the chipset list
-        clear b32 $r14
-        clear b32 $r15
-        ld b16 $r14 D[$r1 + 4]
-        ld b16 $r15 D[$r1 + 6]
-        st b16 D[$r0 + #gpc_mmio_list_head] $r14
-        st b16 D[$r0 + #gpc_mmio_list_tail] $r15
-        call #mmctx_size
-        add b32 $r2 $r15
-        add b32 $r3 $r15
-
-        // calculate per-TPC mmio context size, store the list pointers
-        ld b16 $r14 D[$r1 + 8]
-        ld b16 $r15 D[$r1 + 10]
-        st b16 D[$r0 + #tpc_mmio_list_head] $r14
-        st b16 D[$r0 + #tpc_mmio_list_tail] $r15
-        call #mmctx_size
-        ld b32 $r14 D[$r0 + #tpc_count]
-        mulu $r14 $r15
-        add b32 $r2 $r14
-        add b32 $r3 $r14
-
-        // round up base/size to 256 byte boundary (for strand SWBASE)
-        add b32 $r4 0x1300
-        shr b32 $r3 2
-        iowr I[$r4 + 0x000] $r3         // MMCTX_LOAD_COUNT, wtf for?!?
-        shr b32 $r2 8
-        shr b32 $r3 6
-        add b32 $r2 1
-        add b32 $r3 1
-        shl b32 $r2 8
-        shl b32 $r3 8
-
-        // calculate size of strand context data
-        mov b32 $r15 $r2
-        call #strand_ctx_init
-        add b32 $r3 $r15
-
-        // save context size, and tell HUB we're done
-        mov $r1 0x800
-        shl b32 $r1 6
-        iowr I[$r1 + 0x100] $r3         // CC_SCRATCH[1]  = context size
-        add b32 $r1 0x800
-        clear b32 $r2
-        bset $r2 31
-        iowr I[$r1 + 0x000] $r2         // CC_SCRATCH[0] |= 0x80000000
-
-// Main program loop, very simple, sleeps until woken up by the interrupt
-// handler, pulls a command from the queue and executes its handler
-//
-main:
-        bset $flags $p0
-        sleep $p0
-        mov $r13 #cmd_queue
-        call #queue_get
-        bra $p1 #main
-
-        // 0x0000-0x0003 are all context transfers
-        cmpu b32 $r14 0x04
-        bra nc #main_not_ctx_xfer
-                // fetch $flags and mask off $p1/$p2
-                mov $r1 $flags
-                mov $r2 0x0006
-                not b32 $r2
-                and $r1 $r2
-                // set $p1/$p2 according to transfer type
-                shl b32 $r14 1
-                or $r1 $r14
-                mov $flags $r1
-                // transfer context data
-                call #ctx_xfer
-                bra #main
-
-        main_not_ctx_xfer:
-        shl b32 $r15 $r14 16
-        or $r15 E_BAD_COMMAND
-        call #error
-        bra #main
-
-// interrupt handler
-ih:
-        push $r8
-        mov $r8 $flags
-        push $r8
-        push $r9
-        push $r10
-        push $r11
-        push $r13
-        push $r14
-        push $r15
-
-        // incoming fifo command?
-        iord $r10 I[$r0 + 0x200]        // INTR
-        and $r11 $r10 0x00000004
-        bra e #ih_no_fifo
-                // queue incoming fifo command for later processing
-                mov $r11 0x1900
-                mov $r13 #cmd_queue
-                iord $r14 I[$r11 + 0x100]       // FIFO_CMD
-                iord $r15 I[$r11 + 0x000]       // FIFO_DATA
-                call #queue_put
-                add b32 $r11 0x400
-                mov $r14 1
-                iowr I[$r11 + 0x000] $r14       // FIFO_ACK
-
-        // ack, and wake up main()
-        ih_no_fifo:
-        iowr I[$r0 + 0x100] $r10        // INTR_ACK
-
-        pop $r15
-        pop $r14
-        pop $r13
-        pop $r11
-        pop $r10
-        pop $r9
-        pop $r8
-        mov $flags $r8
-        pop $r8
-        bclr $flags $p0
-        iret
-
-// Set this GPC's bit in HUB_BAR, used to signal completion of various
-// activities to the HUB fuc
-//
-hub_barrier_done:
-        mov $r15 1
-        ld b32 $r14 D[$r0 + #gpc_id]
-        shl b32 $r15 $r14
-        mov $r14 -0x6be8        // 0x409418 - HUB_BAR_SET
-        sethi $r14 0x400000
-        call #nv_wr32
-        ret
-
-// Disables various things, waits a bit, and re-enables them..
-//
-// Not sure how exactly this helps, perhaps "ENABLE" is not such a
-// good description for the bits we turn off?  Anyways, without this,
-// funny things happen.
-//
-ctx_redswitch:
-        mov $r14 0x614
-        shl b32 $r14 6
-        mov $r15 0x020
-        iowr I[$r14] $r15       // GPC_RED_SWITCH = POWER
-        mov $r15 8
-        ctx_redswitch_delay:
-                sub b32 $r15 1
-                bra ne #ctx_redswitch_delay
-        mov $r15 0xa20
-        iowr I[$r14] $r15       // GPC_RED_SWITCH = UNK11, ENABLE, POWER
-        ret
-
-// Transfer GPC context data between GPU and storage area
-//
-// In: $r15 context base address
-//     $p1 clear on save, set on load
-//     $p2 set if opposite direction done/will be done, so:
-//              on save it means: "a load will follow this save"
-//              on load it means: "a save preceeded this load"
-//
-ctx_xfer:
-        // set context base address
-        mov $r1 0xa04
-        shl b32 $r1 6
-        iowr I[$r1 + 0x000] $r15// MEM_BASE
-        bra not $p1 #ctx_xfer_not_load
-                call #ctx_redswitch
-        ctx_xfer_not_load:
-
-        // strands
-        mov $r1 0x4afc
-        sethi $r1 0x20000
-        mov $r2 0xc
-        iowr I[$r1] $r2         // STRAND_CMD(0x3f) = 0x0c
-        call #strand_wait
-        mov $r2 0x47fc
-        sethi $r2 0x20000
-        iowr I[$r2] $r0         // STRAND_FIRST_GENE(0x3f) = 0x00
-        xbit $r2 $flags $p1
-        add b32 $r2 3
-        iowr I[$r1] $r2         // STRAND_CMD(0x3f) = 0x03/0x04 (SAVE/LOAD)
-
-        // mmio context
-        xbit $r10 $flags $p1    // direction
-        or $r10 2               // first
-        mov $r11 0x0000
-        sethi $r11 0x500000
-        ld b32 $r12 D[$r0 + #gpc_id]
-        shl b32 $r12 15
-        add b32 $r11 $r12       // base = NV_PGRAPH_GPCn
-        ld b32 $r12 D[$r0 + #gpc_mmio_list_head]
-        ld b32 $r13 D[$r0 + #gpc_mmio_list_tail]
-        mov $r14 0              // not multi
-        call #mmctx_xfer
-
-        // per-TPC mmio context
-        xbit $r10 $flags $p1    // direction
-        or $r10 4               // last
-        mov $r11 0x4000
-        sethi $r11 0x500000     // base = NV_PGRAPH_GPC0_TPC0
-        ld b32 $r12 D[$r0 + #gpc_id]
-        shl b32 $r12 15
-        add b32 $r11 $r12       // base = NV_PGRAPH_GPCn_TPC0
-        ld b32 $r12 D[$r0 + #tpc_mmio_list_head]
-        ld b32 $r13 D[$r0 + #tpc_mmio_list_tail]
-        ld b32 $r15 D[$r0 + #tpc_mask]
-        mov $r14 0x800          // stride = 0x800
-        call #mmctx_xfer
-
-        // wait for strands to finish
-        call #strand_wait
-
-        // if load, or a save without a load following, do some
-        // unknown stuff that's done after finishing a block of
-        // strand commands
-        bra $p1 #ctx_xfer_post
-        bra not $p2 #ctx_xfer_done
-        ctx_xfer_post:
-                mov $r1 0x4afc
-                sethi $r1 0x20000
-                mov $r2 0xd
-                iowr I[$r1] $r2         // STRAND_CMD(0x3f) = 0x0d
-                call #strand_wait
-
-        // mark completion in HUB's barrier
-        ctx_xfer_done:
-        call #hub_barrier_done
-        ret
-
+#include "com.fuc"
+#include "gpc.fuc"
 .align 256
+#undef INCLUDE_CODE
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnve0.fuc.h b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnve0.fuc.h
index 09ee4702c8b2..7ff5ef6b0804 100644
--- a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnve0.fuc.h
+++ b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnve0.fuc.h
@@ -1,19 +1,27 @@
 uint32_t nve0_grgpc_data[] = {
-/* 0x0000: gpc_id */
+/* 0x0000: gpc_mmio_list_head */
+        0x0000006c,
+/* 0x0004: gpc_mmio_list_tail */
+/* 0x0004: tpc_mmio_list_head */
+        0x0000006c,
+/* 0x0008: tpc_mmio_list_tail */
+/* 0x0008: unk_mmio_list_head */
+        0x0000006c,
+/* 0x000c: unk_mmio_list_tail */
+        0x0000006c,
+/* 0x0010: gpc_id */
         0x00000000,
-/* 0x0004: gpc_mmio_list_head */
+/* 0x0014: tpc_count */
         0x00000000,
-/* 0x0008: gpc_mmio_list_tail */
+/* 0x0018: tpc_mask */
         0x00000000,
-/* 0x000c: tpc_count */
+/* 0x001c: unk_count */
         0x00000000,
-/* 0x0010: tpc_mask */
+/* 0x0020: unk_mask */
         0x00000000,
-/* 0x0014: tpc_mmio_list_head */
+/* 0x0024: cmd_queue */
         0x00000000,
-/* 0x0018: tpc_mmio_list_tail */
         0x00000000,
-/* 0x001c: cmd_queue */
         0x00000000,
         0x00000000,
         0x00000000,
@@ -30,84 +38,17 @@ uint32_t nve0_grgpc_data[] = {
         0x00000000,
         0x00000000,
         0x00000000,
-        0x00000000,
-        0x00000000,
-/* 0x0064: chipsets */
-        0x000000e4,
-        0x0110008c,
-        0x01580110,
-        0x000000e7,
-        0x0110008c,
-        0x01580110,
-        0x000000e6,
-        0x0110008c,
-        0x01580110,
-        0x00000000,
-/* 0x008c: nve4_gpc_mmio_head */
-        0x00000380,
-        0x04000400,
-        0x0800040c,
-        0x20000450,
-        0x00000600,
-        0x00000684,
-        0x10000700,
-        0x00000800,
-        0x08000808,
-        0x00000828,
-        0x00000830,
-        0x000008d8,
-        0x000008e0,
-        0x140008e8,
-        0x0000091c,
-        0x08000924,
-        0x00000b00,
-        0x14000b08,
-        0x00000bb8,
-        0x00000c08,
-        0x1c000c10,
-        0x00000c40,
-        0x00000c6c,
-        0x00000c80,
-        0x00000c8c,
-        0x08001000,
-        0x00001014,
-        0x00003024,
-        0x040030c0,
-        0x000030e4,
-        0x14003100,
-        0x000031d0,
-        0x040031e0,
-/* 0x0110: nve4_gpc_mmio_tail */
-/* 0x0110: nve4_tpc_mmio_head */
-        0x00000048,
-        0x00000064,
-        0x00000088,
-        0x14000200,
-        0x0400021c,
-        0x00000230,
-        0x000002c4,
-        0x08000400,
-        0x08000420,
-        0x000004e8,
-        0x000004f4,
-        0x0c000604,
-        0x54000644,
-        0x040006ac,
-        0x000006c8,
-        0x1c000730,
-        0x00000758,
-        0x00000778,
 };
 
 uint32_t nve0_grgpc_code[] = {
-        0x03060ef5,
+        0x03180ef5,
 /* 0x0004: queue_put */
         0x9800d898,
         0x86f001d9,
         0x0489b808,
         0xf00c1bf4,
         0x21f502f7,
-        0x00f802ec,
+        0x00f802fe,
 /* 0x001c: queue_put_next */
         0xb60798c4,
         0x8dbb0384,
@@ -139,7 +80,7 @@ uint32_t nve0_grgpc_code[] = {
         0xc800bccf,
         0x1bf41fcc,
         0x06a7f0fa,
-        0x010321f5,
+        0x010921f5,
         0xf840bfcf,
 /* 0x008d: nv_wr32 */
         0x28b7f100,
@@ -161,63 +102,66 @@ uint32_t nve0_grgpc_code[] = {
         0x0684b604,
         0xf80080d0,
 /* 0x00c9: wait_donez */
-        0x3c87f100,
-        0x0684b608,
-        0x99f094bd,
-        0x0089d000,
-        0x081887f1,
-        0xd00684b6,
-/* 0x00e2: wait_done_wait_donez */
-        0x87f1008a,
-        0x84b60400,
-        0x0088cf06,
+        0xf094bd00,
+        0x07f10099,
+        0x03f00f00,
+        0x0009d002,
+        0x07f104bd,
+        0x03f00600,
+        0x000ad002,
+/* 0x00e6: wait_donez_ne */
+        0x87f104bd,
+        0x83f00000,
+        0x0088cf01,
         0xf4888aff,
-        0x87f1f31b,
-        0x84b6085c,
-        0xf094bd06,
-        0x89d00099,
-/* 0x0103: wait_doneo */
-        0xf100f800,
-        0xb6083c87,
-        0x94bd0684,
-        0xd00099f0,
-        0x87f10089,
+        0x94bdf31b,
+        0xf10099f0,
+        0xf0170007,
+        0x09d00203,
+        0xf804bd00,
+/* 0x0109: wait_doneo */
+        0xf094bd00,
+        0x07f10099,
+        0x03f00f00,
+        0x0009d002,
+        0x87f104bd,
         0x84b60818,
         0x008ad006,
-/* 0x011c: wait_done_wait_doneo */
+/* 0x0124: wait_doneo_e */
         0x040087f1,
         0xcf0684b6,
         0x8aff0088,
         0xf30bf488,
-        0x085c87f1,
-        0xbd0684b6,
-        0x0099f094,
-        0xf80089d0,
-/* 0x013d: mmctx_size */
-/* 0x013f: nv_mmctx_size_loop */
-        0x9894bd00,
-        0x85b600e8,
-        0x0180b61a,
-        0xbb0284b6,
-        0xe0b60098,
-        0x04efb804,
-        0xb9eb1bf4,
-        0x00f8029f,
-/* 0x015c: mmctx_xfer */
-        0x083c87f1,
-        0xbd0684b6,
-        0x0199f094,
-        0xf10089d0,
+        0x99f094bd,
+        0x0007f100,
+        0x0203f017,
+        0xbd0009d0,
+/* 0x0147: mmctx_size */
+        0xbd00f804,
+/* 0x0149: nv_mmctx_size_loop */
+        0x00e89894,
+        0xb61a85b6,
+        0x84b60180,
+        0x0098bb02,
+        0xb804e0b6,
+        0x1bf404ef,
+        0x029fb9eb,
+/* 0x0166: mmctx_xfer */
+        0x94bd00f8,
+        0xf10199f0,
+        0xf00f0007,
+        0x09d00203,
+        0xf104bd00,
         0xb6071087,
         0x94bd0684,
         0xf405bbfd,
         0x8bd0090b,
         0x0099f000,
-/* 0x0180: mmctx_base_disabled */
+/* 0x018c: mmctx_base_disabled */
         0xf405eefd,
         0x8ed00c0b,
         0xc08fd080,
-/* 0x018f: mmctx_multi_disabled */
+/* 0x019b: mmctx_multi_disabled */
         0xb70199f0,
         0xc8010080,
         0xb4b600ab,
@@ -225,8 +169,8 @@ uint32_t nve0_grgpc_code[] = {
         0xb601aec8,
         0xbefd11e4,
         0x008bd005,
-/* 0x01a8: mmctx_exec_loop */
-/* 0x01a8: mmctx_wait_free */
+/* 0x01b4: mmctx_exec_loop */
+/* 0x01b4: mmctx_wait_free */
         0xf0008ecf,
         0x0bf41fe4,
         0x00ce98fa,
@@ -235,76 +179,77 @@ uint32_t nve0_grgpc_code[] = {
         0x04cdb804,
         0xc8e81bf4,
         0x1bf402ab,
-/* 0x01c9: mmctx_fini_wait */
+/* 0x01d5: mmctx_fini_wait */
         0x008bcf18,
         0xb01fb4f0,
         0x1bf410b4,
         0x02a7f0f7,
         0xf4c921f4,
-/* 0x01de: mmctx_stop */
+/* 0x01ea: mmctx_stop */
         0xabc81b0e,
         0x10b4b600,
         0xf00cb9f0,
         0x8bd012b9,
-/* 0x01ed: mmctx_stop_wait */
+/* 0x01f9: mmctx_stop_wait */
         0x008bcf00,
         0xf412bbc8,
-/* 0x01f6: mmctx_done */
-        0x87f1fa1b,
-        0x84b6085c,
-        0xf094bd06,
-        0x89d00199,
-/* 0x0207: strand_wait */
-        0xf900f800,
-        0x02a7f0a0,
-        0xfcc921f4,
-/* 0x0213: strand_pre */
-        0xf100f8a0,
-        0xf04afc87,
-        0x97f00283,
-        0x0089d00c,
-        0x020721f5,
-/* 0x0226: strand_post */
-        0x87f100f8,
-        0x83f04afc,
-        0x0d97f002,
-        0xf50089d0,
-        0xf8020721,
-/* 0x0239: strand_set */
-        0xfca7f100,
-        0x02a3f04f,
-        0x0500aba2,
-        0xd00fc7f0,
-        0xc7f000ac,
-        0x00bcd00b,
-        0x020721f5,
-        0xf000aed0,
-        0xbcd00ac7,
-        0x0721f500,
-/* 0x0263: strand_ctx_init */
-        0xf100f802,
-        0xb6083c87,
-        0x94bd0684,
-        0xd00399f0,
+/* 0x0202: mmctx_done */
+        0x94bdfa1b,
+        0xf10199f0,
+        0xf0170007,
+        0x09d00203,
+        0xf804bd00,
+/* 0x0215: strand_wait */
+        0xf0a0f900,
+        0x21f402a7,
+        0xf8a0fcc9,
+/* 0x0221: strand_pre */
+        0xfc87f100,
+        0x0283f04a,
+        0xd00c97f0,
         0x21f50089,
-        0xe7f00213,
-        0x3921f503,
+        0x00f80215,
+/* 0x0234: strand_post */
+        0x4afc87f1,
+        0xf00283f0,
+        0x89d00d97,
+        0x1521f500,
+/* 0x0247: strand_set */
+        0xf100f802,
+        0xf04ffca7,
+        0xaba202a3,
+        0xc7f00500,
+        0x00acd00f,
+        0xd00bc7f0,
+        0x21f500bc,
+        0xaed00215,
+        0x0ac7f000,
+        0xf500bcd0,
+        0xf8021521,
+/* 0x0271: strand_ctx_init */
+        0xf094bd00,
+        0x07f10399,
+        0x03f00f00,
+        0x0009d002,
+        0x21f504bd,
+        0xe7f00221,
+        0x4721f503,
         0xfca7f102,
         0x02a3f046,
         0x0400aba0,
         0xf040a0d0,
         0xbcd001c7,
-        0x0721f500,
+        0x1521f500,
         0x010c9202,
         0xf000acd0,
         0xbcd002c7,
-        0x0721f500,
-        0x2621f502,
+        0x1521f500,
+        0x3421f502,
         0x8087f102,
         0x0684b608,
         0xb70089cf,
         0x95220080,
-/* 0x02ba: ctx_init_strand_loop */
+/* 0x02ca: ctx_init_strand_loop */
         0x8ed008fe,
         0x408ed000,
         0xb6808acf,
@@ -313,150 +258,160 @@ uint32_t nve0_grgpc_code[] = {
         0xb60480b6,
         0x1bf40192,
         0x08e4b6e8,
-        0xf1f2efbc,
-        0xb6085c87,
-        0x94bd0684,
-        0xd00399f0,
-        0x00f80089,
-/* 0x02ec: error */
-        0xe7f1e0f9,
-        0xe3f09814,
-        0x8d21f440,
-        0x041ce0b7,
-        0xf401f7f0,
-        0xe0fc8d21,
-/* 0x0306: init */
-        0x04bd00f8,
-        0xf10004fe,
-        0xf0120017,
-        0x12d00227,
-        0x3e17f100,
-        0x0010fe04,
-        0x040017f1,
-        0xf0c010d0,
-        0x12d00427,
-        0x1031f400,
-        0x060817f1,
-        0xcf0614b6,
-        0x37f00012,
-        0x1f24f001,
-        0xb60432bb,
-        0x02800132,
-        0x04038003,
-        0x040010b7,
-        0x800012cf,
-        0x27f10002,
-        0x24b60800,
-        0x0022cf06,
-/* 0x035f: init_find_chipset */
-        0xb65817f0,
-        0x13980c10,
-        0x0432b800,
-        0xb00b0bf4,
-        0x1bf40034,
-/* 0x0373: init_context */
-        0xf100f8f1,
-        0xb6080027,
-        0x22cf0624,
-        0xf134bd40,
-        0xb6070047,
-        0x25950644,
-        0x0045d008,
-        0xbd4045d0,
-        0x58f4bde4,
-        0x1f58021e,
-        0x020e4003,
-        0xf5040f40,
-        0xbb013d21,
-        0x3fbb002f,
-        0x041e5800,
-        0x40051f58,
-        0x0f400a0e,
-        0x3d21f50c,
-        0x030e9801,
-        0xbb00effd,
-        0x3ebb002e,
-        0x0040b700,
-        0x0235b613,
-        0xb60043d0,
-        0x35b60825,
-        0x0120b606,
-        0xb60130b6,
-        0x34b60824,
-        0x022fb908,
-        0x026321f5,
-        0xf1003fbb,
-        0xb6080017,
-        0x13d00614,
-        0x0010b740,
-        0xf024bd08,
-        0x12d01f29,
-/* 0x0401: main */
-        0x0031f400,
-        0xf00028f4,
-        0x21f41cd7,
-        0xf401f439,
-        0xf404e4b0,
-        0x81fe1e18,
-        0x0627f001,
-        0x12fd20bd,
-        0x01e4b604,
-        0xfe051efd,
-        0x21f50018,
-        0x0ef404c3,
-/* 0x0431: main_not_ctx_xfer */
-        0x10ef94d3,
-        0xf501f5f0,
-        0xf402ec21,
-/* 0x043e: ih */
-        0x80f9c60e,
-        0xf90188fe,
-        0xf990f980,
-        0xf9b0f9a0,
-        0xf9e0f9d0,
-        0x800acff0,
+        0xbdf2efbc,
+        0x0399f094,
+        0x170007f1,
+        0xd00203f0,
+        0x04bd0009,
+/* 0x02fe: error */
+        0xe0f900f8,
+        0x9814e7f1,
+        0xf440e3f0,
+        0xe0b78d21,
+        0xf7f0041c,
+        0x8d21f401,
+        0x00f8e0fc,
+/* 0x0318: init */
+        0x04fe04bd,
+        0x0017f100,
+        0x0227f012,
+        0xf10012d0,
+        0xfe047017,
+        0x17f10010,
+        0x10d00400,
+        0x0427f0c0,
+        0xf40012d0,
+        0x17f11031,
+        0x14b60608,
+        0x0012cf06,
+        0xf00137f0,
+        0x32bb1f24,
+        0x0132b604,
+        0x80050280,
+        0x10b70603,
+        0x12cf0400,
+        0x04028000,
+        0x0c30e7f1,
+        0xbd50e3f0,
+        0xbd34bd24,
+/* 0x0371: init_unk_loop */
+        0x6821f444,
+        0xf400f6b0,
+        0xf7f00f0b,
+        0x04f2bb01,
+        0xb6054ffd,
+/* 0x0386: init_unk_next */
+        0x20b60130,
+        0x04e0b601,
+        0xf40126b0,
+/* 0x0392: init_unk_done */
+        0x0380e21b,
+        0x08048007,
+        0x010027f1,
+        0xcf0223f0,
+        0x34bd0022,
+        0x070047f1,
+        0x950644b6,
+        0x45d00825,
+        0x4045d000,
+        0x98000e98,
+        0x21f5010f,
+        0x2fbb0147,
+        0x003fbb00,
+        0x98010e98,
+        0x21f5020f,
+        0x0e980147,
+        0x00effd05,
+        0xbb002ebb,
+        0x0e98003e,
+        0x030f9802,
+        0x014721f5,
+        0xfd070e98,
+        0x2ebb00ef,
+        0x003ebb00,
+        0x130040b7,
+        0xd00235b6,
+        0x25b60043,
+        0x0635b608,
+        0xb60120b6,
+        0x24b60130,
+        0x0834b608,
+        0xf5022fb9,
+        0xbb027121,
+        0x07f1003f,
+        0x03f00100,
+        0x0003d002,
+        0x24bd04bd,
+        0xf11f29f0,
+        0xf0080007,
+        0x02d00203,
+/* 0x0433: main */
+        0xf404bd00,
+        0x28f40031,
+        0x24d7f000,
+        0xf43921f4,
+        0xe4b0f401,
+        0x1e18f404,
+        0xf00181fe,
+        0x20bd0627,
+        0xb60412fd,
+        0x1efd01e4,
+        0x0018fe05,
+        0x04f721f5,
+/* 0x0463: main_not_ctx_xfer */
+        0x94d30ef4,
+        0xf5f010ef,
+        0xfe21f501,
+        0xc60ef402,
+/* 0x0470: ih */
+        0x88fe80f9,
+        0xf980f901,
+        0xf9a0f990,
+        0xf9d0f9b0,
+        0xbdf0f9e0,
+        0x800acf04,
         0xf404abc4,
         0xb7f11d0b,
         0xd7f01900,
-        0x40becf1c,
+        0x40becf24,
         0xf400bfcf,
         0xb0b70421,
         0xe7f00400,
         0x00bed001,
-/* 0x0474: ih_no_fifo */
+/* 0x04a8: ih_no_fifo */
         0xfc400ad0,
         0xfce0fcf0,
         0xfcb0fcd0,
         0xfc90fca0,
         0x0088fe80,
         0x32f480fc,
-/* 0x048f: hub_barrier_done */
+/* 0x04c3: hub_barrier_done */
         0xf001f800,
         0x0e9801f7,
-        0x04febb00,
+        0x04febb04,
         0x9418e7f1,
         0xf440e3f0,
         0x00f88d21,
-/* 0x04a4: ctx_redswitch */
+/* 0x04d8: ctx_redswitch */
         0x0614e7f1,
         0xf006e4b6,
         0xefd020f7,
         0x08f7f000,
-/* 0x04b4: ctx_redswitch_delay */
+/* 0x04e8: ctx_redswitch_delay */
         0xf401f2b6,
         0xf7f1fd1b,
         0xefd00a20,
-/* 0x04c3: ctx_xfer */
+/* 0x04f7: ctx_xfer */
         0xf100f800,
         0xb60a0417,
         0x1fd00614,
         0x0711f400,
-        0x04a421f5,
-/* 0x04d4: ctx_xfer_not_load */
+        0x04d821f5,
+/* 0x0508: ctx_xfer_not_load */
         0x4afc17f1,
         0xf00213f0,
         0x12d00c27,
-        0x0721f500,
+        0x1521f500,
         0xfc27f102,
         0x0223f047,
         0xf00020d0,
@@ -465,31 +420,40 @@ uint32_t nve0_grgpc_code[] = {
         0xf001acf0,
         0xb7f002a5,
         0x50b3f000,
-        0xb6000c98,
+        0xb6040c98,
         0xbcbb0fc4,
-        0x010c9800,
-        0xf0020d98,
+        0x000c9800,
+        0xf0010d98,
         0x21f500e7,
-        0xacf0015c,
+        0xacf00166,
+        0x00b7f101,
+        0x50b3f040,
+        0xb6040c98,
+        0xbcbb0fc4,
+        0x010c9800,
+        0x98020d98,
+        0xe7f1060f,
+        0x21f50800,
+        0xacf00166,
         0x04a5f001,
-        0x4000b7f1,
+        0x3000b7f1,
         0x9850b3f0,
-        0xc4b6000c,
+        0xc4b6040c,
         0x00bcbb0f,
-        0x98050c98,
-        0x0f98060d,
-        0x00e7f104,
-        0x5c21f508,
-        0x0721f501,
+        0x98020c98,
+        0x0f98030d,
+        0x00e7f108,
+        0x6621f502,
+        0x1521f501,
         0x0601f402,
-/* 0x054b: ctx_xfer_post */
+/* 0x05a3: ctx_xfer_post */
         0xf11412f4,
         0xf04afc17,
         0x27f00213,
         0x0012d00d,
-        0x020721f5,
-/* 0x055c: ctx_xfer_done */
-        0x048f21f5,
+        0x021521f5,
+/* 0x05b4: ctx_xfer_done */
+        0x04c321f5,
         0x000000f8,
         0x00000000,
         0x00000000,
@@ -508,26 +472,4 @@ uint32_t nve0_grgpc_code[] = {
         0x00000000,
         0x00000000,
         0x00000000,
-        0x00000000,
-        0x00000000,
-        0x00000000,
-        0x00000000,
-        0x00000000,
-        0x00000000,
-        0x00000000,
-        0x00000000,
-        0x00000000,
-        0x00000000,
-        0x00000000,
-        0x00000000,
-        0x00000000,
-        0x00000000,
-        0x00000000,
-        0x00000000,
-        0x00000000,
-        0x00000000,
-        0x00000000,
-        0x00000000,
-        0x00000000,
-        0x00000000,
 };
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvf0.fuc b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvf0.fuc
new file mode 100644
index 000000000000..90bbe525b626
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvf0.fuc
@@ -0,0 +1,42 @@
+/*
+ * Copyright 2013 Red Hat Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Ben Skeggs <bskeggs@redhat.com>
+ */
+
+#define NV_PGRAPH_GPCX_UNK__SIZE                                     0x00000002
+
+#define CHIPSET GK110
+#include "macros.fuc"
+
+.section #nvf0_grgpc_data
+#define INCLUDE_DATA
+#include "com.fuc"
+#include "gpc.fuc"
+#undef INCLUDE_DATA
+
+.section #nvf0_grgpc_code
+#define INCLUDE_CODE
+bra #init
+#include "com.fuc"
+#include "gpc.fuc"
+.align 256
+#undef INCLUDE_CODE
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvf0.fuc.h b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvf0.fuc.h
new file mode 100644
index 000000000000..f870507be880
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvf0.fuc.h
@@ -0,0 +1,475 @@
+uint32_t nvf0_grgpc_data[] = {
+/* 0x0000: gpc_mmio_list_head */
+        0x0000006c,
+/* 0x0004: gpc_mmio_list_tail */
+/* 0x0004: tpc_mmio_list_head */
+        0x0000006c,
+/* 0x0008: tpc_mmio_list_tail */
+/* 0x0008: unk_mmio_list_head */
+        0x0000006c,
+/* 0x000c: unk_mmio_list_tail */
+        0x0000006c,
+/* 0x0010: gpc_id */
+        0x00000000,
+/* 0x0014: tpc_count */
+        0x00000000,
+/* 0x0018: tpc_mask */
+        0x00000000,
+/* 0x001c: unk_count */
+        0x00000000,
+/* 0x0020: unk_mask */
+        0x00000000,
+/* 0x0024: cmd_queue */
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+};
+
+uint32_t nvf0_grgpc_code[] = {
+        0x03180ef5,
+/* 0x0004: queue_put */
+        0x9800d898,
+        0x86f001d9,
+        0x0489b808,
+        0xf00c1bf4,
+        0x21f502f7,
+        0x00f802fe,
+/* 0x001c: queue_put_next */
+        0xb60798c4,
+        0x8dbb0384,
+        0x0880b600,
+        0x80008e80,
+        0x90b6018f,
+        0x0f94f001,
+        0xf801d980,
+/* 0x0039: queue_get */
+        0x0131f400,
+        0x9800d898,
+        0x89b801d9,
+        0x210bf404,
+        0xb60789c4,
+        0x9dbb0394,
+        0x0890b600,
+        0x98009e98,
+        0x80b6019f,
+        0x0f84f001,
+        0xf400d880,
+/* 0x0066: queue_get_done */
+        0x00f80132,
+/* 0x0068: nv_rd32 */
+        0x0728b7f1,
+        0xb906b4b6,
+        0xc9f002ec,
+        0x00bcd01f,
+/* 0x0078: nv_rd32_wait */
+        0xc800bccf,
+        0x1bf41fcc,
+        0x06a7f0fa,
+        0x010921f5,
+        0xf840bfcf,
+/* 0x008d: nv_wr32 */
+        0x28b7f100,
+        0x06b4b607,
+        0xb980bfd0,
+        0xc9f002ec,
+        0x1ec9f01f,
+/* 0x00a3: nv_wr32_wait */
+        0xcf00bcd0,
+        0xccc800bc,
+        0xfa1bf41f,
+/* 0x00ae: watchdog_reset */
+        0x87f100f8,
+        0x84b60430,
+        0x1ff9f006,
+        0xf8008fd0,
+/* 0x00bd: watchdog_clear */
+        0x3087f100,
+        0x0684b604,
+        0xf80080d0,
+/* 0x00c9: wait_donez */
+        0xf094bd00,
+        0x07f10099,
+        0x03f03700,
+        0x0009d002,
+        0x07f104bd,
+        0x03f00600,
+        0x000ad002,
+/* 0x00e6: wait_donez_ne */
+        0x87f104bd,
+        0x83f00000,
+        0x0088cf01,
+        0xf4888aff,
+        0x94bdf31b,
+        0xf10099f0,
+        0xf0170007,
+        0x09d00203,
+        0xf804bd00,
+/* 0x0109: wait_doneo */
+        0xf094bd00,
+        0x07f10099,
+        0x03f03700,
+        0x0009d002,
+        0x87f104bd,
+        0x84b60818,
+        0x008ad006,
+/* 0x0124: wait_doneo_e */
+        0x040087f1,
+        0xcf0684b6,
+        0x8aff0088,
+        0xf30bf488,
+        0x99f094bd,
+        0x0007f100,
+        0x0203f017,
+        0xbd0009d0,
+/* 0x0147: mmctx_size */
+        0xbd00f804,
+/* 0x0149: nv_mmctx_size_loop */
+        0x00e89894,
+        0xb61a85b6,
+        0x84b60180,
+        0x0098bb02,
+        0xb804e0b6,
+        0x1bf404ef,
+        0x029fb9eb,
+/* 0x0166: mmctx_xfer */
+        0x94bd00f8,
+        0xf10199f0,
+        0xf0370007,
+        0x09d00203,
+        0xf104bd00,
+        0xb6071087,
+        0x94bd0684,
+        0xf405bbfd,
+        0x8bd0090b,
+        0x0099f000,
+/* 0x018c: mmctx_base_disabled */
+        0xf405eefd,
+        0x8ed00c0b,
+        0xc08fd080,
+/* 0x019b: mmctx_multi_disabled */
+        0xb70199f0,
+        0xc8010080,
+        0xb4b600ab,
+        0x0cb9f010,
+        0xb601aec8,
+        0xbefd11e4,
+        0x008bd005,
+/* 0x01b4: mmctx_exec_loop */
+/* 0x01b4: mmctx_wait_free */
+        0xf0008ecf,
+        0x0bf41fe4,
+        0x00ce98fa,
+        0xd005e9fd,
+        0xc0b6c08e,
+        0x04cdb804,
+        0xc8e81bf4,
+        0x1bf402ab,
+/* 0x01d5: mmctx_fini_wait */
+        0x008bcf18,
+        0xb01fb4f0,
+        0x1bf410b4,
+        0x02a7f0f7,
+        0xf4c921f4,
+/* 0x01ea: mmctx_stop */
+        0xabc81b0e,
+        0x10b4b600,
+        0xf00cb9f0,
+        0x8bd012b9,
+/* 0x01f9: mmctx_stop_wait */
+        0x008bcf00,
+        0xf412bbc8,
+/* 0x0202: mmctx_done */
+        0x94bdfa1b,
+        0xf10199f0,
+        0xf0170007,
+        0x09d00203,
+        0xf804bd00,
+/* 0x0215: strand_wait */
+        0xf0a0f900,
+        0x21f402a7,
+        0xf8a0fcc9,
+/* 0x0221: strand_pre */
+        0xfc87f100,
+        0x0283f04a,
+        0xd00c97f0,
+        0x21f50089,
+        0x00f80215,
+/* 0x0234: strand_post */
+        0x4afc87f1,
+        0xf00283f0,
+        0x89d00d97,
+        0x1521f500,
+/* 0x0247: strand_set */
+        0xf100f802,
+        0xf04ffca7,
+        0xaba202a3,
+        0xc7f00500,
+        0x00acd00f,
+        0xd00bc7f0,
+        0x21f500bc,
+        0xaed00215,
+        0x0ac7f000,
+        0xf500bcd0,
+        0xf8021521,
+/* 0x0271: strand_ctx_init */
+        0xf094bd00,
+        0x07f10399,
+        0x03f03700,
+        0x0009d002,
+        0x21f504bd,
+        0xe7f00221,
+        0x4721f503,
+        0xfca7f102,
+        0x02a3f046,
+        0x0400aba0,
+        0xf040a0d0,
+        0xbcd001c7,
+        0x1521f500,
+        0x010c9202,
+        0xf000acd0,
+        0xbcd002c7,
+        0x1521f500,
+        0x3421f502,
+        0x8087f102,
+        0x0684b608,
+        0xb70089cf,
+        0x95220080,
+/* 0x02ca: ctx_init_strand_loop */
+        0x8ed008fe,
+        0x408ed000,
+        0xb6808acf,
+        0xa0b606a5,
+        0x00eabb01,
+        0xb60480b6,
+        0x1bf40192,
+        0x08e4b6e8,
+        0xbdf2efbc,
+        0x0399f094,
+        0x170007f1,
+        0xd00203f0,
+        0x04bd0009,
+/* 0x02fe: error */
+        0xe0f900f8,
+        0x9814e7f1,
+        0xf440e3f0,
+        0xe0b78d21,
+        0xf7f0041c,
+        0x8d21f401,
+        0x00f8e0fc,
+/* 0x0318: init */
+        0x04fe04bd,
+        0x0017f100,
+        0x0227f012,
+        0xf10012d0,
+        0xfe047017,
+        0x17f10010,
+        0x10d00400,
+        0x0427f0c0,
+        0xf40012d0,
+        0x17f11031,
+        0x14b60608,
+        0x0012cf06,
+        0xf00137f0,
+        0x32bb1f24,
+        0x0132b604,
+        0x80050280,
+        0x10b70603,
+        0x12cf0400,
+        0x04028000,
+        0x0c30e7f1,
+        0xbd50e3f0,
+        0xbd34bd24,
+/* 0x0371: init_unk_loop */
+        0x6821f444,
+        0xf400f6b0,
+        0xf7f00f0b,
+        0x04f2bb01,
+        0xb6054ffd,
+/* 0x0386: init_unk_next */
+        0x20b60130,
+        0x04e0b601,
+        0xf40226b0,
+/* 0x0392: init_unk_done */
+        0x0380e21b,
+        0x08048007,
+        0x010027f1,
+        0xcf0223f0,
+        0x34bd0022,
+        0x070047f1,
+        0x950644b6,
+        0x45d00825,
+        0x4045d000,
+        0x98000e98,
+        0x21f5010f,
+        0x2fbb0147,
+        0x003fbb00,
+        0x98010e98,
+        0x21f5020f,
+        0x0e980147,
+        0x00effd05,
+        0xbb002ebb,
+        0x0e98003e,
+        0x030f9802,
+        0x014721f5,
+        0xfd070e98,
+        0x2ebb00ef,
+        0x003ebb00,
+        0x130040b7,
+        0xd00235b6,
+        0x25b60043,
+        0x0635b608,
+        0xb60120b6,
+        0x24b60130,
+        0x0834b608,
+        0xf5022fb9,
+        0xbb027121,
+        0x07f1003f,
+        0x03f00100,
+        0x0003d002,
+        0x24bd04bd,
+        0xf11f29f0,
+        0xf0300007,
+        0x02d00203,
+/* 0x0433: main */
+        0xf404bd00,
+        0x28f40031,
+        0x24d7f000,
+        0xf43921f4,
+        0xe4b0f401,
+        0x1e18f404,
+        0xf00181fe,
+        0x20bd0627,
+        0xb60412fd,
+        0x1efd01e4,
+        0x0018fe05,
+        0x04f721f5,
+/* 0x0463: main_not_ctx_xfer */
+        0x94d30ef4,
+        0xf5f010ef,
+        0xfe21f501,
+        0xc60ef402,
+/* 0x0470: ih */
+        0x88fe80f9,
+        0xf980f901,
+        0xf9a0f990,
+        0xf9d0f9b0,
+        0xbdf0f9e0,
+        0x800acf04,
+        0xf404abc4,
+        0xb7f11d0b,
+        0xd7f01900,
+        0x40becf24,
+        0xf400bfcf,
+        0xb0b70421,
+        0xe7f00400,
+        0x00bed001,
+/* 0x04a8: ih_no_fifo */
+        0xfc400ad0,
+        0xfce0fcf0,
+        0xfcb0fcd0,
+        0xfc90fca0,
+        0x0088fe80,
+        0x32f480fc,
+/* 0x04c3: hub_barrier_done */
+        0xf001f800,
+        0x0e9801f7,
+        0x04febb04,
+        0x9418e7f1,
+        0xf440e3f0,
+        0x00f88d21,
+/* 0x04d8: ctx_redswitch */
+        0x0614e7f1,
+        0xf006e4b6,
+        0xefd020f7,
+        0x08f7f000,
+/* 0x04e8: ctx_redswitch_delay */
+        0xf401f2b6,
+        0xf7f1fd1b,
+        0xefd00a20,
+/* 0x04f7: ctx_xfer */
+        0xf100f800,
+        0xb60a0417,
+        0x1fd00614,
+        0x0711f400,
+        0x04d821f5,
+/* 0x0508: ctx_xfer_not_load */
+        0x4afc17f1,
+        0xf00213f0,
+        0x12d00c27,
+        0x1521f500,
+        0xfc27f102,
+        0x0223f047,
+        0xf00020d0,
+        0x20b6012c,
+        0x0012d003,
+        0xf001acf0,
+        0xb7f002a5,
+        0x50b3f000,
+        0xb6040c98,
+        0xbcbb0fc4,
+        0x000c9800,
+        0xf0010d98,
+        0x21f500e7,
+        0xacf00166,
+        0x00b7f101,
+        0x50b3f040,
+        0xb6040c98,
+        0xbcbb0fc4,
+        0x010c9800,
+        0x98020d98,
+        0xe7f1060f,
+        0x21f50800,
+        0xacf00166,
+        0x04a5f001,
+        0x3000b7f1,
+        0x9850b3f0,
+        0xc4b6040c,
+        0x00bcbb0f,
+        0x98020c98,
+        0x0f98030d,
+        0x00e7f108,
+        0x6621f502,
+        0x1521f501,
+        0x0601f402,
+/* 0x05a3: ctx_xfer_post */
+        0xf11412f4,
+        0xf04afc17,
+        0x27f00213,
+        0x0012d00d,
+        0x021521f5,
+/* 0x05b4: ctx_xfer_done */
+        0x04c321f5,
+        0x000000f8,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+};
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hub.fuc b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hub.fuc
new file mode 100644
index 000000000000..b82d2ae89917
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hub.fuc
@@ -0,0 +1,724 @@
+/* fuc microcode for nvc0 PGRAPH/HUB
+ *
+ * Copyright 2011 Red Hat Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Ben Skeggs
+ */
+
+#ifdef INCLUDE_DATA
+hub_mmio_list_head:     .b32 #hub_mmio_list_base
+hub_mmio_list_tail:     .b32 #hub_mmio_list_next
+
+gpc_count:              .b32 0
+rop_count:              .b32 0
+cmd_queue:              queue_init
+
+ctx_current:            .b32 0
+
+.align 256
+chan_data:
+chan_mmio_count:        .b32 0
+chan_mmio_address:      .b32 0
+
+.align 256
+xfer_data:              .skip 256
+
+hub_mmio_list_base:
+.b32 0x0417e91c // 0x17e91c, 2
+hub_mmio_list_next:
+#endif
+
+#ifdef INCLUDE_CODE
+// reports an exception to the host
+//
+// In: $r15 error code (see nvc0.fuc)
+//
+error:
+        nv_iowr(NV_PGRAPH_FECS_CC_SCRATCH_VAL(5), 0, $r15)
+        mov $r15 1
+        nv_iowr(NV_PGRAPH_FECS_INTR_UP_SET, 0, $r15)
+        ret
+
+// HUB fuc initialisation, executed by triggering ucode start, will
+// fall through to main loop after completion.
+//
+// Output:
+//   CC_SCRATCH[0]:
+//           31:31: set to signal completion
+//   CC_SCRATCH[1]:
+//            31:0: total PGRAPH context size
+//
+init:
+        clear b32 $r0
+        mov $sp $r0
+        mov $xdbase $r0
+
+        // enable fifo access
+        mov $r1 0x1200
+        mov $r2 2
+        iowr I[$r1 + 0x000] $r2 // FIFO_ENABLE
+
+        // setup i0 handler, and route all interrupts to it
+        mov $r1 #ih
+        mov $iv0 $r1
+        mov $r1 0x400
+        iowr I[$r1 + 0x300] $r0 // INTR_DISPATCH
+
+        // route HUB_CHANNEL_SWITCH to fuc interrupt 8
+        mov $r3 0x404
+        shl b32 $r3 6
+        mov $r2 0x2003          // { HUB_CHANNEL_SWITCH, ZERO } -> intr 8
+        iowr I[$r3 + 0x000] $r2
+
+        // not sure what these are, route them because NVIDIA does, and
+        // the IRQ handler will signal the host if we ever get one.. we
+        // may find out if/why we need to handle these if so..
+        //
+        mov $r2 0x2004
+        iowr I[$r3 + 0x004] $r2 // { 0x04, ZERO } -> intr 9
+        mov $r2 0x200b
+        iowr I[$r3 + 0x008] $r2 // { 0x0b, ZERO } -> intr 10
+        mov $r2 0x200c
+        iowr I[$r3 + 0x01c] $r2 // { 0x0c, ZERO } -> intr 15
+
+        // enable all INTR_UP interrupts
+        mov $r2 0xc24
+        shl b32 $r2 6
+        not b32 $r3 $r0
+        iowr I[$r2] $r3
+
+        // enable fifo, ctxsw, 9, 10, 15 interrupts
+        mov $r2 -0x78fc         // 0x8704
+        sethi $r2 0
+        iowr I[$r1 + 0x000] $r2 // INTR_EN_SET
+
+        // fifo level triggered, rest edge
+        sub b32 $r1 0x100
+        mov $r2 4
+        iowr I[$r1] $r2
+
+        // enable interrupts
+        bset $flags ie0
+
+        // fetch enabled GPC/ROP counts
+        mov $r14 -0x69fc        // 0x409604
+        sethi $r14 0x400000
+        call #nv_rd32
+        extr $r1 $r15 16:20
+        st b32 D[$r0 + #rop_count] $r1
+        and $r15 0x1f
+        st b32 D[$r0 + #gpc_count] $r15
+
+        // set BAR_REQMASK to GPC mask
+        mov $r1 1
+        shl b32 $r1 $r15
+        sub b32 $r1 1
+        mov $r2 0x40c
+        shl b32 $r2 6
+        iowr I[$r2 + 0x000] $r1
+        iowr I[$r2 + 0x100] $r1
+
+        // context size calculation, reserve first 256 bytes for use by fuc
+        mov $r1 256
+
+        // calculate size of mmio context data
+        ld b32 $r14 D[$r0 + #hub_mmio_list_head]
+        ld b32 $r15 D[$r0 + #hub_mmio_list_tail]
+        call #mmctx_size
+
+        // set mmctx base addresses now so we don't have to do it later,
+        // they don't (currently) ever change
+        mov $r3 0x700
+        shl b32 $r3 6
+        shr b32 $r4 $r1 8
+        iowr I[$r3 + 0x000] $r4         // MMCTX_SAVE_SWBASE
+        iowr I[$r3 + 0x100] $r4         // MMCTX_LOAD_SWBASE
+        add b32 $r3 0x1300
+        add b32 $r1 $r15
+        shr b32 $r15 2
+        iowr I[$r3 + 0x000] $r15        // MMCTX_LOAD_COUNT, wtf for?!?
+
+        // strands, base offset needs to be aligned to 256 bytes
+        shr b32 $r1 8
+        add b32 $r1 1
+        shl b32 $r1 8
+        mov b32 $r15 $r1
+        call #strand_ctx_init
+        add b32 $r1 $r15
+
+        // initialise each GPC in sequence by passing in the offset of its
+        // context data in GPCn_CC_SCRATCH[1], and starting its FUC (which
+        // has previously been uploaded by the host) running.
+        //
+        // the GPC fuc init sequence will set GPCn_CC_SCRATCH[0] bit 31
+        // when it has completed, and return the size of its context data
+        // in GPCn_CC_SCRATCH[1]
+        //
+        ld b32 $r3 D[$r0 + #gpc_count]
+        mov $r4 0x2000
+        sethi $r4 0x500000
+        init_gpc:
+                // setup, and start GPC ucode running
+                add b32 $r14 $r4 0x804
+                mov b32 $r15 $r1
+                call #nv_wr32                   // CC_SCRATCH[1] = ctx offset
+                add b32 $r14 $r4 0x10c
+                clear b32 $r15
+                call #nv_wr32
+                add b32 $r14 $r4 0x104
+                call #nv_wr32                   // ENTRY
+                add b32 $r14 $r4 0x100
+                mov $r15 2                      // CTRL_START_TRIGGER
+                call #nv_wr32                   // CTRL
+
+                // wait for it to complete, and adjust context size
+                add b32 $r14 $r4 0x800
+                init_gpc_wait:
+                        call #nv_rd32
+                        xbit $r15 $r15 31
+                        bra e #init_gpc_wait
+                add b32 $r14 $r4 0x804
+                call #nv_rd32
+                add b32 $r1 $r15
+
+                // next!
+                add b32 $r4 0x8000
+                sub b32 $r3 1
+                bra ne #init_gpc
+
+        // save context size, and tell host we're ready
+        nv_iowr(NV_PGRAPH_FECS_CC_SCRATCH_VAL(1), 0, $r1)
+        clear b32 $r1
+        bset $r1 31
+        nv_iowr(NV_PGRAPH_FECS_CC_SCRATCH_SET(0), 0, $r1)
+
+// Main program loop, very simple, sleeps until woken up by the interrupt
+// handler, pulls a command from the queue and executes its handler
+//
+main:
+        // sleep until we have something to do
+        bset $flags $p0
+        sleep $p0
+        mov $r13 #cmd_queue
+        call #queue_get
+        bra $p1 #main
+
+        // context switch, requested by GPU?
+        cmpu b32 $r14 0x4001
+        bra ne #main_not_ctx_switch
+                trace_set(T_AUTO)
+                mov $r1 0xb00
+                shl b32 $r1 6
+                iord $r2 I[$r1 + 0x100]         // CHAN_NEXT
+                iord $r1 I[$r1 + 0x000]         // CHAN_CUR
+
+                xbit $r3 $r1 31
+                bra e #chsw_no_prev
+                        xbit $r3 $r2 31
+                        bra e #chsw_prev_no_next
+                                push $r2
+                                mov b32 $r2 $r1
+                                trace_set(T_SAVE)
+                                bclr $flags $p1
+                                bset $flags $p2
+                                call #ctx_xfer
+                                trace_clr(T_SAVE);
+                                pop $r2
+                                trace_set(T_LOAD);
+                                bset $flags $p1
+                                call #ctx_xfer
+                                trace_clr(T_LOAD);
+                                bra #chsw_done
+                        chsw_prev_no_next:
+                                push $r2
+                                mov b32 $r2 $r1
+                                bclr $flags $p1
+                                bclr $flags $p2
+                                call #ctx_xfer
+                                pop $r2
+                                mov $r1 0xb00
+                                shl b32 $r1 6
+                                iowr I[$r1] $r2
+                                bra #chsw_done
+                chsw_no_prev:
+                        xbit $r3 $r2 31
+                        bra e #chsw_done
+                                bset $flags $p1
+                                bclr $flags $p2
+                                call #ctx_xfer
+
+                // ack the context switch request
+                chsw_done:
+                mov $r1 0xb0c
+                shl b32 $r1 6
+                mov $r2 1
+                iowr I[$r1 + 0x000] $r2         // 0x409b0c
+                trace_clr(T_AUTO)
+                bra #main
+
+        // request to set current channel? (*not* a context switch)
+        main_not_ctx_switch:
+        cmpu b32 $r14 0x0001
+        bra ne #main_not_ctx_chan
+                mov b32 $r2 $r15
+                call #ctx_chan
+                bra #main_done
+
+        // request to store current channel context?
+        main_not_ctx_chan:
+        cmpu b32 $r14 0x0002
+        bra ne #main_not_ctx_save
+                trace_set(T_SAVE)
+                bclr $flags $p1
+                bclr $flags $p2
+                call #ctx_xfer
+                trace_clr(T_SAVE)
+                bra #main_done
+
+        main_not_ctx_save:
+                shl b32 $r15 $r14 16
+                or $r15 E_BAD_COMMAND
+                call #error
+                bra #main
+
+        main_done:
+        clear b32 $r2
+        bset $r2 31
+        nv_iowr(NV_PGRAPH_FECS_CC_SCRATCH_SET(0), 0, $r2)
+        bra #main
+
+// interrupt handler
+ih:
+        push $r8
+        mov $r8 $flags
+        push $r8
+        push $r9
+        push $r10
+        push $r11
+        push $r13
+        push $r14
+        push $r15
+        clear b32 $r0
+
+        // incoming fifo command?
+        iord $r10 I[$r0 + 0x200]        // INTR
+        and $r11 $r10 0x00000004
+        bra e #ih_no_fifo
+                // queue incoming fifo command for later processing
+                mov $r11 0x1900
+                mov $r13 #cmd_queue
+                iord $r14 I[$r11 + 0x100]       // FIFO_CMD
+                iord $r15 I[$r11 + 0x000]       // FIFO_DATA
+                call #queue_put
+                add b32 $r11 0x400
+                mov $r14 1
+                iowr I[$r11 + 0x000] $r14       // FIFO_ACK
+
+        // context switch request?
+        ih_no_fifo:
+        and $r11 $r10 0x00000100
+        bra e #ih_no_ctxsw
+                // enqueue a context switch for later processing
+                mov $r13 #cmd_queue
+                mov $r14 0x4001
+                call #queue_put
+
+        // anything we didn't handle, bring it to the host's attention
+        ih_no_ctxsw:
+        mov $r11 0x104
+        not b32 $r11
+        and $r11 $r10 $r11
+        bra e #ih_no_other
+                mov $r10 0xc1c
+                shl b32 $r10 6
+                iowr I[$r10] $r11       // INTR_UP_SET
+
+        // ack, and wake up main()
+        ih_no_other:
+        iowr I[$r0 + 0x100] $r10        // INTR_ACK
+
+        pop $r15
+        pop $r14
+        pop $r13
+        pop $r11
+        pop $r10
+        pop $r9
+        pop $r8
+        mov $flags $r8
+        pop $r8
+        bclr $flags $p0
+        iret
+
+#if CHIPSET < GK100
+// Not real sure, but, MEM_CMD 7 will hang forever if this isn't done
+ctx_4160s:
+        mov $r14 0x4160
+        sethi $r14 0x400000
+        mov $r15 1
+        call #nv_wr32
+        ctx_4160s_wait:
+                call #nv_rd32
+                xbit $r15 $r15 4
+                bra e #ctx_4160s_wait
+        ret
+
+// Without clearing again at end of xfer, some things cause PGRAPH
+// to hang with STATUS=0x00000007 until it's cleared.. fbcon can
+// still function with it set however...
+ctx_4160c:
+        mov $r14 0x4160
+        sethi $r14 0x400000
+        clear b32 $r15
+        call #nv_wr32
+        ret
+#endif
+
+// Again, not real sure
+//
+// In: $r15 value to set 0x404170 to
+//
+ctx_4170s:
+        mov $r14 0x4170
+        sethi $r14 0x400000
+        or $r15 0x10
+        call #nv_wr32
+        ret
+
+// Waits for a ctx_4170s() call to complete
+//
+ctx_4170w:
+        mov $r14 0x4170
+        sethi $r14 0x400000
+        call #nv_rd32
+        and $r15 0x10
+        bra ne #ctx_4170w
+        ret
+
+// Disables various things, waits a bit, and re-enables them..
+//
+// Not sure how exactly this helps, perhaps "ENABLE" is not such a
+// good description for the bits we turn off?  Anyways, without this,
+// funny things happen.
+//
+ctx_redswitch:
+        mov $r14 0x614
+        shl b32 $r14 6
+        mov $r15 0x270
+        iowr I[$r14] $r15       // HUB_RED_SWITCH = ENABLE_GPC, POWER_ALL
+        mov $r15 8
+        ctx_redswitch_delay:
+                sub b32 $r15 1
+                bra ne #ctx_redswitch_delay
+        mov $r15 0x770
+        iowr I[$r14] $r15       // HUB_RED_SWITCH = ENABLE_ALL, POWER_ALL
+        ret
+
+// Not a clue what this is for, except that unless the value is 0x10, the
+// strand context is saved (and presumably restored) incorrectly..
+//
+// In: $r15 value to set to (0x00/0x10 are used)
+//
+ctx_86c:
+        mov $r14 0x86c
+        shl b32 $r14 6
+        iowr I[$r14] $r15       // HUB(0x86c) = val
+        mov $r14 -0x75ec
+        sethi $r14 0x400000
+        call #nv_wr32           // ROP(0xa14) = val
+        mov $r14 -0x5794
+        sethi $r14 0x410000
+        call #nv_wr32           // GPC(0x86c) = val
+        ret
+
+// ctx_load - load's a channel's ctxctl data, and selects its vm
+//
+// In: $r2 channel address
+//
+ctx_load:
+        trace_set(T_CHAN)
+
+        // switch to channel, somewhat magic in parts..
+        mov $r10 12             // DONE_UNK12
+        call #wait_donez
+        mov $r1 0xa24
+        shl b32 $r1 6
+        iowr I[$r1 + 0x000] $r0 // 0x409a24
+        mov $r3 0xb00
+        shl b32 $r3 6
+        iowr I[$r3 + 0x100] $r2 // CHAN_NEXT
+        mov $r1 0xa0c
+        shl b32 $r1 6
+        mov $r4 7
+        iowr I[$r1 + 0x000] $r2 // MEM_CHAN
+        iowr I[$r1 + 0x100] $r4 // MEM_CMD
+        ctx_chan_wait_0:
+                iord $r4 I[$r1 + 0x100]
+                and $r4 0x1f
+                bra ne #ctx_chan_wait_0
+        iowr I[$r3 + 0x000] $r2 // CHAN_CUR
+
+        // load channel header, fetch PGRAPH context pointer
+        mov $xtargets $r0
+        bclr $r2 31
+        shl b32 $r2 4
+        add b32 $r2 2
+
+        trace_set(T_LCHAN)
+        mov $r1 0xa04
+        shl b32 $r1 6
+        iowr I[$r1 + 0x000] $r2         // MEM_BASE
+        mov $r1 0xa20
+        shl b32 $r1 6
+        mov $r2 0x0002
+        sethi $r2 0x80000000
+        iowr I[$r1 + 0x000] $r2         // MEM_TARGET = vram
+        mov $r1 0x10                    // chan + 0x0210
+        mov $r2 #xfer_data
+        sethi $r2 0x00020000            // 16 bytes
+        xdld $r1 $r2
+        xdwait
+        trace_clr(T_LCHAN)
+
+        // update current context
+        ld b32 $r1 D[$r0 + #xfer_data + 4]
+        shl b32 $r1 24
+        ld b32 $r2 D[$r0 + #xfer_data + 0]
+        shr b32 $r2 8
+        or $r1 $r2
+        st b32 D[$r0 + #ctx_current] $r1
+
+        // set transfer base to start of context, and fetch context header
+        trace_set(T_LCTXH)
+        mov $r2 0xa04
+        shl b32 $r2 6
+        iowr I[$r2 + 0x000] $r1         // MEM_BASE
+        mov $r2 1
+        mov $r1 0xa20
+        shl b32 $r1 6
+        iowr I[$r1 + 0x000] $r2         // MEM_TARGET = vm
+        mov $r1 #chan_data
+        sethi $r1 0x00060000            // 256 bytes
+        xdld $r0 $r1
+        xdwait
+        trace_clr(T_LCTXH)
+
+        trace_clr(T_CHAN)
+        ret
+
+// ctx_chan - handler for HUB_SET_CHAN command, will set a channel as
+//            the active channel for ctxctl, but not actually transfer
+//            any context data.  intended for use only during initial
+//            context construction.
+//
+// In: $r2 channel address
+//
+ctx_chan:
+#if CHIPSET < GK100
+        call #ctx_4160s
+#endif
+        call #ctx_load
+        mov $r10 12                     // DONE_UNK12
+        call #wait_donez
+        mov $r1 0xa10
+        shl b32 $r1 6
+        mov $r2 5
+        iowr I[$r1 + 0x000] $r2         // MEM_CMD = 5 (???)
+        ctx_chan_wait:
+                iord $r2 I[$r1 + 0x000]
+                or $r2 $r2
+                bra ne #ctx_chan_wait
+#if CHIPSET < GK100
+        call #ctx_4160c
+#endif
+        ret
+
+// Execute per-context state overrides list
+//
+// Only executed on the first load of a channel.  Might want to look into
+// removing this and having the host directly modify the channel's context
+// to change this state...  The nouveau DRM already builds this list as
+// it's definitely needed for NVIDIA's, so we may as well use it for now
+//
+// Input: $r1 mmio list length
+//
+ctx_mmio_exec:
+        // set transfer base to be the mmio list
+        ld b32 $r3 D[$r0 + #chan_mmio_address]
+        mov $r2 0xa04
+        shl b32 $r2 6
+        iowr I[$r2 + 0x000] $r3         // MEM_BASE
+
+        clear b32 $r3
+        ctx_mmio_loop:
+                // fetch next 256 bytes of mmio list if necessary
+                and $r4 $r3 0xff
+                bra ne #ctx_mmio_pull
+                        mov $r5 #xfer_data
+                        sethi $r5 0x00060000    // 256 bytes
+                        xdld $r3 $r5
+                        xdwait
+
+                // execute a single list entry
+                ctx_mmio_pull:
+                ld b32 $r14 D[$r4 + #xfer_data + 0x00]
+                ld b32 $r15 D[$r4 + #xfer_data + 0x04]
+                call #nv_wr32
+
+                // next!
+                add b32 $r3 8
+                sub b32 $r1 1
+                bra ne #ctx_mmio_loop
+
+        // set transfer base back to the current context
+        ctx_mmio_done:
+        ld b32 $r3 D[$r0 + #ctx_current]
+        iowr I[$r2 + 0x000] $r3         // MEM_BASE
+
+        // disable the mmio list now, we don't need/want to execute it again
+        st b32 D[$r0 + #chan_mmio_count] $r0
+        mov $r1 #chan_data
+        sethi $r1 0x00060000            // 256 bytes
+        xdst $r0 $r1
+        xdwait
+        ret
+
+// Transfer HUB context data between GPU and storage area
+//
+// In: $r2 channel address
+//     $p1 clear on save, set on load
+//     $p2 set if opposite direction done/will be done, so:
+//              on save it means: "a load will follow this save"
+//              on load it means: "a save preceeded this load"
+//
+ctx_xfer:
+        // according to mwk, some kind of wait for idle
+        mov $r15 0xc00
+        shl b32 $r15 6
+        mov $r14 4
+        iowr I[$r15 + 0x200] $r14
+        ctx_xfer_idle:
+                iord $r14 I[$r15 + 0x000]
+                and $r14 0x2000
+                bra ne #ctx_xfer_idle
+
+        bra not $p1 #ctx_xfer_pre
+        bra $p2 #ctx_xfer_pre_load
+        ctx_xfer_pre:
+                mov $r15 0x10
+                call #ctx_86c
+#if CHIPSET < GK100
+                call #ctx_4160s
+#endif
+                bra not $p1 #ctx_xfer_exec
+
+        ctx_xfer_pre_load:
+                mov $r15 2
+                call #ctx_4170s
+                call #ctx_4170w
+                call #ctx_redswitch
+                clear b32 $r15
+                call #ctx_4170s
+                call #ctx_load
+
+        // fetch context pointer, and initiate xfer on all GPCs
+        ctx_xfer_exec:
+        ld b32 $r1 D[$r0 + #ctx_current]
+        mov $r2 0x414
+        shl b32 $r2 6
+        iowr I[$r2 + 0x000] $r0 // BAR_STATUS = reset
+        mov $r14 -0x5b00
+        sethi $r14 0x410000
+        mov b32 $r15 $r1
+        call #nv_wr32           // GPC_BCAST_WRCMD_DATA = ctx pointer
+        add b32 $r14 4
+        xbit $r15 $flags $p1
+        xbit $r2 $flags $p2
+        shl b32 $r2 1
+        or $r15 $r2
+        call #nv_wr32           // GPC_BCAST_WRCMD_CMD = GPC_XFER(type)
+
+        // strands
+        mov $r1 0x4afc
+        sethi $r1 0x20000
+        mov $r2 0xc
+        iowr I[$r1] $r2         // STRAND_CMD(0x3f) = 0x0c
+        call #strand_wait
+        mov $r2 0x47fc
+        sethi $r2 0x20000
+        iowr I[$r2] $r0         // STRAND_FIRST_GENE(0x3f) = 0x00
+        xbit $r2 $flags $p1
+        add b32 $r2 3
+        iowr I[$r1] $r2         // STRAND_CMD(0x3f) = 0x03/0x04 (SAVE/LOAD)
+
+        // mmio context
+        xbit $r10 $flags $p1    // direction
+        or $r10 6               // first, last
+        mov $r11 0              // base = 0
+        ld b32 $r12 D[$r0 + #hub_mmio_list_head]
+        ld b32 $r13 D[$r0 + #hub_mmio_list_tail]
+        mov $r14 0              // not multi
+        call #mmctx_xfer
+
+        // wait for GPCs to all complete
+        mov $r10 8              // DONE_BAR
+        call #wait_doneo
+
+        // wait for strand xfer to complete
+        call #strand_wait
+
+        // post-op
+        bra $p1 #ctx_xfer_post
+                mov $r10 12             // DONE_UNK12
+                call #wait_donez
+                mov $r1 0xa10
+                shl b32 $r1 6
+                mov $r2 5
+                iowr I[$r1] $r2         // MEM_CMD
+                ctx_xfer_post_save_wait:
+                        iord $r2 I[$r1]
+                        or $r2 $r2
+                        bra ne #ctx_xfer_post_save_wait
+
+        bra $p2 #ctx_xfer_done
+        ctx_xfer_post:
+                mov $r15 2
+                call #ctx_4170s
+                clear b32 $r15
+                call #ctx_86c
+                call #strand_post
+                call #ctx_4170w
+                clear b32 $r15
+                call #ctx_4170s
+
+                bra not $p1 #ctx_xfer_no_post_mmio
+                ld b32 $r1 D[$r0 + #chan_mmio_count]
+                or $r1 $r1
+                bra e #ctx_xfer_no_post_mmio
+                        call #ctx_mmio_exec
+
+                ctx_xfer_no_post_mmio:
+#if CHIPSET < GK100
+                call #ctx_4160c
+#endif
+
+        ctx_xfer_done:
+        ret
+#endif
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvc0.fuc b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvc0.fuc
index 7fbdebb2bafb..3ff52badf932 100644
--- a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvc0.fuc
+++ b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvc0.fuc
@@ -1,6 +1,5 @@
-/* fuc microcode for nvc0 PGRAPH/HUB
- *
- * Copyright 2011 Red Hat Inc.
+/*
+ * Copyright 2013 Red Hat Inc.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -20,850 +19,22 @@
  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  * OTHER DEALINGS IN THE SOFTWARE.
  *
- * Authors: Ben Skeggs
+ * Authors: Ben Skeggs <bskeggs@redhat.com>
  */
 
-/* To build:
- *    m4 hubnvc0.fuc | envyas -a -w -m fuc -V fuc3 -o hubnvc0.fuc.h
- */
+#define CHIPSET GF100
+#include "macros.fuc"
 
 .section #nvc0_grhub_data
-include(`nvc0.fuc')
-gpc_count:              .b32 0
-rop_count:              .b32 0
-cmd_queue:              queue_init
-hub_mmio_list_head:     .b32 0
-hub_mmio_list_tail:     .b32 0
-
-ctx_current:            .b32 0
-
-chipsets:
-.b8  0xc0 0 0 0
-.b16 #nvc0_hub_mmio_head
-.b16 #nvc0_hub_mmio_tail
-.b8  0xc1 0 0 0
-.b16 #nvc0_hub_mmio_head
-.b16 #nvc1_hub_mmio_tail
-.b8  0xc3 0 0 0
-.b16 #nvc0_hub_mmio_head
-.b16 #nvc0_hub_mmio_tail
-.b8  0xc4 0 0 0
-.b16 #nvc0_hub_mmio_head
-.b16 #nvc0_hub_mmio_tail
-.b8  0xc8 0 0 0
-.b16 #nvc0_hub_mmio_head
-.b16 #nvc0_hub_mmio_tail
-.b8  0xce 0 0 0
-.b16 #nvc0_hub_mmio_head
-.b16 #nvc0_hub_mmio_tail
-.b8  0xcf 0 0 0
-.b16 #nvc0_hub_mmio_head
-.b16 #nvc0_hub_mmio_tail
-.b8  0xd9 0 0 0
-.b16 #nvd9_hub_mmio_head
-.b16 #nvd9_hub_mmio_tail
-.b8  0xd7 0 0 0
-.b16 #nvd9_hub_mmio_head
-.b16 #nvd9_hub_mmio_tail
-.b8  0 0 0 0
-
-nvc0_hub_mmio_head:
-mmctx_data(0x17e91c, 2)
-mmctx_data(0x400204, 2)
-mmctx_data(0x404004, 11)
-mmctx_data(0x404044, 1)
-mmctx_data(0x404094, 14)
-mmctx_data(0x4040d0, 7)
-mmctx_data(0x4040f8, 1)
-mmctx_data(0x404130, 3)
-mmctx_data(0x404150, 3)
-mmctx_data(0x404164, 2)
-mmctx_data(0x404174, 3)
-mmctx_data(0x404200, 8)
-mmctx_data(0x404404, 14)
-mmctx_data(0x404460, 4)
-mmctx_data(0x404480, 1)
-mmctx_data(0x404498, 1)
-mmctx_data(0x404604, 4)
-mmctx_data(0x404618, 32)
-mmctx_data(0x404698, 21)
-mmctx_data(0x4046f0, 2)
-mmctx_data(0x404700, 22)
-mmctx_data(0x405800, 1)
-mmctx_data(0x405830, 3)
-mmctx_data(0x405854, 1)
-mmctx_data(0x405870, 4)
-mmctx_data(0x405a00, 2)
-mmctx_data(0x405a18, 1)
-mmctx_data(0x406020, 1)
-mmctx_data(0x406028, 4)
-mmctx_data(0x4064a8, 2)
-mmctx_data(0x4064b4, 2)
-mmctx_data(0x407804, 1)
-mmctx_data(0x40780c, 6)
-mmctx_data(0x4078bc, 1)
-mmctx_data(0x408000, 7)
-mmctx_data(0x408064, 1)
-mmctx_data(0x408800, 3)
-mmctx_data(0x408900, 4)
-mmctx_data(0x408980, 1)
-nvc0_hub_mmio_tail:
-mmctx_data(0x4064c0, 2)
-nvc1_hub_mmio_tail:
-
-nvd9_hub_mmio_head:
-mmctx_data(0x17e91c, 2)
-mmctx_data(0x400204, 2)
-mmctx_data(0x404004, 10)
-mmctx_data(0x404044, 1)
-mmctx_data(0x404094, 14)
-mmctx_data(0x4040d0, 7)
-mmctx_data(0x4040f8, 1)
-mmctx_data(0x404130, 3)
-mmctx_data(0x404150, 3)
-mmctx_data(0x404164, 2)
-mmctx_data(0x404178, 2)
-mmctx_data(0x404200, 8)
-mmctx_data(0x404404, 14)
-mmctx_data(0x404460, 4)
-mmctx_data(0x404480, 1)
-mmctx_data(0x404498, 1)
-mmctx_data(0x404604, 4)
-mmctx_data(0x404618, 32)
-mmctx_data(0x404698, 21)
-mmctx_data(0x4046f0, 2)
-mmctx_data(0x404700, 22)
-mmctx_data(0x405800, 1)
-mmctx_data(0x405830, 3)
-mmctx_data(0x405854, 1)
-mmctx_data(0x405870, 4)
-mmctx_data(0x405a00, 2)
-mmctx_data(0x405a18, 1)
-mmctx_data(0x406020, 1)
-mmctx_data(0x406028, 4)
-mmctx_data(0x4064a8, 2)
-mmctx_data(0x4064b4, 5)
-mmctx_data(0x407804, 1)
-mmctx_data(0x40780c, 6)
-mmctx_data(0x4078bc, 1)
-mmctx_data(0x408000, 7)
-mmctx_data(0x408064, 1)
-mmctx_data(0x408800, 3)
-mmctx_data(0x408900, 4)
-mmctx_data(0x408980, 1)
-nvd9_hub_mmio_tail:
-
-.align 256
-chan_data:
-chan_mmio_count:        .b32 0
-chan_mmio_address:      .b32 0
-
-.align 256
-xfer_data:              .b32 0
+#define INCLUDE_DATA
+#include "com.fuc"
+#include "hub.fuc"
+#undef INCLUDE_DATA
 
 .section #nvc0_grhub_code
+#define INCLUDE_CODE
 bra #init
-define(`include_code')
-include(`nvc0.fuc')
-
-// reports an exception to the host
-//
-// In: $r15 error code (see nvc0.fuc)
-//
-error:
-        push $r14
-        mov $r14 0x814
-        shl b32 $r14 6
-        iowr I[$r14 + 0x000] $r15       // CC_SCRATCH[5] = error code
-        mov $r14 0xc1c
-        shl b32 $r14 6
-        mov $r15 1
-        iowr I[$r14 + 0x000] $r15       // INTR_UP_SET
-        pop $r14
-        ret
-
-// HUB fuc initialisation, executed by triggering ucode start, will
-// fall through to main loop after completion.
-//
-// Input:
-//   CC_SCRATCH[0]: chipset (PMC_BOOT_0 read returns 0x0bad0bad... sigh)
-//
-// Output:
-//   CC_SCRATCH[0]:
-//           31:31: set to signal completion
-//   CC_SCRATCH[1]:
-//            31:0: total PGRAPH context size
-//
-init:
-        clear b32 $r0
-        mov $sp $r0
-        mov $xdbase $r0
-
-        // enable fifo access
-        mov $r1 0x1200
-        mov $r2 2
-        iowr I[$r1 + 0x000] $r2 // FIFO_ENABLE
-
-        // setup i0 handler, and route all interrupts to it
-        mov $r1 #ih
-        mov $iv0 $r1
-        mov $r1 0x400
-        iowr I[$r1 + 0x300] $r0 // INTR_DISPATCH
-
-        // route HUB_CHANNEL_SWITCH to fuc interrupt 8
-        mov $r3 0x404
-        shl b32 $r3 6
-        mov $r2 0x2003          // { HUB_CHANNEL_SWITCH, ZERO } -> intr 8
-        iowr I[$r3 + 0x000] $r2
-
-        // not sure what these are, route them because NVIDIA does, and
-        // the IRQ handler will signal the host if we ever get one.. we
-        // may find out if/why we need to handle these if so..
-        //
-        mov $r2 0x2004
-        iowr I[$r3 + 0x004] $r2 // { 0x04, ZERO } -> intr 9
-        mov $r2 0x200b
-        iowr I[$r3 + 0x008] $r2 // { 0x0b, ZERO } -> intr 10
-        mov $r2 0x200c
-        iowr I[$r3 + 0x01c] $r2 // { 0x0c, ZERO } -> intr 15
-
-        // enable all INTR_UP interrupts
-        mov $r2 0xc24
-        shl b32 $r2 6
-        not b32 $r3 $r0
-        iowr I[$r2] $r3
-
-        // enable fifo, ctxsw, 9, 10, 15 interrupts
-        mov $r2 -0x78fc         // 0x8704
-        sethi $r2 0
-        iowr I[$r1 + 0x000] $r2 // INTR_EN_SET
-
-        // fifo level triggered, rest edge
-        sub b32 $r1 0x100
-        mov $r2 4
-        iowr I[$r1] $r2
-
-        // enable interrupts
-        bset $flags ie0
-
-        // fetch enabled GPC/ROP counts
-        mov $r14 -0x69fc        // 0x409604
-        sethi $r14 0x400000
-        call #nv_rd32
-        extr $r1 $r15 16:20
-        st b32 D[$r0 + #rop_count] $r1
-        and $r15 0x1f
-        st b32 D[$r0 + #gpc_count] $r15
-
-        // set BAR_REQMASK to GPC mask
-        mov $r1 1
-        shl b32 $r1 $r15
-        sub b32 $r1 1
-        mov $r2 0x40c
-        shl b32 $r2 6
-        iowr I[$r2 + 0x000] $r1
-        iowr I[$r2 + 0x100] $r1
-
-        // find context data for this chipset
-        mov $r2 0x800
-        shl b32 $r2 6
-        iord $r2 I[$r2 + 0x000]         // CC_SCRATCH[0]
-        mov $r15 #chipsets - 8
-        init_find_chipset:
-                add b32 $r15 8
-                ld b32 $r3 D[$r15 + 0x00]
-                cmpu b32 $r3 $r2
-                bra e #init_context
-                cmpu b32 $r3 0
-                bra ne #init_find_chipset
-                // unknown chipset
-                ret
-
-        // context size calculation, reserve first 256 bytes for use by fuc
-        init_context:
-        mov $r1 256
-
-        // calculate size of mmio context data
-        ld b16 $r14 D[$r15 + 4]
-        ld b16 $r15 D[$r15 + 6]
-        sethi $r14 0
-        st b32 D[$r0 + #hub_mmio_list_head] $r14
-        st b32 D[$r0 + #hub_mmio_list_tail] $r15
-        call #mmctx_size
-
-        // set mmctx base addresses now so we don't have to do it later,
-        // they don't (currently) ever change
-        mov $r3 0x700
-        shl b32 $r3 6
-        shr b32 $r4 $r1 8
-        iowr I[$r3 + 0x000] $r4         // MMCTX_SAVE_SWBASE
-        iowr I[$r3 + 0x100] $r4         // MMCTX_LOAD_SWBASE
-        add b32 $r3 0x1300
-        add b32 $r1 $r15
-        shr b32 $r15 2
-        iowr I[$r3 + 0x000] $r15        // MMCTX_LOAD_COUNT, wtf for?!?
-
-        // strands, base offset needs to be aligned to 256 bytes
-        shr b32 $r1 8
-        add b32 $r1 1
-        shl b32 $r1 8
-        mov b32 $r15 $r1
-        call #strand_ctx_init
-        add b32 $r1 $r15
-
-        // initialise each GPC in sequence by passing in the offset of its
-        // context data in GPCn_CC_SCRATCH[1], and starting its FUC (which
-        // has previously been uploaded by the host) running.
-        //
-        // the GPC fuc init sequence will set GPCn_CC_SCRATCH[0] bit 31
-        // when it has completed, and return the size of its context data
-        // in GPCn_CC_SCRATCH[1]
-        //
-        ld b32 $r3 D[$r0 + #gpc_count]
-        mov $r4 0x2000
-        sethi $r4 0x500000
-        init_gpc:
-                // setup, and start GPC ucode running
-                add b32 $r14 $r4 0x804
-                mov b32 $r15 $r1
-                call #nv_wr32                   // CC_SCRATCH[1] = ctx offset
-                add b32 $r14 $r4 0x800
-                mov b32 $r15 $r2
-                call #nv_wr32                   // CC_SCRATCH[0] = chipset
-                add b32 $r14 $r4 0x10c
-                clear b32 $r15
-                call #nv_wr32
-                add b32 $r14 $r4 0x104
-                call #nv_wr32                   // ENTRY
-                add b32 $r14 $r4 0x100
-                mov $r15 2                      // CTRL_START_TRIGGER
-                call #nv_wr32                   // CTRL
-
-                // wait for it to complete, and adjust context size
-                add b32 $r14 $r4 0x800
-                init_gpc_wait:
-                        call #nv_rd32
-                        xbit $r15 $r15 31
-                        bra e #init_gpc_wait
-                add b32 $r14 $r4 0x804
-                call #nv_rd32
-                add b32 $r1 $r15
-
-                // next!
-                add b32 $r4 0x8000
-                sub b32 $r3 1
-                bra ne #init_gpc
-
-        // save context size, and tell host we're ready
-        mov $r2 0x800
-        shl b32 $r2 6
-        iowr I[$r2 + 0x100] $r1         // CC_SCRATCH[1]  = context size
-        add b32 $r2 0x800
-        clear b32 $r1
-        bset $r1 31
-        iowr I[$r2 + 0x000] $r1         // CC_SCRATCH[0] |= 0x80000000
-
-// Main program loop, very simple, sleeps until woken up by the interrupt
-// handler, pulls a command from the queue and executes its handler
-//
-main:
-        // sleep until we have something to do
-        bset $flags $p0
-        sleep $p0
-        mov $r13 #cmd_queue
-        call #queue_get
-        bra $p1 #main
-
-        // context switch, requested by GPU?
-        cmpu b32 $r14 0x4001
-        bra ne #main_not_ctx_switch
-                trace_set(T_AUTO)
-                mov $r1 0xb00
-                shl b32 $r1 6
-                iord $r2 I[$r1 + 0x100]         // CHAN_NEXT
-                iord $r1 I[$r1 + 0x000]         // CHAN_CUR
-
-                xbit $r3 $r1 31
-                bra e #chsw_no_prev
-                        xbit $r3 $r2 31
-                        bra e #chsw_prev_no_next
-                                push $r2
-                                mov b32 $r2 $r1
-                                trace_set(T_SAVE)
-                                bclr $flags $p1
-                                bset $flags $p2
-                                call #ctx_xfer
-                                trace_clr(T_SAVE);
-                                pop $r2
-                                trace_set(T_LOAD);
-                                bset $flags $p1
-                                call #ctx_xfer
-                                trace_clr(T_LOAD);
-                                bra #chsw_done
-                        chsw_prev_no_next:
-                                push $r2
-                                mov b32 $r2 $r1
-                                bclr $flags $p1
-                                bclr $flags $p2
-                                call #ctx_xfer
-                                pop $r2
-                                mov $r1 0xb00
-                                shl b32 $r1 6
-                                iowr I[$r1] $r2
-                                bra #chsw_done
-                chsw_no_prev:
-                        xbit $r3 $r2 31
-                        bra e #chsw_done
-                                bset $flags $p1
-                                bclr $flags $p2
-                                call #ctx_xfer
-
-                // ack the context switch request
-                chsw_done:
-                mov $r1 0xb0c
-                shl b32 $r1 6
-                mov $r2 1
-                iowr I[$r1 + 0x000] $r2         // 0x409b0c
-                trace_clr(T_AUTO)
-                bra #main
-
-        // request to set current channel? (*not* a context switch)
-        main_not_ctx_switch:
-        cmpu b32 $r14 0x0001
-        bra ne #main_not_ctx_chan
-                mov b32 $r2 $r15
-                call #ctx_chan
-                bra #main_done
-
-        // request to store current channel context?
-        main_not_ctx_chan:
-        cmpu b32 $r14 0x0002
-        bra ne #main_not_ctx_save
-                trace_set(T_SAVE)
-                bclr $flags $p1
-                bclr $flags $p2
-                call #ctx_xfer
-                trace_clr(T_SAVE)
-                bra #main_done
-
-        main_not_ctx_save:
-                shl b32 $r15 $r14 16
-                or $r15 E_BAD_COMMAND
-                call #error
-                bra #main
-
-        main_done:
-        mov $r1 0x820
-        shl b32 $r1 6
-        clear b32 $r2
-        bset $r2 31
-        iowr I[$r1 + 0x000] $r2         // CC_SCRATCH[0] |= 0x80000000
-        bra #main
-
-// interrupt handler
-ih:
-        push $r8
-        mov $r8 $flags
-        push $r8
-        push $r9
-        push $r10
-        push $r11
-        push $r13
-        push $r14
-        push $r15
-
-        // incoming fifo command?
-        iord $r10 I[$r0 + 0x200]        // INTR
-        and $r11 $r10 0x00000004
-        bra e #ih_no_fifo
-                // queue incoming fifo command for later processing
-                mov $r11 0x1900
-                mov $r13 #cmd_queue
-                iord $r14 I[$r11 + 0x100]       // FIFO_CMD
-                iord $r15 I[$r11 + 0x000]       // FIFO_DATA
-                call #queue_put
-                add b32 $r11 0x400
-                mov $r14 1
-                iowr I[$r11 + 0x000] $r14       // FIFO_ACK
-
-        // context switch request?
-        ih_no_fifo:
-        and $r11 $r10 0x00000100
-        bra e #ih_no_ctxsw
-                // enqueue a context switch for later processing
-                mov $r13 #cmd_queue
-                mov $r14 0x4001
-                call #queue_put
-
-        // anything we didn't handle, bring it to the host's attention
-        ih_no_ctxsw:
-        mov $r11 0x104
-        not b32 $r11
-        and $r11 $r10 $r11
-        bra e #ih_no_other
-                mov $r10 0xc1c
-                shl b32 $r10 6
-                iowr I[$r10] $r11       // INTR_UP_SET
-
-        // ack, and wake up main()
-        ih_no_other:
-        iowr I[$r0 + 0x100] $r10        // INTR_ACK
-
-        pop $r15
-        pop $r14
-        pop $r13
-        pop $r11
-        pop $r10
-        pop $r9
-        pop $r8
-        mov $flags $r8
-        pop $r8
-        bclr $flags $p0
-        iret
-
-// Not real sure, but, MEM_CMD 7 will hang forever if this isn't done
-ctx_4160s:
-        mov $r14 0x4160
-        sethi $r14 0x400000
-        mov $r15 1
-        call #nv_wr32
-        ctx_4160s_wait:
-                call #nv_rd32
-                xbit $r15 $r15 4
-                bra e #ctx_4160s_wait
-        ret
-
-// Without clearing again at end of xfer, some things cause PGRAPH
-// to hang with STATUS=0x00000007 until it's cleared.. fbcon can
-// still function with it set however...
-ctx_4160c:
-        mov $r14 0x4160
-        sethi $r14 0x400000
-        clear b32 $r15
-        call #nv_wr32
-        ret
-
-// Again, not real sure
-//
-// In: $r15 value to set 0x404170 to
-//
-ctx_4170s:
-        mov $r14 0x4170
-        sethi $r14 0x400000
-        or $r15 0x10
-        call #nv_wr32
-        ret
-
-// Waits for a ctx_4170s() call to complete
-//
-ctx_4170w:
-        mov $r14 0x4170
-        sethi $r14 0x400000
-        call #nv_rd32
-        and $r15 0x10
-        bra ne #ctx_4170w
-        ret
-
-// Disables various things, waits a bit, and re-enables them..
-//
-// Not sure how exactly this helps, perhaps "ENABLE" is not such a
-// good description for the bits we turn off?  Anyways, without this,
-// funny things happen.
-//
-ctx_redswitch:
-        mov $r14 0x614
-        shl b32 $r14 6
-        mov $r15 0x270
-        iowr I[$r14] $r15       // HUB_RED_SWITCH = ENABLE_GPC, POWER_ALL
-        mov $r15 8
-        ctx_redswitch_delay:
-                sub b32 $r15 1
-                bra ne #ctx_redswitch_delay
-        mov $r15 0x770
-        iowr I[$r14] $r15       // HUB_RED_SWITCH = ENABLE_ALL, POWER_ALL
-        ret
-
-// Not a clue what this is for, except that unless the value is 0x10, the
-// strand context is saved (and presumably restored) incorrectly..
-//
-// In: $r15 value to set to (0x00/0x10 are used)
-//
-ctx_86c:
-        mov $r14 0x86c
-        shl b32 $r14 6
-        iowr I[$r14] $r15       // HUB(0x86c) = val
-        mov $r14 -0x75ec
-        sethi $r14 0x400000
-        call #nv_wr32           // ROP(0xa14) = val
-        mov $r14 -0x5794
-        sethi $r14 0x410000
-        call #nv_wr32           // GPC(0x86c) = val
-        ret
-
-// ctx_load - load's a channel's ctxctl data, and selects its vm
-//
-// In: $r2 channel address
-//
-ctx_load:
-        trace_set(T_CHAN)
-
-        // switch to channel, somewhat magic in parts..
-        mov $r10 12             // DONE_UNK12
-        call #wait_donez
-        mov $r1 0xa24
-        shl b32 $r1 6
-        iowr I[$r1 + 0x000] $r0 // 0x409a24
-        mov $r3 0xb00
-        shl b32 $r3 6
-        iowr I[$r3 + 0x100] $r2 // CHAN_NEXT
-        mov $r1 0xa0c
-        shl b32 $r1 6
-        mov $r4 7
-        iowr I[$r1 + 0x000] $r2 // MEM_CHAN
-        iowr I[$r1 + 0x100] $r4 // MEM_CMD
-        ctx_chan_wait_0:
-                iord $r4 I[$r1 + 0x100]
-                and $r4 0x1f
-                bra ne #ctx_chan_wait_0
-        iowr I[$r3 + 0x000] $r2 // CHAN_CUR
-
-        // load channel header, fetch PGRAPH context pointer
-        mov $xtargets $r0
-        bclr $r2 31
-        shl b32 $r2 4
-        add b32 $r2 2
-
-        trace_set(T_LCHAN)
-        mov $r1 0xa04
-        shl b32 $r1 6
-        iowr I[$r1 + 0x000] $r2         // MEM_BASE
-        mov $r1 0xa20
-        shl b32 $r1 6
-        mov $r2 0x0002
-        sethi $r2 0x80000000
-        iowr I[$r1 + 0x000] $r2         // MEM_TARGET = vram
-        mov $r1 0x10                    // chan + 0x0210
-        mov $r2 #xfer_data
-        sethi $r2 0x00020000            // 16 bytes
-        xdld $r1 $r2
-        xdwait
-        trace_clr(T_LCHAN)
-
-        // update current context
-        ld b32 $r1 D[$r0 + #xfer_data + 4]
-        shl b32 $r1 24
-        ld b32 $r2 D[$r0 + #xfer_data + 0]
-        shr b32 $r2 8
-        or $r1 $r2
-        st b32 D[$r0 + #ctx_current] $r1
-
-        // set transfer base to start of context, and fetch context header
-        trace_set(T_LCTXH)
-        mov $r2 0xa04
-        shl b32 $r2 6
-        iowr I[$r2 + 0x000] $r1         // MEM_BASE
-        mov $r2 1
-        mov $r1 0xa20
-        shl b32 $r1 6
-        iowr I[$r1 + 0x000] $r2         // MEM_TARGET = vm
-        mov $r1 #chan_data
-        sethi $r1 0x00060000            // 256 bytes
-        xdld $r0 $r1
-        xdwait
-        trace_clr(T_LCTXH)
-
-        trace_clr(T_CHAN)
-        ret
-
-// ctx_chan - handler for HUB_SET_CHAN command, will set a channel as
-//            the active channel for ctxctl, but not actually transfer
-//            any context data.  intended for use only during initial
-//            context construction.
-//
-// In: $r2 channel address
-//
-ctx_chan:
-        call #ctx_4160s
-        call #ctx_load
-        mov $r10 12                     // DONE_UNK12
-        call #wait_donez
-        mov $r1 0xa10
-        shl b32 $r1 6
-        mov $r2 5
-        iowr I[$r1 + 0x000] $r2         // MEM_CMD = 5 (???)
-        ctx_chan_wait:
-                iord $r2 I[$r1 + 0x000]
-                or $r2 $r2
-                bra ne #ctx_chan_wait
-        call #ctx_4160c
-        ret
-
-// Execute per-context state overrides list
-//
-// Only executed on the first load of a channel.  Might want to look into
-// removing this and having the host directly modify the channel's context
-// to change this state...  The nouveau DRM already builds this list as
-// it's definitely needed for NVIDIA's, so we may as well use it for now
-//
-// Input: $r1 mmio list length
-//
-ctx_mmio_exec:
-        // set transfer base to be the mmio list
-        ld b32 $r3 D[$r0 + #chan_mmio_address]
-        mov $r2 0xa04
-        shl b32 $r2 6
-        iowr I[$r2 + 0x000] $r3         // MEM_BASE
-
-        clear b32 $r3
-        ctx_mmio_loop:
-                // fetch next 256 bytes of mmio list if necessary
-                and $r4 $r3 0xff
-                bra ne #ctx_mmio_pull
-                        mov $r5 #xfer_data
-                        sethi $r5 0x00060000    // 256 bytes
-                        xdld $r3 $r5
-                        xdwait
-
-                // execute a single list entry
-                ctx_mmio_pull:
-                ld b32 $r14 D[$r4 + #xfer_data + 0x00]
-                ld b32 $r15 D[$r4 + #xfer_data + 0x04]
-                call #nv_wr32
-
-                // next!
-                add b32 $r3 8
-                sub b32 $r1 1
-                bra ne #ctx_mmio_loop
-
-        // set transfer base back to the current context
-        ctx_mmio_done:
-        ld b32 $r3 D[$r0 + #ctx_current]
-        iowr I[$r2 + 0x000] $r3         // MEM_BASE
-
-        // disable the mmio list now, we don't need/want to execute it again
-        st b32 D[$r0 + #chan_mmio_count] $r0
-        mov $r1 #chan_data
-        sethi $r1 0x00060000            // 256 bytes
-        xdst $r0 $r1
-        xdwait
-        ret
-
-// Transfer HUB context data between GPU and storage area
-//
-// In: $r2 channel address
-//     $p1 clear on save, set on load
-//     $p2 set if opposite direction done/will be done, so:
-//              on save it means: "a load will follow this save"
-//              on load it means: "a save preceeded this load"
-//
-ctx_xfer:
-        // according to mwk, some kind of wait for idle
-        mov $r15 0xc00
-        shl b32 $r15 6
-        mov $r14 4
-        iowr I[$r15 + 0x200] $r14
-        ctx_xfer_idle:
-                iord $r14 I[$r15 + 0x000]
-                and $r14 0x2000
-                bra ne #ctx_xfer_idle
-
-        bra not $p1 #ctx_xfer_pre
-        bra $p2 #ctx_xfer_pre_load
-        ctx_xfer_pre:
-                mov $r15 0x10
-                call #ctx_86c
-                call #ctx_4160s
-                bra not $p1 #ctx_xfer_exec
-
-        ctx_xfer_pre_load:
-                mov $r15 2
-                call #ctx_4170s
-                call #ctx_4170w
-                call #ctx_redswitch
-                clear b32 $r15
-                call #ctx_4170s
-                call #ctx_load
-
-        // fetch context pointer, and initiate xfer on all GPCs
-        ctx_xfer_exec:
-        ld b32 $r1 D[$r0 + #ctx_current]
-        mov $r2 0x414
-        shl b32 $r2 6
-        iowr I[$r2 + 0x000] $r0 // BAR_STATUS = reset
-        mov $r14 -0x5b00
-        sethi $r14 0x410000
-        mov b32 $r15 $r1
-        call #nv_wr32           // GPC_BCAST_WRCMD_DATA = ctx pointer
-        add b32 $r14 4
-        xbit $r15 $flags $p1
-        xbit $r2 $flags $p2
-        shl b32 $r2 1
-        or $r15 $r2
-        call #nv_wr32           // GPC_BCAST_WRCMD_CMD = GPC_XFER(type)
-
-        // strands
-        mov $r1 0x4afc
-        sethi $r1 0x20000
-        mov $r2 0xc
-        iowr I[$r1] $r2         // STRAND_CMD(0x3f) = 0x0c
-        call #strand_wait
-        mov $r2 0x47fc
-        sethi $r2 0x20000
-        iowr I[$r2] $r0         // STRAND_FIRST_GENE(0x3f) = 0x00
-        xbit $r2 $flags $p1
-        add b32 $r2 3
-        iowr I[$r1] $r2         // STRAND_CMD(0x3f) = 0x03/0x04 (SAVE/LOAD)
-
-        // mmio context
-        xbit $r10 $flags $p1    // direction
-        or $r10 6               // first, last
-        mov $r11 0              // base = 0
-        ld b32 $r12 D[$r0 + #hub_mmio_list_head]
-        ld b32 $r13 D[$r0 + #hub_mmio_list_tail]
-        mov $r14 0              // not multi
-        call #mmctx_xfer
-
-        // wait for GPCs to all complete
-        mov $r10 8              // DONE_BAR
-        call #wait_doneo
-
-        // wait for strand xfer to complete
-        call #strand_wait
-
-        // post-op
-        bra $p1 #ctx_xfer_post
-                mov $r10 12             // DONE_UNK12
-                call #wait_donez
-                mov $r1 0xa10
-                shl b32 $r1 6
-                mov $r2 5
-                iowr I[$r1] $r2         // MEM_CMD
-                ctx_xfer_post_save_wait:
-                        iord $r2 I[$r1]
-                        or $r2 $r2
-                        bra ne #ctx_xfer_post_save_wait
-
-        bra $p2 #ctx_xfer_done
-        ctx_xfer_post:
-                mov $r15 2
-                call #ctx_4170s
-                clear b32 $r15
-                call #ctx_86c
-                call #strand_post
-                call #ctx_4170w
-                clear b32 $r15
-                call #ctx_4170s
-
-                bra not $p1 #ctx_xfer_no_post_mmio
-                ld b32 $r1 D[$r0 + #chan_mmio_count]
-                or $r1 $r1
-                bra e #ctx_xfer_no_post_mmio
-                        call #ctx_mmio_exec
-
-                ctx_xfer_no_post_mmio:
-                call #ctx_4160c
-
-        ctx_xfer_done:
-        ret
-
+#include "com.fuc"
+#include "hub.fuc"
 .align 256
+#undef INCLUDE_CODE
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvc0.fuc.h b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvc0.fuc.h
index bb03d2a1d57b..b59f694c0423 100644
--- a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvc0.fuc.h
+++ b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvc0.fuc.h
@@ -1,9 +1,90 @@
 uint32_t nvc0_grhub_data[] = {
-/* 0x0000: gpc_count */
+/* 0x0000: hub_mmio_list_head */
+        0x00000300,
+/* 0x0004: hub_mmio_list_tail */
+        0x00000304,
+/* 0x0008: gpc_count */
+        0x00000000,
+/* 0x000c: rop_count */
+        0x00000000,
+/* 0x0010: cmd_queue */
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+/* 0x0058: ctx_current */
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+/* 0x0100: chan_data */
+/* 0x0100: chan_mmio_count */
+        0x00000000,
+/* 0x0104: chan_mmio_address */
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
         0x00000000,
-/* 0x0004: rop_count */
         0x00000000,
-/* 0x0008: cmd_queue */
         0x00000000,
         0x00000000,
         0x00000000,
@@ -22,114 +103,9 @@ uint32_t nvc0_grhub_data[] = {
         0x00000000,
         0x00000000,
         0x00000000,
-/* 0x0050: hub_mmio_list_head */
         0x00000000,
-/* 0x0054: hub_mmio_list_tail */
         0x00000000,
-/* 0x0058: ctx_current */
         0x00000000,
-/* 0x005c: chipsets */
-        0x000000c0,
-        0x013c00a0,
-        0x000000c1,
-        0x014000a0,
-        0x000000c3,
-        0x013c00a0,
-        0x000000c4,
-        0x013c00a0,
-        0x000000c8,
-        0x013c00a0,
-        0x000000ce,
-        0x013c00a0,
-        0x000000cf,
-        0x013c00a0,
-        0x000000d9,
-        0x01dc0140,
-        0x00000000,
-/* 0x00a0: nvc0_hub_mmio_head */
-        0x0417e91c,
-        0x04400204,
-        0x28404004,
-        0x00404044,
-        0x34404094,
-        0x184040d0,
-        0x004040f8,
-        0x08404130,
-        0x08404150,
-        0x04404164,
-        0x08404174,
-        0x1c404200,
-        0x34404404,
-        0x0c404460,
-        0x00404480,
-        0x00404498,
-        0x0c404604,
-        0x7c404618,
-        0x50404698,
-        0x044046f0,
-        0x54404700,
-        0x00405800,
-        0x08405830,
-        0x00405854,
-        0x0c405870,
-        0x04405a00,
-        0x00405a18,
-        0x00406020,
-        0x0c406028,
-        0x044064a8,
-        0x044064b4,
-        0x00407804,
-        0x1440780c,
-        0x004078bc,
-        0x18408000,
-        0x00408064,
-        0x08408800,
-        0x0c408900,
-        0x00408980,
-/* 0x013c: nvc0_hub_mmio_tail */
-        0x044064c0,
-/* 0x0140: nvc1_hub_mmio_tail */
-/* 0x0140: nvd9_hub_mmio_head */
-        0x0417e91c,
-        0x04400204,
-        0x24404004,
-        0x00404044,
-        0x34404094,
-        0x184040d0,
-        0x004040f8,
-        0x08404130,
-        0x08404150,
-        0x04404164,
-        0x04404178,
-        0x1c404200,
-        0x34404404,
-        0x0c404460,
-        0x00404480,
-        0x00404498,
-        0x0c404604,
-        0x7c404618,
-        0x50404698,
-        0x044046f0,
-        0x54404700,
-        0x00405800,
-        0x08405830,
-        0x00405854,
-        0x0c405870,
-        0x04405a00,
-        0x00405a18,
-        0x00406020,
-        0x0c406028,
-        0x044064a8,
-        0x104064b4,
-        0x00407804,
-        0x1440780c,
-        0x004078bc,
-        0x18408000,
-        0x00408064,
-        0x08408800,
-        0x0c408900,
-        0x00408980,
-/* 0x01dc: nvd9_hub_mmio_tail */
         0x00000000,
         0x00000000,
         0x00000000,
@@ -139,10 +115,7 @@ uint32_t nvc0_grhub_data[] = {
         0x00000000,
         0x00000000,
         0x00000000,
-/* 0x0200: chan_data */
-/* 0x0200: chan_mmio_count */
         0x00000000,
-/* 0x0204: chan_mmio_address */
         0x00000000,
         0x00000000,
         0x00000000,
@@ -163,6 +136,7 @@ uint32_t nvc0_grhub_data[] = {
         0x00000000,
         0x00000000,
         0x00000000,
+/* 0x0200: xfer_data */
         0x00000000,
         0x00000000,
         0x00000000,
@@ -206,19 +180,40 @@ uint32_t nvc0_grhub_data[] = {
         0x00000000,
         0x00000000,
         0x00000000,
-/* 0x0300: xfer_data */
         0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+/* 0x0300: hub_mmio_list_base */
+        0x0417e91c,
 };
 
 uint32_t nvc0_grhub_code[] = {
-        0x03090ef5,
+        0x031b0ef5,
 /* 0x0004: queue_put */
         0x9800d898,
         0x86f001d9,
         0x0489b808,
         0xf00c1bf4,
         0x21f502f7,
-        0x00f802ec,
+        0x00f802fe,
 /* 0x001c: queue_put_next */
         0xb60798c4,
         0x8dbb0384,
@@ -250,7 +245,7 @@ uint32_t nvc0_grhub_code[] = {
         0xc800bccf,
         0x1bf41fcc,
         0x06a7f0fa,
-        0x010321f5,
+        0x010921f5,
         0xf840bfcf,
 /* 0x008d: nv_wr32 */
         0x28b7f100,
@@ -272,63 +267,66 @@ uint32_t nvc0_grhub_code[] = {
         0x0684b604,
         0xf80080d0,
 /* 0x00c9: wait_donez */
-        0x3c87f100,
-        0x0684b608,
-        0x99f094bd,
-        0x0089d000,
-        0x081887f1,
-        0xd00684b6,
-/* 0x00e2: wait_done_wait_donez */
-        0x87f1008a,
-        0x84b60400,
-        0x0088cf06,
+        0xf094bd00,
+        0x07f10099,
+        0x03f00f00,
+        0x0009d002,
+        0x07f104bd,
+        0x03f00600,
+        0x000ad002,
+/* 0x00e6: wait_donez_ne */
+        0x87f104bd,
+        0x83f00000,
+        0x0088cf01,
         0xf4888aff,
-        0x87f1f31b,
-        0x84b6085c,
-        0xf094bd06,
-        0x89d00099,
-/* 0x0103: wait_doneo */
-        0xf100f800,
-        0xb6083c87,
-        0x94bd0684,
-        0xd00099f0,
-        0x87f10089,
+        0x94bdf31b,
+        0xf10099f0,
+        0xf0170007,
+        0x09d00203,
+        0xf804bd00,
+/* 0x0109: wait_doneo */
+        0xf094bd00,
+        0x07f10099,
+        0x03f00f00,
+        0x0009d002,
+        0x87f104bd,
         0x84b60818,
         0x008ad006,
-/* 0x011c: wait_done_wait_doneo */
+/* 0x0124: wait_doneo_e */
         0x040087f1,
         0xcf0684b6,
         0x8aff0088,
         0xf30bf488,
-        0x085c87f1,
-        0xbd0684b6,
-        0x0099f094,
-        0xf80089d0,
-/* 0x013d: mmctx_size */
-/* 0x013f: nv_mmctx_size_loop */
-        0x9894bd00,
-        0x85b600e8,
-        0x0180b61a,
-        0xbb0284b6,
-        0xe0b60098,
-        0x04efb804,
-        0xb9eb1bf4,
-        0x00f8029f,
-/* 0x015c: mmctx_xfer */
-        0x083c87f1,
-        0xbd0684b6,
-        0x0199f094,
-        0xf10089d0,
+        0x99f094bd,
+        0x0007f100,
+        0x0203f017,
+        0xbd0009d0,
+/* 0x0147: mmctx_size */
+        0xbd00f804,
+/* 0x0149: nv_mmctx_size_loop */
+        0x00e89894,
+        0xb61a85b6,
+        0x84b60180,
+        0x0098bb02,
+        0xb804e0b6,
+        0x1bf404ef,
+        0x029fb9eb,
+/* 0x0166: mmctx_xfer */
+        0x94bd00f8,
+        0xf10199f0,
+        0xf00f0007,
+        0x09d00203,
+        0xf104bd00,
         0xb6071087,
         0x94bd0684,
         0xf405bbfd,
         0x8bd0090b,
         0x0099f000,
-/* 0x0180: mmctx_base_disabled */
+/* 0x018c: mmctx_base_disabled */
         0xf405eefd,
         0x8ed00c0b,
         0xc08fd080,
-/* 0x018f: mmctx_multi_disabled */
+/* 0x019b: mmctx_multi_disabled */
         0xb70199f0,
         0xc8010080,
         0xb4b600ab,
@@ -336,8 +334,8 @@ uint32_t nvc0_grhub_code[] = {
         0xb601aec8,
         0xbefd11e4,
         0x008bd005,
-/* 0x01a8: mmctx_exec_loop */
-/* 0x01a8: mmctx_wait_free */
+/* 0x01b4: mmctx_exec_loop */
+/* 0x01b4: mmctx_wait_free */
         0xf0008ecf,
         0x0bf41fe4,
         0x00ce98fa,
@@ -346,76 +344,77 @@ uint32_t nvc0_grhub_code[] = {
         0x04cdb804,
         0xc8e81bf4,
         0x1bf402ab,
-/* 0x01c9: mmctx_fini_wait */
+/* 0x01d5: mmctx_fini_wait */
         0x008bcf18,
         0xb01fb4f0,
         0x1bf410b4,
         0x02a7f0f7,
         0xf4c921f4,
-/* 0x01de: mmctx_stop */
+/* 0x01ea: mmctx_stop */
         0xabc81b0e,
         0x10b4b600,
         0xf00cb9f0,
         0x8bd012b9,
-/* 0x01ed: mmctx_stop_wait */
+/* 0x01f9: mmctx_stop_wait */
         0x008bcf00,
         0xf412bbc8,
-/* 0x01f6: mmctx_done */
-        0x87f1fa1b,
-        0x84b6085c,
-        0xf094bd06,
-        0x89d00199,
-/* 0x0207: strand_wait */
-        0xf900f800,
-        0x02a7f0a0,
-        0xfcc921f4,
-/* 0x0213: strand_pre */
-        0xf100f8a0,
-        0xf04afc87,
-        0x97f00283,
-        0x0089d00c,
-        0x020721f5,
-/* 0x0226: strand_post */
-        0x87f100f8,
-        0x83f04afc,
-        0x0d97f002,
-        0xf50089d0,
-        0xf8020721,
-/* 0x0239: strand_set */
-        0xfca7f100,
-        0x02a3f04f,
-        0x0500aba2,
-        0xd00fc7f0,
-        0xc7f000ac,
-        0x00bcd00b,
-        0x020721f5,
-        0xf000aed0,
-        0xbcd00ac7,
-        0x0721f500,
-/* 0x0263: strand_ctx_init */
-        0xf100f802,
-        0xb6083c87,
-        0x94bd0684,
-        0xd00399f0,
+/* 0x0202: mmctx_done */
+        0x94bdfa1b,
+        0xf10199f0,
+        0xf0170007,
+        0x09d00203,
+        0xf804bd00,
+/* 0x0215: strand_wait */
+        0xf0a0f900,
+        0x21f402a7,
+        0xf8a0fcc9,
+/* 0x0221: strand_pre */
+        0xfc87f100,
+        0x0283f04a,
+        0xd00c97f0,
         0x21f50089,
-        0xe7f00213,
-        0x3921f503,
+        0x00f80215,
+/* 0x0234: strand_post */
+        0x4afc87f1,
+        0xf00283f0,
+        0x89d00d97,
+        0x1521f500,
+/* 0x0247: strand_set */
+        0xf100f802,
+        0xf04ffca7,
+        0xaba202a3,
+        0xc7f00500,
+        0x00acd00f,
+        0xd00bc7f0,
+        0x21f500bc,
+        0xaed00215,
+        0x0ac7f000,
+        0xf500bcd0,
+        0xf8021521,
+/* 0x0271: strand_ctx_init */
+        0xf094bd00,
+        0x07f10399,
+        0x03f00f00,
+        0x0009d002,
+        0x21f504bd,
+        0xe7f00221,
+        0x4721f503,
         0xfca7f102,
         0x02a3f046,
         0x0400aba0,
         0xf040a0d0,
         0xbcd001c7,
-        0x0721f500,
+        0x1521f500,
         0x010c9202,
         0xf000acd0,
         0xbcd002c7,
-        0x0721f500,
-        0x2621f502,
+        0x1521f500,
+        0x3421f502,
         0x8087f102,
         0x0684b608,
         0xb70089cf,
         0x95220080,
-/* 0x02ba: ctx_init_strand_loop */
+/* 0x02ca: ctx_init_strand_loop */
         0x8ed008fe,
         0x408ed000,
         0xb6808acf,
@@ -424,73 +423,61 @@ uint32_t nvc0_grhub_code[] = {
         0xb60480b6,
         0x1bf40192,
         0x08e4b6e8,
-        0xf1f2efbc,
-        0xb6085c87,
-        0x94bd0684,
-        0xd00399f0,
-        0x00f80089,
-/* 0x02ec: error */
-        0xe7f1e0f9,
-        0xe4b60814,
-        0x00efd006,
-        0x0c1ce7f1,
-        0xf006e4b6,
-        0xefd001f7,
-        0xf8e0fc00,
-/* 0x0309: init */
-        0xfe04bd00,
-        0x07fe0004,
-        0x0017f100,
-        0x0227f012,
-        0xf10012d0,
-        0xfe05b917,
-        0x17f10010,
-        0x10d00400,
-        0x0437f1c0,
-        0x0634b604,
-        0x200327f1,
-        0xf10032d0,
-        0xd0200427,
-        0x27f10132,
-        0x32d0200b,
-        0x0c27f102,
-        0x0732d020,
-        0x0c2427f1,
-        0xb90624b6,
-        0x23d00003,
+        0xbdf2efbc,
+        0x0399f094,
+        0x170007f1,
+        0xd00203f0,
+        0x04bd0009,
+/* 0x02fe: error */
+        0x07f100f8,
+        0x03f00500,
+        0x000fd002,
+        0xf7f004bd,
+        0x0007f101,
+        0x0303f007,
+        0xbd000fd0,
+/* 0x031b: init */
+        0xbd00f804,
+        0x0004fe04,
+        0xf10007fe,
+        0xf0120017,
+        0x12d00227,
+        0xb117f100,
+        0x0010fe05,
+        0x040017f1,
+        0xf1c010d0,
+        0xb6040437,
+        0x27f10634,
+        0x32d02003,
         0x0427f100,
-        0x0023f087,
-        0xb70012d0,
-        0xf0010012,
-        0x12d00427,
-        0x1031f400,
-        0x9604e7f1,
-        0xf440e3f0,
-        0xf1c76821,
-        0x01018090,
-        0x801ff4f0,
-        0x17f0000f,
-        0x041fbb01,
-        0xf10112b6,
-        0xb6040c27,
-        0x21d00624,
-        0x4021d000,
-        0x080027f1,
-        0xcf0624b6,
-        0xf7f00022,
-/* 0x03a9: init_find_chipset */
-        0x08f0b654,
-        0xb800f398,
-        0x0bf40432,
-        0x0034b00b,
-        0xf8f11bf4,
-/* 0x03bd: init_context */
-        0x0017f100,
-        0x02fe5801,
-        0xf003ff58,
-        0x0e8000e3,
-        0x150f8014,
-        0x013d21f5,
+        0x0132d020,
+        0x200b27f1,
+        0xf10232d0,
+        0xd0200c27,
+        0x27f10732,
+        0x24b60c24,
+        0x0003b906,
+        0xf10023d0,
+        0xf0870427,
+        0x12d00023,
+        0x0012b700,
+        0x0427f001,
+        0xf40012d0,
+        0xe7f11031,
+        0xe3f09604,
+        0x6821f440,
+        0x8090f1c7,
+        0xf4f00301,
+        0x020f801f,
+        0xbb0117f0,
+        0x12b6041f,
+        0x0c27f101,
+        0x0624b604,
+        0xd00021d0,
+        0x17f14021,
+        0x0e980100,
+        0x010f9800,
+        0x014721f5,
         0x070037f1,
         0x950634b6,
         0x34d00814,
@@ -501,208 +488,213 @@ uint32_t nvc0_grhub_code[] = {
         0x0815b600,
         0xb60110b6,
         0x1fb90814,
-        0x6321f502,
+        0x7121f502,
         0x001fbb02,
-        0xf1000398,
+        0xf1020398,
         0xf0200047,
-/* 0x040e: init_gpc */
+/* 0x03f6: init_gpc */
         0x4ea05043,
         0x1fb90804,
         0x8d21f402,
-        0x08004ea0,
-        0xf4022fb9,
-        0x4ea08d21,
-        0xf4bd010c,
-        0xa08d21f4,
-        0xf401044e,
+        0x010c4ea0,
+        0x21f4f4bd,
+        0x044ea08d,
+        0x8d21f401,
+        0x01004ea0,
+        0xf402f7f0,
         0x4ea08d21,
-        0xf7f00100,
-        0x8d21f402,
-        0x08004ea0,
-/* 0x0440: init_gpc_wait */
-        0xc86821f4,
-        0x0bf41fff,
-        0x044ea0fa,
-        0x6821f408,
-        0xb7001fbb,
-        0xb6800040,
-        0x1bf40132,
-        0x0027f1b4,
-        0x0624b608,
-        0xb74021d0,
-        0xbd080020,
+/* 0x041e: init_gpc_wait */
+        0x21f40800,
+        0x1fffc868,
+        0xa0fa0bf4,
+        0xf408044e,
+        0x1fbb6821,
+        0x0040b700,
+        0x0132b680,
+        0xf1be1bf4,
+        0xf0010007,
+        0x01d00203,
+        0xbd04bd00,
         0x1f19f014,
-/* 0x0473: main */
-        0xf40021d0,
-        0x28f40031,
-        0x08d7f000,
-        0xf43921f4,
-        0xe4b1f401,
-        0x1bf54001,
-        0x87f100d1,
-        0x84b6083c,
-        0xf094bd06,
-        0x89d00499,
-        0x0017f100,
-        0x0614b60b,
-        0xcf4012cf,
-        0x13c80011,
-        0x7e0bf41f,
+        0x080007f1,
+        0xd00203f0,
+        0x04bd0001,
+/* 0x0458: main */
+        0xf40031f4,
+        0xd7f00028,
+        0x3921f410,
+        0xb1f401f4,
+        0xf54001e4,
+        0xbd00de1b,
+        0x0499f094,
+        0x0f0007f1,
+        0xd00203f0,
+        0x04bd0009,
+        0x0b0017f1,
+        0xcf0614b6,
+        0x11cf4012,
+        0x1f13c800,
+        0x00870bf5,
         0xf41f23c8,
-        0x20f95a0b,
-        0xf10212b9,
-        0xb6083c87,
-        0x94bd0684,
-        0xd00799f0,
-        0x32f40089,
-        0x0231f401,
-        0x082921f5,
-        0x085c87f1,
-        0xbd0684b6,
+        0x20f9620b,
+        0xbd0212b9,
         0x0799f094,
-        0xfc0089d0,
-        0x3c87f120,
-        0x0684b608,
-        0x99f094bd,
-        0x0089d006,
-        0xf50131f4,
-        0xf1082921,
-        0xb6085c87,
-        0x94bd0684,
-        0xd00699f0,
-        0x0ef40089,
-/* 0x0509: chsw_prev_no_next */
+        0x0f0007f1,
+        0xd00203f0,
+        0x04bd0009,
+        0xf40132f4,
+        0x21f50231,
+        0x94bd082f,
+        0xf10799f0,
+        0xf0170007,
+        0x09d00203,
+        0xfc04bd00,
+        0xf094bd20,
+        0x07f10699,
+        0x03f00f00,
+        0x0009d002,
+        0x31f404bd,
+        0x2f21f501,
+        0xf094bd08,
+        0x07f10699,
+        0x03f01700,
+        0x0009d002,
+        0x0ef404bd,
+/* 0x04f9: chsw_prev_no_next */
         0xb920f931,
         0x32f40212,
         0x0232f401,
-        0x082921f5,
+        0x082f21f5,
         0x17f120fc,
         0x14b60b00,
         0x0012d006,
-/* 0x0527: chsw_no_prev */
+/* 0x0517: chsw_no_prev */
         0xc8130ef4,
         0x0bf41f23,
         0x0131f40d,
         0xf50232f4,
-/* 0x0537: chsw_done */
-        0xf1082921,
+/* 0x0527: chsw_done */
+        0xf1082f21,
         0xb60b0c17,
         0x27f00614,
         0x0012d001,
-        0x085c87f1,
-        0xbd0684b6,
-        0x0499f094,
-        0xf50089d0,
-/* 0x0557: main_not_ctx_switch */
-        0xb0ff200e,
-        0x1bf401e4,
-        0x02f2b90d,
-        0x07b521f5,
-/* 0x0567: main_not_ctx_chan */
-        0xb0420ef4,
-        0x1bf402e4,
-        0x3c87f12e,
-        0x0684b608,
         0x99f094bd,
-        0x0089d007,
+        0x0007f104,
+        0x0203f017,
+        0xbd0009d0,
+        0x130ef504,
+/* 0x0549: main_not_ctx_switch */
+        0x01e4b0ff,
+        0xb90d1bf4,
+        0x21f502f2,
+        0x0ef407bb,
+/* 0x0559: main_not_ctx_chan */
+        0x02e4b046,
+        0xbd321bf4,
+        0x0799f094,
+        0x0f0007f1,
+        0xd00203f0,
+        0x04bd0009,
         0xf40132f4,
         0x21f50232,
-        0x87f10829,
-        0x84b6085c,
-        0xf094bd06,
-        0x89d00799,
-        0x110ef400,
-/* 0x0598: main_not_ctx_save */
-        0xf010ef94,
-        0x21f501f5,
-        0x0ef502ec,
-/* 0x05a6: main_done */
-        0x17f1fed1,
-        0x14b60820,
-        0xf024bd06,
-        0x12d01f29,
-        0xbe0ef500,
-/* 0x05b9: ih */
+        0x94bd082f,
+        0xf10799f0,
+        0xf0170007,
+        0x09d00203,
+        0xf404bd00,
+/* 0x058e: main_not_ctx_save */
+        0xef94110e,
+        0x01f5f010,
+        0x02fe21f5,
+        0xfec00ef5,
+/* 0x059c: main_done */
+        0x29f024bd,
+        0x0007f11f,
+        0x0203f008,
+        0xbd0002d0,
+        0xab0ef504,
+/* 0x05b1: ih */
         0xfe80f9fe,
         0x80f90188,
         0xa0f990f9,
         0xd0f9b0f9,
         0xf0f9e0f9,
-        0xc4800acf,
-        0x0bf404ab,
-        0x00b7f11d,
-        0x08d7f019,
-        0xcf40becf,
-        0x21f400bf,
-        0x00b0b704,
-        0x01e7f004,
-/* 0x05ef: ih_no_fifo */
-        0xe400bed0,
-        0xf40100ab,
-        0xd7f00d0b,
-        0x01e7f108,
-        0x0421f440,
-/* 0x0600: ih_no_ctxsw */
-        0x0104b7f1,
-        0xabffb0bd,
-        0x0d0bf4b4,
-        0x0c1ca7f1,
-        0xd006a4b6,
-/* 0x0616: ih_no_other */
-        0x0ad000ab,
-        0xfcf0fc40,
-        0xfcd0fce0,
-        0xfca0fcb0,
-        0xfe80fc90,
-        0x80fc0088,
-        0xf80032f4,
-/* 0x0631: ctx_4160s */
-        0x60e7f101,
-        0x40e3f041,
-        0xf401f7f0,
-/* 0x063e: ctx_4160s_wait */
-        0x21f48d21,
-        0x04ffc868,
-        0xf8fa0bf4,
-/* 0x0649: ctx_4160c */
-        0x60e7f100,
+        0x0acf04bd,
+        0x04abc480,
+        0xf11d0bf4,
+        0xf01900b7,
+        0xbecf10d7,
+        0x00bfcf40,
+        0xb70421f4,
+        0xf00400b0,
+        0xbed001e7,
+/* 0x05e9: ih_no_fifo */
+        0x00abe400,
+        0x0d0bf401,
+        0xf110d7f0,
+        0xf44001e7,
+/* 0x05fa: ih_no_ctxsw */
+        0xb7f10421,
+        0xb0bd0104,
+        0xf4b4abff,
+        0xa7f10d0b,
+        0xa4b60c1c,
+        0x00abd006,
+/* 0x0610: ih_no_other */
+        0xfc400ad0,
+        0xfce0fcf0,
+        0xfcb0fcd0,
+        0xfc90fca0,
+        0x0088fe80,
+        0x32f480fc,
+/* 0x062b: ctx_4160s */
+        0xf101f800,
+        0xf04160e7,
+        0xf7f040e3,
+        0x8d21f401,
+/* 0x0638: ctx_4160s_wait */
+        0xc86821f4,
+        0x0bf404ff,
+/* 0x0643: ctx_4160c */
+        0xf100f8fa,
+        0xf04160e7,
+        0xf4bd40e3,
+        0xf88d21f4,
+/* 0x0651: ctx_4170s */
+        0x70e7f100,
         0x40e3f041,
-        0x21f4f4bd,
-/* 0x0657: ctx_4170s */
-        0xf100f88d,
-        0xf04170e7,
-        0xf5f040e3,
-        0x8d21f410,
-/* 0x0666: ctx_4170w */
-        0xe7f100f8,
-        0xe3f04170,
-        0x6821f440,
-        0xf410f4f0,
-        0x00f8f31b,
-/* 0x0678: ctx_redswitch */
-        0x0614e7f1,
-        0xf106e4b6,
-        0xd00270f7,
-        0xf7f000ef,
-/* 0x0689: ctx_redswitch_delay */
-        0x01f2b608,
-        0xf1fd1bf4,
-        0xd00770f7,
-        0x00f800ef,
-/* 0x0698: ctx_86c */
-        0x086ce7f1,
-        0xd006e4b6,
-        0xe7f100ef,
-        0xe3f08a14,
-        0x8d21f440,
-        0xa86ce7f1,
-        0xf441e3f0,
+        0xf410f5f0,
         0x00f88d21,
-/* 0x06b8: ctx_load */
-        0x083c87f1,
-        0xbd0684b6,
-        0x0599f094,
-        0xf00089d0,
+/* 0x0660: ctx_4170w */
+        0x4170e7f1,
+        0xf440e3f0,
+        0xf4f06821,
+        0xf31bf410,
+/* 0x0672: ctx_redswitch */
+        0xe7f100f8,
+        0xe4b60614,
+        0x70f7f106,
+        0x00efd002,
+/* 0x0683: ctx_redswitch_delay */
+        0xb608f7f0,
+        0x1bf401f2,
+        0x70f7f1fd,
+        0x00efd007,
+/* 0x0692: ctx_86c */
+        0xe7f100f8,
+        0xe4b6086c,
+        0x00efd006,
+        0x8a14e7f1,
+        0xf440e3f0,
+        0xe7f18d21,
+        0xe3f0a86c,
+        0x8d21f441,
+/* 0x06b2: ctx_load */
+        0x94bd00f8,
+        0xf10599f0,
+        0xf00f0007,
+        0x09d00203,
+        0xf004bd00,
         0x21f40ca7,
         0x2417f1c9,
         0x0614b60a,
@@ -713,168 +705,169 @@ uint32_t nvc0_grhub_code[] = {
         0x0614b60a,
         0xd00747f0,
         0x14d00012,
-/* 0x06f1: ctx_chan_wait_0 */
+/* 0x06ed: ctx_chan_wait_0 */
         0x4014cf40,
         0xf41f44f0,
         0x32d0fa1b,
         0x000bfe00,
         0xb61f2af0,
         0x20b60424,
-        0x3c87f102,
-        0x0684b608,
+        0xf094bd02,
+        0x07f10899,
+        0x03f00f00,
+        0x0009d002,
+        0x17f104bd,
+        0x14b60a04,
+        0x0012d006,
+        0x0a2017f1,
+        0xf00614b6,
+        0x23f10227,
+        0x12d08000,
+        0x1017f000,
+        0x020027f1,
+        0xfa0223f0,
+        0x03f80512,
         0x99f094bd,
-        0x0089d008,
-        0x0a0417f1,
-        0xd00614b6,
-        0x17f10012,
-        0x14b60a20,
-        0x0227f006,
-        0x800023f1,
-        0xf00012d0,
-        0x27f11017,
-        0x23f00300,
-        0x0512fa02,
-        0x87f103f8,
-        0x84b6085c,
-        0xf094bd06,
-        0x89d00899,
-        0xc1019800,
+        0x0007f108,
+        0x0203f017,
+        0xbd0009d0,
+        0x81019804,
         0x981814b6,
-        0x25b6c002,
+        0x25b68002,
         0x0512fd08,
-        0xf1160180,
-        0xb6083c87,
-        0x94bd0684,
-        0xd00999f0,
-        0x27f10089,
-        0x24b60a04,
-        0x0021d006,
-        0xf10127f0,
-        0xb60a2017,
-        0x12d00614,
-        0x0017f100,
-        0x0613f002,
-        0xf80501fa,
-        0x5c87f103,
-        0x0684b608,
-        0x99f094bd,
-        0x0089d009,
-        0x085c87f1,
-        0xbd0684b6,
-        0x0599f094,
-        0xf80089d0,
-/* 0x07b5: ctx_chan */
-        0x3121f500,
-        0xb821f506,
-        0x0ca7f006,
-        0xf1c921f4,
-        0xb60a1017,
-        0x27f00614,
-        0x0012d005,
-/* 0x07d0: ctx_chan_wait */
-        0xfd0012cf,
-        0x1bf40522,
-        0x4921f5fa,
-/* 0x07df: ctx_mmio_exec */
-        0x9800f806,
-        0x27f18103,
-        0x24b60a04,
-        0x0023d006,
-/* 0x07ee: ctx_mmio_loop */
-        0x34c434bd,
-        0x0f1bf4ff,
-        0x030057f1,
-        0xfa0653f0,
-        0x03f80535,
-/* 0x0800: ctx_mmio_pull */
-        0x98c04e98,
-        0x21f4c14f,
-        0x0830b68d,
-        0xf40112b6,
-/* 0x0812: ctx_mmio_done */
-        0x0398df1b,
-        0x0023d016,
-        0xf1800080,
-        0xf0020017,
+        0xbd160180,
+        0x0999f094,
+        0x0f0007f1,
+        0xd00203f0,
+        0x04bd0009,
+        0x0a0427f1,
+        0xd00624b6,
+        0x27f00021,
+        0x2017f101,
+        0x0614b60a,
+        0xf10012d0,
+        0xf0010017,
         0x01fa0613,
-        0xf803f806,
-/* 0x0829: ctx_xfer */
-        0x00f7f100,
-        0x06f4b60c,
-        0xd004e7f0,
-/* 0x0836: ctx_xfer_idle */
-        0xfecf80fe,
-        0x00e4f100,
-        0xf91bf420,
-        0xf40611f4,
-/* 0x0846: ctx_xfer_pre */
-        0xf7f01102,
-        0x9821f510,
-        0x3121f506,
-        0x1c11f406,
-/* 0x0854: ctx_xfer_pre_load */
-        0xf502f7f0,
-        0xf5065721,
-        0xf5066621,
-        0xbd067821,
-        0x5721f5f4,
-        0xb821f506,
-/* 0x086d: ctx_xfer_exec */
-        0x16019806,
-        0x041427f1,
+        0xbd03f805,
+        0x0999f094,
+        0x170007f1,
+        0xd00203f0,
+        0x04bd0009,
+        0x99f094bd,
+        0x0007f105,
+        0x0203f017,
+        0xbd0009d0,
+/* 0x07bb: ctx_chan */
+        0xf500f804,
+        0xf5062b21,
+        0xf006b221,
+        0x21f40ca7,
+        0x1017f1c9,
+        0x0614b60a,
+        0xd00527f0,
+/* 0x07d6: ctx_chan_wait */
+        0x12cf0012,
+        0x0522fd00,
+        0xf5fa1bf4,
+        0xf8064321,
+/* 0x07e5: ctx_mmio_exec */
+        0x41039800,
+        0x0a0427f1,
         0xd00624b6,
-        0xe7f10020,
-        0xe3f0a500,
-        0x021fb941,
+        0x34bd0023,
+/* 0x07f4: ctx_mmio_loop */
+        0xf4ff34c4,
+        0x57f10f1b,
+        0x53f00200,
+        0x0535fa06,
+/* 0x0806: ctx_mmio_pull */
+        0x4e9803f8,
+        0x814f9880,
         0xb68d21f4,
-        0xfcf004e0,
-        0x022cf001,
-        0xfd0124b6,
-        0x21f405f2,
-        0xfc17f18d,
-        0x0213f04a,
-        0xd00c27f0,
-        0x21f50012,
-        0x27f10207,
-        0x23f047fc,
-        0x0020d002,
-        0xb6012cf0,
-        0x12d00320,
-        0x01acf000,
-        0xf006a5f0,
-        0x0c9800b7,
-        0x150d9814,
-        0xf500e7f0,
-        0xf0015c21,
-        0x21f508a7,
-        0x21f50103,
-        0x01f40207,
-        0x0ca7f022,
-        0xf1c921f4,
-        0xb60a1017,
-        0x27f00614,
-        0x0012d005,
-/* 0x08f4: ctx_xfer_post_save_wait */
-        0xfd0012cf,
-        0x1bf40522,
-        0x3202f4fa,
-/* 0x0900: ctx_xfer_post */
-        0xf502f7f0,
-        0xbd065721,
-        0x9821f5f4,
-        0x2621f506,
-        0x6621f502,
+        0x12b60830,
+        0xdf1bf401,
+/* 0x0818: ctx_mmio_done */
+        0xd0160398,
+        0x00800023,
+        0x0017f140,
+        0x0613f001,
+        0xf80601fa,
+/* 0x082f: ctx_xfer */
+        0xf100f803,
+        0xb60c00f7,
+        0xe7f006f4,
+        0x80fed004,
+/* 0x083c: ctx_xfer_idle */
+        0xf100fecf,
+        0xf42000e4,
+        0x11f4f91b,
+        0x1102f406,
+/* 0x084c: ctx_xfer_pre */
+        0xf510f7f0,
+        0xf5069221,
+        0xf4062b21,
+/* 0x085a: ctx_xfer_pre_load */
+        0xf7f01c11,
+        0x5121f502,
+        0x6021f506,
+        0x7221f506,
         0xf5f4bd06,
-        0xf4065721,
-        0x01981011,
-        0x0511fd80,
-        0xf5070bf4,
-/* 0x092b: ctx_xfer_no_post_mmio */
-        0xf507df21,
-/* 0x092f: ctx_xfer_done */
-        0xf8064921,
-        0x00000000,
-        0x00000000,
+        0xf5065121,
+/* 0x0873: ctx_xfer_exec */
+        0x9806b221,
+        0x27f11601,
+        0x24b60414,
+        0x0020d006,
+        0xa500e7f1,
+        0xb941e3f0,
+        0x21f4021f,
+        0x04e0b68d,
+        0xf001fcf0,
+        0x24b6022c,
+        0x05f2fd01,
+        0xf18d21f4,
+        0xf04afc17,
+        0x27f00213,
+        0x0012d00c,
+        0x021521f5,
+        0x47fc27f1,
+        0xd00223f0,
+        0x2cf00020,
+        0x0320b601,
+        0xf00012d0,
+        0xa5f001ac,
+        0x00b7f006,
+        0x98000c98,
+        0xe7f0010d,
+        0x6621f500,
+        0x08a7f001,
+        0x010921f5,
+        0x021521f5,
+        0xf02201f4,
+        0x21f40ca7,
+        0x1017f1c9,
+        0x0614b60a,
+        0xd00527f0,
+/* 0x08fa: ctx_xfer_post_save_wait */
+        0x12cf0012,
+        0x0522fd00,
+        0xf4fa1bf4,
+/* 0x0906: ctx_xfer_post */
+        0xf7f03202,
+        0x5121f502,
+        0xf5f4bd06,
+        0xf5069221,
+        0xf5023421,
+        0xbd066021,
+        0x5121f5f4,
+        0x1011f406,
+        0xfd400198,
+        0x0bf40511,
+        0xe521f507,
+/* 0x0931: ctx_xfer_no_post_mmio */
+        0x4321f507,
+/* 0x0935: ctx_xfer_done */
+        0x0000f806,
         0x00000000,
         0x00000000,
         0x00000000,
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvd7.fuc b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvd7.fuc
new file mode 100644
index 000000000000..afbe03ac9077
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvd7.fuc
@@ -0,0 +1,40 @@
+/*
+ * Copyright 2013 Red Hat Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Ben Skeggs <bskeggs@redhat.com>
+ */
+
+#define CHIPSET GF117
+#include "macros.fuc"
+
+.section #nvd7_grhub_data
+#define INCLUDE_DATA
+#include "com.fuc"
+#include "hub.fuc"
+#undef INCLUDE_DATA
+
+.section #nvd7_grhub_code
+#define INCLUDE_CODE
+bra #init
+#include "com.fuc"
+#include "hub.fuc"
+.align 256
+#undef INCLUDE_CODE
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvd7.fuc.h b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvd7.fuc.h
new file mode 100644
index 000000000000..a1b9f763996a
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvd7.fuc.h
@@ -0,0 +1,921 @@
+uint32_t nvd7_grhub_data[] = {
+/* 0x0000: hub_mmio_list_head */
+        0x00000300,
+/* 0x0004: hub_mmio_list_tail */
+        0x00000304,
+/* 0x0008: gpc_count */
+        0x00000000,
+/* 0x000c: rop_count */
+        0x00000000,
+/* 0x0010: cmd_queue */
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+/* 0x0058: ctx_current */
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+/* 0x0100: chan_data */
+/* 0x0100: chan_mmio_count */
+        0x00000000,
+/* 0x0104: chan_mmio_address */
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+/* 0x0200: xfer_data */
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+/* 0x0300: hub_mmio_list_base */
+        0x0417e91c,
+};
+
+uint32_t nvd7_grhub_code[] = {
+        0x031b0ef5,
+/* 0x0004: queue_put */
+        0x9800d898,
+        0x86f001d9,
+        0x0489b808,
+        0xf00c1bf4,
+        0x21f502f7,
+        0x00f802fe,
+/* 0x001c: queue_put_next */
+        0xb60798c4,
+        0x8dbb0384,
+        0x0880b600,
+        0x80008e80,
+        0x90b6018f,
+        0x0f94f001,
+        0xf801d980,
+/* 0x0039: queue_get */
+        0x0131f400,
+        0x9800d898,
+        0x89b801d9,
+        0x210bf404,
+        0xb60789c4,
+        0x9dbb0394,
+        0x0890b600,
+        0x98009e98,
+        0x80b6019f,
+        0x0f84f001,
+        0xf400d880,
+/* 0x0066: queue_get_done */
+        0x00f80132,
+/* 0x0068: nv_rd32 */
+        0x0728b7f1,
+        0xb906b4b6,
+        0xc9f002ec,
+        0x00bcd01f,
+/* 0x0078: nv_rd32_wait */
+        0xc800bccf,
+        0x1bf41fcc,
+        0x06a7f0fa,
+        0x010921f5,
+        0xf840bfcf,
+/* 0x008d: nv_wr32 */
+        0x28b7f100,
+        0x06b4b607,
+        0xb980bfd0,
+        0xc9f002ec,
+        0x1ec9f01f,
+/* 0x00a3: nv_wr32_wait */
+        0xcf00bcd0,
+        0xccc800bc,
+        0xfa1bf41f,
+/* 0x00ae: watchdog_reset */
+        0x87f100f8,
+        0x84b60430,
+        0x1ff9f006,
+        0xf8008fd0,
+/* 0x00bd: watchdog_clear */
+        0x3087f100,
+        0x0684b604,
+        0xf80080d0,
+/* 0x00c9: wait_donez */
+        0xf094bd00,
+        0x07f10099,
+        0x03f00f00,
+        0x0009d002,
+        0x07f104bd,
+        0x03f00600,
+        0x000ad002,
+/* 0x00e6: wait_donez_ne */
+        0x87f104bd,
+        0x83f00000,
+        0x0088cf01,
+        0xf4888aff,
+        0x94bdf31b,
+        0xf10099f0,
+        0xf0170007,
+        0x09d00203,
+        0xf804bd00,
+/* 0x0109: wait_doneo */
+        0xf094bd00,
+        0x07f10099,
+        0x03f00f00,
+        0x0009d002,
+        0x87f104bd,
+        0x84b60818,
+        0x008ad006,
+/* 0x0124: wait_doneo_e */
+        0x040087f1,
+        0xcf0684b6,
+        0x8aff0088,
+        0xf30bf488,
+        0x99f094bd,
+        0x0007f100,
+        0x0203f017,
+        0xbd0009d0,
+/* 0x0147: mmctx_size */
+        0xbd00f804,
+/* 0x0149: nv_mmctx_size_loop */
+        0x00e89894,
+        0xb61a85b6,
+        0x84b60180,
+        0x0098bb02,
+        0xb804e0b6,
+        0x1bf404ef,
+        0x029fb9eb,
+/* 0x0166: mmctx_xfer */
+        0x94bd00f8,
+        0xf10199f0,
+        0xf00f0007,
+        0x09d00203,
+        0xf104bd00,
+        0xb6071087,
+        0x94bd0684,
+        0xf405bbfd,
+        0x8bd0090b,
+        0x0099f000,
+/* 0x018c: mmctx_base_disabled */
+        0xf405eefd,
+        0x8ed00c0b,
+        0xc08fd080,
+/* 0x019b: mmctx_multi_disabled */
+        0xb70199f0,
+        0xc8010080,
+        0xb4b600ab,
+        0x0cb9f010,
+        0xb601aec8,
+        0xbefd11e4,
+        0x008bd005,
+/* 0x01b4: mmctx_exec_loop */
+/* 0x01b4: mmctx_wait_free */
+        0xf0008ecf,
+        0x0bf41fe4,
+        0x00ce98fa,
+        0xd005e9fd,
+        0xc0b6c08e,
+        0x04cdb804,
+        0xc8e81bf4,
+        0x1bf402ab,
+/* 0x01d5: mmctx_fini_wait */
+        0x008bcf18,
+        0xb01fb4f0,
+        0x1bf410b4,
+        0x02a7f0f7,
+        0xf4c921f4,
+/* 0x01ea: mmctx_stop */
+        0xabc81b0e,
+        0x10b4b600,
+        0xf00cb9f0,
+        0x8bd012b9,
+/* 0x01f9: mmctx_stop_wait */
+        0x008bcf00,
+        0xf412bbc8,
+/* 0x0202: mmctx_done */
+        0x94bdfa1b,
+        0xf10199f0,
+        0xf0170007,
+        0x09d00203,
+        0xf804bd00,
+/* 0x0215: strand_wait */
+        0xf0a0f900,
+        0x21f402a7,
+        0xf8a0fcc9,
+/* 0x0221: strand_pre */
+        0xfc87f100,
+        0x0283f04a,
+        0xd00c97f0,
+        0x21f50089,
+        0x00f80215,
+/* 0x0234: strand_post */
+        0x4afc87f1,
+        0xf00283f0,
+        0x89d00d97,
+        0x1521f500,
+/* 0x0247: strand_set */
+        0xf100f802,
+        0xf04ffca7,
+        0xaba202a3,
+        0xc7f00500,
+        0x00acd00f,
+        0xd00bc7f0,
+        0x21f500bc,
+        0xaed00215,
+        0x0ac7f000,
+        0xf500bcd0,
+        0xf8021521,
+/* 0x0271: strand_ctx_init */
+        0xf094bd00,
+        0x07f10399,
+        0x03f00f00,
+        0x0009d002,
+        0x21f504bd,
+        0xe7f00221,
+        0x4721f503,
+        0xfca7f102,
+        0x02a3f046,
+        0x0400aba0,
+        0xf040a0d0,
+        0xbcd001c7,
+        0x1521f500,
+        0x010c9202,
+        0xf000acd0,
+        0xbcd002c7,
+        0x1521f500,
+        0x3421f502,
+        0x8087f102,
+        0x0684b608,
+        0xb70089cf,
+        0x95220080,
+/* 0x02ca: ctx_init_strand_loop */
+        0x8ed008fe,
+        0x408ed000,
+        0xb6808acf,
+        0xa0b606a5,
+        0x00eabb01,
+        0xb60480b6,
+        0x1bf40192,
+        0x08e4b6e8,
+        0xbdf2efbc,
+        0x0399f094,
+        0x170007f1,
+        0xd00203f0,
+        0x04bd0009,
+/* 0x02fe: error */
+        0x07f100f8,
+        0x03f00500,
+        0x000fd002,
+        0xf7f004bd,
+        0x0007f101,
+        0x0303f007,
+        0xbd000fd0,
+/* 0x031b: init */
+        0xbd00f804,
+        0x0004fe04,
+        0xf10007fe,
+        0xf0120017,
+        0x12d00227,
+        0xb117f100,
+        0x0010fe05,
+        0x040017f1,
+        0xf1c010d0,
+        0xb6040437,
+        0x27f10634,
+        0x32d02003,
+        0x0427f100,
+        0x0132d020,
+        0x200b27f1,
+        0xf10232d0,
+        0xd0200c27,
+        0x27f10732,
+        0x24b60c24,
+        0x0003b906,
+        0xf10023d0,
+        0xf0870427,
+        0x12d00023,
+        0x0012b700,
+        0x0427f001,
+        0xf40012d0,
+        0xe7f11031,
+        0xe3f09604,
+        0x6821f440,
+        0x8090f1c7,
+        0xf4f00301,
+        0x020f801f,
+        0xbb0117f0,
+        0x12b6041f,
+        0x0c27f101,
+        0x0624b604,
+        0xd00021d0,
+        0x17f14021,
+        0x0e980100,
+        0x010f9800,
+        0x014721f5,
+        0x070037f1,
+        0x950634b6,
+        0x34d00814,
+        0x4034d000,
+        0x130030b7,
+        0xb6001fbb,
+        0x3fd002f5,
+        0x0815b600,
+        0xb60110b6,
+        0x1fb90814,
+        0x7121f502,
+        0x001fbb02,
+        0xf1020398,
+        0xf0200047,
+/* 0x03f6: init_gpc */
+        0x4ea05043,
+        0x1fb90804,
+        0x8d21f402,
+        0x010c4ea0,
+        0x21f4f4bd,
+        0x044ea08d,
+        0x8d21f401,
+        0x01004ea0,
+        0xf402f7f0,
+        0x4ea08d21,
+/* 0x041e: init_gpc_wait */
+        0x21f40800,
+        0x1fffc868,
+        0xa0fa0bf4,
+        0xf408044e,
+        0x1fbb6821,
+        0x0040b700,
+        0x0132b680,
+        0xf1be1bf4,
+        0xf0010007,
+        0x01d00203,
+        0xbd04bd00,
+        0x1f19f014,
+        0x080007f1,
+        0xd00203f0,
+        0x04bd0001,
+/* 0x0458: main */
+        0xf40031f4,
+        0xd7f00028,
+        0x3921f410,
+        0xb1f401f4,
+        0xf54001e4,
+        0xbd00de1b,
+        0x0499f094,
+        0x0f0007f1,
+        0xd00203f0,
+        0x04bd0009,
+        0x0b0017f1,
+        0xcf0614b6,
+        0x11cf4012,
+        0x1f13c800,
+        0x00870bf5,
+        0xf41f23c8,
+        0x20f9620b,
+        0xbd0212b9,
+        0x0799f094,
+        0x0f0007f1,
+        0xd00203f0,
+        0x04bd0009,
+        0xf40132f4,
+        0x21f50231,
+        0x94bd082f,
+        0xf10799f0,
+        0xf0170007,
+        0x09d00203,
+        0xfc04bd00,
+        0xf094bd20,
+        0x07f10699,
+        0x03f00f00,
+        0x0009d002,
+        0x31f404bd,
+        0x2f21f501,
+        0xf094bd08,
+        0x07f10699,
+        0x03f01700,
+        0x0009d002,
+        0x0ef404bd,
+/* 0x04f9: chsw_prev_no_next */
+        0xb920f931,
+        0x32f40212,
+        0x0232f401,
+        0x082f21f5,
+        0x17f120fc,
+        0x14b60b00,
+        0x0012d006,
+/* 0x0517: chsw_no_prev */
+        0xc8130ef4,
+        0x0bf41f23,
+        0x0131f40d,
+        0xf50232f4,
+/* 0x0527: chsw_done */
+        0xf1082f21,
+        0xb60b0c17,
+        0x27f00614,
+        0x0012d001,
+        0x99f094bd,
+        0x0007f104,
+        0x0203f017,
+        0xbd0009d0,
+        0x130ef504,
+/* 0x0549: main_not_ctx_switch */
+        0x01e4b0ff,
+        0xb90d1bf4,
+        0x21f502f2,
+        0x0ef407bb,
+/* 0x0559: main_not_ctx_chan */
+        0x02e4b046,
+        0xbd321bf4,
+        0x0799f094,
+        0x0f0007f1,
+        0xd00203f0,
+        0x04bd0009,
+        0xf40132f4,
+        0x21f50232,
+        0x94bd082f,
+        0xf10799f0,
+        0xf0170007,
+        0x09d00203,
+        0xf404bd00,
+/* 0x058e: main_not_ctx_save */
+        0xef94110e,
+        0x01f5f010,
+        0x02fe21f5,
+        0xfec00ef5,
+/* 0x059c: main_done */
+        0x29f024bd,
+        0x0007f11f,
+        0x0203f008,
+        0xbd0002d0,
+        0xab0ef504,
+/* 0x05b1: ih */
+        0xfe80f9fe,
+        0x80f90188,
+        0xa0f990f9,
+        0xd0f9b0f9,
+        0xf0f9e0f9,
+        0x0acf04bd,
+        0x04abc480,
+        0xf11d0bf4,
+        0xf01900b7,
+        0xbecf10d7,
+        0x00bfcf40,
+        0xb70421f4,
+        0xf00400b0,
+        0xbed001e7,
+/* 0x05e9: ih_no_fifo */
+        0x00abe400,
+        0x0d0bf401,
+        0xf110d7f0,
+        0xf44001e7,
+/* 0x05fa: ih_no_ctxsw */
+        0xb7f10421,
+        0xb0bd0104,
+        0xf4b4abff,
+        0xa7f10d0b,
+        0xa4b60c1c,
+        0x00abd006,
+/* 0x0610: ih_no_other */
+        0xfc400ad0,
+        0xfce0fcf0,
+        0xfcb0fcd0,
+        0xfc90fca0,
+        0x0088fe80,
+        0x32f480fc,
+/* 0x062b: ctx_4160s */
+        0xf101f800,
+        0xf04160e7,
+        0xf7f040e3,
+        0x8d21f401,
+/* 0x0638: ctx_4160s_wait */
+        0xc86821f4,
+        0x0bf404ff,
+/* 0x0643: ctx_4160c */
+        0xf100f8fa,
+        0xf04160e7,
+        0xf4bd40e3,
+        0xf88d21f4,
+/* 0x0651: ctx_4170s */
+        0x70e7f100,
+        0x40e3f041,
+        0xf410f5f0,
+        0x00f88d21,
+/* 0x0660: ctx_4170w */
+        0x4170e7f1,
+        0xf440e3f0,
+        0xf4f06821,
+        0xf31bf410,
+/* 0x0672: ctx_redswitch */
+        0xe7f100f8,
+        0xe4b60614,
+        0x70f7f106,
+        0x00efd002,
+/* 0x0683: ctx_redswitch_delay */
+        0xb608f7f0,
+        0x1bf401f2,
+        0x70f7f1fd,
+        0x00efd007,
+/* 0x0692: ctx_86c */
+        0xe7f100f8,
+        0xe4b6086c,
+        0x00efd006,
+        0x8a14e7f1,
+        0xf440e3f0,
+        0xe7f18d21,
+        0xe3f0a86c,
+        0x8d21f441,
+/* 0x06b2: ctx_load */
+        0x94bd00f8,
+        0xf10599f0,
+        0xf00f0007,
+        0x09d00203,
+        0xf004bd00,
+        0x21f40ca7,
+        0x2417f1c9,
+        0x0614b60a,
+        0xf10010d0,
+        0xb60b0037,
+        0x32d00634,
+        0x0c17f140,
+        0x0614b60a,
+        0xd00747f0,
+        0x14d00012,
+/* 0x06ed: ctx_chan_wait_0 */
+        0x4014cf40,
+        0xf41f44f0,
+        0x32d0fa1b,
+        0x000bfe00,
+        0xb61f2af0,
+        0x20b60424,
+        0xf094bd02,
+        0x07f10899,
+        0x03f00f00,
+        0x0009d002,
+        0x17f104bd,
+        0x14b60a04,
+        0x0012d006,
+        0x0a2017f1,
+        0xf00614b6,
+        0x23f10227,
+        0x12d08000,
+        0x1017f000,
+        0x020027f1,
+        0xfa0223f0,
+        0x03f80512,
+        0x99f094bd,
+        0x0007f108,
+        0x0203f017,
+        0xbd0009d0,
+        0x81019804,
+        0x981814b6,
+        0x25b68002,
+        0x0512fd08,
+        0xbd160180,
+        0x0999f094,
+        0x0f0007f1,
+        0xd00203f0,
+        0x04bd0009,
+        0x0a0427f1,
+        0xd00624b6,
+        0x27f00021,
+        0x2017f101,
+        0x0614b60a,
+        0xf10012d0,
+        0xf0010017,
+        0x01fa0613,
+        0xbd03f805,
+        0x0999f094,
+        0x170007f1,
+        0xd00203f0,
+        0x04bd0009,
+        0x99f094bd,
+        0x0007f105,
+        0x0203f017,
+        0xbd0009d0,
+/* 0x07bb: ctx_chan */
+        0xf500f804,
+        0xf5062b21,
+        0xf006b221,
+        0x21f40ca7,
+        0x1017f1c9,
+        0x0614b60a,
+        0xd00527f0,
+/* 0x07d6: ctx_chan_wait */
+        0x12cf0012,
+        0x0522fd00,
+        0xf5fa1bf4,
+        0xf8064321,
+/* 0x07e5: ctx_mmio_exec */
+        0x41039800,
+        0x0a0427f1,
+        0xd00624b6,
+        0x34bd0023,
+/* 0x07f4: ctx_mmio_loop */
+        0xf4ff34c4,
+        0x57f10f1b,
+        0x53f00200,
+        0x0535fa06,
+/* 0x0806: ctx_mmio_pull */
+        0x4e9803f8,
+        0x814f9880,
+        0xb68d21f4,
+        0x12b60830,
+        0xdf1bf401,
+/* 0x0818: ctx_mmio_done */
+        0xd0160398,
+        0x00800023,
+        0x0017f140,
+        0x0613f001,
+        0xf80601fa,
+/* 0x082f: ctx_xfer */
+        0xf100f803,
+        0xb60c00f7,
+        0xe7f006f4,
+        0x80fed004,
+/* 0x083c: ctx_xfer_idle */
+        0xf100fecf,
+        0xf42000e4,
+        0x11f4f91b,
+        0x1102f406,
+/* 0x084c: ctx_xfer_pre */
+        0xf510f7f0,
+        0xf5069221,
+        0xf4062b21,
+/* 0x085a: ctx_xfer_pre_load */
+        0xf7f01c11,
+        0x5121f502,
+        0x6021f506,
+        0x7221f506,
+        0xf5f4bd06,
+        0xf5065121,
+/* 0x0873: ctx_xfer_exec */
+        0x9806b221,
+        0x27f11601,
+        0x24b60414,
+        0x0020d006,
+        0xa500e7f1,
+        0xb941e3f0,
+        0x21f4021f,
+        0x04e0b68d,
+        0xf001fcf0,
+        0x24b6022c,
+        0x05f2fd01,
+        0xf18d21f4,
+        0xf04afc17,
+        0x27f00213,
+        0x0012d00c,
+        0x021521f5,
+        0x47fc27f1,
+        0xd00223f0,
+        0x2cf00020,
+        0x0320b601,
+        0xf00012d0,
+        0xa5f001ac,
+        0x00b7f006,
+        0x98000c98,
+        0xe7f0010d,
+        0x6621f500,
+        0x08a7f001,
+        0x010921f5,
+        0x021521f5,
+        0xf02201f4,
+        0x21f40ca7,
+        0x1017f1c9,
+        0x0614b60a,
+        0xd00527f0,
+/* 0x08fa: ctx_xfer_post_save_wait */
+        0x12cf0012,
+        0x0522fd00,
+        0xf4fa1bf4,
+/* 0x0906: ctx_xfer_post */
+        0xf7f03202,
+        0x5121f502,
+        0xf5f4bd06,
+        0xf5069221,
+        0xf5023421,
+        0xbd066021,
+        0x5121f5f4,
+        0x1011f406,
+        0xfd400198,
+        0x0bf40511,
+        0xe521f507,
+/* 0x0931: ctx_xfer_no_post_mmio */
+        0x4321f507,
+/* 0x0935: ctx_xfer_done */
+        0x0000f806,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+};
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnve0.fuc b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnve0.fuc
index 7fe9d7cf486b..d4840f1879fd 100644
--- a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnve0.fuc
+++ b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnve0.fuc
@@ -1,6 +1,5 @@
-/* fuc microcode for nve0 PGRAPH/HUB
- *
- * Copyright 2011 Red Hat Inc.
+/*
+ * Copyright 2013 Red Hat Inc.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -20,774 +19,22 @@
  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  * OTHER DEALINGS IN THE SOFTWARE.
  *
- * Authors: Ben Skeggs
+ * Authors: Ben Skeggs <bskeggs@redhat.com>
  */
 
-/* To build:
- *    m4 nve0_grhub.fuc | envyas -a -w -m fuc -V nva3 -o nve0_grhub.fuc.h
- */
+#define CHIPSET GK100
+#include "macros.fuc"
 
 .section #nve0_grhub_data
-include(`nve0.fuc')
-gpc_count:              .b32 0
-rop_count:              .b32 0
-cmd_queue:              queue_init
-hub_mmio_list_head:     .b32 0
-hub_mmio_list_tail:     .b32 0
-
-ctx_current:            .b32 0
-
-chipsets:
-.b8  0xe4 0 0 0
-.b16 #nve4_hub_mmio_head
-.b16 #nve4_hub_mmio_tail
-.b8  0xe7 0 0 0
-.b16 #nve4_hub_mmio_head
-.b16 #nve4_hub_mmio_tail
-.b8  0xe6 0 0 0
-.b16 #nve4_hub_mmio_head
-.b16 #nve4_hub_mmio_tail
-.b8  0 0 0 0
-
-nve4_hub_mmio_head:
-mmctx_data(0x17e91c, 2)
-mmctx_data(0x400204, 2)
-mmctx_data(0x404010, 7)
-mmctx_data(0x4040a8, 9)
-mmctx_data(0x4040d0, 7)
-mmctx_data(0x4040f8, 1)
-mmctx_data(0x404130, 3)
-mmctx_data(0x404150, 3)
-mmctx_data(0x404164, 1)
-mmctx_data(0x4041a0, 4)
-mmctx_data(0x404200, 4)
-mmctx_data(0x404404, 14)
-mmctx_data(0x404460, 4)
-mmctx_data(0x404480, 1)
-mmctx_data(0x404498, 1)
-mmctx_data(0x404604, 4)
-mmctx_data(0x404618, 4)
-mmctx_data(0x40462c, 2)
-mmctx_data(0x404640, 1)
-mmctx_data(0x404654, 1)
-mmctx_data(0x404660, 1)
-mmctx_data(0x404678, 19)
-mmctx_data(0x4046c8, 3)
-mmctx_data(0x404700, 3)
-mmctx_data(0x404718, 10)
-mmctx_data(0x404744, 2)
-mmctx_data(0x404754, 1)
-mmctx_data(0x405800, 1)
-mmctx_data(0x405830, 3)
-mmctx_data(0x405854, 1)
-mmctx_data(0x405870, 4)
-mmctx_data(0x405a00, 2)
-mmctx_data(0x405a18, 1)
-mmctx_data(0x405b00, 1)
-mmctx_data(0x405b10, 1)
-mmctx_data(0x406020, 1)
-mmctx_data(0x406028, 4)
-mmctx_data(0x4064a8, 2)
-mmctx_data(0x4064b4, 2)
-mmctx_data(0x4064c0, 12)
-mmctx_data(0x4064fc, 1)
-mmctx_data(0x407040, 1)
-mmctx_data(0x407804, 1)
-mmctx_data(0x40780c, 6)
-mmctx_data(0x4078bc, 1)
-mmctx_data(0x408000, 7)
-mmctx_data(0x408064, 1)
-mmctx_data(0x408800, 3)
-mmctx_data(0x408840, 1)
-mmctx_data(0x408900, 3)
-mmctx_data(0x408980, 1)
-nve4_hub_mmio_tail:
-
-.align 256
-chan_data:
-chan_mmio_count:        .b32 0
-chan_mmio_address:      .b32 0
-
-.align 256
-xfer_data:              .b32 0
+#define INCLUDE_DATA
+#include "com.fuc"
+#include "hub.fuc"
+#undef INCLUDE_DATA
 
 .section #nve0_grhub_code
+#define INCLUDE_CODE
 bra #init
-define(`include_code')
-include(`nve0.fuc')
-
-// reports an exception to the host
-//
-// In: $r15 error code (see nve0.fuc)
-//
-error:
-        push $r14
-        mov $r14 0x814
-        shl b32 $r14 6
-        iowr I[$r14 + 0x000] $r15       // CC_SCRATCH[5] = error code
-        mov $r14 0xc1c
-        shl b32 $r14 6
-        mov $r15 1
-        iowr I[$r14 + 0x000] $r15       // INTR_UP_SET
-        pop $r14
-        ret
-
-// HUB fuc initialisation, executed by triggering ucode start, will
-// fall through to main loop after completion.
-//
-// Input:
-//   CC_SCRATCH[0]: chipset (PMC_BOOT_0 read returns 0x0bad0bad... sigh)
-//
-// Output:
-//   CC_SCRATCH[0]:
-//           31:31: set to signal completion
-//   CC_SCRATCH[1]:
-//            31:0: total PGRAPH context size
-//
-init:
-        clear b32 $r0
-        mov $sp $r0
-        mov $xdbase $r0
-
-        // enable fifo access
-        mov $r1 0x1200
-        mov $r2 2
-        iowr I[$r1 + 0x000] $r2 // FIFO_ENABLE
-
-        // setup i0 handler, and route all interrupts to it
-        mov $r1 #ih
-        mov $iv0 $r1
-        mov $r1 0x400
-        iowr I[$r1 + 0x300] $r0 // INTR_DISPATCH
-
-        // route HUB_CHANNEL_SWITCH to fuc interrupt 8
-        mov $r3 0x404
-        shl b32 $r3 6
-        mov $r2 0x2003          // { HUB_CHANNEL_SWITCH, ZERO } -> intr 8
-        iowr I[$r3 + 0x000] $r2
-
-        // not sure what these are, route them because NVIDIA does, and
-        // the IRQ handler will signal the host if we ever get one.. we
-        // may find out if/why we need to handle these if so..
-        //
-        mov $r2 0x2004
-        iowr I[$r3 + 0x004] $r2 // { 0x04, ZERO } -> intr 9
-        mov $r2 0x200b
-        iowr I[$r3 + 0x008] $r2 // { 0x0b, ZERO } -> intr 10
-        mov $r2 0x200c
-        iowr I[$r3 + 0x01c] $r2 // { 0x0c, ZERO } -> intr 15
-
-        // enable all INTR_UP interrupts
-        mov $r2 0xc24
-        shl b32 $r2 6
-        not b32 $r3 $r0
-        iowr I[$r2] $r3
-
-        // enable fifo, ctxsw, 9, 10, 15 interrupts
-        mov $r2 -0x78fc         // 0x8704
-        sethi $r2 0
-        iowr I[$r1 + 0x000] $r2 // INTR_EN_SET
-
-        // fifo level triggered, rest edge
-        sub b32 $r1 0x100
-        mov $r2 4
-        iowr I[$r1] $r2
-
-        // enable interrupts
-        bset $flags ie0
-
-        // fetch enabled GPC/ROP counts
-        mov $r14 -0x69fc        // 0x409604
-        sethi $r14 0x400000
-        call #nv_rd32
-        extr $r1 $r15 16:20
-        st b32 D[$r0 + #rop_count] $r1
-        and $r15 0x1f
-        st b32 D[$r0 + #gpc_count] $r15
-
-        // set BAR_REQMASK to GPC mask
-        mov $r1 1
-        shl b32 $r1 $r15
-        sub b32 $r1 1
-        mov $r2 0x40c
-        shl b32 $r2 6
-        iowr I[$r2 + 0x000] $r1
-        iowr I[$r2 + 0x100] $r1
-
-        // find context data for this chipset
-        mov $r2 0x800
-        shl b32 $r2 6
-        iord $r2 I[$r2 + 0x000]         // CC_SCRATCH[0]
-        mov $r15 #chipsets - 8
-        init_find_chipset:
-                add b32 $r15 8
-                ld b32 $r3 D[$r15 + 0x00]
-                cmpu b32 $r3 $r2
-                bra e #init_context
-                cmpu b32 $r3 0
-                bra ne #init_find_chipset
-                // unknown chipset
-                ret
-
-        // context size calculation, reserve first 256 bytes for use by fuc
-        init_context:
-        mov $r1 256
-
-        // calculate size of mmio context data
-        ld b16 $r14 D[$r15 + 4]
-        ld b16 $r15 D[$r15 + 6]
-        sethi $r14 0
-        st b32 D[$r0 + #hub_mmio_list_head] $r14
-        st b32 D[$r0 + #hub_mmio_list_tail] $r15
-        call #mmctx_size
-
-        // set mmctx base addresses now so we don't have to do it later,
-        // they don't (currently) ever change
-        mov $r3 0x700
-        shl b32 $r3 6
-        shr b32 $r4 $r1 8
-        iowr I[$r3 + 0x000] $r4         // MMCTX_SAVE_SWBASE
-        iowr I[$r3 + 0x100] $r4         // MMCTX_LOAD_SWBASE
-        add b32 $r3 0x1300
-        add b32 $r1 $r15
-        shr b32 $r15 2
-        iowr I[$r3 + 0x000] $r15        // MMCTX_LOAD_COUNT, wtf for?!?
-
-        // strands, base offset needs to be aligned to 256 bytes
-        shr b32 $r1 8
-        add b32 $r1 1
-        shl b32 $r1 8
-        mov b32 $r15 $r1
-        call #strand_ctx_init
-        add b32 $r1 $r15
-
-        // initialise each GPC in sequence by passing in the offset of its
-        // context data in GPCn_CC_SCRATCH[1], and starting its FUC (which
-        // has previously been uploaded by the host) running.
-        //
-        // the GPC fuc init sequence will set GPCn_CC_SCRATCH[0] bit 31
-        // when it has completed, and return the size of its context data
-        // in GPCn_CC_SCRATCH[1]
-        //
-        ld b32 $r3 D[$r0 + #gpc_count]
-        mov $r4 0x2000
-        sethi $r4 0x500000
-        init_gpc:
-                // setup, and start GPC ucode running
-                add b32 $r14 $r4 0x804
-                mov b32 $r15 $r1
-                call #nv_wr32                   // CC_SCRATCH[1] = ctx offset
-                add b32 $r14 $r4 0x800
-                mov b32 $r15 $r2
-                call #nv_wr32                   // CC_SCRATCH[0] = chipset
-                add b32 $r14 $r4 0x10c
-                clear b32 $r15
-                call #nv_wr32
-                add b32 $r14 $r4 0x104
-                call #nv_wr32                   // ENTRY
-                add b32 $r14 $r4 0x100
-                mov $r15 2                      // CTRL_START_TRIGGER
-                call #nv_wr32                   // CTRL
-
-                // wait for it to complete, and adjust context size
-                add b32 $r14 $r4 0x800
-                init_gpc_wait:
-                        call #nv_rd32
-                        xbit $r15 $r15 31
-                        bra e #init_gpc_wait
-                add b32 $r14 $r4 0x804
-                call #nv_rd32
-                add b32 $r1 $r15
-
-                // next!
-                add b32 $r4 0x8000
-                sub b32 $r3 1
-                bra ne #init_gpc
-
-        // save context size, and tell host we're ready
-        mov $r2 0x800
-        shl b32 $r2 6
-        iowr I[$r2 + 0x100] $r1         // CC_SCRATCH[1]  = context size
-        add b32 $r2 0x800
-        clear b32 $r1
-        bset $r1 31
-        iowr I[$r2 + 0x000] $r1         // CC_SCRATCH[0] |= 0x80000000
-
-// Main program loop, very simple, sleeps until woken up by the interrupt
-// handler, pulls a command from the queue and executes its handler
-//
-main:
-        // sleep until we have something to do
-        bset $flags $p0
-        sleep $p0
-        mov $r13 #cmd_queue
-        call #queue_get
-        bra $p1 #main
-
-        // context switch, requested by GPU?
-        cmpu b32 $r14 0x4001
-        bra ne #main_not_ctx_switch
-                trace_set(T_AUTO)
-                mov $r1 0xb00
-                shl b32 $r1 6
-                iord $r2 I[$r1 + 0x100]         // CHAN_NEXT
-                iord $r1 I[$r1 + 0x000]         // CHAN_CUR
-
-                xbit $r3 $r1 31
-                bra e #chsw_no_prev
-                        xbit $r3 $r2 31
-                        bra e #chsw_prev_no_next
-                                push $r2
-                                mov b32 $r2 $r1
-                                trace_set(T_SAVE)
-                                bclr $flags $p1
-                                bset $flags $p2
-                                call #ctx_xfer
-                                trace_clr(T_SAVE);
-                                pop $r2
-                                trace_set(T_LOAD);
-                                bset $flags $p1
-                                call #ctx_xfer
-                                trace_clr(T_LOAD);
-                                bra #chsw_done
-                        chsw_prev_no_next:
-                                push $r2
-                                mov b32 $r2 $r1
-                                bclr $flags $p1
-                                bclr $flags $p2
-                                call #ctx_xfer
-                                pop $r2
-                                mov $r1 0xb00
-                                shl b32 $r1 6
-                                iowr I[$r1] $r2
-                                bra #chsw_done
-                chsw_no_prev:
-                        xbit $r3 $r2 31
-                        bra e #chsw_done
-                                bset $flags $p1
-                                bclr $flags $p2
-                                call #ctx_xfer
-
-                // ack the context switch request
-                chsw_done:
-                mov $r1 0xb0c
-                shl b32 $r1 6
-                mov $r2 1
-                iowr I[$r1 + 0x000] $r2         // 0x409b0c
-                trace_clr(T_AUTO)
-                bra #main
-
-        // request to set current channel? (*not* a context switch)
-        main_not_ctx_switch:
-        cmpu b32 $r14 0x0001
-        bra ne #main_not_ctx_chan
-                mov b32 $r2 $r15
-                call #ctx_chan
-                bra #main_done
-
-        // request to store current channel context?
-        main_not_ctx_chan:
-        cmpu b32 $r14 0x0002
-        bra ne #main_not_ctx_save
-                trace_set(T_SAVE)
-                bclr $flags $p1
-                bclr $flags $p2
-                call #ctx_xfer
-                trace_clr(T_SAVE)
-                bra #main_done
-
-        main_not_ctx_save:
-                shl b32 $r15 $r14 16
-                or $r15 E_BAD_COMMAND
-                call #error
-                bra #main
-
-        main_done:
-        mov $r1 0x820
-        shl b32 $r1 6
-        clear b32 $r2
-        bset $r2 31
-        iowr I[$r1 + 0x000] $r2         // CC_SCRATCH[0] |= 0x80000000
-        bra #main
-
-// interrupt handler
-ih:
-        push $r8
-        mov $r8 $flags
-        push $r8
-        push $r9
-        push $r10
-        push $r11
-        push $r13
-        push $r14
-        push $r15
-
-        // incoming fifo command?
-        iord $r10 I[$r0 + 0x200]        // INTR
-        and $r11 $r10 0x00000004
-        bra e #ih_no_fifo
-                // queue incoming fifo command for later processing
-                mov $r11 0x1900
-                mov $r13 #cmd_queue
-                iord $r14 I[$r11 + 0x100]       // FIFO_CMD
-                iord $r15 I[$r11 + 0x000]       // FIFO_DATA
-                call #queue_put
-                add b32 $r11 0x400
-                mov $r14 1
-                iowr I[$r11 + 0x000] $r14       // FIFO_ACK
-
-        // context switch request?
-        ih_no_fifo:
-        and $r11 $r10 0x00000100
-        bra e #ih_no_ctxsw
-                // enqueue a context switch for later processing
-                mov $r13 #cmd_queue
-                mov $r14 0x4001
-                call #queue_put
-
-        // anything we didn't handle, bring it to the host's attention
-        ih_no_ctxsw:
-        mov $r11 0x104
-        not b32 $r11
-        and $r11 $r10 $r11
-        bra e #ih_no_other
-                mov $r10 0xc1c
-                shl b32 $r10 6
-                iowr I[$r10] $r11       // INTR_UP_SET
-
-        // ack, and wake up main()
-        ih_no_other:
-        iowr I[$r0 + 0x100] $r10        // INTR_ACK
-
-        pop $r15
-        pop $r14
-        pop $r13
-        pop $r11
-        pop $r10
-        pop $r9
-        pop $r8
-        mov $flags $r8
-        pop $r8
-        bclr $flags $p0
-        iret
-
-// Again, not real sure
-//
-// In: $r15 value to set 0x404170 to
-//
-ctx_4170s:
-        mov $r14 0x4170
-        sethi $r14 0x400000
-        or $r15 0x10
-        call #nv_wr32
-        ret
-
-// Waits for a ctx_4170s() call to complete
-//
-ctx_4170w:
-        mov $r14 0x4170
-        sethi $r14 0x400000
-        call #nv_rd32
-        and $r15 0x10
-        bra ne #ctx_4170w
-        ret
-
-// Disables various things, waits a bit, and re-enables them..
-//
-// Not sure how exactly this helps, perhaps "ENABLE" is not such a
-// good description for the bits we turn off?  Anyways, without this,
-// funny things happen.
-//
-ctx_redswitch:
-        mov $r14 0x614
-        shl b32 $r14 6
-        mov $r15 0x270
-        iowr I[$r14] $r15       // HUB_RED_SWITCH = ENABLE_GPC, POWER_ALL
-        mov $r15 8
-        ctx_redswitch_delay:
-                sub b32 $r15 1
-                bra ne #ctx_redswitch_delay
-        mov $r15 0x770
-        iowr I[$r14] $r15       // HUB_RED_SWITCH = ENABLE_ALL, POWER_ALL
-        ret
-
-// Not a clue what this is for, except that unless the value is 0x10, the
-// strand context is saved (and presumably restored) incorrectly..
-//
-// In: $r15 value to set to (0x00/0x10 are used)
-//
-ctx_86c:
-        mov $r14 0x86c
-        shl b32 $r14 6
-        iowr I[$r14] $r15       // HUB(0x86c) = val
-        mov $r14 -0x75ec
-        sethi $r14 0x400000
-        call #nv_wr32           // ROP(0xa14) = val
-        mov $r14 -0x5794
-        sethi $r14 0x410000
-        call #nv_wr32           // GPC(0x86c) = val
-        ret
-
-// ctx_load - load's a channel's ctxctl data, and selects its vm
-//
-// In: $r2 channel address
-//
-ctx_load:
-        trace_set(T_CHAN)
-
-        // switch to channel, somewhat magic in parts..
-        mov $r10 12             // DONE_UNK12
-        call #wait_donez
-        mov $r1 0xa24
-        shl b32 $r1 6
-        iowr I[$r1 + 0x000] $r0 // 0x409a24
-        mov $r3 0xb00
-        shl b32 $r3 6
-        iowr I[$r3 + 0x100] $r2 // CHAN_NEXT
-        mov $r1 0xa0c
-        shl b32 $r1 6
-        mov $r4 7
-        iowr I[$r1 + 0x000] $r2 // MEM_CHAN
-        iowr I[$r1 + 0x100] $r4 // MEM_CMD
-        ctx_chan_wait_0:
-                iord $r4 I[$r1 + 0x100]
-                and $r4 0x1f
-                bra ne #ctx_chan_wait_0
-        iowr I[$r3 + 0x000] $r2 // CHAN_CUR
-
-        // load channel header, fetch PGRAPH context pointer
-        mov $xtargets $r0
-        bclr $r2 31
-        shl b32 $r2 4
-        add b32 $r2 2
-
-        trace_set(T_LCHAN)
-        mov $r1 0xa04
-        shl b32 $r1 6
-        iowr I[$r1 + 0x000] $r2         // MEM_BASE
-        mov $r1 0xa20
-        shl b32 $r1 6
-        mov $r2 0x0002
-        sethi $r2 0x80000000
-        iowr I[$r1 + 0x000] $r2         // MEM_TARGET = vram
-        mov $r1 0x10                    // chan + 0x0210
-        mov $r2 #xfer_data
-        sethi $r2 0x00020000            // 16 bytes
-        xdld $r1 $r2
-        xdwait
-        trace_clr(T_LCHAN)
-
-        // update current context
-        ld b32 $r1 D[$r0 + #xfer_data + 4]
-        shl b32 $r1 24
-        ld b32 $r2 D[$r0 + #xfer_data + 0]
-        shr b32 $r2 8
-        or $r1 $r2
-        st b32 D[$r0 + #ctx_current] $r1
-
-        // set transfer base to start of context, and fetch context header
-        trace_set(T_LCTXH)
-        mov $r2 0xa04
-        shl b32 $r2 6
-        iowr I[$r2 + 0x000] $r1         // MEM_BASE
-        mov $r2 1
-        mov $r1 0xa20
-        shl b32 $r1 6
-        iowr I[$r1 + 0x000] $r2         // MEM_TARGET = vm
-        mov $r1 #chan_data
-        sethi $r1 0x00060000            // 256 bytes
-        xdld $r0 $r1
-        xdwait
-        trace_clr(T_LCTXH)
-
-        trace_clr(T_CHAN)
-        ret
-
-// ctx_chan - handler for HUB_SET_CHAN command, will set a channel as
-//            the active channel for ctxctl, but not actually transfer
-//            any context data.  intended for use only during initial
-//            context construction.
-//
-// In: $r2 channel address
-//
-ctx_chan:
-        call #ctx_load
-        mov $r10 12                     // DONE_UNK12
-        call #wait_donez
-        mov $r1 0xa10
-        shl b32 $r1 6
-        mov $r2 5
-        iowr I[$r1 + 0x000] $r2         // MEM_CMD = 5 (???)
-        ctx_chan_wait:
-                iord $r2 I[$r1 + 0x000]
-                or $r2 $r2
-                bra ne #ctx_chan_wait
-        ret
-
-// Execute per-context state overrides list
-//
-// Only executed on the first load of a channel.  Might want to look into
-// removing this and having the host directly modify the channel's context
-// to change this state...  The nouveau DRM already builds this list as
-// it's definitely needed for NVIDIA's, so we may as well use it for now
-//
-// Input: $r1 mmio list length
-//
-ctx_mmio_exec:
-        // set transfer base to be the mmio list
-        ld b32 $r3 D[$r0 + #chan_mmio_address]
-        mov $r2 0xa04
-        shl b32 $r2 6
-        iowr I[$r2 + 0x000] $r3         // MEM_BASE
-
-        clear b32 $r3
-        ctx_mmio_loop:
-                // fetch next 256 bytes of mmio list if necessary
-                and $r4 $r3 0xff
-                bra ne #ctx_mmio_pull
-                        mov $r5 #xfer_data
-                        sethi $r5 0x00060000    // 256 bytes
-                        xdld $r3 $r5
-                        xdwait
-
-                // execute a single list entry
-                ctx_mmio_pull:
-                ld b32 $r14 D[$r4 + #xfer_data + 0x00]
-                ld b32 $r15 D[$r4 + #xfer_data + 0x04]
-                call #nv_wr32
-
-                // next!
-                add b32 $r3 8
-                sub b32 $r1 1
-                bra ne #ctx_mmio_loop
-
-        // set transfer base back to the current context
-        ctx_mmio_done:
-        ld b32 $r3 D[$r0 + #ctx_current]
-        iowr I[$r2 + 0x000] $r3         // MEM_BASE
-
-        // disable the mmio list now, we don't need/want to execute it again
-        st b32 D[$r0 + #chan_mmio_count] $r0
-        mov $r1 #chan_data
-        sethi $r1 0x00060000            // 256 bytes
-        xdst $r0 $r1
-        xdwait
-        ret
-
-// Transfer HUB context data between GPU and storage area
-//
-// In: $r2 channel address
-//     $p1 clear on save, set on load
-//     $p2 set if opposite direction done/will be done, so:
-//              on save it means: "a load will follow this save"
-//              on load it means: "a save preceeded this load"
-//
-ctx_xfer:
-        // according to mwk, some kind of wait for idle
-        mov $r15 0xc00
-        shl b32 $r15 6
-        mov $r14 4
-        iowr I[$r15 + 0x200] $r14
-        ctx_xfer_idle:
-                iord $r14 I[$r15 + 0x000]
-                and $r14 0x2000
-                bra ne #ctx_xfer_idle
-
-        bra not $p1 #ctx_xfer_pre
-        bra $p2 #ctx_xfer_pre_load
-        ctx_xfer_pre:
-                mov $r15 0x10
-                call #ctx_86c
-                bra not $p1 #ctx_xfer_exec
-
-        ctx_xfer_pre_load:
-                mov $r15 2
-                call #ctx_4170s
-                call #ctx_4170w
-                call #ctx_redswitch
-                clear b32 $r15
-                call #ctx_4170s
-                call #ctx_load
-
-        // fetch context pointer, and initiate xfer on all GPCs
-        ctx_xfer_exec:
-        ld b32 $r1 D[$r0 + #ctx_current]
-        mov $r2 0x414
-        shl b32 $r2 6
-        iowr I[$r2 + 0x000] $r0 // BAR_STATUS = reset
-        mov $r14 -0x5b00
-        sethi $r14 0x410000
-        mov b32 $r15 $r1
-        call #nv_wr32           // GPC_BCAST_WRCMD_DATA = ctx pointer
-        add b32 $r14 4
-        xbit $r15 $flags $p1
-        xbit $r2 $flags $p2
-        shl b32 $r2 1
-        or $r15 $r2
-        call #nv_wr32           // GPC_BCAST_WRCMD_CMD = GPC_XFER(type)
-
-        // strands
-        mov $r1 0x4afc
-        sethi $r1 0x20000
-        mov $r2 0xc
-        iowr I[$r1] $r2         // STRAND_CMD(0x3f) = 0x0c
-        call #strand_wait
-        mov $r2 0x47fc
-        sethi $r2 0x20000
-        iowr I[$r2] $r0         // STRAND_FIRST_GENE(0x3f) = 0x00
-        xbit $r2 $flags $p1
-        add b32 $r2 3
-        iowr I[$r1] $r2         // STRAND_CMD(0x3f) = 0x03/0x04 (SAVE/LOAD)
-
-        // mmio context
-        xbit $r10 $flags $p1    // direction
-        or $r10 6               // first, last
-        mov $r11 0              // base = 0
-        ld b32 $r12 D[$r0 + #hub_mmio_list_head]
-        ld b32 $r13 D[$r0 + #hub_mmio_list_tail]
-        mov $r14 0              // not multi
-        call #mmctx_xfer
-
-        // wait for GPCs to all complete
-        mov $r10 8              // DONE_BAR
-        call #wait_doneo
-
-        // wait for strand xfer to complete
-        call #strand_wait
-
-        // post-op
-        bra $p1 #ctx_xfer_post
-                mov $r10 12             // DONE_UNK12
-                call #wait_donez
-                mov $r1 0xa10
-                shl b32 $r1 6
-                mov $r2 5
-                iowr I[$r1] $r2         // MEM_CMD
-                ctx_xfer_post_save_wait:
-                        iord $r2 I[$r1]
-                        or $r2 $r2
-                        bra ne #ctx_xfer_post_save_wait
-
-        bra $p2 #ctx_xfer_done
-        ctx_xfer_post:
-                mov $r15 2
-                call #ctx_4170s
-                clear b32 $r15
-                call #ctx_86c
-                call #strand_post
-                call #ctx_4170w
-                clear b32 $r15
-                call #ctx_4170s
-
-                bra not $p1 #ctx_xfer_no_post_mmio
-                ld b32 $r1 D[$r0 + #chan_mmio_count]
-                or $r1 $r1
-                bra e #ctx_xfer_no_post_mmio
-                        call #ctx_mmio_exec
-
-                ctx_xfer_no_post_mmio:
-
-        ctx_xfer_done:
-        ret
-
+#include "com.fuc"
+#include "hub.fuc"
 .align 256
+#undef INCLUDE_CODE
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnve0.fuc.h b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnve0.fuc.h
index e3421af68ab9..eb7bc0e9576e 100644
--- a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnve0.fuc.h
+++ b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnve0.fuc.h
@@ -1,9 +1,13 @@
 uint32_t nve0_grhub_data[] = {
-/* 0x0000: gpc_count */
+/* 0x0000: hub_mmio_list_head */
+        0x00000300,
+/* 0x0004: hub_mmio_list_tail */
+        0x00000304,
+/* 0x0008: gpc_count */
         0x00000000,
-/* 0x0004: rop_count */
+/* 0x000c: rop_count */
         0x00000000,
-/* 0x0008: cmd_queue */
+/* 0x0010: cmd_queue */
         0x00000000,
         0x00000000,
         0x00000000,
@@ -22,73 +26,11 @@ uint32_t nve0_grhub_data[] = {
         0x00000000,
         0x00000000,
         0x00000000,
-/* 0x0050: hub_mmio_list_head */
+/* 0x0058: ctx_current */
         0x00000000,
-/* 0x0054: hub_mmio_list_tail */
         0x00000000,
-/* 0x0058: ctx_current */
         0x00000000,
-/* 0x005c: chipsets */
-        0x000000e4,
-        0x01440078,
-        0x000000e7,
-        0x01440078,
-        0x000000e6,
-        0x01440078,
         0x00000000,
-/* 0x0078: nve4_hub_mmio_head */
-        0x0417e91c,
-        0x04400204,
-        0x18404010,
-        0x204040a8,
-        0x184040d0,
-        0x004040f8,
-        0x08404130,
-        0x08404150,
-        0x00404164,
-        0x0c4041a0,
-        0x0c404200,
-        0x34404404,
-        0x0c404460,
-        0x00404480,
-        0x00404498,
-        0x0c404604,
-        0x0c404618,
-        0x0440462c,
-        0x00404640,
-        0x00404654,
-        0x00404660,
-        0x48404678,
-        0x084046c8,
-        0x08404700,
-        0x24404718,
-        0x04404744,
-        0x00404754,
-        0x00405800,
-        0x08405830,
-        0x00405854,
-        0x0c405870,
-        0x04405a00,
-        0x00405a18,
-        0x00405b00,
-        0x00405b10,
-        0x00406020,
-        0x0c406028,
-        0x044064a8,
-        0x044064b4,
-        0x2c4064c0,
-        0x004064fc,
-        0x00407040,
-        0x00407804,
-        0x1440780c,
-        0x004078bc,
-        0x18408000,
-        0x00408064,
-        0x08408800,
-        0x00408840,
-        0x08408900,
-        0x00408980,
-/* 0x0144: nve4_hub_mmio_tail */
         0x00000000,
         0x00000000,
         0x00000000,
@@ -127,6 +69,47 @@ uint32_t nve0_grhub_data[] = {
         0x00000000,
         0x00000000,
         0x00000000,
+/* 0x0100: chan_data */
+/* 0x0100: chan_mmio_count */
+        0x00000000,
+/* 0x0104: chan_mmio_address */
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
         0x00000000,
         0x00000000,
         0x00000000,
@@ -136,10 +119,7 @@ uint32_t nve0_grhub_data[] = {
         0x00000000,
         0x00000000,
         0x00000000,
-/* 0x0200: chan_data */
-/* 0x0200: chan_mmio_count */
         0x00000000,
-/* 0x0204: chan_mmio_address */
         0x00000000,
         0x00000000,
         0x00000000,
@@ -156,6 +136,7 @@ uint32_t nve0_grhub_data[] = {
         0x00000000,
         0x00000000,
         0x00000000,
+/* 0x0200: xfer_data */
         0x00000000,
         0x00000000,
         0x00000000,
@@ -203,19 +184,36 @@ uint32_t nve0_grhub_data[] = {
         0x00000000,
         0x00000000,
         0x00000000,
-/* 0x0300: xfer_data */
         0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+/* 0x0300: hub_mmio_list_base */
+        0x0417e91c,
 };
 
 uint32_t nve0_grhub_code[] = {
-        0x03090ef5,
+        0x031b0ef5,
 /* 0x0004: queue_put */
         0x9800d898,
         0x86f001d9,
         0x0489b808,
         0xf00c1bf4,
         0x21f502f7,
-        0x00f802ec,
+        0x00f802fe,
 /* 0x001c: queue_put_next */
         0xb60798c4,
         0x8dbb0384,
@@ -247,7 +245,7 @@ uint32_t nve0_grhub_code[] = {
         0xc800bccf,
         0x1bf41fcc,
         0x06a7f0fa,
-        0x010321f5,
+        0x010921f5,
         0xf840bfcf,
 /* 0x008d: nv_wr32 */
         0x28b7f100,
@@ -269,63 +267,66 @@ uint32_t nve0_grhub_code[] = {
         0x0684b604,
         0xf80080d0,
 /* 0x00c9: wait_donez */
-        0x3c87f100,
-        0x0684b608,
-        0x99f094bd,
-        0x0089d000,
-        0x081887f1,
-        0xd00684b6,
-/* 0x00e2: wait_done_wait_donez */
-        0x87f1008a,
-        0x84b60400,
-        0x0088cf06,
+        0xf094bd00,
+        0x07f10099,
+        0x03f00f00,
+        0x0009d002,
+        0x07f104bd,
+        0x03f00600,
+        0x000ad002,
+/* 0x00e6: wait_donez_ne */
+        0x87f104bd,
+        0x83f00000,
+        0x0088cf01,
         0xf4888aff,
-        0x87f1f31b,
-        0x84b6085c,
-        0xf094bd06,
-        0x89d00099,
-/* 0x0103: wait_doneo */
-        0xf100f800,
-        0xb6083c87,
-        0x94bd0684,
-        0xd00099f0,
-        0x87f10089,
+        0x94bdf31b,
+        0xf10099f0,
+        0xf0170007,
+        0x09d00203,
+        0xf804bd00,
+/* 0x0109: wait_doneo */
+        0xf094bd00,
+        0x07f10099,
+        0x03f00f00,
+        0x0009d002,
+        0x87f104bd,
         0x84b60818,
         0x008ad006,
-/* 0x011c: wait_done_wait_doneo */
+/* 0x0124: wait_doneo_e */
         0x040087f1,
         0xcf0684b6,
         0x8aff0088,
         0xf30bf488,
-        0x085c87f1,
-        0xbd0684b6,
-        0x0099f094,
-        0xf80089d0,
-/* 0x013d: mmctx_size */
-/* 0x013f: nv_mmctx_size_loop */
-        0x9894bd00,
-        0x85b600e8,
-        0x0180b61a,
-        0xbb0284b6,
-        0xe0b60098,
-        0x04efb804,
-        0xb9eb1bf4,
-        0x00f8029f,
-/* 0x015c: mmctx_xfer */
-        0x083c87f1,
-        0xbd0684b6,
-        0x0199f094,
-        0xf10089d0,
+        0x99f094bd,
+        0x0007f100,
+        0x0203f017,
+        0xbd0009d0,
+/* 0x0147: mmctx_size */
+        0xbd00f804,
+/* 0x0149: nv_mmctx_size_loop */
+        0x00e89894,
+        0xb61a85b6,
+        0x84b60180,
+        0x0098bb02,
+        0xb804e0b6,
+        0x1bf404ef,
+        0x029fb9eb,
+/* 0x0166: mmctx_xfer */
+        0x94bd00f8,
+        0xf10199f0,
+        0xf00f0007,
+        0x09d00203,
+        0xf104bd00,
         0xb6071087,
         0x94bd0684,
         0xf405bbfd,
         0x8bd0090b,
         0x0099f000,
-/* 0x0180: mmctx_base_disabled */
+/* 0x018c: mmctx_base_disabled */
         0xf405eefd,
         0x8ed00c0b,
         0xc08fd080,
-/* 0x018f: mmctx_multi_disabled */
+/* 0x019b: mmctx_multi_disabled */
         0xb70199f0,
         0xc8010080,
         0xb4b600ab,
@@ -333,8 +334,8 @@ uint32_t nve0_grhub_code[] = {
         0xb601aec8,
         0xbefd11e4,
         0x008bd005,
-/* 0x01a8: mmctx_exec_loop */
-/* 0x01a8: mmctx_wait_free */
+/* 0x01b4: mmctx_exec_loop */
+/* 0x01b4: mmctx_wait_free */
         0xf0008ecf,
         0x0bf41fe4,
         0x00ce98fa,
@@ -343,76 +344,77 @@ uint32_t nve0_grhub_code[] = {
         0x04cdb804,
         0xc8e81bf4,
         0x1bf402ab,
-/* 0x01c9: mmctx_fini_wait */
+/* 0x01d5: mmctx_fini_wait */
         0x008bcf18,
         0xb01fb4f0,
         0x1bf410b4,
         0x02a7f0f7,
         0xf4c921f4,
-/* 0x01de: mmctx_stop */
+/* 0x01ea: mmctx_stop */
         0xabc81b0e,
         0x10b4b600,
         0xf00cb9f0,
         0x8bd012b9,
-/* 0x01ed: mmctx_stop_wait */
+/* 0x01f9: mmctx_stop_wait */
         0x008bcf00,
         0xf412bbc8,
-/* 0x01f6: mmctx_done */
-        0x87f1fa1b,
-        0x84b6085c,
-        0xf094bd06,
-        0x89d00199,
-/* 0x0207: strand_wait */
-        0xf900f800,
-        0x02a7f0a0,
-        0xfcc921f4,
-/* 0x0213: strand_pre */
-        0xf100f8a0,
-        0xf04afc87,
-        0x97f00283,
-        0x0089d00c,
-        0x020721f5,
-/* 0x0226: strand_post */
-        0x87f100f8,
-        0x83f04afc,
-        0x0d97f002,
-        0xf50089d0,
-        0xf8020721,
-/* 0x0239: strand_set */
-        0xfca7f100,
-        0x02a3f04f,
-        0x0500aba2,
-        0xd00fc7f0,
-        0xc7f000ac,
-        0x00bcd00b,
-        0x020721f5,
-        0xf000aed0,
-        0xbcd00ac7,
-        0x0721f500,
-/* 0x0263: strand_ctx_init */
-        0xf100f802,
-        0xb6083c87,
-        0x94bd0684,
-        0xd00399f0,
+/* 0x0202: mmctx_done */
+        0x94bdfa1b,
+        0xf10199f0,
+        0xf0170007,
+        0x09d00203,
+        0xf804bd00,
+/* 0x0215: strand_wait */
+        0xf0a0f900,
+        0x21f402a7,
+        0xf8a0fcc9,
+/* 0x0221: strand_pre */
+        0xfc87f100,
+        0x0283f04a,
+        0xd00c97f0,
         0x21f50089,
-        0xe7f00213,
-        0x3921f503,
+        0x00f80215,
+/* 0x0234: strand_post */
+        0x4afc87f1,
+        0xf00283f0,
+        0x89d00d97,
+        0x1521f500,
+/* 0x0247: strand_set */
+        0xf100f802,
+        0xf04ffca7,
+        0xaba202a3,
+        0xc7f00500,
+        0x00acd00f,
+        0xd00bc7f0,
+        0x21f500bc,
+        0xaed00215,
+        0x0ac7f000,
+        0xf500bcd0,
+        0xf8021521,
+/* 0x0271: strand_ctx_init */
+        0xf094bd00,
+        0x07f10399,
+        0x03f00f00,
+        0x0009d002,
+        0x21f504bd,
+        0xe7f00221,
+        0x4721f503,
         0xfca7f102,
         0x02a3f046,
         0x0400aba0,
         0xf040a0d0,
         0xbcd001c7,
-        0x0721f500,
+        0x1521f500,
         0x010c9202,
         0xf000acd0,
         0xbcd002c7,
-        0x0721f500,
-        0x2621f502,
+        0x1521f500,
+        0x3421f502,
         0x8087f102,
         0x0684b608,
         0xb70089cf,
         0x95220080,
-/* 0x02ba: ctx_init_strand_loop */
+/* 0x02ca: ctx_init_strand_loop */
         0x8ed008fe,
         0x408ed000,
         0xb6808acf,
@@ -421,73 +423,61 @@ uint32_t nve0_grhub_code[] = {
         0xb60480b6,
         0x1bf40192,
         0x08e4b6e8,
-        0xf1f2efbc,
-        0xb6085c87,
-        0x94bd0684,
-        0xd00399f0,
-        0x00f80089,
-/* 0x02ec: error */
-        0xe7f1e0f9,
-        0xe4b60814,
-        0x00efd006,
-        0x0c1ce7f1,
-        0xf006e4b6,
-        0xefd001f7,
-        0xf8e0fc00,
-/* 0x0309: init */
-        0xfe04bd00,
-        0x07fe0004,
-        0x0017f100,
-        0x0227f012,
-        0xf10012d0,
-        0xfe05b917,
-        0x17f10010,
-        0x10d00400,
-        0x0437f1c0,
-        0x0634b604,
-        0x200327f1,
-        0xf10032d0,
-        0xd0200427,
-        0x27f10132,
-        0x32d0200b,
-        0x0c27f102,
-        0x0732d020,
-        0x0c2427f1,
-        0xb90624b6,
-        0x23d00003,
+        0xbdf2efbc,
+        0x0399f094,
+        0x170007f1,
+        0xd00203f0,
+        0x04bd0009,
+/* 0x02fe: error */
+        0x07f100f8,
+        0x03f00500,
+        0x000fd002,
+        0xf7f004bd,
+        0x0007f101,
+        0x0303f007,
+        0xbd000fd0,
+/* 0x031b: init */
+        0xbd00f804,
+        0x0004fe04,
+        0xf10007fe,
+        0xf0120017,
+        0x12d00227,
+        0xb117f100,
+        0x0010fe05,
+        0x040017f1,
+        0xf1c010d0,
+        0xb6040437,
+        0x27f10634,
+        0x32d02003,
         0x0427f100,
-        0x0023f087,
-        0xb70012d0,
-        0xf0010012,
-        0x12d00427,
-        0x1031f400,
-        0x9604e7f1,
-        0xf440e3f0,
-        0xf1c76821,
-        0x01018090,
-        0x801ff4f0,
-        0x17f0000f,
-        0x041fbb01,
-        0xf10112b6,
-        0xb6040c27,
-        0x21d00624,
-        0x4021d000,
-        0x080027f1,
-        0xcf0624b6,
-        0xf7f00022,
-/* 0x03a9: init_find_chipset */
-        0x08f0b654,
-        0xb800f398,
-        0x0bf40432,
-        0x0034b00b,
-        0xf8f11bf4,
-/* 0x03bd: init_context */
-        0x0017f100,
-        0x02fe5801,
-        0xf003ff58,
-        0x0e8000e3,
-        0x150f8014,
-        0x013d21f5,
+        0x0132d020,
+        0x200b27f1,
+        0xf10232d0,
+        0xd0200c27,
+        0x27f10732,
+        0x24b60c24,
+        0x0003b906,
+        0xf10023d0,
+        0xf0870427,
+        0x12d00023,
+        0x0012b700,
+        0x0427f001,
+        0xf40012d0,
+        0xe7f11031,
+        0xe3f09604,
+        0x6821f440,
+        0x8090f1c7,
+        0xf4f00301,
+        0x020f801f,
+        0xbb0117f0,
+        0x12b6041f,
+        0x0c27f101,
+        0x0624b604,
+        0xd00021d0,
+        0x17f14021,
+        0x0e980100,
+        0x010f9800,
+        0x014721f5,
         0x070037f1,
         0x950634b6,
         0x34d00814,
@@ -498,196 +488,201 @@ uint32_t nve0_grhub_code[] = {
         0x0815b600,
         0xb60110b6,
         0x1fb90814,
-        0x6321f502,
+        0x7121f502,
         0x001fbb02,
-        0xf1000398,
+        0xf1020398,
         0xf0200047,
-/* 0x040e: init_gpc */
+/* 0x03f6: init_gpc */
         0x4ea05043,
         0x1fb90804,
         0x8d21f402,
-        0x08004ea0,
-        0xf4022fb9,
-        0x4ea08d21,
-        0xf4bd010c,
-        0xa08d21f4,
-        0xf401044e,
+        0x010c4ea0,
+        0x21f4f4bd,
+        0x044ea08d,
+        0x8d21f401,
+        0x01004ea0,
+        0xf402f7f0,
         0x4ea08d21,
-        0xf7f00100,
-        0x8d21f402,
-        0x08004ea0,
-/* 0x0440: init_gpc_wait */
-        0xc86821f4,
-        0x0bf41fff,
-        0x044ea0fa,
-        0x6821f408,
-        0xb7001fbb,
-        0xb6800040,
-        0x1bf40132,
-        0x0027f1b4,
-        0x0624b608,
-        0xb74021d0,
-        0xbd080020,
+/* 0x041e: init_gpc_wait */
+        0x21f40800,
+        0x1fffc868,
+        0xa0fa0bf4,
+        0xf408044e,
+        0x1fbb6821,
+        0x0040b700,
+        0x0132b680,
+        0xf1be1bf4,
+        0xf0010007,
+        0x01d00203,
+        0xbd04bd00,
         0x1f19f014,
-/* 0x0473: main */
-        0xf40021d0,
-        0x28f40031,
-        0x08d7f000,
-        0xf43921f4,
-        0xe4b1f401,
-        0x1bf54001,
-        0x87f100d1,
-        0x84b6083c,
-        0xf094bd06,
-        0x89d00499,
-        0x0017f100,
-        0x0614b60b,
-        0xcf4012cf,
-        0x13c80011,
-        0x7e0bf41f,
+        0x080007f1,
+        0xd00203f0,
+        0x04bd0001,
+/* 0x0458: main */
+        0xf40031f4,
+        0xd7f00028,
+        0x3921f410,
+        0xb1f401f4,
+        0xf54001e4,
+        0xbd00de1b,
+        0x0499f094,
+        0x0f0007f1,
+        0xd00203f0,
+        0x04bd0009,
+        0x0b0017f1,
+        0xcf0614b6,
+        0x11cf4012,
+        0x1f13c800,
+        0x00870bf5,
         0xf41f23c8,
-        0x20f95a0b,
-        0xf10212b9,
-        0xb6083c87,
-        0x94bd0684,
-        0xd00799f0,
-        0x32f40089,
-        0x0231f401,
-        0x07fb21f5,
-        0x085c87f1,
-        0xbd0684b6,
+        0x20f9620b,
+        0xbd0212b9,
         0x0799f094,
-        0xfc0089d0,
-        0x3c87f120,
-        0x0684b608,
-        0x99f094bd,
-        0x0089d006,
-        0xf50131f4,
-        0xf107fb21,
-        0xb6085c87,
-        0x94bd0684,
-        0xd00699f0,
-        0x0ef40089,
-/* 0x0509: chsw_prev_no_next */
+        0x0f0007f1,
+        0xd00203f0,
+        0x04bd0009,
+        0xf40132f4,
+        0x21f50231,
+        0x94bd0801,
+        0xf10799f0,
+        0xf0170007,
+        0x09d00203,
+        0xfc04bd00,
+        0xf094bd20,
+        0x07f10699,
+        0x03f00f00,
+        0x0009d002,
+        0x31f404bd,
+        0x0121f501,
+        0xf094bd08,
+        0x07f10699,
+        0x03f01700,
+        0x0009d002,
+        0x0ef404bd,
+/* 0x04f9: chsw_prev_no_next */
         0xb920f931,
         0x32f40212,
         0x0232f401,
-        0x07fb21f5,
+        0x080121f5,
         0x17f120fc,
         0x14b60b00,
         0x0012d006,
-/* 0x0527: chsw_no_prev */
+/* 0x0517: chsw_no_prev */
         0xc8130ef4,
         0x0bf41f23,
         0x0131f40d,
         0xf50232f4,
-/* 0x0537: chsw_done */
-        0xf107fb21,
+/* 0x0527: chsw_done */
+        0xf1080121,
         0xb60b0c17,
         0x27f00614,
         0x0012d001,
-        0x085c87f1,
-        0xbd0684b6,
-        0x0499f094,
-        0xf50089d0,
-/* 0x0557: main_not_ctx_switch */
-        0xb0ff200e,
-        0x1bf401e4,
-        0x02f2b90d,
-        0x078f21f5,
-/* 0x0567: main_not_ctx_chan */
-        0xb0420ef4,
-        0x1bf402e4,
-        0x3c87f12e,
-        0x0684b608,
         0x99f094bd,
-        0x0089d007,
+        0x0007f104,
+        0x0203f017,
+        0xbd0009d0,
+        0x130ef504,
+/* 0x0549: main_not_ctx_switch */
+        0x01e4b0ff,
+        0xb90d1bf4,
+        0x21f502f2,
+        0x0ef40795,
+/* 0x0559: main_not_ctx_chan */
+        0x02e4b046,
+        0xbd321bf4,
+        0x0799f094,
+        0x0f0007f1,
+        0xd00203f0,
+        0x04bd0009,
         0xf40132f4,
         0x21f50232,
-        0x87f107fb,
-        0x84b6085c,
-        0xf094bd06,
-        0x89d00799,
-        0x110ef400,
-/* 0x0598: main_not_ctx_save */
-        0xf010ef94,
-        0x21f501f5,
-        0x0ef502ec,
-/* 0x05a6: main_done */
-        0x17f1fed1,
-        0x14b60820,
-        0xf024bd06,
-        0x12d01f29,
-        0xbe0ef500,
-/* 0x05b9: ih */
+        0x94bd0801,
+        0xf10799f0,
+        0xf0170007,
+        0x09d00203,
+        0xf404bd00,
+/* 0x058e: main_not_ctx_save */
+        0xef94110e,
+        0x01f5f010,
+        0x02fe21f5,
+        0xfec00ef5,
+/* 0x059c: main_done */
+        0x29f024bd,
+        0x0007f11f,
+        0x0203f008,
+        0xbd0002d0,
+        0xab0ef504,
+/* 0x05b1: ih */
         0xfe80f9fe,
         0x80f90188,
         0xa0f990f9,
         0xd0f9b0f9,
         0xf0f9e0f9,
-        0xc4800acf,
-        0x0bf404ab,
-        0x00b7f11d,
-        0x08d7f019,
-        0xcf40becf,
-        0x21f400bf,
-        0x00b0b704,
-        0x01e7f004,
-/* 0x05ef: ih_no_fifo */
-        0xe400bed0,
-        0xf40100ab,
-        0xd7f00d0b,
-        0x01e7f108,
-        0x0421f440,
-/* 0x0600: ih_no_ctxsw */
-        0x0104b7f1,
-        0xabffb0bd,
-        0x0d0bf4b4,
-        0x0c1ca7f1,
-        0xd006a4b6,
-/* 0x0616: ih_no_other */
-        0x0ad000ab,
-        0xfcf0fc40,
-        0xfcd0fce0,
-        0xfca0fcb0,
-        0xfe80fc90,
-        0x80fc0088,
-        0xf80032f4,
-/* 0x0631: ctx_4170s */
-        0x70e7f101,
-        0x40e3f041,
-        0xf410f5f0,
-        0x00f88d21,
-/* 0x0640: ctx_4170w */
-        0x4170e7f1,
-        0xf440e3f0,
-        0xf4f06821,
-        0xf31bf410,
-/* 0x0652: ctx_redswitch */
+        0x0acf04bd,
+        0x04abc480,
+        0xf11d0bf4,
+        0xf01900b7,
+        0xbecf10d7,
+        0x00bfcf40,
+        0xb70421f4,
+        0xf00400b0,
+        0xbed001e7,
+/* 0x05e9: ih_no_fifo */
+        0x00abe400,
+        0x0d0bf401,
+        0xf110d7f0,
+        0xf44001e7,
+/* 0x05fa: ih_no_ctxsw */
+        0xb7f10421,
+        0xb0bd0104,
+        0xf4b4abff,
+        0xa7f10d0b,
+        0xa4b60c1c,
+        0x00abd006,
+/* 0x0610: ih_no_other */
+        0xfc400ad0,
+        0xfce0fcf0,
+        0xfcb0fcd0,
+        0xfc90fca0,
+        0x0088fe80,
+        0x32f480fc,
+/* 0x062b: ctx_4170s */
+        0xf101f800,
+        0xf04170e7,
+        0xf5f040e3,
+        0x8d21f410,
+/* 0x063a: ctx_4170w */
         0xe7f100f8,
-        0xe4b60614,
-        0x70f7f106,
-        0x00efd002,
-/* 0x0663: ctx_redswitch_delay */
-        0xb608f7f0,
-        0x1bf401f2,
-        0x70f7f1fd,
-        0x00efd007,
-/* 0x0672: ctx_86c */
-        0xe7f100f8,
-        0xe4b6086c,
-        0x00efd006,
-        0x8a14e7f1,
-        0xf440e3f0,
-        0xe7f18d21,
-        0xe3f0a86c,
-        0x8d21f441,
-/* 0x0692: ctx_load */
-        0x87f100f8,
-        0x84b6083c,
-        0xf094bd06,
-        0x89d00599,
-        0x0ca7f000,
+        0xe3f04170,
+        0x6821f440,
+        0xf410f4f0,
+        0x00f8f31b,
+/* 0x064c: ctx_redswitch */
+        0x0614e7f1,
+        0xf106e4b6,
+        0xd00270f7,
+        0xf7f000ef,
+/* 0x065d: ctx_redswitch_delay */
+        0x01f2b608,
+        0xf1fd1bf4,
+        0xd00770f7,
+        0x00f800ef,
+/* 0x066c: ctx_86c */
+        0x086ce7f1,
+        0xd006e4b6,
+        0xe7f100ef,
+        0xe3f08a14,
+        0x8d21f440,
+        0xa86ce7f1,
+        0xf441e3f0,
+        0x00f88d21,
+/* 0x068c: ctx_load */
+        0x99f094bd,
+        0x0007f105,
+        0x0203f00f,
+        0xbd0009d0,
+        0x0ca7f004,
         0xf1c921f4,
         0xb60a2417,
         0x10d00614,
@@ -697,162 +692,227 @@ uint32_t nve0_grhub_code[] = {
         0xb60a0c17,
         0x47f00614,
         0x0012d007,
-/* 0x06cb: ctx_chan_wait_0 */
+/* 0x06c7: ctx_chan_wait_0 */
         0xcf4014d0,
         0x44f04014,
         0xfa1bf41f,
         0xfe0032d0,
         0x2af0000b,
         0x0424b61f,
-        0xf10220b6,
-        0xb6083c87,
-        0x94bd0684,
-        0xd00899f0,
-        0x17f10089,
-        0x14b60a04,
-        0x0012d006,
-        0x0a2017f1,
-        0xf00614b6,
-        0x23f10227,
-        0x12d08000,
-        0x1017f000,
-        0x030027f1,
-        0xfa0223f0,
-        0x03f80512,
-        0x085c87f1,
-        0xbd0684b6,
+        0xbd0220b6,
         0x0899f094,
-        0x980089d0,
-        0x14b6c101,
-        0xc0029818,
+        0x0f0007f1,
+        0xd00203f0,
+        0x04bd0009,
+        0x0a0417f1,
+        0xd00614b6,
+        0x17f10012,
+        0x14b60a20,
+        0x0227f006,
+        0x800023f1,
+        0xf00012d0,
+        0x27f11017,
+        0x23f00200,
+        0x0512fa02,
+        0x94bd03f8,
+        0xf10899f0,
+        0xf0170007,
+        0x09d00203,
+        0x9804bd00,
+        0x14b68101,
+        0x80029818,
         0xfd0825b6,
         0x01800512,
-        0x3c87f116,
-        0x0684b608,
-        0x99f094bd,
-        0x0089d009,
-        0x0a0427f1,
-        0xd00624b6,
-        0x27f00021,
-        0x2017f101,
-        0x0614b60a,
-        0xf10012d0,
-        0xf0020017,
+        0xf094bd16,
+        0x07f10999,
+        0x03f00f00,
+        0x0009d002,
+        0x27f104bd,
+        0x24b60a04,
+        0x0021d006,
+        0xf10127f0,
+        0xb60a2017,
+        0x12d00614,
+        0x0017f100,
+        0x0613f001,
+        0xf80501fa,
+        0xf094bd03,
+        0x07f10999,
+        0x03f01700,
+        0x0009d002,
+        0x94bd04bd,
+        0xf10599f0,
+        0xf0170007,
+        0x09d00203,
+        0xf804bd00,
+/* 0x0795: ctx_chan */
+        0x8c21f500,
+        0x0ca7f006,
+        0xf1c921f4,
+        0xb60a1017,
+        0x27f00614,
+        0x0012d005,
+/* 0x07ac: ctx_chan_wait */
+        0xfd0012cf,
+        0x1bf40522,
+/* 0x07b7: ctx_mmio_exec */
+        0x9800f8fa,
+        0x27f14103,
+        0x24b60a04,
+        0x0023d006,
+/* 0x07c6: ctx_mmio_loop */
+        0x34c434bd,
+        0x0f1bf4ff,
+        0x020057f1,
+        0xfa0653f0,
+        0x03f80535,
+/* 0x07d8: ctx_mmio_pull */
+        0x98804e98,
+        0x21f4814f,
+        0x0830b68d,
+        0xf40112b6,
+/* 0x07ea: ctx_mmio_done */
+        0x0398df1b,
+        0x0023d016,
+        0xf1400080,
+        0xf0010017,
         0x01fa0613,
-        0xf103f805,
-        0xb6085c87,
-        0x94bd0684,
-        0xd00999f0,
-        0x87f10089,
-        0x84b6085c,
-        0xf094bd06,
-        0x89d00599,
-/* 0x078f: ctx_chan */
-        0xf500f800,
-        0xf0069221,
-        0x21f40ca7,
-        0x1017f1c9,
-        0x0614b60a,
-        0xd00527f0,
-/* 0x07a6: ctx_chan_wait */
-        0x12cf0012,
-        0x0522fd00,
-        0xf8fa1bf4,
-/* 0x07b1: ctx_mmio_exec */
-        0x81039800,
-        0x0a0427f1,
+        0xf803f806,
+/* 0x0801: ctx_xfer */
+        0x00f7f100,
+        0x06f4b60c,
+        0xd004e7f0,
+/* 0x080e: ctx_xfer_idle */
+        0xfecf80fe,
+        0x00e4f100,
+        0xf91bf420,
+        0xf40611f4,
+/* 0x081e: ctx_xfer_pre */
+        0xf7f00d02,
+        0x6c21f510,
+        0x1c11f406,
+/* 0x0828: ctx_xfer_pre_load */
+        0xf502f7f0,
+        0xf5062b21,
+        0xf5063a21,
+        0xbd064c21,
+        0x2b21f5f4,
+        0x8c21f506,
+/* 0x0841: ctx_xfer_exec */
+        0x16019806,
+        0x041427f1,
         0xd00624b6,
-        0x34bd0023,
-/* 0x07c0: ctx_mmio_loop */
-        0xf4ff34c4,
-        0x57f10f1b,
-        0x53f00300,
-        0x0535fa06,
-/* 0x07d2: ctx_mmio_pull */
-        0x4e9803f8,
-        0xc14f98c0,
+        0xe7f10020,
+        0xe3f0a500,
+        0x021fb941,
         0xb68d21f4,
-        0x12b60830,
-        0xdf1bf401,
-/* 0x07e4: ctx_mmio_done */
-        0xd0160398,
-        0x00800023,
-        0x0017f180,
-        0x0613f002,
-        0xf80601fa,
-/* 0x07fb: ctx_xfer */
-        0xf100f803,
-        0xb60c00f7,
-        0xe7f006f4,
-        0x80fed004,
-/* 0x0808: ctx_xfer_idle */
-        0xf100fecf,
-        0xf42000e4,
-        0x11f4f91b,
-        0x0d02f406,
-/* 0x0818: ctx_xfer_pre */
-        0xf510f7f0,
-        0xf4067221,
-/* 0x0822: ctx_xfer_pre_load */
-        0xf7f01c11,
-        0x3121f502,
-        0x4021f506,
-        0x5221f506,
-        0xf5f4bd06,
-        0xf5063121,
-/* 0x083b: ctx_xfer_exec */
-        0x98069221,
-        0x27f11601,
-        0x24b60414,
-        0x0020d006,
-        0xa500e7f1,
-        0xb941e3f0,
-        0x21f4021f,
-        0x04e0b68d,
-        0xf001fcf0,
-        0x24b6022c,
-        0x05f2fd01,
-        0xf18d21f4,
-        0xf04afc17,
-        0x27f00213,
-        0x0012d00c,
-        0x020721f5,
-        0x47fc27f1,
-        0xd00223f0,
-        0x2cf00020,
-        0x0320b601,
-        0xf00012d0,
-        0xa5f001ac,
-        0x00b7f006,
-        0x98140c98,
-        0xe7f0150d,
-        0x5c21f500,
-        0x08a7f001,
-        0x010321f5,
-        0x020721f5,
-        0xf02201f4,
-        0x21f40ca7,
-        0x1017f1c9,
-        0x0614b60a,
-        0xd00527f0,
-/* 0x08c2: ctx_xfer_post_save_wait */
-        0x12cf0012,
-        0x0522fd00,
-        0xf4fa1bf4,
-/* 0x08ce: ctx_xfer_post */
-        0xf7f02e02,
-        0x3121f502,
+        0xfcf004e0,
+        0x022cf001,
+        0xfd0124b6,
+        0x21f405f2,
+        0xfc17f18d,
+        0x0213f04a,
+        0xd00c27f0,
+        0x21f50012,
+        0x27f10215,
+        0x23f047fc,
+        0x0020d002,
+        0xb6012cf0,
+        0x12d00320,
+        0x01acf000,
+        0xf006a5f0,
+        0x0c9800b7,
+        0x010d9800,
+        0xf500e7f0,
+        0xf0016621,
+        0x21f508a7,
+        0x21f50109,
+        0x01f40215,
+        0x0ca7f022,
+        0xf1c921f4,
+        0xb60a1017,
+        0x27f00614,
+        0x0012d005,
+/* 0x08c8: ctx_xfer_post_save_wait */
+        0xfd0012cf,
+        0x1bf40522,
+        0x2e02f4fa,
+/* 0x08d4: ctx_xfer_post */
+        0xf502f7f0,
+        0xbd062b21,
+        0x6c21f5f4,
+        0x3421f506,
+        0x3a21f502,
         0xf5f4bd06,
-        0xf5067221,
-        0xf5022621,
-        0xbd064021,
-        0x3121f5f4,
-        0x1011f406,
-        0xfd800198,
-        0x0bf40511,
-        0xb121f507,
-/* 0x08f9: ctx_xfer_no_post_mmio */
-/* 0x08f9: ctx_xfer_done */
-        0x0000f807,
+        0xf4062b21,
+        0x01981011,
+        0x0511fd40,
+        0xf5070bf4,
+/* 0x08ff: ctx_xfer_no_post_mmio */
+/* 0x08ff: ctx_xfer_done */
+        0xf807b721,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
         0x00000000,
 };
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvf0.fuc b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvf0.fuc
new file mode 100644
index 000000000000..ec42ed29b50d
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvf0.fuc
@@ -0,0 +1,40 @@
+/*
+ * Copyright 2013 Red Hat Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Ben Skeggs <bskeggs@redhat.com>
+ */
+
+#define CHIPSET GK110
+#include "macros.fuc"
+
+.section #nvf0_grhub_data
+#define INCLUDE_DATA
+#include "com.fuc"
+#include "hub.fuc"
+#undef INCLUDE_DATA
+
+.section #nvf0_grhub_code
+#define INCLUDE_CODE
+bra #init
+#include "com.fuc"
+#include "hub.fuc"
+.align 256
+#undef INCLUDE_CODE
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvf0.fuc.h b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvf0.fuc.h
new file mode 100644
index 000000000000..438506d14749
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvf0.fuc.h
@@ -0,0 +1,918 @@
+uint32_t nvf0_grhub_data[] = {
+/* 0x0000: hub_mmio_list_head */
+        0x00000300,
+/* 0x0004: hub_mmio_list_tail */
+        0x00000304,
+/* 0x0008: gpc_count */
+        0x00000000,
+/* 0x000c: rop_count */
+        0x00000000,
+/* 0x0010: cmd_queue */
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+/* 0x0058: ctx_current */
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+/* 0x0100: chan_data */
+/* 0x0100: chan_mmio_count */
+        0x00000000,
+/* 0x0104: chan_mmio_address */
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+/* 0x0200: xfer_data */
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+/* 0x0300: hub_mmio_list_base */
+        0x0417e91c,
+};
+
+uint32_t nvf0_grhub_code[] = {
+        0x031b0ef5,
+/* 0x0004: queue_put */
+        0x9800d898,
+        0x86f001d9,
+        0x0489b808,
+        0xf00c1bf4,
+        0x21f502f7,
+        0x00f802fe,
+/* 0x001c: queue_put_next */
+        0xb60798c4,
+        0x8dbb0384,
+        0x0880b600,
+        0x80008e80,
+        0x90b6018f,
+        0x0f94f001,
+        0xf801d980,
+/* 0x0039: queue_get */
+        0x0131f400,
+        0x9800d898,
+        0x89b801d9,
+        0x210bf404,
+        0xb60789c4,
+        0x9dbb0394,
+        0x0890b600,
+        0x98009e98,
+        0x80b6019f,
+        0x0f84f001,
+        0xf400d880,
+/* 0x0066: queue_get_done */
+        0x00f80132,
+/* 0x0068: nv_rd32 */
+        0x0728b7f1,
+        0xb906b4b6,
+        0xc9f002ec,
+        0x00bcd01f,
+/* 0x0078: nv_rd32_wait */
+        0xc800bccf,
+        0x1bf41fcc,
+        0x06a7f0fa,
+        0x010921f5,
+        0xf840bfcf,
+/* 0x008d: nv_wr32 */
+        0x28b7f100,
+        0x06b4b607,
+        0xb980bfd0,
+        0xc9f002ec,
+        0x1ec9f01f,
+/* 0x00a3: nv_wr32_wait */
+        0xcf00bcd0,
+        0xccc800bc,
+        0xfa1bf41f,
+/* 0x00ae: watchdog_reset */
+        0x87f100f8,
+        0x84b60430,
+        0x1ff9f006,
+        0xf8008fd0,
+/* 0x00bd: watchdog_clear */
+        0x3087f100,
+        0x0684b604,
+        0xf80080d0,
+/* 0x00c9: wait_donez */
+        0xf094bd00,
+        0x07f10099,
+        0x03f03700,
+        0x0009d002,
+        0x07f104bd,
+        0x03f00600,
+        0x000ad002,
+/* 0x00e6: wait_donez_ne */
+        0x87f104bd,
+        0x83f00000,
+        0x0088cf01,
+        0xf4888aff,
+        0x94bdf31b,
+        0xf10099f0,
+        0xf0170007,
+        0x09d00203,
+        0xf804bd00,
+/* 0x0109: wait_doneo */
+        0xf094bd00,
+        0x07f10099,
+        0x03f03700,
+        0x0009d002,
+        0x87f104bd,
+        0x84b60818,
+        0x008ad006,
+/* 0x0124: wait_doneo_e */
+        0x040087f1,
+        0xcf0684b6,
+        0x8aff0088,
+        0xf30bf488,
+        0x99f094bd,
+        0x0007f100,
+        0x0203f017,
+        0xbd0009d0,
+/* 0x0147: mmctx_size */
+        0xbd00f804,
+/* 0x0149: nv_mmctx_size_loop */
+        0x00e89894,
+        0xb61a85b6,
+        0x84b60180,
+        0x0098bb02,
+        0xb804e0b6,
+        0x1bf404ef,
+        0x029fb9eb,
+/* 0x0166: mmctx_xfer */
+        0x94bd00f8,
+        0xf10199f0,
+        0xf0370007,
+        0x09d00203,
+        0xf104bd00,
+        0xb6071087,
+        0x94bd0684,
+        0xf405bbfd,
+        0x8bd0090b,
+        0x0099f000,
+/* 0x018c: mmctx_base_disabled */
+        0xf405eefd,
+        0x8ed00c0b,
+        0xc08fd080,
+/* 0x019b: mmctx_multi_disabled */
+        0xb70199f0,
+        0xc8010080,
+        0xb4b600ab,
+        0x0cb9f010,
+        0xb601aec8,
+        0xbefd11e4,
+        0x008bd005,
+/* 0x01b4: mmctx_exec_loop */
+/* 0x01b4: mmctx_wait_free */
+        0xf0008ecf,
+        0x0bf41fe4,
+        0x00ce98fa,
+        0xd005e9fd,
+        0xc0b6c08e,
+        0x04cdb804,
+        0xc8e81bf4,
+        0x1bf402ab,
+/* 0x01d5: mmctx_fini_wait */
+        0x008bcf18,
+        0xb01fb4f0,
+        0x1bf410b4,
+        0x02a7f0f7,
+        0xf4c921f4,
+/* 0x01ea: mmctx_stop */
+        0xabc81b0e,
+        0x10b4b600,
+        0xf00cb9f0,
+        0x8bd012b9,
+/* 0x01f9: mmctx_stop_wait */
+        0x008bcf00,
+        0xf412bbc8,
+/* 0x0202: mmctx_done */
+        0x94bdfa1b,
+        0xf10199f0,
+        0xf0170007,
+        0x09d00203,
+        0xf804bd00,
+/* 0x0215: strand_wait */
+        0xf0a0f900,
+        0x21f402a7,
+        0xf8a0fcc9,
+/* 0x0221: strand_pre */
+        0xfc87f100,
+        0x0283f04a,
+        0xd00c97f0,
+        0x21f50089,
+        0x00f80215,
+/* 0x0234: strand_post */
+        0x4afc87f1,
+        0xf00283f0,
+        0x89d00d97,
+        0x1521f500,
+/* 0x0247: strand_set */
+        0xf100f802,
+        0xf04ffca7,
+        0xaba202a3,
+        0xc7f00500,
+        0x00acd00f,
+        0xd00bc7f0,
+        0x21f500bc,
+        0xaed00215,
+        0x0ac7f000,
+        0xf500bcd0,
+        0xf8021521,
+/* 0x0271: strand_ctx_init */
+        0xf094bd00,
+        0x07f10399,
+        0x03f03700,
+        0x0009d002,
+        0x21f504bd,
+        0xe7f00221,
+        0x4721f503,
+        0xfca7f102,
+        0x02a3f046,
+        0x0400aba0,
+        0xf040a0d0,
+        0xbcd001c7,
+        0x1521f500,
+        0x010c9202,
+        0xf000acd0,
+        0xbcd002c7,
+        0x1521f500,
+        0x3421f502,
+        0x8087f102,
+        0x0684b608,
+        0xb70089cf,
+        0x95220080,
+/* 0x02ca: ctx_init_strand_loop */
+        0x8ed008fe,
+        0x408ed000,
+        0xb6808acf,
+        0xa0b606a5,
+        0x00eabb01,
+        0xb60480b6,
+        0x1bf40192,
+        0x08e4b6e8,
+        0xbdf2efbc,
+        0x0399f094,
+        0x170007f1,
+        0xd00203f0,
+        0x04bd0009,
+/* 0x02fe: error */
+        0x07f100f8,
+        0x03f00500,
+        0x000fd002,
+        0xf7f004bd,
+        0x0007f101,
+        0x0303f007,
+        0xbd000fd0,
+/* 0x031b: init */
+        0xbd00f804,
+        0x0004fe04,
+        0xf10007fe,
+        0xf0120017,
+        0x12d00227,
+        0xb117f100,
+        0x0010fe05,
+        0x040017f1,
+        0xf1c010d0,
+        0xb6040437,
+        0x27f10634,
+        0x32d02003,
+        0x0427f100,
+        0x0132d020,
+        0x200b27f1,
+        0xf10232d0,
+        0xd0200c27,
+        0x27f10732,
+        0x24b60c24,
+        0x0003b906,
+        0xf10023d0,
+        0xf0870427,
+        0x12d00023,
+        0x0012b700,
+        0x0427f001,
+        0xf40012d0,
+        0xe7f11031,
+        0xe3f09604,
+        0x6821f440,
+        0x8090f1c7,
+        0xf4f00301,
+        0x020f801f,
+        0xbb0117f0,
+        0x12b6041f,
+        0x0c27f101,
+        0x0624b604,
+        0xd00021d0,
+        0x17f14021,
+        0x0e980100,
+        0x010f9800,
+        0x014721f5,
+        0x070037f1,
+        0x950634b6,
+        0x34d00814,
+        0x4034d000,
+        0x130030b7,
+        0xb6001fbb,
+        0x3fd002f5,
+        0x0815b600,
+        0xb60110b6,
+        0x1fb90814,
+        0x7121f502,
+        0x001fbb02,
+        0xf1020398,
+        0xf0200047,
+/* 0x03f6: init_gpc */
+        0x4ea05043,
+        0x1fb90804,
+        0x8d21f402,
+        0x010c4ea0,
+        0x21f4f4bd,
+        0x044ea08d,
+        0x8d21f401,
+        0x01004ea0,
+        0xf402f7f0,
+        0x4ea08d21,
+/* 0x041e: init_gpc_wait */
+        0x21f40800,
+        0x1fffc868,
+        0xa0fa0bf4,
+        0xf408044e,
+        0x1fbb6821,
+        0x0040b700,
+        0x0132b680,
+        0xf1be1bf4,
+        0xf0010007,
+        0x01d00203,
+        0xbd04bd00,
+        0x1f19f014,
+        0x300007f1,
+        0xd00203f0,
+        0x04bd0001,
+/* 0x0458: main */
+        0xf40031f4,
+        0xd7f00028,
+        0x3921f410,
+        0xb1f401f4,
+        0xf54001e4,
+        0xbd00de1b,
+        0x0499f094,
+        0x370007f1,
+        0xd00203f0,
+        0x04bd0009,
+        0x0b0017f1,
+        0xcf0614b6,
+        0x11cf4012,
+        0x1f13c800,
+        0x00870bf5,
+        0xf41f23c8,
+        0x20f9620b,
+        0xbd0212b9,
+        0x0799f094,
+        0x370007f1,
+        0xd00203f0,
+        0x04bd0009,
+        0xf40132f4,
+        0x21f50231,
+        0x94bd0801,
+        0xf10799f0,
+        0xf0170007,
+        0x09d00203,
+        0xfc04bd00,
+        0xf094bd20,
+        0x07f10699,
+        0x03f03700,
+        0x0009d002,
+        0x31f404bd,
+        0x0121f501,
+        0xf094bd08,
+        0x07f10699,
+        0x03f01700,
+        0x0009d002,
+        0x0ef404bd,
+/* 0x04f9: chsw_prev_no_next */
+        0xb920f931,
+        0x32f40212,
+        0x0232f401,
+        0x080121f5,
+        0x17f120fc,
+        0x14b60b00,
+        0x0012d006,
+/* 0x0517: chsw_no_prev */
+        0xc8130ef4,
+        0x0bf41f23,
+        0x0131f40d,
+        0xf50232f4,
+/* 0x0527: chsw_done */
+        0xf1080121,
+        0xb60b0c17,
+        0x27f00614,
+        0x0012d001,
+        0x99f094bd,
+        0x0007f104,
+        0x0203f017,
+        0xbd0009d0,
+        0x130ef504,
+/* 0x0549: main_not_ctx_switch */
+        0x01e4b0ff,
+        0xb90d1bf4,
+        0x21f502f2,
+        0x0ef40795,
+/* 0x0559: main_not_ctx_chan */
+        0x02e4b046,
+        0xbd321bf4,
+        0x0799f094,
+        0x370007f1,
+        0xd00203f0,
+        0x04bd0009,
+        0xf40132f4,
+        0x21f50232,
+        0x94bd0801,
+        0xf10799f0,
+        0xf0170007,
+        0x09d00203,
+        0xf404bd00,
+/* 0x058e: main_not_ctx_save */
+        0xef94110e,
+        0x01f5f010,
+        0x02fe21f5,
+        0xfec00ef5,
+/* 0x059c: main_done */
+        0x29f024bd,
+        0x0007f11f,
+        0x0203f030,
+        0xbd0002d0,
+        0xab0ef504,
+/* 0x05b1: ih */
+        0xfe80f9fe,
+        0x80f90188,
+        0xa0f990f9,
+        0xd0f9b0f9,
+        0xf0f9e0f9,
+        0x0acf04bd,
+        0x04abc480,
+        0xf11d0bf4,
+        0xf01900b7,
+        0xbecf10d7,
+        0x00bfcf40,
+        0xb70421f4,
+        0xf00400b0,
+        0xbed001e7,
+/* 0x05e9: ih_no_fifo */
+        0x00abe400,
+        0x0d0bf401,
+        0xf110d7f0,
+        0xf44001e7,
+/* 0x05fa: ih_no_ctxsw */
+        0xb7f10421,
+        0xb0bd0104,
+        0xf4b4abff,
+        0xa7f10d0b,
+        0xa4b60c1c,
+        0x00abd006,
+/* 0x0610: ih_no_other */
+        0xfc400ad0,
+        0xfce0fcf0,
+        0xfcb0fcd0,
+        0xfc90fca0,
+        0x0088fe80,
+        0x32f480fc,
+/* 0x062b: ctx_4170s */
+        0xf101f800,
+        0xf04170e7,
+        0xf5f040e3,
+        0x8d21f410,
+/* 0x063a: ctx_4170w */
+        0xe7f100f8,
+        0xe3f04170,
+        0x6821f440,
+        0xf410f4f0,
+        0x00f8f31b,
+/* 0x064c: ctx_redswitch */
+        0x0614e7f1,
+        0xf106e4b6,
+        0xd00270f7,
+        0xf7f000ef,
+/* 0x065d: ctx_redswitch_delay */
+        0x01f2b608,
+        0xf1fd1bf4,
+        0xd00770f7,
+        0x00f800ef,
+/* 0x066c: ctx_86c */
+        0x086ce7f1,
+        0xd006e4b6,
+        0xe7f100ef,
+        0xe3f08a14,
+        0x8d21f440,
+        0xa86ce7f1,
+        0xf441e3f0,
+        0x00f88d21,
+/* 0x068c: ctx_load */
+        0x99f094bd,
+        0x0007f105,
+        0x0203f037,
+        0xbd0009d0,
+        0x0ca7f004,
+        0xf1c921f4,
+        0xb60a2417,
+        0x10d00614,
+        0x0037f100,
+        0x0634b60b,
+        0xf14032d0,
+        0xb60a0c17,
+        0x47f00614,
+        0x0012d007,
+/* 0x06c7: ctx_chan_wait_0 */
+        0xcf4014d0,
+        0x44f04014,
+        0xfa1bf41f,
+        0xfe0032d0,
+        0x2af0000b,
+        0x0424b61f,
+        0xbd0220b6,
+        0x0899f094,
+        0x370007f1,
+        0xd00203f0,
+        0x04bd0009,
+        0x0a0417f1,
+        0xd00614b6,
+        0x17f10012,
+        0x14b60a20,
+        0x0227f006,
+        0x800023f1,
+        0xf00012d0,
+        0x27f11017,
+        0x23f00200,
+        0x0512fa02,
+        0x94bd03f8,
+        0xf10899f0,
+        0xf0170007,
+        0x09d00203,
+        0x9804bd00,
+        0x14b68101,
+        0x80029818,
+        0xfd0825b6,
+        0x01800512,
+        0xf094bd16,
+        0x07f10999,
+        0x03f03700,
+        0x0009d002,
+        0x27f104bd,
+        0x24b60a04,
+        0x0021d006,
+        0xf10127f0,
+        0xb60a2017,
+        0x12d00614,
+        0x0017f100,
+        0x0613f001,
+        0xf80501fa,
+        0xf094bd03,
+        0x07f10999,
+        0x03f01700,
+        0x0009d002,
+        0x94bd04bd,
+        0xf10599f0,
+        0xf0170007,
+        0x09d00203,
+        0xf804bd00,
+/* 0x0795: ctx_chan */
+        0x8c21f500,
+        0x0ca7f006,
+        0xf1c921f4,
+        0xb60a1017,
+        0x27f00614,
+        0x0012d005,
+/* 0x07ac: ctx_chan_wait */
+        0xfd0012cf,
+        0x1bf40522,
+/* 0x07b7: ctx_mmio_exec */
+        0x9800f8fa,
+        0x27f14103,
+        0x24b60a04,
+        0x0023d006,
+/* 0x07c6: ctx_mmio_loop */
+        0x34c434bd,
+        0x0f1bf4ff,
+        0x020057f1,
+        0xfa0653f0,
+        0x03f80535,
+/* 0x07d8: ctx_mmio_pull */
+        0x98804e98,
+        0x21f4814f,
+        0x0830b68d,
+        0xf40112b6,
+/* 0x07ea: ctx_mmio_done */
+        0x0398df1b,
+        0x0023d016,
+        0xf1400080,
+        0xf0010017,
+        0x01fa0613,
+        0xf803f806,
+/* 0x0801: ctx_xfer */
+        0x00f7f100,
+        0x06f4b60c,
+        0xd004e7f0,
+/* 0x080e: ctx_xfer_idle */
+        0xfecf80fe,
+        0x00e4f100,
+        0xf91bf420,
+        0xf40611f4,
+/* 0x081e: ctx_xfer_pre */
+        0xf7f00d02,
+        0x6c21f510,
+        0x1c11f406,
+/* 0x0828: ctx_xfer_pre_load */
+        0xf502f7f0,
+        0xf5062b21,
+        0xf5063a21,
+        0xbd064c21,
+        0x2b21f5f4,
+        0x8c21f506,
+/* 0x0841: ctx_xfer_exec */
+        0x16019806,
+        0x041427f1,
+        0xd00624b6,
+        0xe7f10020,
+        0xe3f0a500,
+        0x021fb941,
+        0xb68d21f4,
+        0xfcf004e0,
+        0x022cf001,
+        0xfd0124b6,
+        0x21f405f2,
+        0xfc17f18d,
+        0x0213f04a,
+        0xd00c27f0,
+        0x21f50012,
+        0x27f10215,
+        0x23f047fc,
+        0x0020d002,
+        0xb6012cf0,
+        0x12d00320,
+        0x01acf000,
+        0xf006a5f0,
+        0x0c9800b7,
+        0x010d9800,
+        0xf500e7f0,
+        0xf0016621,
+        0x21f508a7,
+        0x21f50109,
+        0x01f40215,
+        0x0ca7f022,
+        0xf1c921f4,
+        0xb60a1017,
+        0x27f00614,
+        0x0012d005,
+/* 0x08c8: ctx_xfer_post_save_wait */
+        0xfd0012cf,
+        0x1bf40522,
+        0x2e02f4fa,
+/* 0x08d4: ctx_xfer_post */
+        0xf502f7f0,
+        0xbd062b21,
+        0x6c21f5f4,
+        0x3421f506,
+        0x3a21f502,
+        0xf5f4bd06,
+        0xf4062b21,
+        0x01981011,
+        0x0511fd40,
+        0xf5070bf4,
+/* 0x08ff: ctx_xfer_no_post_mmio */
+/* 0x08ff: ctx_xfer_done */
+        0xf807b721,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+        0x00000000,
+};
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/macros.fuc b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/macros.fuc
new file mode 100644
index 000000000000..33a5a82eccbd
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/macros.fuc
@@ -0,0 +1,89 @@
+/*
+ * Copyright 2013 Red Hat Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Ben Skeggs <bskeggs@redhat.com>
+ */
+
+#include "os.h"
+
+#define GF100 0xc0
+#define GF117 0xd7
+#define GK100 0xe0
+#define GK110 0xf0
+
+#define NV_PGRAPH_FECS_SIGNAL                                          0x409400
+#if CHIPSET < GK110
+#define NV_PGRAPH_FECS_CC_SCRATCH_VAL(n)                    ((n) * 4 + 0x409800)
+#define NV_PGRAPH_FECS_CC_SCRATCH_SET(n)                    ((n) * 4 + 0x409820)
+#define NV_PGRAPH_FECS_CC_SCRATCH_CLR(n)                    ((n) * 4 + 0x409840)
+#else
+#define NV_PGRAPH_FECS_CC_SCRATCH_VAL(n)                    ((n) * 4 + 0x409800)
+#define NV_PGRAPH_FECS_CC_SCRATCH_CLR(n)                    ((n) * 4 + 0x409840)
+#define NV_PGRAPH_FECS_CC_SCRATCH_SET(n)                    ((n) * 4 + 0x4098c0)
+#endif
+#define NV_PGRAPH_FECS_INTR_UP_SET                                     0x409c1c
+
+#if CHIPSET < GK110
+#define NV_PGRAPH_GPCX_GPCCS_CC_SCRATCH_VAL(n)              ((n) * 4 + 0x41a800)
+#define NV_PGRAPH_GPCX_GPCCS_CC_SCRATCH_SET(n)              ((n) * 4 + 0x41a820)
+#define NV_PGRAPH_GPCX_GPCCS_CC_SCRATCH_CLR(n)              ((n) * 4 + 0x41a840)
+#else
+#define NV_PGRAPH_GPCX_GPCCS_CC_SCRATCH_VAL(n)              ((n) * 4 + 0x41a800)
+#define NV_PGRAPH_GPCX_GPCCS_CC_SCRATCH_CLR(n)              ((n) * 4 + 0x41a840)
+#define NV_PGRAPH_GPCX_GPCCS_CC_SCRATCH_SET(n)              ((n) * 4 + 0x41a8c0)
+#endif
+
+#define mmctx_data(r,c) .b32 (((c - 1) << 26) | r)
+#define queue_init      .skip 72 // (2 * 4) + ((8 * 4) * 2)
+
+#define T_WAIT    0
+#define T_MMCTX   1
+#define T_STRWAIT 2
+#define T_STRINIT 3
+#define T_AUTO    4
+#define T_CHAN    5
+#define T_LOAD    6
+#define T_SAVE    7
+#define T_LCHAN   8
+#define T_LCTXH   9
+
+#define nv_mkmm(rv,r) /*
+*/      movw rv  ((r) & 0x0000fffc) /*
+*/      sethi rv ((r) & 0x00ff0000)
+#define nv_mkio(rv,r,i) /*
+*/      nv_mkmm(rv, (((r) & 0xffc) << 6) | ((i) << 2))
+
+#define nv_iord(rv,r,i) /*
+*/      nv_mkio(rv,r,i) /*
+*/      iord rv I[rv]
+#define nv_iowr(r,i,rv) /*
+*/      nv_mkio($r0,r,i) /*
+*/      iowr I[$r0] rv /*
+*/      clear b32 $r0
+
+#define trace_set(bit) /*
+*/      clear b32 $r9 /*
+*/      bset $r9 bit /*
+*/      nv_iowr(NV_PGRAPH_FECS_CC_SCRATCH_SET(7), 0, $r9)
+#define trace_clr(bit) /*
+*/      clear b32 $r9 /*
+*/      bset $r9 bit /*
+*/      nv_iowr(NV_PGRAPH_FECS_CC_SCRATCH_CLR(7), 0, $r9)
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/nve0.fuc b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/nve0.fuc
deleted file mode 100644
index f16a5d53319d..000000000000
--- a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/nve0.fuc
+++ /dev/null
@@ -1,400 +0,0 @@
-/* fuc microcode util functions for nve0 PGRAPH
- *
- * Copyright 2011 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-
-define(`mmctx_data', `.b32 eval((($2 - 1) << 26) | $1)')
-define(`queue_init', `.skip eval((2 * 4) + ((8 * 4) * 2))')
-
-ifdef(`include_code', `
-// Error codes
-define(`E_BAD_COMMAND', 0x01)
-define(`E_CMD_OVERFLOW', 0x02)
-
-// Util macros to help with debugging ucode hangs etc
-define(`T_WAIT', 0)
-define(`T_MMCTX', 1)
-define(`T_STRWAIT', 2)
-define(`T_STRINIT', 3)
-define(`T_AUTO', 4)
-define(`T_CHAN', 5)
-define(`T_LOAD', 6)
-define(`T_SAVE', 7)
-define(`T_LCHAN', 8)
-define(`T_LCTXH', 9)
-
-define(`trace_set', `
-        mov $r8 0x83c
-        shl b32 $r8 6
-        clear b32 $r9
-        bset $r9 $1
-        iowr I[$r8 + 0x000] $r9         // CC_SCRATCH[7]
-')
-
-define(`trace_clr', `
-        mov $r8 0x85c
-        shl b32 $r8 6
-        clear b32 $r9
-        bset $r9 $1
-        iowr I[$r8 + 0x000] $r9         // CC_SCRATCH[7]
-')
-
-// queue_put - add request to queue
-//
-// In : $r13 queue pointer
-//      $r14 command
-//      $r15 data
-//
-queue_put:
-        // make sure we have space..
-        ld b32 $r8 D[$r13 + 0x0]        // GET
-        ld b32 $r9 D[$r13 + 0x4]        // PUT
-        xor $r8 8
-        cmpu b32 $r8 $r9
-        bra ne #queue_put_next
-                mov $r15 E_CMD_OVERFLOW
-                call #error
-                ret
-
-        // store cmd/data on queue
-        queue_put_next:
-        and $r8 $r9 7
-        shl b32 $r8 3
-        add b32 $r8 $r13
-        add b32 $r8 8
-        st b32 D[$r8 + 0x0] $r14
-        st b32 D[$r8 + 0x4] $r15
-
-        // update PUT
-        add b32 $r9 1
-        and $r9 0xf
-        st b32 D[$r13 + 0x4] $r9
-        ret
-
-// queue_get - fetch request from queue
-//
-// In : $r13 queue pointer
-//
-// Out: $p1  clear on success (data available)
-//      $r14 command
-//      $r15 data
-//
-queue_get:
-        bset $flags $p1
-        ld b32 $r8 D[$r13 + 0x0]        // GET
-        ld b32 $r9 D[$r13 + 0x4]        // PUT
-        cmpu b32 $r8 $r9
-        bra e #queue_get_done
-                // fetch first cmd/data pair
-                and $r9 $r8 7
-                shl b32 $r9 3
-                add b32 $r9 $r13
-                add b32 $r9 8
-                ld b32 $r14 D[$r9 + 0x0]
-                ld b32 $r15 D[$r9 + 0x4]
-
-                // update GET
-                add b32 $r8 1
-                and $r8 0xf
-                st b32 D[$r13 + 0x0] $r8
-                bclr $flags $p1
-queue_get_done:
-        ret
-
-// nv_rd32 - read 32-bit value from nv register
-//
-// In : $r14 register
-// Out: $r15 value
-//
-nv_rd32:
-        mov $r11 0x728
-        shl b32 $r11 6
-        mov b32 $r12 $r14
-        bset $r12 31                    // MMIO_CTRL_PENDING
-        iowr I[$r11 + 0x000] $r12       // MMIO_CTRL
-        nv_rd32_wait:
-                iord $r12 I[$r11 + 0x000]
-                xbit $r12 $r12 31
-                bra ne #nv_rd32_wait
-        mov $r10 6                      // DONE_MMIO_RD
-        call #wait_doneo
-        iord $r15 I[$r11 + 0x100]       // MMIO_RDVAL
-        ret
-
-// nv_wr32 - write 32-bit value to nv register
-//
-// In : $r14 register
-//      $r15 value
-//
-nv_wr32:
-        mov $r11 0x728
-        shl b32 $r11 6
-        iowr I[$r11 + 0x200] $r15       // MMIO_WRVAL
-        mov b32 $r12 $r14
-        bset $r12 31                    // MMIO_CTRL_PENDING
-        bset $r12 30                    // MMIO_CTRL_WRITE
-        iowr I[$r11 + 0x000] $r12       // MMIO_CTRL
-        nv_wr32_wait:
-                iord $r12 I[$r11 + 0x000]
-                xbit $r12 $r12 31
-                bra ne #nv_wr32_wait
-        ret
-
-// (re)set watchdog timer
-//
-// In : $r15 timeout
-//
-watchdog_reset:
-        mov $r8 0x430
-        shl b32 $r8 6
-        bset $r15 31
-        iowr I[$r8 + 0x000] $r15
-        ret
-
-// clear watchdog timer
-watchdog_clear:
-        mov $r8 0x430
-        shl b32 $r8 6
-        iowr I[$r8 + 0x000] $r0
-        ret
-
-// wait_done{z,o} - wait on FUC_DONE bit to become clear/set
-//
-// In : $r10 bit to wait on
-//
-define(`wait_done', `
-$1:
-        trace_set(T_WAIT);
-        mov $r8 0x818
-        shl b32 $r8 6
-        iowr I[$r8 + 0x000] $r10        // CC_SCRATCH[6] = wait bit
-        wait_done_$1:
-                mov $r8 0x400
-                shl b32 $r8 6
-                iord $r8 I[$r8 + 0x000] // DONE
-                xbit $r8 $r8 $r10
-                bra $2 #wait_done_$1
-        trace_clr(T_WAIT)
-        ret
-')
-wait_done(wait_donez, ne)
-wait_done(wait_doneo, e)
-
-// mmctx_size - determine size of a mmio list transfer
-//
-// In : $r14 mmio list head
-//      $r15 mmio list tail
-// Out: $r15 transfer size (in bytes)
-//
-mmctx_size:
-        clear b32 $r9
-        nv_mmctx_size_loop:
-                ld b32 $r8 D[$r14]
-                shr b32 $r8 26
-                add b32 $r8 1
-                shl b32 $r8 2
-                add b32 $r9 $r8
-                add b32 $r14 4
-                cmpu b32 $r14 $r15
-                bra ne #nv_mmctx_size_loop
-        mov b32 $r15 $r9
-        ret
-
-// mmctx_xfer - execute a list of mmio transfers
-//
-// In : $r10 flags
-//              bit 0: direction (0 = save, 1 = load)
-//              bit 1: set if first transfer
-//              bit 2: set if last transfer
-//      $r11 base
-//      $r12 mmio list head
-//      $r13 mmio list tail
-//      $r14 multi_stride
-//      $r15 multi_mask
-//
-mmctx_xfer:
-        trace_set(T_MMCTX)
-        mov $r8 0x710
-        shl b32 $r8 6
-        clear b32 $r9
-        or $r11 $r11
-        bra e #mmctx_base_disabled
-                iowr I[$r8 + 0x000] $r11        // MMCTX_BASE
-                bset $r9 0                      // BASE_EN
-        mmctx_base_disabled:
-        or $r14 $r14
-        bra e #mmctx_multi_disabled
-                iowr I[$r8 + 0x200] $r14        // MMCTX_MULTI_STRIDE
-                iowr I[$r8 + 0x300] $r15        // MMCTX_MULTI_MASK
-                bset $r9 1                      // MULTI_EN
-        mmctx_multi_disabled:
-        add b32 $r8 0x100
-
-        xbit $r11 $r10 0
-        shl b32 $r11 16                 // DIR
-        bset $r11 12                    // QLIMIT = 0x10
-        xbit $r14 $r10 1
-        shl b32 $r14 17
-        or $r11 $r14                    // START_TRIGGER
-        iowr I[$r8 + 0x000] $r11        // MMCTX_CTRL
-
-        // loop over the mmio list, and send requests to the hw
-        mmctx_exec_loop:
-                // wait for space in mmctx queue
-                mmctx_wait_free:
-                        iord $r14 I[$r8 + 0x000] // MMCTX_CTRL
-                        and $r14 0x1f
-                        bra e #mmctx_wait_free
-
-                // queue up an entry
-                ld b32 $r14 D[$r12]
-                or $r14 $r9
-                iowr I[$r8 + 0x300] $r14
-                add b32 $r12 4
-                cmpu b32 $r12 $r13
-                bra ne #mmctx_exec_loop
-
-        xbit $r11 $r10 2
-        bra ne #mmctx_stop
-                // wait for queue to empty
-                mmctx_fini_wait:
-                        iord $r11 I[$r8 + 0x000]        // MMCTX_CTRL
-                        and $r11 0x1f
-                        cmpu b32 $r11 0x10
-                        bra ne #mmctx_fini_wait
-                mov $r10 2                              // DONE_MMCTX
-                call #wait_donez
-                bra #mmctx_done
-        mmctx_stop:
-                xbit $r11 $r10 0
-                shl b32 $r11 16                 // DIR
-                bset $r11 12                    // QLIMIT = 0x10
-                bset $r11 18                    // STOP_TRIGGER
-                iowr I[$r8 + 0x000] $r11        // MMCTX_CTRL
-                mmctx_stop_wait:
-                        // wait for STOP_TRIGGER to clear
-                        iord $r11 I[$r8 + 0x000] // MMCTX_CTRL
-                        xbit $r11 $r11 18
-                        bra ne #mmctx_stop_wait
-        mmctx_done:
-        trace_clr(T_MMCTX)
-        ret
-
-// Wait for DONE_STRAND
-//
-strand_wait:
-        push $r10
-        mov $r10 2
-        call #wait_donez
-        pop $r10
-        ret
-
-// unknown - call before issuing strand commands
-//
-strand_pre:
-        mov $r8 0x4afc
-        sethi $r8 0x20000
-        mov $r9 0xc
-        iowr I[$r8] $r9
-        call #strand_wait
-        ret
-
-// unknown - call after issuing strand commands
-//
-strand_post:
-        mov $r8 0x4afc
-        sethi $r8 0x20000
-        mov $r9 0xd
-        iowr I[$r8] $r9
-        call #strand_wait
-        ret
-
-// Selects strand set?!
-//
-// In: $r14 id
-//
-strand_set:
-        mov $r10 0x4ffc
-        sethi $r10 0x20000
-        sub b32 $r11 $r10 0x500
-        mov $r12 0xf
-        iowr I[$r10 + 0x000] $r12               // 0x93c = 0xf
-        mov $r12 0xb
-        iowr I[$r11 + 0x000] $r12               // 0x928 = 0xb
-        call #strand_wait
-        iowr I[$r10 + 0x000] $r14               // 0x93c = <id>
-        mov $r12 0xa
-        iowr I[$r11 + 0x000] $r12               // 0x928 = 0xa
-        call #strand_wait
-        ret
-
-// Initialise strand context data
-//
-// In : $r15 context base
-// Out: $r15 context size (in bytes)
-//
-// Strandset(?) 3 hardcoded currently
-//
-strand_ctx_init:
-        trace_set(T_STRINIT)
-        call #strand_pre
-        mov $r14 3
-        call #strand_set
-        mov $r10 0x46fc
-        sethi $r10 0x20000
-        add b32 $r11 $r10 0x400
-        iowr I[$r10 + 0x100] $r0        // STRAND_FIRST_GENE = 0
-        mov $r12 1
-        iowr I[$r11 + 0x000] $r12       // STRAND_CMD = LATCH_FIRST_GENE
-        call #strand_wait
-        sub b32 $r12 $r0 1
-        iowr I[$r10 + 0x000] $r12       // STRAND_GENE_CNT = 0xffffffff
-        mov $r12 2
-        iowr I[$r11 + 0x000] $r12       // STRAND_CMD = LATCH_GENE_CNT
-        call #strand_wait
-        call #strand_post
-
-        // read the size of each strand, poke the context offset of
-        // each into STRAND_{SAVE,LOAD}_SWBASE now, no need to worry
-        // about it later then.
-        mov $r8 0x880
-        shl b32 $r8 6
-        iord $r9 I[$r8 + 0x000]         // STRANDS
-        add b32 $r8 0x2200
-        shr b32 $r14 $r15 8
-        ctx_init_strand_loop:
-                iowr I[$r8 + 0x000] $r14        // STRAND_SAVE_SWBASE
-                iowr I[$r8 + 0x100] $r14        // STRAND_LOAD_SWBASE
-                iord $r10 I[$r8 + 0x200]        // STRAND_SIZE
-                shr b32 $r10 6
-                add b32 $r10 1
-                add b32 $r14 $r10
-                add b32 $r8 4
-                sub b32 $r9 1
-                bra ne #ctx_init_strand_loop
-
-        shl b32 $r14 8
-        sub b32 $r15 $r14 $r15
-        trace_clr(T_STRINIT)
-        ret
-')
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/os.h b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/os.h
new file mode 100644
index 000000000000..fd1d380de094
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/os.h
@@ -0,0 +1,7 @@
+#ifndef __NVKM_GRAPH_OS_H__
+#define __NVKM_GRAPH_OS_H__
+
+#define E_BAD_COMMAND  0x00000001
+#define E_CMD_OVERFLOW 0x00000002
+
+#endif
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/nv50.c b/drivers/gpu/drm/nouveau/core/engine/graph/nv50.c
index 1ac36110ca19..03de5175dd9f 100644
--- a/drivers/gpu/drm/nouveau/core/engine/graph/nv50.c
+++ b/drivers/gpu/drm/nouveau/core/engine/graph/nv50.c
@@ -186,13 +186,6 @@ nv50_graph_cclass = {
  * PGRAPH engine/subdev functions
  ******************************************************************************/
 
-static int
-nv50_graph_tlb_flush(struct nouveau_engine *engine)
-{
-        nv50_vm_flush_engine(&engine->base, 0x00);
-        return 0;
-}
-
 static const struct nouveau_bitfield nv50_pgraph_status[] = {
         { 0x00000001, "BUSY" }, /* set when any bit is set */
         { 0x00000002, "DISPATCH" },
@@ -302,8 +295,10 @@ nv84_graph_tlb_flush(struct nouveau_engine *engine)
                                 nv_rd32(priv, 0x400388));
         }
 
-        nv50_vm_flush_engine(&engine->base, 0x00);
 
+        nv_wr32(priv, 0x100c80, 0x00000001);
+        if (!nv_wait(priv, 0x100c80, 0x00000001, 0x00000000))
+                nv_error(priv, "vm flush timeout\n");
         nv_mask(priv, 0x400500, 0x00000001, 0x00000001);
         spin_unlock_irqrestore(&priv->lock, flags);
         return timeout ? -EBUSY : 0;
@@ -857,10 +852,9 @@ nv50_graph_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
 
         };
 
-        if (nv_device(priv)->chipset == 0x50 ||
-            nv_device(priv)->chipset == 0xac)
-                nv_engine(priv)->tlb_flush = nv50_graph_tlb_flush;
-        else
+        /* unfortunate hw bug workaround... */
+        if (nv_device(priv)->chipset != 0x50 &&
+            nv_device(priv)->chipset != 0xac)
                 nv_engine(priv)->tlb_flush = nv84_graph_tlb_flush;
 
         spin_lock_init(&priv->lock);
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/nvc0.c b/drivers/gpu/drm/nouveau/core/engine/graph/nvc0.c
index f9b9d82c287f..3f4f35cc3848 100644
--- a/drivers/gpu/drm/nouveau/core/engine/graph/nvc0.c
+++ b/drivers/gpu/drm/nouveau/core/engine/graph/nvc0.c
@@ -23,14 +23,12 @@
  */
 
 #include "nvc0.h"
-#include "fuc/hubnvc0.fuc.h"
-#include "fuc/gpcnvc0.fuc.h"
 
 /*******************************************************************************
  * Graphics object classes
  ******************************************************************************/
 
-static struct nouveau_oclass
+struct nouveau_oclass
 nvc0_graph_sclass[] = {
         { 0x902d, &nouveau_object_ofuncs },
         { 0x9039, &nouveau_object_ofuncs },
@@ -39,40 +37,6 @@ nvc0_graph_sclass[] = {
         {}
 };
 
-static struct nouveau_oclass
-nvc1_graph_sclass[] = {
-        { 0x902d, &nouveau_object_ofuncs },
-        { 0x9039, &nouveau_object_ofuncs },
-        { 0x9097, &nouveau_object_ofuncs },
-        { 0x90c0, &nouveau_object_ofuncs },
-        { 0x9197, &nouveau_object_ofuncs },
-        {}
-};
-
-static struct nouveau_oclass
-nvc8_graph_sclass[] = {
-        { 0x902d, &nouveau_object_ofuncs },
-        { 0x9039, &nouveau_object_ofuncs },
-        { 0x9097, &nouveau_object_ofuncs },
-        { 0x90c0, &nouveau_object_ofuncs },
-        { 0x9197, &nouveau_object_ofuncs },
-        { 0x9297, &nouveau_object_ofuncs },
-        {}
-};
-
-u64
-nvc0_graph_units(struct nouveau_graph *graph)
-{
-        struct nvc0_graph_priv *priv = (void *)graph;
-        u64 cfg;
-
-        cfg  = (u32)priv->gpc_nr;
-        cfg |= (u32)priv->tpc_total << 8;
-        cfg |= (u64)priv->rop_nr << 32;
-
-        return cfg;
-}
-
 /*******************************************************************************
  * PGRAPH context
  ******************************************************************************/
@@ -181,60 +145,308 @@ nvc0_graph_context_dtor(struct nouveau_object *object)
         nouveau_graph_context_destroy(&chan->base);
 }
 
-static struct nouveau_oclass
-nvc0_graph_cclass = {
-        .ofuncs = &(struct nouveau_ofuncs) {
-                .ctor = nvc0_graph_context_ctor,
-                .dtor = nvc0_graph_context_dtor,
-                .init = _nouveau_graph_context_init,
-                .fini = _nouveau_graph_context_fini,
-                .rd32 = _nouveau_graph_context_rd32,
-                .wr32 = _nouveau_graph_context_wr32,
-        },
-};
-
 /*******************************************************************************
  * PGRAPH engine/subdev functions
  ******************************************************************************/
 
-static void
-nvc0_graph_ctxctl_debug_unit(struct nvc0_graph_priv *priv, u32 base)
+struct nvc0_graph_init
+nvc0_graph_init_regs[] = {
+        { 0x400080,   1, 0x04, 0x003083c2 },
+        { 0x400088,   1, 0x04, 0x00006fe7 },
+        { 0x40008c,   1, 0x04, 0x00000000 },
+        { 0x400090,   1, 0x04, 0x00000030 },
+        { 0x40013c,   1, 0x04, 0x013901f7 },
+        { 0x400140,   1, 0x04, 0x00000100 },
+        { 0x400144,   1, 0x04, 0x00000000 },
+        { 0x400148,   1, 0x04, 0x00000110 },
+        { 0x400138,   1, 0x04, 0x00000000 },
+        { 0x400130,   2, 0x04, 0x00000000 },
+        { 0x400124,   1, 0x04, 0x00000002 },
+        {}
+};
+
+struct nvc0_graph_init
+nvc0_graph_init_unk40xx[] = {
+        { 0x40415c,   1, 0x04, 0x00000000 },
+        { 0x404170,   1, 0x04, 0x00000000 },
+        {}
+};
+
+struct nvc0_graph_init
+nvc0_graph_init_unk44xx[] = {
+        { 0x404488,   2, 0x04, 0x00000000 },
+        {}
+};
+
+struct nvc0_graph_init
+nvc0_graph_init_unk78xx[] = {
+        { 0x407808,   1, 0x04, 0x00000000 },
+        {}
+};
+
+struct nvc0_graph_init
+nvc0_graph_init_unk60xx[] = {
+        { 0x406024,   1, 0x04, 0x00000000 },
+        {}
+};
+
+struct nvc0_graph_init
+nvc0_graph_init_unk58xx[] = {
+        { 0x405844,   1, 0x04, 0x00ffffff },
+        { 0x405850,   1, 0x04, 0x00000000 },
+        { 0x405908,   1, 0x04, 0x00000000 },
+        {}
+};
+
+struct nvc0_graph_init
+nvc0_graph_init_unk80xx[] = {
+        { 0x40803c,   1, 0x04, 0x00000000 },
+        {}
+};
+
+struct nvc0_graph_init
+nvc0_graph_init_gpc[] = {
+        { 0x4184a0,   1, 0x04, 0x00000000 },
+        { 0x418604,   1, 0x04, 0x00000000 },
+        { 0x418680,   1, 0x04, 0x00000000 },
+        { 0x418714,   1, 0x04, 0x80000000 },
+        { 0x418384,   1, 0x04, 0x00000000 },
+        { 0x418814,   3, 0x04, 0x00000000 },
+        { 0x418b04,   1, 0x04, 0x00000000 },
+        { 0x4188c8,   1, 0x04, 0x80000000 },
+        { 0x4188cc,   1, 0x04, 0x00000000 },
+        { 0x4188d0,   1, 0x04, 0x00010000 },
+        { 0x4188d4,   1, 0x04, 0x00000001 },
+        { 0x418910,   1, 0x04, 0x00010001 },
+        { 0x418914,   1, 0x04, 0x00000301 },
+        { 0x418918,   1, 0x04, 0x00800000 },
+        { 0x418980,   1, 0x04, 0x77777770 },
+        { 0x418984,   3, 0x04, 0x77777777 },
+        { 0x418c04,   1, 0x04, 0x00000000 },
+        { 0x418c88,   1, 0x04, 0x00000000 },
+        { 0x418d00,   1, 0x04, 0x00000000 },
+        { 0x418f08,   1, 0x04, 0x00000000 },
+        { 0x418e00,   1, 0x04, 0x00000050 },
+        { 0x418e08,   1, 0x04, 0x00000000 },
+        { 0x41900c,   1, 0x04, 0x00000000 },
+        { 0x419018,   1, 0x04, 0x00000000 },
+        {}
+};
+
+static struct nvc0_graph_init
+nvc0_graph_init_tpc[] = {
+        { 0x419d08,   2, 0x04, 0x00000000 },
+        { 0x419d10,   1, 0x04, 0x00000014 },
+        { 0x419ab0,   1, 0x04, 0x00000000 },
+        { 0x419ab8,   1, 0x04, 0x000000e7 },
+        { 0x419abc,   2, 0x04, 0x00000000 },
+        { 0x41980c,   3, 0x04, 0x00000000 },
+        { 0x419844,   1, 0x04, 0x00000000 },
+        { 0x41984c,   1, 0x04, 0x00005bc5 },
+        { 0x419850,   4, 0x04, 0x00000000 },
+        { 0x419c98,   1, 0x04, 0x00000000 },
+        { 0x419ca8,   1, 0x04, 0x80000000 },
+        { 0x419cb4,   1, 0x04, 0x00000000 },
+        { 0x419cb8,   1, 0x04, 0x00008bf4 },
+        { 0x419cbc,   1, 0x04, 0x28137606 },
+        { 0x419cc0,   2, 0x04, 0x00000000 },
+        { 0x419bd4,   1, 0x04, 0x00800000 },
+        { 0x419bdc,   1, 0x04, 0x00000000 },
+        { 0x419d2c,   1, 0x04, 0x00000000 },
+        { 0x419c0c,   1, 0x04, 0x00000000 },
+        { 0x419e00,   1, 0x04, 0x00000000 },
+        { 0x419ea0,   1, 0x04, 0x00000000 },
+        { 0x419ea4,   1, 0x04, 0x00000100 },
+        { 0x419ea8,   1, 0x04, 0x00001100 },
+        { 0x419eac,   1, 0x04, 0x11100702 },
+        { 0x419eb0,   1, 0x04, 0x00000003 },
+        { 0x419eb4,   4, 0x04, 0x00000000 },
+        { 0x419ec8,   1, 0x04, 0x06060618 },
+        { 0x419ed0,   1, 0x04, 0x0eff0e38 },
+        { 0x419ed4,   1, 0x04, 0x011104f1 },
+        { 0x419edc,   1, 0x04, 0x00000000 },
+        { 0x419f00,   1, 0x04, 0x00000000 },
+        { 0x419f2c,   1, 0x04, 0x00000000 },
+        {}
+};
+
+struct nvc0_graph_init
+nvc0_graph_init_unk88xx[] = {
+        { 0x40880c,   1, 0x04, 0x00000000 },
+        { 0x408910,   9, 0x04, 0x00000000 },
+        { 0x408950,   1, 0x04, 0x00000000 },
+        { 0x408954,   1, 0x04, 0x0000ffff },
+        { 0x408984,   1, 0x04, 0x00000000 },
+        { 0x408988,   1, 0x04, 0x08040201 },
+        { 0x40898c,   1, 0x04, 0x80402010 },
+        {}
+};
+
+struct nvc0_graph_init
+nvc0_graph_tpc_0[] = {
+        { 0x50405c,   1, 0x04, 0x00000001 },
+        {}
+};
+
+void
+nvc0_graph_mmio(struct nvc0_graph_priv *priv, struct nvc0_graph_init *init)
 {
-        nv_error(priv, "%06x - done 0x%08x\n", base,
-                 nv_rd32(priv, base + 0x400));
-        nv_error(priv, "%06x - stat 0x%08x 0x%08x 0x%08x 0x%08x\n", base,
-                 nv_rd32(priv, base + 0x800), nv_rd32(priv, base + 0x804),
-                 nv_rd32(priv, base + 0x808), nv_rd32(priv, base + 0x80c));
-        nv_error(priv, "%06x - stat 0x%08x 0x%08x 0x%08x 0x%08x\n", base,
-                 nv_rd32(priv, base + 0x810), nv_rd32(priv, base + 0x814),
-                 nv_rd32(priv, base + 0x818), nv_rd32(priv, base + 0x81c));
+        for (; init && init->count; init++) {
+                u32 addr = init->addr, i;
+                for (i = 0; i < init->count; i++) {
+                        nv_wr32(priv, addr, init->data);
+                        addr += init->pitch;
+                }
+        }
 }
 
 void
-nvc0_graph_ctxctl_debug(struct nvc0_graph_priv *priv)
+nvc0_graph_icmd(struct nvc0_graph_priv *priv, struct nvc0_graph_init *init)
 {
-        u32 gpcnr = nv_rd32(priv, 0x409604) & 0xffff;
-        u32 gpc;
+        u32 addr, data;
+        int i, j;
+
+        nv_wr32(priv, 0x400208, 0x80000000);
+        for (i = 0; init->count; init++, i++) {
+                if (!i || data != init->data) {
+                        nv_wr32(priv, 0x400204, init->data);
+                        data = init->data;
+                }
 
-        nvc0_graph_ctxctl_debug_unit(priv, 0x409000);
-        for (gpc = 0; gpc < gpcnr; gpc++)
-                nvc0_graph_ctxctl_debug_unit(priv, 0x502000 + (gpc * 0x8000));
+                addr = init->addr;
+                for (j = 0; j < init->count; j++) {
+                        nv_wr32(priv, 0x400200, addr);
+                        addr += init->pitch;
+                        while (nv_rd32(priv, 0x400700) & 0x00000002) {}
+                }
+        }
+        nv_wr32(priv, 0x400208, 0x00000000);
+}
+
+void
+nvc0_graph_mthd(struct nvc0_graph_priv *priv, struct nvc0_graph_mthd *mthds)
+{
+        struct nvc0_graph_mthd *mthd;
+        struct nvc0_graph_init *init;
+        int i = 0, j;
+        u32 data;
+
+        while ((mthd = &mthds[i++]) && (init = mthd->init)) {
+                u32  addr = 0x80000000 | mthd->oclass;
+                for (data = 0; init->count; init++) {
+                        if (data != init->data) {
+                                nv_wr32(priv, 0x40448c, init->data);
+                                data = init->data;
+                        }
+
+                        addr = (addr & 0x8000ffff) | (init->addr << 14);
+                        for (j = 0; j < init->count; j++) {
+                                nv_wr32(priv, 0x404488, addr);
+                                addr += init->pitch << 14;
+                        }
+                }
+        }
+}
+
+u64
+nvc0_graph_units(struct nouveau_graph *graph)
+{
+        struct nvc0_graph_priv *priv = (void *)graph;
+        u64 cfg;
+
+        cfg  = (u32)priv->gpc_nr;
+        cfg |= (u32)priv->tpc_total << 8;
+        cfg |= (u64)priv->rop_nr << 32;
+
+        return cfg;
 }
 
+static const struct nouveau_enum nve0_sked_error[] = {
+        { 7, "CONSTANT_BUFFER_SIZE" },
+        { 9, "LOCAL_MEMORY_SIZE_POS" },
+        { 10, "LOCAL_MEMORY_SIZE_NEG" },
+        { 11, "WARP_CSTACK_SIZE" },
+        { 12, "TOTAL_TEMP_SIZE" },
+        { 13, "REGISTER_COUNT" },
+        { 18, "TOTAL_THREADS" },
+        { 20, "PROGRAM_OFFSET" },
+        { 21, "SHARED_MEMORY_SIZE" },
+        { 25, "SHARED_CONFIG_TOO_SMALL" },
+        { 26, "TOTAL_REGISTER_COUNT" },
+        {}
+};
+
+static const struct nouveau_enum nvc0_gpc_rop_error[] = {
+        { 1, "RT_PITCH_OVERRUN" },
+        { 4, "RT_WIDTH_OVERRUN" },
+        { 5, "RT_HEIGHT_OVERRUN" },
+        { 7, "ZETA_STORAGE_TYPE_MISMATCH" },
+        { 8, "RT_STORAGE_TYPE_MISMATCH" },
+        { 10, "RT_LINEAR_MISMATCH" },
+        {}
+};
+
 static void
-nvc0_graph_ctxctl_isr(struct nvc0_graph_priv *priv)
+nvc0_graph_trap_gpc_rop(struct nvc0_graph_priv *priv, int gpc)
 {
-        u32 ustat = nv_rd32(priv, 0x409c18);
+        u32 trap[4];
+        int i;
 
-        if (ustat & 0x00000001)
-                nv_error(priv, "CTXCTRL ucode error\n");
-        if (ustat & 0x00080000)
-                nv_error(priv, "CTXCTRL watchdog timeout\n");
-        if (ustat & ~0x00080001)
-                nv_error(priv, "CTXCTRL 0x%08x\n", ustat);
+        trap[0] = nv_rd32(priv, GPC_UNIT(gpc, 0x0420));
+        trap[1] = nv_rd32(priv, GPC_UNIT(gpc, 0x0434));
+        trap[2] = nv_rd32(priv, GPC_UNIT(gpc, 0x0438));
+        trap[3] = nv_rd32(priv, GPC_UNIT(gpc, 0x043c));
+
+        nv_error(priv, "GPC%d/PROP trap:", gpc);
+        for (i = 0; i <= 29; ++i) {
+                if (!(trap[0] & (1 << i)))
+                        continue;
+                pr_cont(" ");
+                nouveau_enum_print(nvc0_gpc_rop_error, i);
+        }
+        pr_cont("\n");
 
-        nvc0_graph_ctxctl_debug(priv);
-        nv_wr32(priv, 0x409c20, ustat);
+        nv_error(priv, "x = %u, y = %u, format = %x, storage type = %x\n",
+                 trap[1] & 0xffff, trap[1] >> 16, (trap[2] >> 8) & 0x3f,
+                 trap[3] & 0xff);
+        nv_wr32(priv, GPC_UNIT(gpc, 0x0420), 0xc0000000);
+}
+
+static const struct nouveau_enum nvc0_mp_warp_error[] = {
+        { 0x00, "NO_ERROR" },
+        { 0x01, "STACK_MISMATCH" },
+        { 0x05, "MISALIGNED_PC" },
+        { 0x08, "MISALIGNED_GPR" },
+        { 0x09, "INVALID_OPCODE" },
+        { 0x0d, "GPR_OUT_OF_BOUNDS" },
+        { 0x0e, "MEM_OUT_OF_BOUNDS" },
+        { 0x0f, "UNALIGNED_MEM_ACCESS" },
+        { 0x11, "INVALID_PARAM" },
+        {}
+};
+
+static const struct nouveau_bitfield nvc0_mp_global_error[] = {
+        { 0x00000004, "MULTIPLE_WARP_ERRORS" },
+        { 0x00000008, "OUT_OF_STACK_SPACE" },
+        {}
+};
+
+static void
+nvc0_graph_trap_mp(struct nvc0_graph_priv *priv, int gpc, int tpc)
+{
+        u32 werr = nv_rd32(priv, TPC_UNIT(gpc, tpc, 0x648));
+        u32 gerr = nv_rd32(priv, TPC_UNIT(gpc, tpc, 0x650));
+
+        nv_error(priv, "GPC%i/TPC%i/MP trap:", gpc, tpc);
+        nouveau_bitfield_print(nvc0_mp_global_error, gerr);
+        if (werr) {
+                pr_cont(" ");
+                nouveau_enum_print(nvc0_mp_warp_error, werr & 0xffff);
+        }
+        pr_cont("\n");
+
+        nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x648), 0x00000000);
+        nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x650), gerr);
 }
 
 static void
@@ -246,18 +458,11 @@ nvc0_graph_trap_tpc(struct nvc0_graph_priv *priv, int gpc, int tpc)
                 u32 trap = nv_rd32(priv, TPC_UNIT(gpc, tpc, 0x0224));
                 nv_error(priv, "GPC%d/TPC%d/TEX: 0x%08x\n", gpc, tpc, trap);
                 nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x0224), 0xc0000000);
-                nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x0508), 0x00000001);
                 stat &= ~0x00000001;
         }
 
         if (stat & 0x00000002) {
-                u32 trap0 = nv_rd32(priv, TPC_UNIT(gpc, tpc, 0x0644));
-                u32 trap1 = nv_rd32(priv, TPC_UNIT(gpc, tpc, 0x064c));
-                nv_error(priv, "GPC%d/TPC%d/MP: 0x%08x 0x%08x\n",
-                               gpc, tpc, trap0, trap1);
-                nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x0644), 0x001ffffe);
-                nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x064c), 0x0000000f);
-                nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x0508), 0x00000002);
+                nvc0_graph_trap_mp(priv, gpc, tpc);
                 stat &= ~0x00000002;
         }
 
@@ -265,7 +470,6 @@ nvc0_graph_trap_tpc(struct nvc0_graph_priv *priv, int gpc, int tpc)
                 u32 trap = nv_rd32(priv, TPC_UNIT(gpc, tpc, 0x0084));
                 nv_error(priv, "GPC%d/TPC%d/POLY: 0x%08x\n", gpc, tpc, trap);
                 nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x0084), 0xc0000000);
-                nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x0508), 0x00000004);
                 stat &= ~0x00000004;
         }
 
@@ -273,13 +477,11 @@ nvc0_graph_trap_tpc(struct nvc0_graph_priv *priv, int gpc, int tpc)
                 u32 trap = nv_rd32(priv, TPC_UNIT(gpc, tpc, 0x048c));
                 nv_error(priv, "GPC%d/TPC%d/L1C: 0x%08x\n", gpc, tpc, trap);
                 nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x048c), 0xc0000000);
-                nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x0508), 0x00000008);
                 stat &= ~0x00000008;
         }
 
         if (stat) {
                 nv_error(priv, "GPC%d/TPC%d/0x%08x: unknown\n", gpc, tpc, stat);
-                nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x0508), stat);
         }
 }
 
@@ -290,10 +492,7 @@ nvc0_graph_trap_gpc(struct nvc0_graph_priv *priv, int gpc)
         int tpc;
 
         if (stat & 0x00000001) {
-                u32 trap = nv_rd32(priv, GPC_UNIT(gpc, 0x0420));
-                nv_error(priv, "GPC%d/PROP: 0x%08x\n", gpc, trap);
-                nv_wr32(priv, GPC_UNIT(gpc, 0x0420), 0xc0000000);
-                nv_wr32(priv, GPC_UNIT(gpc, 0x2c90), 0x00000001);
+                nvc0_graph_trap_gpc_rop(priv, gpc);
                 stat &= ~0x00000001;
         }
 
@@ -301,7 +500,6 @@ nvc0_graph_trap_gpc(struct nvc0_graph_priv *priv, int gpc)
                 u32 trap = nv_rd32(priv, GPC_UNIT(gpc, 0x0900));
                 nv_error(priv, "GPC%d/ZCULL: 0x%08x\n", gpc, trap);
                 nv_wr32(priv, GPC_UNIT(gpc, 0x0900), 0xc0000000);
-                nv_wr32(priv, GPC_UNIT(gpc, 0x2c90), 0x00000002);
                 stat &= ~0x00000002;
         }
 
@@ -309,7 +507,6 @@ nvc0_graph_trap_gpc(struct nvc0_graph_priv *priv, int gpc)
                 u32 trap = nv_rd32(priv, GPC_UNIT(gpc, 0x1028));
                 nv_error(priv, "GPC%d/CCACHE: 0x%08x\n", gpc, trap);
                 nv_wr32(priv, GPC_UNIT(gpc, 0x1028), 0xc0000000);
-                nv_wr32(priv, GPC_UNIT(gpc, 0x2c90), 0x00000004);
                 stat &= ~0x00000004;
         }
 
@@ -317,7 +514,6 @@ nvc0_graph_trap_gpc(struct nvc0_graph_priv *priv, int gpc)
                 u32 trap = nv_rd32(priv, GPC_UNIT(gpc, 0x0824));
                 nv_error(priv, "GPC%d/ESETUP: 0x%08x\n", gpc, trap);
                 nv_wr32(priv, GPC_UNIT(gpc, 0x0824), 0xc0000000);
-                nv_wr32(priv, GPC_UNIT(gpc, 0x2c90), 0x00000008);
                 stat &= ~0x00000009;
         }
 
@@ -332,7 +528,6 @@ nvc0_graph_trap_gpc(struct nvc0_graph_priv *priv, int gpc)
 
         if (stat) {
                 nv_error(priv, "GPC%d/0x%08x: unknown\n", gpc, stat);
-                nv_wr32(priv, GPC_UNIT(gpc, 0x2c90), stat);
         }
 }
 
@@ -340,7 +535,7 @@ static void
 nvc0_graph_trap_intr(struct nvc0_graph_priv *priv)
 {
         u32 trap = nv_rd32(priv, 0x400108);
-        int rop, gpc;
+        int rop, gpc, i;
 
         if (trap & 0x00000001) {
                 u32 stat = nv_rd32(priv, 0x404000);
@@ -390,6 +585,24 @@ nvc0_graph_trap_intr(struct nvc0_graph_priv *priv)
                 trap &= ~0x00000080;
         }
 
+        if (trap & 0x00000100) {
+                u32 stat = nv_rd32(priv, 0x407020);
+
+                nv_error(priv, "SKED:");
+                for (i = 0; i <= 29; ++i) {
+                        if (!(stat & (1 << i)))
+                                continue;
+                        pr_cont(" ");
+                        nouveau_enum_print(nve0_sked_error, i);
+                }
+                pr_cont("\n");
+
+                if (stat & 0x3fffffff)
+                        nv_wr32(priv, 0x407020, 0x40000000);
+                nv_wr32(priv, 0x400108, 0x00000100);
+                trap &= ~0x00000100;
+        }
+
         if (trap & 0x01000000) {
                 u32 stat = nv_rd32(priv, 0x400118);
                 for (gpc = 0; stat && gpc < priv->gpc_nr; gpc++) {
@@ -424,6 +637,46 @@ nvc0_graph_trap_intr(struct nvc0_graph_priv *priv)
 }
 
 static void
+nvc0_graph_ctxctl_debug_unit(struct nvc0_graph_priv *priv, u32 base)
+{
+        nv_error(priv, "%06x - done 0x%08x\n", base,
+                 nv_rd32(priv, base + 0x400));
+        nv_error(priv, "%06x - stat 0x%08x 0x%08x 0x%08x 0x%08x\n", base,
+                 nv_rd32(priv, base + 0x800), nv_rd32(priv, base + 0x804),
+                 nv_rd32(priv, base + 0x808), nv_rd32(priv, base + 0x80c));
+        nv_error(priv, "%06x - stat 0x%08x 0x%08x 0x%08x 0x%08x\n", base,
+                 nv_rd32(priv, base + 0x810), nv_rd32(priv, base + 0x814),
+                 nv_rd32(priv, base + 0x818), nv_rd32(priv, base + 0x81c));
+}
+
+void
+nvc0_graph_ctxctl_debug(struct nvc0_graph_priv *priv)
+{
+        u32 gpcnr = nv_rd32(priv, 0x409604) & 0xffff;
+        u32 gpc;
+
+        nvc0_graph_ctxctl_debug_unit(priv, 0x409000);
+        for (gpc = 0; gpc < gpcnr; gpc++)
+                nvc0_graph_ctxctl_debug_unit(priv, 0x502000 + (gpc * 0x8000));
+}
+
+static void
+nvc0_graph_ctxctl_isr(struct nvc0_graph_priv *priv)
+{
+        u32 ustat = nv_rd32(priv, 0x409c18);
+
+        if (ustat & 0x00000001)
+                nv_error(priv, "CTXCTL ucode error\n");
+        if (ustat & 0x00080000)
+                nv_error(priv, "CTXCTL watchdog timeout\n");
+        if (ustat & ~0x00080001)
+                nv_error(priv, "CTXCTL 0x%08x\n", ustat);
+
+        nvc0_graph_ctxctl_debug(priv);
+        nv_wr32(priv, 0x409c20, ustat);
+}
+
+static void
 nvc0_graph_intr(struct nouveau_subdev *subdev)
 {
         struct nouveau_fifo *pfifo = nouveau_fifo(subdev);
@@ -499,290 +752,6 @@ nvc0_graph_intr(struct nouveau_subdev *subdev)
         nouveau_engctx_put(engctx);
 }
 
-int
-nvc0_graph_ctor_fw(struct nvc0_graph_priv *priv, const char *fwname,
-                   struct nvc0_graph_fuc *fuc)
-{
-        struct nouveau_device *device = nv_device(priv);
-        const struct firmware *fw;
-        char f[32];
-        int ret;
-
-        snprintf(f, sizeof(f), "nouveau/nv%02x_%s", device->chipset, fwname);
-        ret = request_firmware(&fw, f, &device->pdev->dev);
-        if (ret) {
-                snprintf(f, sizeof(f), "nouveau/%s", fwname);
-                ret = request_firmware(&fw, f, &device->pdev->dev);
-                if (ret) {
-                        nv_error(priv, "failed to load %s\n", fwname);
-                        return ret;
-                }
-        }
-
-        fuc->size = fw->size;
-        fuc->data = kmemdup(fw->data, fuc->size, GFP_KERNEL);
-        release_firmware(fw);
-        return (fuc->data != NULL) ? 0 : -ENOMEM;
-}
-
-static int
-nvc0_graph_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
-                struct nouveau_oclass *oclass, void *data, u32 size,
-                struct nouveau_object **pobject)
-{
-        struct nouveau_device *device = nv_device(parent);
-        struct nvc0_graph_priv *priv;
-        bool enable = device->chipset != 0xd7;
-        int ret, i;
-
-        ret = nouveau_graph_create(parent, engine, oclass, enable, &priv);
-        *pobject = nv_object(priv);
-        if (ret)
-                return ret;
-
-        nv_subdev(priv)->unit = 0x18001000;
-        nv_subdev(priv)->intr = nvc0_graph_intr;
-        nv_engine(priv)->cclass = &nvc0_graph_cclass;
-
-        priv->base.units = nvc0_graph_units;
-
-        if (nouveau_boolopt(device->cfgopt, "NvGrUseFW", false)) {
-                nv_info(priv, "using external firmware\n");
-                if (nvc0_graph_ctor_fw(priv, "fuc409c", &priv->fuc409c) ||
-                    nvc0_graph_ctor_fw(priv, "fuc409d", &priv->fuc409d) ||
-                    nvc0_graph_ctor_fw(priv, "fuc41ac", &priv->fuc41ac) ||
-                    nvc0_graph_ctor_fw(priv, "fuc41ad", &priv->fuc41ad))
-                        return -EINVAL;
-                priv->firmware = true;
-        }
-
-        switch (nvc0_graph_class(priv)) {
-        case 0x9097:
-                nv_engine(priv)->sclass = nvc0_graph_sclass;
-                break;
-        case 0x9197:
-                nv_engine(priv)->sclass = nvc1_graph_sclass;
-                break;
-        case 0x9297:
-                nv_engine(priv)->sclass = nvc8_graph_sclass;
-                break;
-        }
-
-        ret = nouveau_gpuobj_new(nv_object(priv), NULL, 0x1000, 256, 0,
-                                &priv->unk4188b4);
-        if (ret)
-                return ret;
-
-        ret = nouveau_gpuobj_new(nv_object(priv), NULL, 0x1000, 256, 0,
-                                &priv->unk4188b8);
-        if (ret)
-                return ret;
-
-        for (i = 0; i < 0x1000; i += 4) {
-                nv_wo32(priv->unk4188b4, i, 0x00000010);
-                nv_wo32(priv->unk4188b8, i, 0x00000010);
-        }
-
-        priv->rop_nr = (nv_rd32(priv, 0x409604) & 0x001f0000) >> 16;
-        priv->gpc_nr =  nv_rd32(priv, 0x409604) & 0x0000001f;
-        for (i = 0; i < priv->gpc_nr; i++) {
-                priv->tpc_nr[i]  = nv_rd32(priv, GPC_UNIT(i, 0x2608));
-                priv->tpc_total += priv->tpc_nr[i];
-        }
-
-        /*XXX: these need figuring out... though it might not even matter */
-        switch (nv_device(priv)->chipset) {
-        case 0xc0:
-                if (priv->tpc_total == 11) { /* 465, 3/4/4/0, 4 */
-                        priv->magic_not_rop_nr = 0x07;
-                } else
-                if (priv->tpc_total == 14) { /* 470, 3/3/4/4, 5 */
-                        priv->magic_not_rop_nr = 0x05;
-                } else
-                if (priv->tpc_total == 15) { /* 480, 3/4/4/4, 6 */
-                        priv->magic_not_rop_nr = 0x06;
-                }
-                break;
-        case 0xc3: /* 450, 4/0/0/0, 2 */
-                priv->magic_not_rop_nr = 0x03;
-                break;
-        case 0xc4: /* 460, 3/4/0/0, 4 */
-                priv->magic_not_rop_nr = 0x01;
-                break;
-        case 0xc1: /* 2/0/0/0, 1 */
-                priv->magic_not_rop_nr = 0x01;
-                break;
-        case 0xc8: /* 4/4/3/4, 5 */
-                priv->magic_not_rop_nr = 0x06;
-                break;
-        case 0xce: /* 4/4/0/0, 4 */
-                priv->magic_not_rop_nr = 0x03;
-                break;
-        case 0xcf: /* 4/0/0/0, 3 */
-                priv->magic_not_rop_nr = 0x03;
-                break;
-        case 0xd9: /* 1/0/0/0, 1 */
-                priv->magic_not_rop_nr = 0x01;
-                break;
-        }
-
-        return 0;
-}
-
-static void
-nvc0_graph_dtor_fw(struct nvc0_graph_fuc *fuc)
-{
-        kfree(fuc->data);
-        fuc->data = NULL;
-}
-
-void
-nvc0_graph_dtor(struct nouveau_object *object)
-{
-        struct nvc0_graph_priv *priv = (void *)object;
-
-        kfree(priv->data);
-
-        nvc0_graph_dtor_fw(&priv->fuc409c);
-        nvc0_graph_dtor_fw(&priv->fuc409d);
-        nvc0_graph_dtor_fw(&priv->fuc41ac);
-        nvc0_graph_dtor_fw(&priv->fuc41ad);
-
-        nouveau_gpuobj_ref(NULL, &priv->unk4188b8);
-        nouveau_gpuobj_ref(NULL, &priv->unk4188b4);
-
-        nouveau_graph_destroy(&priv->base);
-}
-
-static void
-nvc0_graph_init_obj418880(struct nvc0_graph_priv *priv)
-{
-        int i;
-
-        nv_wr32(priv, GPC_BCAST(0x0880), 0x00000000);
-        nv_wr32(priv, GPC_BCAST(0x08a4), 0x00000000);
-        for (i = 0; i < 4; i++)
-                nv_wr32(priv, GPC_BCAST(0x0888) + (i * 4), 0x00000000);
-        nv_wr32(priv, GPC_BCAST(0x08b4), priv->unk4188b4->addr >> 8);
-        nv_wr32(priv, GPC_BCAST(0x08b8), priv->unk4188b8->addr >> 8);
-}
-
-static void
-nvc0_graph_init_regs(struct nvc0_graph_priv *priv)
-{
-        nv_wr32(priv, 0x400080, 0x003083c2);
-        nv_wr32(priv, 0x400088, 0x00006fe7);
-        nv_wr32(priv, 0x40008c, 0x00000000);
-        nv_wr32(priv, 0x400090, 0x00000030);
-        nv_wr32(priv, 0x40013c, 0x013901f7);
-        nv_wr32(priv, 0x400140, 0x00000100);
-        nv_wr32(priv, 0x400144, 0x00000000);
-        nv_wr32(priv, 0x400148, 0x00000110);
-        nv_wr32(priv, 0x400138, 0x00000000);
-        nv_wr32(priv, 0x400130, 0x00000000);
-        nv_wr32(priv, 0x400134, 0x00000000);
-        nv_wr32(priv, 0x400124, 0x00000002);
-}
-
-static void
-nvc0_graph_init_gpc_0(struct nvc0_graph_priv *priv)
-{
-        const u32 magicgpc918 = DIV_ROUND_UP(0x00800000, priv->tpc_total);
-        u32 data[TPC_MAX / 8];
-        u8  tpcnr[GPC_MAX];
-        int i, gpc, tpc;
-
-        nv_wr32(priv, TPC_UNIT(0, 0, 0x5c), 1); /* affects TFB offset queries */
-
-        /*
-         *      TP      ROP UNKVAL(magic_not_rop_nr)
-         * 450: 4/0/0/0 2        3
-         * 460: 3/4/0/0 4        1
-         * 465: 3/4/4/0 4        7
-         * 470: 3/3/4/4 5        5
-         * 480: 3/4/4/4 6        6
-         */
-
-        memset(data, 0x00, sizeof(data));
-        memcpy(tpcnr, priv->tpc_nr, sizeof(priv->tpc_nr));
-        for (i = 0, gpc = -1; i < priv->tpc_total; i++) {
-                do {
-                        gpc = (gpc + 1) % priv->gpc_nr;
-                } while (!tpcnr[gpc]);
-                tpc = priv->tpc_nr[gpc] - tpcnr[gpc]--;
-
-                data[i / 8] |= tpc << ((i % 8) * 4);
-        }
-
-        nv_wr32(priv, GPC_BCAST(0x0980), data[0]);
-        nv_wr32(priv, GPC_BCAST(0x0984), data[1]);
-        nv_wr32(priv, GPC_BCAST(0x0988), data[2]);
-        nv_wr32(priv, GPC_BCAST(0x098c), data[3]);
-
-        for (gpc = 0; gpc < priv->gpc_nr; gpc++) {
-                nv_wr32(priv, GPC_UNIT(gpc, 0x0914), priv->magic_not_rop_nr << 8 |
-                                                  priv->tpc_nr[gpc]);
-                nv_wr32(priv, GPC_UNIT(gpc, 0x0910), 0x00040000 | priv->tpc_total);
-                nv_wr32(priv, GPC_UNIT(gpc, 0x0918), magicgpc918);
-        }
-
-        nv_wr32(priv, GPC_BCAST(0x1bd4), magicgpc918);
-        nv_wr32(priv, GPC_BCAST(0x08ac), nv_rd32(priv, 0x100800));
-}
-
-static void
-nvc0_graph_init_units(struct nvc0_graph_priv *priv)
-{
-        nv_wr32(priv, 0x409c24, 0x000f0000);
-        nv_wr32(priv, 0x404000, 0xc0000000); /* DISPATCH */
-        nv_wr32(priv, 0x404600, 0xc0000000); /* M2MF */
-        nv_wr32(priv, 0x408030, 0xc0000000);
-        nv_wr32(priv, 0x40601c, 0xc0000000);
-        nv_wr32(priv, 0x404490, 0xc0000000); /* MACRO */
-        nv_wr32(priv, 0x406018, 0xc0000000);
-        nv_wr32(priv, 0x405840, 0xc0000000);
-        nv_wr32(priv, 0x405844, 0x00ffffff);
-        nv_mask(priv, 0x419cc0, 0x00000008, 0x00000008);
-        nv_mask(priv, 0x419eb4, 0x00001000, 0x00001000);
-}
-
-static void
-nvc0_graph_init_gpc_1(struct nvc0_graph_priv *priv)
-{
-        int gpc, tpc;
-
-        for (gpc = 0; gpc < priv->gpc_nr; gpc++) {
-                nv_wr32(priv, GPC_UNIT(gpc, 0x0420), 0xc0000000);
-                nv_wr32(priv, GPC_UNIT(gpc, 0x0900), 0xc0000000);
-                nv_wr32(priv, GPC_UNIT(gpc, 0x1028), 0xc0000000);
-                nv_wr32(priv, GPC_UNIT(gpc, 0x0824), 0xc0000000);
-                for (tpc = 0; tpc < priv->tpc_nr[gpc]; tpc++) {
-                        nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x508), 0xffffffff);
-                        nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x50c), 0xffffffff);
-                        nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x224), 0xc0000000);
-                        nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x48c), 0xc0000000);
-                        nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x084), 0xc0000000);
-                        nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x644), 0x001ffffe);
-                        nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x64c), 0x0000000f);
-                }
-                nv_wr32(priv, GPC_UNIT(gpc, 0x2c90), 0xffffffff);
-                nv_wr32(priv, GPC_UNIT(gpc, 0x2c94), 0xffffffff);
-        }
-}
-
-static void
-nvc0_graph_init_rop(struct nvc0_graph_priv *priv)
-{
-        int rop;
-
-        for (rop = 0; rop < priv->rop_nr; rop++) {
-                nv_wr32(priv, ROP_UNIT(rop, 0x144), 0xc0000000);
-                nv_wr32(priv, ROP_UNIT(rop, 0x070), 0xc0000000);
-                nv_wr32(priv, ROP_UNIT(rop, 0x204), 0xffffffff);
-                nv_wr32(priv, ROP_UNIT(rop, 0x208), 0xffffffff);
-        }
-}
-
 void
 nvc0_graph_init_fw(struct nvc0_graph_priv *priv, u32 fuc_base,
                    struct nvc0_graph_fuc *code, struct nvc0_graph_fuc *data)
@@ -801,9 +770,46 @@ nvc0_graph_init_fw(struct nvc0_graph_priv *priv, u32 fuc_base,
         }
 }
 
-static int
+static void
+nvc0_graph_init_csdata(struct nvc0_graph_priv *priv,
+                       struct nvc0_graph_init *init,
+                       u32 falcon, u32 starstar, u32 base)
+{
+        u32 addr = init->addr;
+        u32 next = addr;
+        u32 star, temp;
+
+        nv_wr32(priv, falcon + 0x01c0, 0x02000000 + starstar);
+        star = nv_rd32(priv, falcon + 0x01c4);
+        temp = nv_rd32(priv, falcon + 0x01c4);
+        if (temp > star)
+                star = temp;
+        nv_wr32(priv, falcon + 0x01c0, 0x01000000 + star);
+
+        do {
+                if (init->addr != next) {
+                        while (addr < next) {
+                                u32 nr = min((int)(next - addr) / 4, 32);
+                                nv_wr32(priv, falcon + 0x01c4,
+                                        ((nr - 1) << 26) | (addr - base));
+                                addr += nr * 4;
+                                star += 4;
+                        }
+                        addr = next = init->addr;
+                }
+                next += init->count * 4;
+        } while ((init++)->count);
+
+        nv_wr32(priv, falcon + 0x01c0, 0x01000004 + starstar);
+        nv_wr32(priv, falcon + 0x01c4, star);
+}
+
+int
 nvc0_graph_init_ctxctl(struct nvc0_graph_priv *priv)
 {
+        struct nvc0_graph_oclass *oclass = (void *)nv_object(priv)->oclass;
+        struct nvc0_grctx_oclass *cclass = (void *)nv_engine(priv)->cclass;
+        struct nvc0_graph_init *init;
         u32 r000260;
         int i;
 
@@ -854,6 +860,38 @@ nvc0_graph_init_ctxctl(struct nvc0_graph_priv *priv)
                         return -EBUSY;
                 }
 
+                if (nv_device(priv)->chipset >= 0xe0) {
+                        nv_wr32(priv, 0x409800, 0x00000000);
+                        nv_wr32(priv, 0x409500, 0x00000001);
+                        nv_wr32(priv, 0x409504, 0x00000030);
+                        if (!nv_wait_ne(priv, 0x409800, 0xffffffff, 0x00000000)) {
+                                nv_error(priv, "fuc09 req 0x30 timeout\n");
+                                return -EBUSY;
+                        }
+
+                        nv_wr32(priv, 0x409810, 0xb00095c8);
+                        nv_wr32(priv, 0x409800, 0x00000000);
+                        nv_wr32(priv, 0x409500, 0x00000001);
+                        nv_wr32(priv, 0x409504, 0x00000031);
+                        if (!nv_wait_ne(priv, 0x409800, 0xffffffff, 0x00000000)) {
+                                nv_error(priv, "fuc09 req 0x31 timeout\n");
+                                return -EBUSY;
+                        }
+
+                        nv_wr32(priv, 0x409810, 0x00080420);
+                        nv_wr32(priv, 0x409800, 0x00000000);
+                        nv_wr32(priv, 0x409500, 0x00000001);
+                        nv_wr32(priv, 0x409504, 0x00000032);
+                        if (!nv_wait_ne(priv, 0x409800, 0xffffffff, 0x00000000)) {
+                                nv_error(priv, "fuc09 req 0x32 timeout\n");
+                                return -EBUSY;
+                        }
+
+                        nv_wr32(priv, 0x409614, 0x00000070);
+                        nv_wr32(priv, 0x409614, 0x00000770);
+                        nv_wr32(priv, 0x40802c, 0x00000001);
+                }
+
                 if (priv->data == NULL) {
                         int ret = nvc0_grctx_generate(priv);
                         if (ret) {
@@ -868,31 +906,41 @@ nvc0_graph_init_ctxctl(struct nvc0_graph_priv *priv)
         /* load HUB microcode */
         r000260 = nv_mask(priv, 0x000260, 0x00000001, 0x00000000);
         nv_wr32(priv, 0x4091c0, 0x01000000);
-        for (i = 0; i < sizeof(nvc0_grhub_data) / 4; i++)
-                nv_wr32(priv, 0x4091c4, nvc0_grhub_data[i]);
+        for (i = 0; i < oclass->fecs.ucode->data.size / 4; i++)
+                nv_wr32(priv, 0x4091c4, oclass->fecs.ucode->data.data[i]);
 
         nv_wr32(priv, 0x409180, 0x01000000);
-        for (i = 0; i < sizeof(nvc0_grhub_code) / 4; i++) {
+        for (i = 0; i < oclass->fecs.ucode->code.size / 4; i++) {
                 if ((i & 0x3f) == 0)
                         nv_wr32(priv, 0x409188, i >> 6);
-                nv_wr32(priv, 0x409184, nvc0_grhub_code[i]);
+                nv_wr32(priv, 0x409184, oclass->fecs.ucode->code.data[i]);
+        }
+
+        for (i = 0; (init = cclass->hub[i]); i++) {
+                nvc0_graph_init_csdata(priv, init, 0x409000, 0x000, 0x000000);
         }
 
         /* load GPC microcode */
         nv_wr32(priv, 0x41a1c0, 0x01000000);
-        for (i = 0; i < sizeof(nvc0_grgpc_data) / 4; i++)
-                nv_wr32(priv, 0x41a1c4, nvc0_grgpc_data[i]);
+        for (i = 0; i < oclass->gpccs.ucode->data.size / 4; i++)
+                nv_wr32(priv, 0x41a1c4, oclass->gpccs.ucode->data.data[i]);
 
         nv_wr32(priv, 0x41a180, 0x01000000);
-        for (i = 0; i < sizeof(nvc0_grgpc_code) / 4; i++) {
+        for (i = 0; i < oclass->gpccs.ucode->code.size / 4; i++) {
                 if ((i & 0x3f) == 0)
                         nv_wr32(priv, 0x41a188, i >> 6);
-                nv_wr32(priv, 0x41a184, nvc0_grgpc_code[i]);
+                nv_wr32(priv, 0x41a184, oclass->gpccs.ucode->code.data[i]);
         }
         nv_wr32(priv, 0x000260, r000260);
 
+        if ((init = cclass->gpc[0]))
+                nvc0_graph_init_csdata(priv, init, 0x41a000, 0x000, 0x418000);
+        if ((init = cclass->gpc[2]))
+                nvc0_graph_init_csdata(priv, init, 0x41a000, 0x004, 0x419800);
+        if ((init = cclass->gpc[3]))
+                nvc0_graph_init_csdata(priv, init, 0x41a000, 0x008, 0x41be00);
+
         /* start HUB ucode running, it'll init the GPCs */
-        nv_wr32(priv, 0x409800, nv_device(priv)->chipset);
         nv_wr32(priv, 0x40910c, 0x00000000);
         nv_wr32(priv, 0x409100, 0x00000002);
         if (!nv_wait(priv, 0x409800, 0x80000000, 0x80000000)) {
@@ -913,29 +961,104 @@ nvc0_graph_init_ctxctl(struct nvc0_graph_priv *priv)
         return 0;
 }
 
-static int
+int
 nvc0_graph_init(struct nouveau_object *object)
 {
+        struct nvc0_graph_oclass *oclass = (void *)object->oclass;
         struct nvc0_graph_priv *priv = (void *)object;
-        int ret;
+        const u32 magicgpc918 = DIV_ROUND_UP(0x00800000, priv->tpc_total);
+        u32 data[TPC_MAX / 8] = {};
+        u8  tpcnr[GPC_MAX];
+        int gpc, tpc, rop;
+        int ret, i;
 
         ret = nouveau_graph_init(&priv->base);
         if (ret)
                 return ret;
 
-        nvc0_graph_init_obj418880(priv);
-        nvc0_graph_init_regs(priv);
-        /*nvc0_graph_init_unitplemented_magics(priv);*/
-        nvc0_graph_init_gpc_0(priv);
-        /*nvc0_graph_init_unitplemented_c242(priv);*/
+        nv_wr32(priv, GPC_BCAST(0x0880), 0x00000000);
+        nv_wr32(priv, GPC_BCAST(0x08a4), 0x00000000);
+        nv_wr32(priv, GPC_BCAST(0x0888), 0x00000000);
+        nv_wr32(priv, GPC_BCAST(0x088c), 0x00000000);
+        nv_wr32(priv, GPC_BCAST(0x0890), 0x00000000);
+        nv_wr32(priv, GPC_BCAST(0x0894), 0x00000000);
+        nv_wr32(priv, GPC_BCAST(0x08b4), priv->unk4188b4->addr >> 8);
+        nv_wr32(priv, GPC_BCAST(0x08b8), priv->unk4188b8->addr >> 8);
+
+        for (i = 0; oclass->mmio[i]; i++)
+                nvc0_graph_mmio(priv, oclass->mmio[i]);
+
+        memcpy(tpcnr, priv->tpc_nr, sizeof(priv->tpc_nr));
+        for (i = 0, gpc = -1; i < priv->tpc_total; i++) {
+                do {
+                        gpc = (gpc + 1) % priv->gpc_nr;
+                } while (!tpcnr[gpc]);
+                tpc = priv->tpc_nr[gpc] - tpcnr[gpc]--;
+
+                data[i / 8] |= tpc << ((i % 8) * 4);
+        }
+
+        nv_wr32(priv, GPC_BCAST(0x0980), data[0]);
+        nv_wr32(priv, GPC_BCAST(0x0984), data[1]);
+        nv_wr32(priv, GPC_BCAST(0x0988), data[2]);
+        nv_wr32(priv, GPC_BCAST(0x098c), data[3]);
+
+        for (gpc = 0; gpc < priv->gpc_nr; gpc++) {
+                nv_wr32(priv, GPC_UNIT(gpc, 0x0914),
+                        priv->magic_not_rop_nr << 8 | priv->tpc_nr[gpc]);
+                nv_wr32(priv, GPC_UNIT(gpc, 0x0910), 0x00040000 |
+                        priv->tpc_total);
+                nv_wr32(priv, GPC_UNIT(gpc, 0x0918), magicgpc918);
+        }
+
+        if (nv_device(priv)->chipset != 0xd7)
+                nv_wr32(priv, GPC_BCAST(0x1bd4), magicgpc918);
+        else
+                nv_wr32(priv, GPC_BCAST(0x3fd4), magicgpc918);
+
+        nv_wr32(priv, GPC_BCAST(0x08ac), nv_rd32(priv, 0x100800));
 
         nv_wr32(priv, 0x400500, 0x00010001);
+
         nv_wr32(priv, 0x400100, 0xffffffff);
         nv_wr32(priv, 0x40013c, 0xffffffff);
 
-        nvc0_graph_init_units(priv);
-        nvc0_graph_init_gpc_1(priv);
-        nvc0_graph_init_rop(priv);
+        nv_wr32(priv, 0x409c24, 0x000f0000);
+        nv_wr32(priv, 0x404000, 0xc0000000);
+        nv_wr32(priv, 0x404600, 0xc0000000);
+        nv_wr32(priv, 0x408030, 0xc0000000);
+        nv_wr32(priv, 0x40601c, 0xc0000000);
+        nv_wr32(priv, 0x404490, 0xc0000000);
+        nv_wr32(priv, 0x406018, 0xc0000000);
+        nv_wr32(priv, 0x405840, 0xc0000000);
+        nv_wr32(priv, 0x405844, 0x00ffffff);
+        nv_mask(priv, 0x419cc0, 0x00000008, 0x00000008);
+        nv_mask(priv, 0x419eb4, 0x00001000, 0x00001000);
+
+        for (gpc = 0; gpc < priv->gpc_nr; gpc++) {
+                nv_wr32(priv, GPC_UNIT(gpc, 0x0420), 0xc0000000);
+                nv_wr32(priv, GPC_UNIT(gpc, 0x0900), 0xc0000000);
+                nv_wr32(priv, GPC_UNIT(gpc, 0x1028), 0xc0000000);
+                nv_wr32(priv, GPC_UNIT(gpc, 0x0824), 0xc0000000);
+                for (tpc = 0; tpc < priv->tpc_nr[gpc]; tpc++) {
+                        nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x508), 0xffffffff);
+                        nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x50c), 0xffffffff);
+                        nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x224), 0xc0000000);
+                        nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x48c), 0xc0000000);
+                        nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x084), 0xc0000000);
+                        nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x644), 0x001ffffe);
+                        nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x64c), 0x0000000f);
+                }
+                nv_wr32(priv, GPC_UNIT(gpc, 0x2c90), 0xffffffff);
+                nv_wr32(priv, GPC_UNIT(gpc, 0x2c94), 0xffffffff);
+        }
+
+        for (rop = 0; rop < priv->rop_nr; rop++) {
+                nv_wr32(priv, ROP_UNIT(rop, 0x144), 0xc0000000);
+                nv_wr32(priv, ROP_UNIT(rop, 0x070), 0xc0000000);
+                nv_wr32(priv, ROP_UNIT(rop, 0x204), 0xffffffff);
+                nv_wr32(priv, ROP_UNIT(rop, 0x208), 0xffffffff);
+        }
 
         nv_wr32(priv, 0x400108, 0xffffffff);
         nv_wr32(priv, 0x400138, 0xffffffff);
@@ -943,22 +1066,205 @@ nvc0_graph_init(struct nouveau_object *object)
         nv_wr32(priv, 0x400130, 0xffffffff);
         nv_wr32(priv, 0x40011c, 0xffffffff);
         nv_wr32(priv, 0x400134, 0xffffffff);
+
         nv_wr32(priv, 0x400054, 0x34ce3464);
+        return nvc0_graph_init_ctxctl(priv);
+}
 
-        ret = nvc0_graph_init_ctxctl(priv);
+static void
+nvc0_graph_dtor_fw(struct nvc0_graph_fuc *fuc)
+{
+        kfree(fuc->data);
+        fuc->data = NULL;
+}
+
+int
+nvc0_graph_ctor_fw(struct nvc0_graph_priv *priv, const char *fwname,
+                   struct nvc0_graph_fuc *fuc)
+{
+        struct nouveau_device *device = nv_device(priv);
+        const struct firmware *fw;
+        char f[32];
+        int ret;
+
+        snprintf(f, sizeof(f), "nouveau/nv%02x_%s", device->chipset, fwname);
+        ret = request_firmware(&fw, f, &device->pdev->dev);
+        if (ret) {
+                snprintf(f, sizeof(f), "nouveau/%s", fwname);
+                ret = request_firmware(&fw, f, &device->pdev->dev);
+                if (ret) {
+                        nv_error(priv, "failed to load %s\n", fwname);
+                        return ret;
+                }
+        }
+
+        fuc->size = fw->size;
+        fuc->data = kmemdup(fw->data, fuc->size, GFP_KERNEL);
+        release_firmware(fw);
+        return (fuc->data != NULL) ? 0 : -ENOMEM;
+}
+
+void
+nvc0_graph_dtor(struct nouveau_object *object)
+{
+        struct nvc0_graph_priv *priv = (void *)object;
+
+        kfree(priv->data);
+
+        nvc0_graph_dtor_fw(&priv->fuc409c);
+        nvc0_graph_dtor_fw(&priv->fuc409d);
+        nvc0_graph_dtor_fw(&priv->fuc41ac);
+        nvc0_graph_dtor_fw(&priv->fuc41ad);
+
+        nouveau_gpuobj_ref(NULL, &priv->unk4188b8);
+        nouveau_gpuobj_ref(NULL, &priv->unk4188b4);
+
+        nouveau_graph_destroy(&priv->base);
+}
+
+int
+nvc0_graph_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
+                struct nouveau_oclass *bclass, void *data, u32 size,
+                struct nouveau_object **pobject)
+{
+        struct nvc0_graph_oclass *oclass = (void *)bclass;
+        struct nouveau_device *device = nv_device(parent);
+        struct nvc0_graph_priv *priv;
+        int ret, i;
+
+        ret = nouveau_graph_create(parent, engine, bclass,
+                                   (oclass->fecs.ucode != NULL), &priv);
+        *pobject = nv_object(priv);
         if (ret)
                 return ret;
 
+        nv_subdev(priv)->unit = 0x18001000;
+        nv_subdev(priv)->intr = nvc0_graph_intr;
+
+        priv->base.units = nvc0_graph_units;
+
+        if (nouveau_boolopt(device->cfgopt, "NvGrUseFW", false)) {
+                nv_info(priv, "using external firmware\n");
+                if (nvc0_graph_ctor_fw(priv, "fuc409c", &priv->fuc409c) ||
+                    nvc0_graph_ctor_fw(priv, "fuc409d", &priv->fuc409d) ||
+                    nvc0_graph_ctor_fw(priv, "fuc41ac", &priv->fuc41ac) ||
+                    nvc0_graph_ctor_fw(priv, "fuc41ad", &priv->fuc41ad))
+                        return -EINVAL;
+                priv->firmware = true;
+        }
+
+        ret = nouveau_gpuobj_new(nv_object(priv), NULL, 0x1000, 256, 0,
+                                &priv->unk4188b4);
+        if (ret)
+                return ret;
+
+        ret = nouveau_gpuobj_new(nv_object(priv), NULL, 0x1000, 256, 0,
+                                &priv->unk4188b8);
+        if (ret)
+                return ret;
+
+        for (i = 0; i < 0x1000; i += 4) {
+                nv_wo32(priv->unk4188b4, i, 0x00000010);
+                nv_wo32(priv->unk4188b8, i, 0x00000010);
+        }
+
+        priv->rop_nr = (nv_rd32(priv, 0x409604) & 0x001f0000) >> 16;
+        priv->gpc_nr =  nv_rd32(priv, 0x409604) & 0x0000001f;
+        for (i = 0; i < priv->gpc_nr; i++) {
+                priv->tpc_nr[i]  = nv_rd32(priv, GPC_UNIT(i, 0x2608));
+                priv->tpc_total += priv->tpc_nr[i];
+        }
+
+        /*XXX: these need figuring out... though it might not even matter */
+        switch (nv_device(priv)->chipset) {
+        case 0xc0:
+                if (priv->tpc_total == 11) { /* 465, 3/4/4/0, 4 */
+                        priv->magic_not_rop_nr = 0x07;
+                } else
+                if (priv->tpc_total == 14) { /* 470, 3/3/4/4, 5 */
+                        priv->magic_not_rop_nr = 0x05;
+                } else
+                if (priv->tpc_total == 15) { /* 480, 3/4/4/4, 6 */
+                        priv->magic_not_rop_nr = 0x06;
+                }
+                break;
+        case 0xc3: /* 450, 4/0/0/0, 2 */
+                priv->magic_not_rop_nr = 0x03;
+                break;
+        case 0xc4: /* 460, 3/4/0/0, 4 */
+                priv->magic_not_rop_nr = 0x01;
+                break;
+        case 0xc1: /* 2/0/0/0, 1 */
+                priv->magic_not_rop_nr = 0x01;
+                break;
+        case 0xc8: /* 4/4/3/4, 5 */
+                priv->magic_not_rop_nr = 0x06;
+                break;
+        case 0xce: /* 4/4/0/0, 4 */
+                priv->magic_not_rop_nr = 0x03;
+                break;
+        case 0xcf: /* 4/0/0/0, 3 */
+                priv->magic_not_rop_nr = 0x03;
+                break;
+        case 0xd7:
+        case 0xd9: /* 1/0/0/0, 1 */
+                priv->magic_not_rop_nr = 0x01;
+                break;
+        }
+
+        nv_engine(priv)->cclass = *oclass->cclass;
+        nv_engine(priv)->sclass =  oclass->sclass;
         return 0;
 }
 
-struct nouveau_oclass
-nvc0_graph_oclass = {
-        .handle = NV_ENGINE(GR, 0xc0),
-        .ofuncs = &(struct nouveau_ofuncs) {
+struct nvc0_graph_init *
+nvc0_graph_init_mmio[] = {
+        nvc0_graph_init_regs,
+        nvc0_graph_init_unk40xx,
+        nvc0_graph_init_unk44xx,
+        nvc0_graph_init_unk78xx,
+        nvc0_graph_init_unk60xx,
+        nvc0_graph_init_unk58xx,
+        nvc0_graph_init_unk80xx,
+        nvc0_graph_init_gpc,
+        nvc0_graph_init_tpc,
+        nvc0_graph_init_unk88xx,
+        nvc0_graph_tpc_0,
+        NULL
+};
+
+#include "fuc/hubnvc0.fuc.h"
+
+struct nvc0_graph_ucode
+nvc0_graph_fecs_ucode = {
+        .code.data = nvc0_grhub_code,
+        .code.size = sizeof(nvc0_grhub_code),
+        .data.data = nvc0_grhub_data,
+        .data.size = sizeof(nvc0_grhub_data),
+};
+
+#include "fuc/gpcnvc0.fuc.h"
+
+struct nvc0_graph_ucode
+nvc0_graph_gpccs_ucode = {
+        .code.data = nvc0_grgpc_code,
+        .code.size = sizeof(nvc0_grgpc_code),
+        .data.data = nvc0_grgpc_data,
+        .data.size = sizeof(nvc0_grgpc_data),
+};
+
+struct nouveau_oclass *
+nvc0_graph_oclass = &(struct nvc0_graph_oclass) {
+        .base.handle = NV_ENGINE(GR, 0xc0),
+        .base.ofuncs = &(struct nouveau_ofuncs) {
                 .ctor = nvc0_graph_ctor,
                 .dtor = nvc0_graph_dtor,
                 .init = nvc0_graph_init,
                 .fini = _nouveau_graph_fini,
         },
-};
+        .cclass = &nvc0_grctx_oclass,
+        .sclass =  nvc0_graph_sclass,
+        .mmio = nvc0_graph_init_mmio,
+        .fecs.ucode = &nvc0_graph_fecs_ucode,
+        .gpccs.ucode = &nvc0_graph_gpccs_ucode,
+}.base;
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/nvc0.h b/drivers/gpu/drm/nouveau/core/engine/graph/nvc0.h
index c870dad0f670..ea17a80ad7fc 100644
--- a/drivers/gpu/drm/nouveau/core/engine/graph/nvc0.h
+++ b/drivers/gpu/drm/nouveau/core/engine/graph/nvc0.h
@@ -38,8 +38,8 @@
 #include <engine/fifo.h>
 #include <engine/graph.h>
 
-#define GPC_MAX 4
-#define TPC_MAX 32
+#define GPC_MAX 32
+#define TPC_MAX (GPC_MAX * 8)
 
 #define ROP_BCAST(r)      (0x408800 + (r))
 #define ROP_UNIT(u, r)    (0x410000 + (u) * 0x400 + (r))
@@ -102,74 +102,187 @@ struct nvc0_graph_chan {
         } data[4];
 };
 
-static inline u32
-nvc0_graph_class(void *obj)
-{
-        struct nouveau_device *device = nv_device(obj);
-
-        switch (device->chipset) {
-        case 0xc0:
-        case 0xc3:
-        case 0xc4:
-        case 0xce: /* guess, mmio trace shows only 0x9097 state */
-        case 0xcf: /* guess, mmio trace shows only 0x9097 state */
-                return 0x9097;
-        case 0xc1:
-                return 0x9197;
-        case 0xc8:
-        case 0xd9:
-        case 0xd7:
-                return 0x9297;
-        case 0xe4:
-        case 0xe7:
-        case 0xe6:
-                return 0xa097;
-        default:
-                return 0;
-        }
-}
-
-void nv_icmd(struct nvc0_graph_priv *priv, u32 icmd, u32 data);
-
-static inline void
-nv_mthd(struct nvc0_graph_priv *priv, u32 class, u32 mthd, u32 data)
-{
-        nv_wr32(priv, 0x40448c, data);
-        nv_wr32(priv, 0x404488, 0x80000000 | (mthd << 14) | class);
-}
+int  nvc0_grctx_generate(struct nvc0_graph_priv *);
+
+int  nvc0_graph_context_ctor(struct nouveau_object *, struct nouveau_object *,
+                             struct nouveau_oclass *, void *, u32,
+                             struct nouveau_object **);
+void nvc0_graph_context_dtor(struct nouveau_object *);
+
+void nvc0_graph_ctxctl_debug(struct nvc0_graph_priv *);
+
+u64  nvc0_graph_units(struct nouveau_graph *);
+int  nvc0_graph_ctor(struct nouveau_object *, struct nouveau_object *,
+                     struct nouveau_oclass *, void *data, u32 size,
+                     struct nouveau_object **);
+void nvc0_graph_dtor(struct nouveau_object *);
+int  nvc0_graph_init(struct nouveau_object *);
+int  nve4_graph_init(struct nouveau_object *);
+
+extern struct nouveau_oclass nvc0_graph_sclass[];
+
+extern struct nouveau_oclass nvc8_graph_sclass[];
+
+struct nvc0_graph_init {
+        u32 addr;
+        u8  count;
+        u8  pitch;
+        u32 data;
+};
+
+struct nvc0_graph_mthd {
+        u16 oclass;
+        struct nvc0_graph_init *init;
+};
 
 struct nvc0_grctx {
         struct nvc0_graph_priv *priv;
         struct nvc0_graph_data *data;
         struct nvc0_graph_mmio *mmio;
-        struct nouveau_gpuobj *chan;
         int buffer_nr;
         u64 buffer[4];
         u64 addr;
 };
 
+struct nvc0_grctx_oclass {
+        struct nouveau_oclass base;
+        /* main context generation function */
+        void  (*main)(struct nvc0_graph_priv *, struct nvc0_grctx *);
+        /* context-specific modify-on-first-load list generation function */
+        void  (*mods)(struct nvc0_graph_priv *, struct nvc0_grctx *);
+        void  (*unkn)(struct nvc0_graph_priv *);
+        /* mmio context data */
+        struct nvc0_graph_init **hub;
+        struct nvc0_graph_init **gpc;
+        /* indirect context data, generated with icmds/mthds */
+        struct nvc0_graph_init *icmd;
+        struct nvc0_graph_mthd *mthd;
+};
+
+struct nvc0_graph_ucode {
+        struct nvc0_graph_fuc code;
+        struct nvc0_graph_fuc data;
+};
+
+extern struct nvc0_graph_ucode nvc0_graph_fecs_ucode;
+extern struct nvc0_graph_ucode nvc0_graph_gpccs_ucode;
+
+struct nvc0_graph_oclass {
+        struct nouveau_oclass base;
+        struct nouveau_oclass **cclass;
+        struct nouveau_oclass *sclass;
+        struct nvc0_graph_init **mmio;
+        struct {
+                struct nvc0_graph_ucode *ucode;
+        } fecs;
+        struct {
+                struct nvc0_graph_ucode *ucode;
+        } gpccs;
+};
+
+void nvc0_graph_mmio(struct nvc0_graph_priv *, struct nvc0_graph_init *);
+void nvc0_graph_icmd(struct nvc0_graph_priv *, struct nvc0_graph_init *);
+void nvc0_graph_mthd(struct nvc0_graph_priv *, struct nvc0_graph_mthd *);
+int  nvc0_graph_init_ctxctl(struct nvc0_graph_priv *);
+
+extern struct nvc0_graph_init nvc0_graph_init_regs[];
+extern struct nvc0_graph_init nvc0_graph_init_unk40xx[];
+extern struct nvc0_graph_init nvc0_graph_init_unk44xx[];
+extern struct nvc0_graph_init nvc0_graph_init_unk78xx[];
+extern struct nvc0_graph_init nvc0_graph_init_unk60xx[];
+extern struct nvc0_graph_init nvc0_graph_init_unk58xx[];
+extern struct nvc0_graph_init nvc0_graph_init_unk80xx[];
+extern struct nvc0_graph_init nvc0_graph_init_gpc[];
+extern struct nvc0_graph_init nvc0_graph_init_unk88xx[];
+extern struct nvc0_graph_init nvc0_graph_tpc_0[];
+
+extern struct nvc0_graph_init nvc3_graph_init_unk58xx[];
+
+extern struct nvc0_graph_init nvd9_graph_init_unk58xx[];
+extern struct nvc0_graph_init nvd9_graph_init_unk64xx[];
+
+extern struct nvc0_graph_init nve4_graph_init_regs[];
+extern struct nvc0_graph_init nve4_graph_init_unk[];
+extern struct nvc0_graph_init nve4_graph_init_unk88xx[];
+
 int  nvc0_grctx_generate(struct nvc0_graph_priv *);
-int  nvc0_grctx_init(struct nvc0_graph_priv *, struct nvc0_grctx *);
-void nvc0_grctx_data(struct nvc0_grctx *, u32, u32, u32);
-void nvc0_grctx_mmio(struct nvc0_grctx *, u32, u32, u32, u32);
-int  nvc0_grctx_fini(struct nvc0_grctx *);
+void nvc0_grctx_generate_main(struct nvc0_graph_priv *, struct nvc0_grctx *);
+void nvc0_grctx_generate_mods(struct nvc0_graph_priv *, struct nvc0_grctx *);
+void nvc0_grctx_generate_unkn(struct nvc0_graph_priv *);
+void nvc0_grctx_generate_tpcid(struct nvc0_graph_priv *);
+void nvc0_grctx_generate_r406028(struct nvc0_graph_priv *);
+void nvc0_grctx_generate_r4060a8(struct nvc0_graph_priv *);
+void nvc0_grctx_generate_r418bb8(struct nvc0_graph_priv *);
+void nve4_grctx_generate_r418bb8(struct nvc0_graph_priv *);
+void nvc0_grctx_generate_r406800(struct nvc0_graph_priv *);
 
-int  nve0_grctx_generate(struct nvc0_graph_priv *);
+extern struct nouveau_oclass *nvc0_grctx_oclass;
+extern struct nvc0_graph_init *nvc0_grctx_init_hub[];
+extern struct nvc0_graph_init nvc0_grctx_init_base[];
+extern struct nvc0_graph_init nvc0_grctx_init_unk40xx[];
+extern struct nvc0_graph_init nvc0_grctx_init_unk44xx[];
+extern struct nvc0_graph_init nvc0_grctx_init_unk46xx[];
+extern struct nvc0_graph_init nvc0_grctx_init_unk47xx[];
+extern struct nvc0_graph_init nvc0_grctx_init_unk60xx[];
+extern struct nvc0_graph_init nvc0_grctx_init_unk64xx[];
+extern struct nvc0_graph_init nvc0_grctx_init_unk78xx[];
+extern struct nvc0_graph_init nvc0_grctx_init_unk80xx[];
+extern struct nvc0_graph_init nvc0_grctx_init_gpc_0[];
+extern struct nvc0_graph_init nvc0_grctx_init_gpc_1[];
+extern struct nvc0_graph_init nvc0_grctx_init_tpc[];
+extern struct nvc0_graph_init nvc0_grctx_init_icmd[];
+extern struct nvc0_graph_init nvd9_grctx_init_icmd[]; //
 
-#define mmio_data(s,a,p) nvc0_grctx_data(&info, (s), (a), (p))
-#define mmio_list(r,d,s,b) nvc0_grctx_mmio(&info, (r), (d), (s), (b))
+extern struct nvc0_graph_mthd nvc0_grctx_init_mthd[];
+extern struct nvc0_graph_init nvc0_grctx_init_902d[];
+extern struct nvc0_graph_init nvc0_grctx_init_9039[];
+extern struct nvc0_graph_init nvc0_grctx_init_90c0[];
+extern struct nvc0_graph_init nvc0_grctx_init_mthd_magic[];
 
-void nvc0_graph_ctxctl_debug(struct nvc0_graph_priv *);
-int  nvc0_graph_ctor_fw(struct nvc0_graph_priv *, const char *,
-                        struct nvc0_graph_fuc *);
-void nvc0_graph_dtor(struct nouveau_object *);
-void nvc0_graph_init_fw(struct nvc0_graph_priv *, u32 base,
-                        struct nvc0_graph_fuc *, struct nvc0_graph_fuc *);
-int  nvc0_graph_context_ctor(struct nouveau_object *, struct nouveau_object *,
-                             struct nouveau_oclass *, void *, u32,
-                             struct nouveau_object **);
-void nvc0_graph_context_dtor(struct nouveau_object *);
+void nvc1_grctx_generate_mods(struct nvc0_graph_priv *, struct nvc0_grctx *);
+void nvc1_grctx_generate_unkn(struct nvc0_graph_priv *);
+extern struct nouveau_oclass *nvc1_grctx_oclass;
+extern struct nvc0_graph_init nvc1_grctx_init_9097[];
+
+extern struct nouveau_oclass *nvc3_grctx_oclass;
+
+extern struct nouveau_oclass *nvc8_grctx_oclass;
+extern struct nvc0_graph_init nvc8_grctx_init_9197[];
+extern struct nvc0_graph_init nvc8_grctx_init_9297[];
+
+extern struct nouveau_oclass *nvd7_grctx_oclass;
+
+extern struct nouveau_oclass *nvd9_grctx_oclass;
+extern struct nvc0_graph_init nvd9_grctx_init_rop[];
+extern struct nvc0_graph_mthd nvd9_grctx_init_mthd[];
+
+void nve4_grctx_generate_main(struct nvc0_graph_priv *, struct nvc0_grctx *);
+void nve4_grctx_generate_unkn(struct nvc0_graph_priv *);
+extern struct nouveau_oclass *nve4_grctx_oclass;
+extern struct nvc0_graph_init nve4_grctx_init_unk46xx[];
+extern struct nvc0_graph_init nve4_grctx_init_unk47xx[];
+extern struct nvc0_graph_init nve4_grctx_init_unk58xx[];
+extern struct nvc0_graph_init nve4_grctx_init_unk80xx[];
+extern struct nvc0_graph_init nve4_grctx_init_unk90xx[];
+
+extern struct nouveau_oclass *nvf0_grctx_oclass;
+
+#define mmio_data(s,a,p) do {                                                  \
+        info->buffer[info->buffer_nr] = round_up(info->addr, (a));             \
+        info->addr = info->buffer[info->buffer_nr++] + (s);                    \
+        info->data->size = (s);                                                \
+        info->data->align = (a);                                               \
+        info->data->access = (p);                                              \
+        info->data++;                                                          \
+} while(0)
 
-u64 nvc0_graph_units(struct nouveau_graph *);
+#define mmio_list(r,d,s,b) do {                                                \
+        info->mmio->addr = (r);                                                \
+        info->mmio->data = (d);                                                \
+        info->mmio->shift = (s);                                               \
+        info->mmio->buffer = (b);                                              \
+        info->mmio++;                                                          \
+        nv_wr32(priv, (r), (d) | ((s) ? (info->buffer[(b)] >> (s)) : 0));      \
+} while(0)
 
 #endif
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/nvc1.c b/drivers/gpu/drm/nouveau/core/engine/graph/nvc1.c
new file mode 100644
index 000000000000..bc4a469b86cb
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/core/engine/graph/nvc1.c
@@ -0,0 +1,144 @@
+/*
+ * Copyright 2013 Red Hat Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Ben Skeggs <bskeggs@redhat.com>
+ */
+
+#include "nvc0.h"
+
+/*******************************************************************************
+ * Graphics object classes
+ ******************************************************************************/
+
+static struct nouveau_oclass
+nvc1_graph_sclass[] = {
+        { 0x902d, &nouveau_object_ofuncs },
+        { 0x9039, &nouveau_object_ofuncs },
+        { 0x9097, &nouveau_object_ofuncs },
+        { 0x90c0, &nouveau_object_ofuncs },
+        { 0x9197, &nouveau_object_ofuncs },
+        {}
+};
+
+/*******************************************************************************
+ * PGRAPH engine/subdev functions
+ ******************************************************************************/
+
+static struct nvc0_graph_init
+nvc1_graph_init_gpc[] = {
+        { 0x4184a0,   1, 0x04, 0x00000000 },
+        { 0x418604,   1, 0x04, 0x00000000 },
+        { 0x418680,   1, 0x04, 0x00000000 },
+        { 0x418714,   1, 0x04, 0x00000000 },
+        { 0x418384,   1, 0x04, 0x00000000 },
+        { 0x418814,   3, 0x04, 0x00000000 },
+        { 0x418b04,   1, 0x04, 0x00000000 },
+        { 0x4188c8,   2, 0x04, 0x00000000 },
+        { 0x4188d0,   1, 0x04, 0x00010000 },
+        { 0x4188d4,   1, 0x04, 0x00000001 },
+        { 0x418910,   1, 0x04, 0x00010001 },
+        { 0x418914,   1, 0x04, 0x00000301 },
+        { 0x418918,   1, 0x04, 0x00800000 },
+        { 0x418980,   1, 0x04, 0x77777770 },
+        { 0x418984,   3, 0x04, 0x77777777 },
+        { 0x418c04,   1, 0x04, 0x00000000 },
+        { 0x418c88,   1, 0x04, 0x00000000 },
+        { 0x418d00,   1, 0x04, 0x00000000 },
+        { 0x418f08,   1, 0x04, 0x00000000 },
+        { 0x418e00,   1, 0x04, 0x00000003 },
+        { 0x418e08,   1, 0x04, 0x00000000 },
+        { 0x41900c,   1, 0x04, 0x00000000 },
+        { 0x419018,   1, 0x04, 0x00000000 },
+        {}
+};
+
+static struct nvc0_graph_init
+nvc1_graph_init_tpc[] = {
+        { 0x419d08,   2, 0x04, 0x00000000 },
+        { 0x419d10,   1, 0x04, 0x00000014 },
+        { 0x419ab0,   1, 0x04, 0x00000000 },
+        { 0x419ac8,   1, 0x04, 0x00000000 },
+        { 0x419ab8,   1, 0x04, 0x000000e7 },
+        { 0x419abc,   2, 0x04, 0x00000000 },
+        { 0x41980c,   2, 0x04, 0x00000000 },
+        { 0x419814,   1, 0x04, 0x00000004 },
+        { 0x419844,   1, 0x04, 0x00000000 },
+        { 0x41984c,   1, 0x04, 0x00005bc5 },
+        { 0x419850,   4, 0x04, 0x00000000 },
+        { 0x419880,   1, 0x04, 0x00000002 },
+        { 0x419c98,   1, 0x04, 0x00000000 },
+        { 0x419ca8,   1, 0x04, 0x80000000 },
+        { 0x419cb4,   1, 0x04, 0x00000000 },
+        { 0x419cb8,   1, 0x04, 0x00008bf4 },
+        { 0x419cbc,   1, 0x04, 0x28137606 },
+        { 0x419cc0,   2, 0x04, 0x00000000 },
+        { 0x419bd4,   1, 0x04, 0x00800000 },
+        { 0x419bdc,   1, 0x04, 0x00000000 },
+        { 0x419d2c,   1, 0x04, 0x00000000 },
+        { 0x419c0c,   1, 0x04, 0x00000000 },
+        { 0x419e00,   1, 0x04, 0x00000000 },
+        { 0x419ea0,   1, 0x04, 0x00000000 },
+        { 0x419ea4,   1, 0x04, 0x00000100 },
+        { 0x419ea8,   1, 0x04, 0x00001100 },
+        { 0x419eac,   1, 0x04, 0x11100702 },
+        { 0x419eb0,   1, 0x04, 0x00000003 },
+        { 0x419eb4,   4, 0x04, 0x00000000 },
+        { 0x419ec8,   1, 0x04, 0x0e063818 },
+        { 0x419ecc,   1, 0x04, 0x0e060e06 },
+        { 0x419ed0,   1, 0x04, 0x00003818 },
+        { 0x419ed4,   1, 0x04, 0x011104f1 },
+        { 0x419edc,   1, 0x04, 0x00000000 },
+        { 0x419f00,   1, 0x04, 0x00000000 },
+        { 0x419f2c,   1, 0x04, 0x00000000 },
+        {}
+};
+
+struct nvc0_graph_init *
+nvc1_graph_init_mmio[] = {
+        nvc0_graph_init_regs,
+        nvc0_graph_init_unk40xx,
+        nvc0_graph_init_unk44xx,
+        nvc0_graph_init_unk78xx,
+        nvc0_graph_init_unk60xx,
+        nvc3_graph_init_unk58xx,
+        nvc0_graph_init_unk80xx,
+        nvc1_graph_init_gpc,
+        nvc1_graph_init_tpc,
+        nvc0_graph_init_unk88xx,
+        nvc0_graph_tpc_0,
+        NULL
+};
+
+struct nouveau_oclass *
+nvc1_graph_oclass = &(struct nvc0_graph_oclass) {
+        .base.handle = NV_ENGINE(GR, 0xc1),
+        .base.ofuncs = &(struct nouveau_ofuncs) {
+                .ctor = nvc0_graph_ctor,
+                .dtor = nvc0_graph_dtor,
+                .init = nvc0_graph_init,
+                .fini = _nouveau_graph_fini,
+        },
+        .cclass = &nvc1_grctx_oclass,
+        .sclass = nvc1_graph_sclass,
+        .mmio = nvc1_graph_init_mmio,
+        .fecs.ucode = &nvc0_graph_fecs_ucode,
+        .gpccs.ucode = &nvc0_graph_gpccs_ucode,
+}.base;
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/nvc3.c b/drivers/gpu/drm/nouveau/core/engine/graph/nvc3.c
new file mode 100644
index 000000000000..d44b3b3ee800
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/core/engine/graph/nvc3.c
@@ -0,0 +1,110 @@
+/*
+ * Copyright 2013 Red Hat Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Ben Skeggs <bskeggs@redhat.com>
+ */
+
+#include "nvc0.h"
+
+/*******************************************************************************
+ * PGRAPH engine/subdev functions
+ ******************************************************************************/
+
+struct nvc0_graph_init
+nvc3_graph_init_unk58xx[] = {
+        { 0x405844,   1, 0x04, 0x00ffffff },
+        { 0x405850,   1, 0x04, 0x00000000 },
+        { 0x405900,   1, 0x04, 0x00002834 },
+        { 0x405908,   1, 0x04, 0x00000000 },
+        {}
+};
+
+static struct nvc0_graph_init
+nvc3_graph_init_tpc[] = {
+        { 0x419d08,   2, 0x04, 0x00000000 },
+        { 0x419d10,   1, 0x04, 0x00000014 },
+        { 0x419ab0,   1, 0x04, 0x00000000 },
+        { 0x419ac8,   1, 0x04, 0x00000000 },
+        { 0x419ab8,   1, 0x04, 0x000000e7 },
+        { 0x419abc,   2, 0x04, 0x00000000 },
+        { 0x41980c,   3, 0x04, 0x00000000 },
+        { 0x419844,   1, 0x04, 0x00000000 },
+        { 0x41984c,   1, 0x04, 0x00005bc5 },
+        { 0x419850,   4, 0x04, 0x00000000 },
+        { 0x419880,   1, 0x04, 0x00000002 },
+        { 0x419c98,   1, 0x04, 0x00000000 },
+        { 0x419ca8,   1, 0x04, 0x80000000 },
+        { 0x419cb4,   1, 0x04, 0x00000000 },
+        { 0x419cb8,   1, 0x04, 0x00008bf4 },
+        { 0x419cbc,   1, 0x04, 0x28137606 },
+        { 0x419cc0,   2, 0x04, 0x00000000 },
+        { 0x419bd4,   1, 0x04, 0x00800000 },
+        { 0x419bdc,   1, 0x04, 0x00000000 },
+        { 0x419d2c,   1, 0x04, 0x00000000 },
+        { 0x419c0c,   1, 0x04, 0x00000000 },
+        { 0x419e00,   1, 0x04, 0x00000000 },
+        { 0x419ea0,   1, 0x04, 0x00000000 },
+        { 0x419ea4,   1, 0x04, 0x00000100 },
+        { 0x419ea8,   1, 0x04, 0x00001100 },
+        { 0x419eac,   1, 0x04, 0x11100702 },
+        { 0x419eb0,   1, 0x04, 0x00000003 },
+        { 0x419eb4,   4, 0x04, 0x00000000 },
+        { 0x419ec8,   1, 0x04, 0x0e063818 },
+        { 0x419ecc,   1, 0x04, 0x0e060e06 },
+        { 0x419ed0,   1, 0x04, 0x00003818 },
+        { 0x419ed4,   1, 0x04, 0x011104f1 },
+        { 0x419edc,   1, 0x04, 0x00000000 },
+        { 0x419f00,   1, 0x04, 0x00000000 },
+        { 0x419f2c,   1, 0x04, 0x00000000 },
+        {}
+};
+
+static struct nvc0_graph_init *
+nvc3_graph_init_mmio[] = {
+        nvc0_graph_init_regs,
+        nvc0_graph_init_unk40xx,
+        nvc0_graph_init_unk44xx,
+        nvc0_graph_init_unk78xx,
+        nvc0_graph_init_unk60xx,
+        nvc3_graph_init_unk58xx,
+        nvc0_graph_init_unk80xx,
+        nvc0_graph_init_gpc,
+        nvc3_graph_init_tpc,
+        nvc0_graph_init_unk88xx,
+        nvc0_graph_tpc_0,
+        NULL
+};
+
+struct nouveau_oclass *
+nvc3_graph_oclass = &(struct nvc0_graph_oclass) {
+        .base.handle = NV_ENGINE(GR, 0xc3),
+        .base.ofuncs = &(struct nouveau_ofuncs) {
+                .ctor = nvc0_graph_ctor,
+                .dtor = nvc0_graph_dtor,
+                .init = nvc0_graph_init,
+                .fini = _nouveau_graph_fini,
+        },
+        .cclass = &nvc3_grctx_oclass,
+        .sclass = nvc0_graph_sclass,
+        .mmio = nvc3_graph_init_mmio,
+        .fecs.ucode = &nvc0_graph_fecs_ucode,
+        .gpccs.ucode = &nvc0_graph_gpccs_ucode,
+}.base;
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/nvc8.c b/drivers/gpu/drm/nouveau/core/engine/graph/nvc8.c
new file mode 100644
index 000000000000..02845e567314
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/core/engine/graph/nvc8.c
@@ -0,0 +1,141 @@
+/*
+ * Copyright 2013 Red Hat Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Ben Skeggs <bskeggs@redhat.com>
+ */
+
+#include "nvc0.h"
+
+/*******************************************************************************
+ * Graphics object classes
+ ******************************************************************************/
+
+struct nouveau_oclass
+nvc8_graph_sclass[] = {
+        { 0x902d, &nouveau_object_ofuncs },
+        { 0x9039, &nouveau_object_ofuncs },
+        { 0x9097, &nouveau_object_ofuncs },
+        { 0x90c0, &nouveau_object_ofuncs },
+        { 0x9197, &nouveau_object_ofuncs },
+        { 0x9297, &nouveau_object_ofuncs },
+        {}
+};
+
+/*******************************************************************************
+ * PGRAPH engine/subdev functions
+ ******************************************************************************/
+
+static struct nvc0_graph_init
+nvc8_graph_init_gpc[] = {
+        { 0x4184a0,   1, 0x04, 0x00000000 },
+        { 0x418604,   1, 0x04, 0x00000000 },
+        { 0x418680,   1, 0x04, 0x00000000 },
+        { 0x418714,   1, 0x04, 0x80000000 },
+        { 0x418384,   1, 0x04, 0x00000000 },
+        { 0x418814,   3, 0x04, 0x00000000 },
+        { 0x418b04,   1, 0x04, 0x00000000 },
+        { 0x4188c8,   2, 0x04, 0x00000000 },
+        { 0x4188d0,   1, 0x04, 0x00010000 },
+        { 0x4188d4,   1, 0x04, 0x00000001 },
+        { 0x418910,   1, 0x04, 0x00010001 },
+        { 0x418914,   1, 0x04, 0x00000301 },
+        { 0x418918,   1, 0x04, 0x00800000 },
+        { 0x418980,   1, 0x04, 0x77777770 },
+        { 0x418984,   3, 0x04, 0x77777777 },
+        { 0x418c04,   1, 0x04, 0x00000000 },
+        { 0x418c88,   1, 0x04, 0x00000000 },
+        { 0x418d00,   1, 0x04, 0x00000000 },
+        { 0x418f08,   1, 0x04, 0x00000000 },
+        { 0x418e00,   1, 0x04, 0x00000050 },
+        { 0x418e08,   1, 0x04, 0x00000000 },
+        { 0x41900c,   1, 0x04, 0x00000000 },
+        { 0x419018,   1, 0x04, 0x00000000 },
+        {}
+};
+
+static struct nvc0_graph_init
+nvc8_graph_init_tpc[] = {
+        { 0x419d08,   2, 0x04, 0x00000000 },
+        { 0x419d10,   1, 0x04, 0x00000014 },
+        { 0x419ab0,   1, 0x04, 0x00000000 },
+        { 0x419ab8,   1, 0x04, 0x000000e7 },
+        { 0x419abc,   2, 0x04, 0x00000000 },
+        { 0x41980c,   3, 0x04, 0x00000000 },
+        { 0x419844,   1, 0x04, 0x00000000 },
+        { 0x41984c,   1, 0x04, 0x00005bc5 },
+        { 0x419850,   4, 0x04, 0x00000000 },
+        { 0x419c98,   1, 0x04, 0x00000000 },
+        { 0x419ca8,   1, 0x04, 0x80000000 },
+        { 0x419cb4,   1, 0x04, 0x00000000 },
+        { 0x419cb8,   1, 0x04, 0x00008bf4 },
+        { 0x419cbc,   1, 0x04, 0x28137606 },
+        { 0x419cc0,   2, 0x04, 0x00000000 },
+        { 0x419bd4,   1, 0x04, 0x00800000 },
+        { 0x419bdc,   1, 0x04, 0x00000000 },
+        { 0x419d2c,   1, 0x04, 0x00000000 },
+        { 0x419c0c,   1, 0x04, 0x00000000 },
+        { 0x419e00,   1, 0x04, 0x00000000 },
+        { 0x419ea0,   1, 0x04, 0x00000000 },
+        { 0x419ea4,   1, 0x04, 0x00000100 },
+        { 0x419ea8,   1, 0x04, 0x00001100 },
+        { 0x419eac,   1, 0x04, 0x11100f02 },
+        { 0x419eb0,   1, 0x04, 0x00000003 },
+        { 0x419eb4,   4, 0x04, 0x00000000 },
+        { 0x419ec8,   1, 0x04, 0x06060618 },
+        { 0x419ed0,   1, 0x04, 0x0eff0e38 },
+        { 0x419ed4,   1, 0x04, 0x011104f1 },
+        { 0x419edc,   1, 0x04, 0x00000000 },
+        { 0x419f00,   1, 0x04, 0x00000000 },
+        { 0x419f2c,   1, 0x04, 0x00000000 },
+        {}
+};
+
+static struct nvc0_graph_init *
+nvc8_graph_init_mmio[] = {
+        nvc0_graph_init_regs,
+        nvc0_graph_init_unk40xx,
+        nvc0_graph_init_unk44xx,
+        nvc0_graph_init_unk78xx,
+        nvc0_graph_init_unk60xx,
+        nvc0_graph_init_unk58xx,
+        nvc0_graph_init_unk80xx,
+        nvc8_graph_init_gpc,
+        nvc8_graph_init_tpc,
+        nvc0_graph_init_unk88xx,
+        nvc0_graph_tpc_0,
+        NULL
+};
+
+struct nouveau_oclass *
+nvc8_graph_oclass = &(struct nvc0_graph_oclass) {
+        .base.handle = NV_ENGINE(GR, 0xc8),
+        .base.ofuncs = &(struct nouveau_ofuncs) {
+                .ctor = nvc0_graph_ctor,
+                .dtor = nvc0_graph_dtor,
+                .init = nvc0_graph_init,
+                .fini = _nouveau_graph_fini,
+        },
+        .cclass = &nvc8_grctx_oclass,
+        .sclass = nvc8_graph_sclass,
+        .mmio = nvc8_graph_init_mmio,
+        .fecs.ucode = &nvc0_graph_fecs_ucode,
+        .gpccs.ucode = &nvc0_graph_gpccs_ucode,
+}.base;
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/nvd7.c b/drivers/gpu/drm/nouveau/core/engine/graph/nvd7.c
new file mode 100644
index 000000000000..5052d7ab4d72
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/core/engine/graph/nvd7.c
@@ -0,0 +1,167 @@
+/*
+ * Copyright 2013 Red Hat Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Ben Skeggs <bskeggs@redhat.com>
+ */
+
+#include "nvc0.h"
+
+/*******************************************************************************
+ * PGRAPH engine/subdev functions
+ ******************************************************************************/
+
+#include "fuc/hubnvd7.fuc.h"
+
+struct nvc0_graph_ucode
+nvd7_graph_fecs_ucode = {
+        .code.data = nvd7_grhub_code,
+        .code.size = sizeof(nvd7_grhub_code),
+        .data.data = nvd7_grhub_data,
+        .data.size = sizeof(nvd7_grhub_data),
+};
+
+#include "fuc/gpcnvd7.fuc.h"
+
+struct nvc0_graph_ucode
+nvd7_graph_gpccs_ucode = {
+        .code.data = nvd7_grgpc_code,
+        .code.size = sizeof(nvd7_grgpc_code),
+        .data.data = nvd7_grgpc_data,
+        .data.size = sizeof(nvd7_grgpc_data),
+};
+
+static struct nvc0_graph_init
+nvd7_graph_init_gpc[] = {
+        { 0x418408,   1, 0x04, 0x00000000 },
+        { 0x4184a0,   1, 0x04, 0x00000000 },
+        { 0x4184a4,   2, 0x04, 0x00000000 },
+        { 0x418604,   1, 0x04, 0x00000000 },
+        { 0x418680,   1, 0x04, 0x00000000 },
+        { 0x418714,   1, 0x04, 0x00000000 },
+        { 0x418384,   1, 0x04, 0x00000000 },
+        { 0x418814,   3, 0x04, 0x00000000 },
+        { 0x418b04,   1, 0x04, 0x00000000 },
+        { 0x4188c8,   2, 0x04, 0x00000000 },
+        { 0x4188d0,   1, 0x04, 0x00010000 },
+        { 0x4188d4,   1, 0x04, 0x00000001 },
+        { 0x418910,   1, 0x04, 0x00010001 },
+        { 0x418914,   1, 0x04, 0x00000301 },
+        { 0x418918,   1, 0x04, 0x00800000 },
+        { 0x418980,   1, 0x04, 0x77777770 },
+        { 0x418984,   3, 0x04, 0x77777777 },
+        { 0x418c04,   1, 0x04, 0x00000000 },
+        { 0x418c64,   1, 0x04, 0x00000000 },
+        { 0x418c68,   1, 0x04, 0x00000000 },
+        { 0x418c88,   1, 0x04, 0x00000000 },
+        { 0x418cb4,   2, 0x04, 0x00000000 },
+        { 0x418d00,   1, 0x04, 0x00000000 },
+        { 0x418d28,   1, 0x04, 0x00000000 },
+        { 0x418f00,   1, 0x04, 0x00000000 },
+        { 0x418f08,   1, 0x04, 0x00000000 },
+        { 0x418f20,   2, 0x04, 0x00000000 },
+        { 0x418e00,   1, 0x04, 0x00000003 },
+        { 0x418e08,   1, 0x04, 0x00000000 },
+        { 0x418e1c,   1, 0x04, 0x00000000 },
+        { 0x418e20,   1, 0x04, 0x00000000 },
+        { 0x41900c,   1, 0x04, 0x00000000 },
+        { 0x419018,   1, 0x04, 0x00000000 },
+        {}
+};
+
+static struct nvc0_graph_init
+nvd7_graph_init_tpc[] = {
+        { 0x419d08,   2, 0x04, 0x00000000 },
+        { 0x419d10,   1, 0x04, 0x00000014 },
+        { 0x419ab0,   1, 0x04, 0x00000000 },
+        { 0x419ac8,   1, 0x04, 0x00000000 },
+        { 0x419ab8,   1, 0x04, 0x000000e7 },
+        { 0x419abc,   2, 0x04, 0x00000000 },
+        { 0x419ab4,   1, 0x04, 0x00000000 },
+        { 0x41980c,   1, 0x04, 0x00000010 },
+        { 0x419844,   1, 0x04, 0x00000000 },
+        { 0x41984c,   1, 0x04, 0x00005bc8 },
+        { 0x419850,   2, 0x04, 0x00000000 },
+        { 0x419c98,   1, 0x04, 0x00000000 },
+        { 0x419ca8,   1, 0x04, 0x80000000 },
+        { 0x419cb4,   1, 0x04, 0x00000000 },
+        { 0x419cb8,   1, 0x04, 0x00008bf4 },
+        { 0x419cbc,   1, 0x04, 0x28137606 },
+        { 0x419cc0,   2, 0x04, 0x00000000 },
+        { 0x419c0c,   1, 0x04, 0x00000000 },
+        { 0x419e00,   1, 0x04, 0x00000000 },
+        { 0x419ea0,   1, 0x04, 0x00000000 },
+        { 0x419ea4,   1, 0x04, 0x00000100 },
+        { 0x419ea8,   1, 0x04, 0x02001100 },
+        { 0x419eac,   1, 0x04, 0x11100702 },
+        { 0x419eb0,   1, 0x04, 0x00000003 },
+        { 0x419eb4,   4, 0x04, 0x00000000 },
+        { 0x419ec8,   1, 0x04, 0x0e063818 },
+        { 0x419ecc,   1, 0x04, 0x0e060e06 },
+        { 0x419ed0,   1, 0x04, 0x00003818 },
+        { 0x419ed4,   1, 0x04, 0x011104f1 },
+        { 0x419edc,   1, 0x04, 0x00000000 },
+        { 0x419f00,   1, 0x04, 0x00000000 },
+        { 0x419f2c,   1, 0x04, 0x00000000 },
+        {}
+};
+
+static struct nvc0_graph_init
+nvd7_graph_init_tpc_0[] = {
+        { 0x40402c,   1, 0x04, 0x00000000 },
+        { 0x4040f0,   1, 0x04, 0x00000000 },
+        { 0x404174,   1, 0x04, 0x00000000 },
+        { 0x503018,   1, 0x04, 0x00000001 },
+        {}
+};
+
+static struct nvc0_graph_init *
+nvd7_graph_init_mmio[] = {
+        nvc0_graph_init_regs,
+        nvc0_graph_init_unk40xx,
+        nvc0_graph_init_unk44xx,
+        nvc0_graph_init_unk78xx,
+        nvc0_graph_init_unk60xx,
+        nvd9_graph_init_unk64xx,
+        nvd9_graph_init_unk58xx,
+        nvc0_graph_init_unk80xx,
+        nvd7_graph_init_gpc,
+        nvd7_graph_init_tpc,
+        nve4_graph_init_unk,
+        nvc0_graph_init_unk88xx,
+        nvd7_graph_init_tpc_0,
+        NULL
+};
+
+struct nouveau_oclass *
+nvd7_graph_oclass = &(struct nvc0_graph_oclass) {
+        .base.handle = NV_ENGINE(GR, 0xd7),
+        .base.ofuncs = &(struct nouveau_ofuncs) {
+                .ctor = nvc0_graph_ctor,
+                .dtor = nvc0_graph_dtor,
+                .init = nvc0_graph_init,
+                .fini = _nouveau_graph_fini,
+        },
+        .cclass = &nvd7_grctx_oclass,
+        .sclass = nvc8_graph_sclass,
+        .mmio = nvd7_graph_init_mmio,
+        .fecs.ucode = &nvd7_graph_fecs_ucode,
+        .gpccs.ucode = &nvd7_graph_gpccs_ucode,
+}.base;
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/nvd9.c b/drivers/gpu/drm/nouveau/core/engine/graph/nvd9.c
new file mode 100644
index 000000000000..652098e0df3f
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/core/engine/graph/nvd9.c
@@ -0,0 +1,165 @@
+/*
+ * Copyright 2013 Red Hat Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Ben Skeggs <bskeggs@redhat.com>
+ */
+
+#include "nvc0.h"
+
+/*******************************************************************************
+ * PGRAPH engine/subdev functions
+ ******************************************************************************/
+
+struct nvc0_graph_init
+nvd9_graph_init_unk64xx[] = {
+        { 0x4064f0,   3, 0x04, 0x00000000 },
+        {}
+};
+
+struct nvc0_graph_init
+nvd9_graph_init_unk58xx[] = {
+        { 0x405844,   1, 0x04, 0x00ffffff },
+        { 0x405850,   1, 0x04, 0x00000000 },
+        { 0x405900,   1, 0x04, 0x00002834 },
+        { 0x405908,   1, 0x04, 0x00000000 },
+        { 0x405928,   1, 0x04, 0x00000000 },
+        { 0x40592c,   1, 0x04, 0x00000000 },
+        {}
+};
+
+static struct nvc0_graph_init
+nvd9_graph_init_gpc[] = {
+        { 0x418408,   1, 0x04, 0x00000000 },
+        { 0x4184a0,   1, 0x04, 0x00000000 },
+        { 0x4184a4,   2, 0x04, 0x00000000 },
+        { 0x418604,   1, 0x04, 0x00000000 },
+        { 0x418680,   1, 0x04, 0x00000000 },
+        { 0x418714,   1, 0x04, 0x00000000 },
+        { 0x418384,   1, 0x04, 0x00000000 },
+        { 0x418814,   3, 0x04, 0x00000000 },
+        { 0x418b04,   1, 0x04, 0x00000000 },
+        { 0x4188c8,   2, 0x04, 0x00000000 },
+        { 0x4188d0,   1, 0x04, 0x00010000 },
+        { 0x4188d4,   1, 0x04, 0x00000001 },
+        { 0x418910,   1, 0x04, 0x00010001 },
+        { 0x418914,   1, 0x04, 0x00000301 },
+        { 0x418918,   1, 0x04, 0x00800000 },
+        { 0x418980,   1, 0x04, 0x77777770 },
+        { 0x418984,   3, 0x04, 0x77777777 },
+        { 0x418c04,   1, 0x04, 0x00000000 },
+        { 0x418c64,   1, 0x04, 0x00000000 },
+        { 0x418c68,   1, 0x04, 0x00000000 },
+        { 0x418c88,   1, 0x04, 0x00000000 },
+        { 0x418cb4,   2, 0x04, 0x00000000 },
+        { 0x418d00,   1, 0x04, 0x00000000 },
+        { 0x418d28,   1, 0x04, 0x00000000 },
+        { 0x418d2c,   1, 0x04, 0x00000000 },
+        { 0x418f00,   1, 0x04, 0x00000000 },
+        { 0x418f08,   1, 0x04, 0x00000000 },
+        { 0x418f20,   2, 0x04, 0x00000000 },
+        { 0x418e00,   1, 0x04, 0x00000003 },
+        { 0x418e08,   1, 0x04, 0x00000000 },
+        { 0x418e1c,   1, 0x04, 0x00000000 },
+        { 0x418e20,   1, 0x04, 0x00000000 },
+        { 0x41900c,   1, 0x04, 0x00000000 },
+        { 0x419018,   1, 0x04, 0x00000000 },
+        {}
+};
+
+static struct nvc0_graph_init
+nvd9_graph_init_tpc[] = {
+        { 0x419d08,   2, 0x04, 0x00000000 },
+        { 0x419d10,   1, 0x04, 0x00000014 },
+        { 0x419ab0,   1, 0x04, 0x00000000 },
+        { 0x419ac8,   1, 0x04, 0x00000000 },
+        { 0x419ab8,   1, 0x04, 0x000000e7 },
+        { 0x419abc,   2, 0x04, 0x00000000 },
+        { 0x419ab4,   1, 0x04, 0x00000000 },
+        { 0x41980c,   1, 0x04, 0x00000010 },
+        { 0x419810,   1, 0x04, 0x00000000 },
+        { 0x419814,   1, 0x04, 0x00000004 },
+        { 0x419844,   1, 0x04, 0x00000000 },
+        { 0x41984c,   1, 0x04, 0x0000a918 },
+        { 0x419850,   4, 0x04, 0x00000000 },
+        { 0x419880,   1, 0x04, 0x00000002 },
+        { 0x419c98,   1, 0x04, 0x00000000 },
+        { 0x419ca8,   1, 0x04, 0x80000000 },
+        { 0x419cb4,   1, 0x04, 0x00000000 },
+        { 0x419cb8,   1, 0x04, 0x00008bf4 },
+        { 0x419cbc,   1, 0x04, 0x28137606 },
+        { 0x419cc0,   2, 0x04, 0x00000000 },
+        { 0x419bd4,   1, 0x04, 0x00800000 },
+        { 0x419bdc,   1, 0x04, 0x00000000 },
+        { 0x419bf8,   1, 0x04, 0x00000000 },
+        { 0x419bfc,   1, 0x04, 0x00000000 },
+        { 0x419d2c,   1, 0x04, 0x00000000 },
+        { 0x419d48,   1, 0x04, 0x00000000 },
+        { 0x419d4c,   1, 0x04, 0x00000000 },
+        { 0x419c0c,   1, 0x04, 0x00000000 },
+        { 0x419e00,   1, 0x04, 0x00000000 },
+        { 0x419ea0,   1, 0x04, 0x00000000 },
+        { 0x419ea4,   1, 0x04, 0x00000100 },
+        { 0x419ea8,   1, 0x04, 0x02001100 },
+        { 0x419eac,   1, 0x04, 0x11100702 },
+        { 0x419eb0,   1, 0x04, 0x00000003 },
+        { 0x419eb4,   4, 0x04, 0x00000000 },
+        { 0x419ec8,   1, 0x04, 0x0e063818 },
+        { 0x419ecc,   1, 0x04, 0x0e060e06 },
+        { 0x419ed0,   1, 0x04, 0x00003818 },
+        { 0x419ed4,   1, 0x04, 0x011104f1 },
+        { 0x419edc,   1, 0x04, 0x00000000 },
+        { 0x419f00,   1, 0x04, 0x00000000 },
+        { 0x419f2c,   1, 0x04, 0x00000000 },
+        {}
+};
+
+static struct nvc0_graph_init *
+nvd9_graph_init_mmio[] = {
+        nvc0_graph_init_regs,
+        nvc0_graph_init_unk40xx,
+        nvc0_graph_init_unk44xx,
+        nvc0_graph_init_unk78xx,
+        nvc0_graph_init_unk60xx,
+        nvd9_graph_init_unk64xx,
+        nvd9_graph_init_unk58xx,
+        nvc0_graph_init_unk80xx,
+        nvd9_graph_init_gpc,
+        nvd9_graph_init_tpc,
+        nvc0_graph_init_unk88xx,
+        nvc0_graph_tpc_0,
+        NULL
+};
+
+struct nouveau_oclass *
+nvd9_graph_oclass = &(struct nvc0_graph_oclass) {
+        .base.handle = NV_ENGINE(GR, 0xd9),
+        .base.ofuncs = &(struct nouveau_ofuncs) {
+                .ctor = nvc0_graph_ctor,
+                .dtor = nvc0_graph_dtor,
+                .init = nvc0_graph_init,
+                .fini = _nouveau_graph_fini,
+        },
+        .cclass = &nvd9_grctx_oclass,
+        .sclass = nvc8_graph_sclass,
+        .mmio = nvd9_graph_init_mmio,
+        .fecs.ucode = &nvc0_graph_fecs_ucode,
+        .gpccs.ucode = &nvc0_graph_gpccs_ucode,
+}.base;
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/nve0.c b/drivers/gpu/drm/nouveau/core/engine/graph/nve0.c
deleted file mode 100644
index 678c16f63055..000000000000
--- a/drivers/gpu/drm/nouveau/core/engine/graph/nve0.c
+++ /dev/null
@@ -1,807 +0,0 @@
-/*
- * Copyright 2012 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-
-#include "nvc0.h"
-#include "fuc/hubnve0.fuc.h"
-#include "fuc/gpcnve0.fuc.h"
-
-/*******************************************************************************
- * Graphics object classes
- ******************************************************************************/
-
-static struct nouveau_oclass
-nve0_graph_sclass[] = {
-        { 0x902d, &nouveau_object_ofuncs },
-        { 0xa040, &nouveau_object_ofuncs },
-        { 0xa097, &nouveau_object_ofuncs },
-        { 0xa0c0, &nouveau_object_ofuncs },
-        { 0xa0b5, &nouveau_object_ofuncs },
-        {}
-};
-
-/*******************************************************************************
- * PGRAPH context
- ******************************************************************************/
-
-static struct nouveau_oclass
-nve0_graph_cclass = {
-        .handle = NV_ENGCTX(GR, 0xe0),
-        .ofuncs = &(struct nouveau_ofuncs) {
-                .ctor = nvc0_graph_context_ctor,
-                .dtor = nvc0_graph_context_dtor,
-                .init = _nouveau_graph_context_init,
-                .fini = _nouveau_graph_context_fini,
-                .rd32 = _nouveau_graph_context_rd32,
-                .wr32 = _nouveau_graph_context_wr32,
-        },
-};
-
-/*******************************************************************************
- * PGRAPH engine/subdev functions
- ******************************************************************************/
-
-static void
-nve0_graph_ctxctl_isr(struct nvc0_graph_priv *priv)
-{
-        u32 ustat = nv_rd32(priv, 0x409c18);
-
-        if (ustat & 0x00000001)
-                nv_error(priv, "CTXCTRL ucode error\n");
-        if (ustat & 0x00080000)
-                nv_error(priv, "CTXCTRL watchdog timeout\n");
-        if (ustat & ~0x00080001)
-                nv_error(priv, "CTXCTRL 0x%08x\n", ustat);
-
-        nvc0_graph_ctxctl_debug(priv);
-        nv_wr32(priv, 0x409c20, ustat);
-}
-
-static const struct nouveau_enum nve0_mp_warp_error[] = {
-        { 0x00, "NO_ERROR" },
-        { 0x01, "STACK_MISMATCH" },
-        { 0x05, "MISALIGNED_PC" },
-        { 0x08, "MISALIGNED_GPR" },
-        { 0x09, "INVALID_OPCODE" },
-        { 0x0d, "GPR_OUT_OF_BOUNDS" },
-        { 0x0e, "MEM_OUT_OF_BOUNDS" },
-        { 0x0f, "UNALIGNED_MEM_ACCESS" },
-        { 0x11, "INVALID_PARAM" },
-        {}
-};
-
-static const struct nouveau_enum nve0_mp_global_error[] = {
-        { 2, "MULTIPLE_WARP_ERRORS" },
-        { 3, "OUT_OF_STACK_SPACE" },
-        {}
-};
-
-static const struct nouveau_enum nve0_gpc_rop_error[] = {
-        { 1, "RT_PITCH_OVERRUN" },
-        { 4, "RT_WIDTH_OVERRUN" },
-        { 5, "RT_HEIGHT_OVERRUN" },
-        { 7, "ZETA_STORAGE_TYPE_MISMATCH" },
-        { 8, "RT_STORAGE_TYPE_MISMATCH" },
-        { 10, "RT_LINEAR_MISMATCH" },
-        {}
-};
-
-static const struct nouveau_enum nve0_sked_error[] = {
-        { 7, "CONSTANT_BUFFER_SIZE" },
-        { 9, "LOCAL_MEMORY_SIZE_POS" },
-        { 10, "LOCAL_MEMORY_SIZE_NEG" },
-        { 11, "WARP_CSTACK_SIZE" },
-        { 12, "TOTAL_TEMP_SIZE" },
-        { 13, "REGISTER_COUNT" },
-        { 18, "TOTAL_THREADS" },
-        { 20, "PROGRAM_OFFSET" },
-        { 21, "SHARED_MEMORY_SIZE" },
-        { 25, "SHARED_CONFIG_TOO_SMALL" },
-        { 26, "TOTAL_REGISTER_COUNT" },
-        {}
-};
-
-static void
-nve0_graph_mp_trap(struct nvc0_graph_priv *priv, int gpc, int tp)
-{
-        int i;
-        u32 werr = nv_rd32(priv, TPC_UNIT(gpc, tp, 0x648));
-        u32 gerr = nv_rd32(priv, TPC_UNIT(gpc, tp, 0x650));
-
-        nv_error(priv, "GPC%i/TP%i/MP trap:", gpc, tp);
-
-        for (i = 0; i <= 31; ++i) {
-                if (!(gerr & (1 << i)))
-                        continue;
-                pr_cont(" ");
-                nouveau_enum_print(nve0_mp_global_error, i);
-        }
-        if (werr) {
-                pr_cont(" ");
-                nouveau_enum_print(nve0_mp_warp_error, werr & 0xffff);
-        }
-        pr_cont("\n");
-
-        /* disable MP trap to avoid spam */
-        nv_mask(priv, TPC_UNIT(gpc, tp, 0x50c), 0x2, 0x0);
-
-        /* TODO: figure out how to resume after an MP trap */
-}
-
-static void
-nve0_graph_tp_trap(struct nvc0_graph_priv *priv, int gpc, int tp)
-{
-        u32 stat = nv_rd32(priv, TPC_UNIT(gpc, tp, 0x508));
-
-        if (stat & 0x1) {
-                u32 trap = nv_rd32(priv, TPC_UNIT(gpc, tp, 0x224));
-                nv_error(priv, "GPC%i/TP%i/TEX trap: %08x\n",
-                         gpc, tp, trap);
-
-                nv_wr32(priv, TPC_UNIT(gpc, tp, 0x224), 0xc0000000);
-                stat &= ~0x1;
-        }
-
-        if (stat & 0x2) {
-                nve0_graph_mp_trap(priv, gpc, tp);
-                stat &= ~0x2;
-        }
-
-        if (stat & 0x4) {
-                u32 trap = nv_rd32(priv, TPC_UNIT(gpc, tp, 0x084));
-                nv_error(priv, "GPC%i/TP%i/POLY trap: %08x\n",
-                         gpc, tp, trap);
-
-                nv_wr32(priv, TPC_UNIT(gpc, tp, 0x084), 0xc0000000);
-                stat &= ~0x4;
-        }
-
-        if (stat & 0x8) {
-                u32 trap = nv_rd32(priv, TPC_UNIT(gpc, tp, 0x48c));
-                nv_error(priv, "GPC%i/TP%i/L1C trap: %08x\n",
-                         gpc, tp, trap);
-
-                nv_wr32(priv, TPC_UNIT(gpc, tp, 0x48c), 0xc0000000);
-                stat &= ~0x8;
-        }
-
-        if (stat) {
-                nv_error(priv, "GPC%i/TP%i: unknown stat %08x\n",
-                         gpc, tp, stat);
-        }
-}
-
-static void
-nve0_graph_gpc_trap(struct nvc0_graph_priv *priv)
-{
-        const u32 mask = nv_rd32(priv, 0x400118);
-        int gpc;
-
-        for (gpc = 0; gpc < 4; ++gpc) {
-                u32 stat;
-                int tp;
-
-                if (!(mask & (1 << gpc)))
-                        continue;
-                stat = nv_rd32(priv, GPC_UNIT(gpc, 0x2c90));
-
-                if (stat & 0x0001) {
-                        u32 trap[4];
-                        int i;
-
-                        trap[0] = nv_rd32(priv, GPC_UNIT(gpc, 0x0420));
-                        trap[1] = nv_rd32(priv, GPC_UNIT(gpc, 0x0434));
-                        trap[2] = nv_rd32(priv, GPC_UNIT(gpc, 0x0438));
-                        trap[3] = nv_rd32(priv, GPC_UNIT(gpc, 0x043c));
-
-                        nv_error(priv, "GPC%i/PROP trap:", gpc);
-                        for (i = 0; i <= 29; ++i) {
-                                if (!(trap[0] & (1 << i)))
-                                        continue;
-                                pr_cont(" ");
-                                nouveau_enum_print(nve0_gpc_rop_error, i);
-                        }
-                        pr_cont("\n");
-
-                        nv_error(priv, "x = %u, y = %u, "
-                                 "format = %x, storage type = %x\n",
-                                 trap[1] & 0xffff,
-                                 trap[1] >> 16,
-                                 (trap[2] >> 8) & 0x3f,
-                                 trap[3] & 0xff);
-
-                        nv_wr32(priv, GPC_UNIT(gpc, 0x0420), 0xc0000000);
-                        stat &= ~0x0001;
-                }
-
-                if (stat & 0x0002) {
-                        u32 trap = nv_rd32(priv, GPC_UNIT(gpc, 0x0900));
-                        nv_error(priv, "GPC%i/ZCULL trap: %08x\n", gpc,
-                                 trap);
-                        nv_wr32(priv, GPC_UNIT(gpc, 0x0900), 0xc0000000);
-                        stat &= ~0x0002;
-                }
-
-                if (stat & 0x0004) {
-                        u32 trap = nv_rd32(priv, GPC_UNIT(gpc, 0x1028));
-                        nv_error(priv, "GPC%i/CCACHE trap: %08x\n", gpc,
-                                 trap);
-                        nv_wr32(priv, GPC_UNIT(gpc, 0x1028), 0xc0000000);
-                        stat &= ~0x0004;
-                }
-
-                if (stat & 0x0008) {
-                        u32 trap = nv_rd32(priv, GPC_UNIT(gpc, 0x0824));
-                        nv_error(priv, "GPC%i/ESETUP trap %08x\n", gpc,
-                                 trap);
-                        nv_wr32(priv, GPC_UNIT(gpc, 0x0824), 0xc0000000);
-                        stat &= ~0x0008;
-                }
-
-                for (tp = 0; tp < 8; ++tp) {
-                        if (stat & (1 << (16 + tp)))
-                                nve0_graph_tp_trap(priv, gpc, tp);
-                }
-                stat &= ~0xff0000;
-
-                if (stat) {
-                        nv_error(priv, "GPC%i: unknown stat %08x\n",
-                                 gpc, stat);
-                }
-        }
-}
-
-
-static void
-nve0_graph_trap_isr(struct nvc0_graph_priv *priv, int chid, u64 inst,
-                struct nouveau_object *engctx)
-{
-        u32 trap = nv_rd32(priv, 0x400108);
-        int i;
-        int rop;
-
-        if (trap & 0x00000001) {
-                u32 stat = nv_rd32(priv, 0x404000);
-                nv_error(priv, "DISPATCH ch %d [0x%010llx %s] 0x%08x\n",
-                         chid, inst, nouveau_client_name(engctx), stat);
-                nv_wr32(priv, 0x404000, 0xc0000000);
-                nv_wr32(priv, 0x400108, 0x00000001);
-                trap &= ~0x00000001;
-        }
-
-        if (trap & 0x00000010) {
-                u32 stat = nv_rd32(priv, 0x405840);
-                nv_error(priv, "SHADER ch %d [0x%010llx %s] 0x%08x\n",
-                         chid, inst, nouveau_client_name(engctx), stat);
-                nv_wr32(priv, 0x405840, 0xc0000000);
-                nv_wr32(priv, 0x400108, 0x00000010);
-                trap &= ~0x00000010;
-        }
-
-        if (trap & 0x00000100) {
-                u32 stat = nv_rd32(priv, 0x407020);
-                nv_error(priv, "SKED ch %d [0x%010llx %s]:",
-                         chid, inst, nouveau_client_name(engctx));
-
-                for (i = 0; i <= 29; ++i) {
-                        if (!(stat & (1 << i)))
-                                continue;
-                        pr_cont(" ");
-                        nouveau_enum_print(nve0_sked_error, i);
-                }
-                pr_cont("\n");
-
-                if (stat & 0x3fffffff)
-                        nv_wr32(priv, 0x407020, 0x40000000);
-                nv_wr32(priv, 0x400108, 0x00000100);
-                trap &= ~0x00000100;
-        }
-
-        if (trap & 0x01000000) {
-                nv_error(priv, "GPC ch %d [0x%010llx %s]:\n",
-                         chid, inst, nouveau_client_name(engctx));
-                nve0_graph_gpc_trap(priv);
-                trap &= ~0x01000000;
-        }
-
-        if (trap & 0x02000000) {
-                for (rop = 0; rop < priv->rop_nr; rop++) {
-                        u32 statz = nv_rd32(priv, ROP_UNIT(rop, 0x070));
-                        u32 statc = nv_rd32(priv, ROP_UNIT(rop, 0x144));
-                        nv_error(priv,
-                                 "ROP%d ch %d [0x%010llx %s] 0x%08x 0x%08x\n",
-                                 rop, chid, inst, nouveau_client_name(engctx),
-                                 statz, statc);
-                        nv_wr32(priv, ROP_UNIT(rop, 0x070), 0xc0000000);
-                        nv_wr32(priv, ROP_UNIT(rop, 0x144), 0xc0000000);
-                }
-                nv_wr32(priv, 0x400108, 0x02000000);
-                trap &= ~0x02000000;
-        }
-
-        if (trap) {
-                nv_error(priv, "TRAP ch %d [0x%010llx %s] 0x%08x\n",
-                         chid, inst, nouveau_client_name(engctx), trap);
-                nv_wr32(priv, 0x400108, trap);
-        }
-}
-
-static void
-nve0_graph_intr(struct nouveau_subdev *subdev)
-{
-        struct nouveau_fifo *pfifo = nouveau_fifo(subdev);
-        struct nouveau_engine *engine = nv_engine(subdev);
-        struct nouveau_object *engctx;
-        struct nouveau_handle *handle;
-        struct nvc0_graph_priv *priv = (void *)subdev;
-        u64 inst = nv_rd32(priv, 0x409b00) & 0x0fffffff;
-        u32 stat = nv_rd32(priv, 0x400100);
-        u32 addr = nv_rd32(priv, 0x400704);
-        u32 mthd = (addr & 0x00003ffc);
-        u32 subc = (addr & 0x00070000) >> 16;
-        u32 data = nv_rd32(priv, 0x400708);
-        u32 code = nv_rd32(priv, 0x400110);
-        u32 class = nv_rd32(priv, 0x404200 + (subc * 4));
-        int chid;
-
-        engctx = nouveau_engctx_get(engine, inst);
-        chid   = pfifo->chid(pfifo, engctx);
-
-        if (stat & 0x00000010) {
-                handle = nouveau_handle_get_class(engctx, class);
-                if (!handle || nv_call(handle->object, mthd, data)) {
-                        nv_error(priv,
-                                 "ILLEGAL_MTHD ch %d [0x%010llx %s] subc %d class 0x%04x mthd 0x%04x data 0x%08x\n",
-                                 chid, inst, nouveau_client_name(engctx), subc,
-                                 class, mthd, data);
-                }
-                nouveau_handle_put(handle);
-                nv_wr32(priv, 0x400100, 0x00000010);
-                stat &= ~0x00000010;
-        }
-
-        if (stat & 0x00000020) {
-                nv_error(priv,
-                         "ILLEGAL_CLASS ch %d [0x%010llx %s] subc %d class 0x%04x mthd 0x%04x data 0x%08x\n",
-                         chid, inst, nouveau_client_name(engctx), subc, class,
-                         mthd, data);
-                nv_wr32(priv, 0x400100, 0x00000020);
-                stat &= ~0x00000020;
-        }
-
-        if (stat & 0x00100000) {
-                nv_error(priv, "DATA_ERROR [");
-                nouveau_enum_print(nv50_data_error_names, code);
-                pr_cont("] ch %d [0x%010llx %s] subc %d class 0x%04x mthd 0x%04x data 0x%08x\n",
-                        chid, inst, nouveau_client_name(engctx), subc, class,
-                        mthd, data);
-                nv_wr32(priv, 0x400100, 0x00100000);
-                stat &= ~0x00100000;
-        }
-
-        if (stat & 0x00200000) {
-                nve0_graph_trap_isr(priv, chid, inst, engctx);
-                nv_wr32(priv, 0x400100, 0x00200000);
-                stat &= ~0x00200000;
-        }
-
-        if (stat & 0x00080000) {
-                nve0_graph_ctxctl_isr(priv);
-                nv_wr32(priv, 0x400100, 0x00080000);
-                stat &= ~0x00080000;
-        }
-
-        if (stat) {
-                nv_error(priv, "unknown stat 0x%08x\n", stat);
-                nv_wr32(priv, 0x400100, stat);
-        }
-
-        nv_wr32(priv, 0x400500, 0x00010001);
-        nouveau_engctx_put(engctx);
-}
-
-static int
-nve0_graph_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
-               struct nouveau_oclass *oclass, void *data, u32 size,
-               struct nouveau_object **pobject)
-{
-        struct nouveau_device *device = nv_device(parent);
-        struct nvc0_graph_priv *priv;
-        int ret, i;
-
-        ret = nouveau_graph_create(parent, engine, oclass, true, &priv);
-        *pobject = nv_object(priv);
-        if (ret)
-                return ret;
-
-        nv_subdev(priv)->unit = 0x18001000;
-        nv_subdev(priv)->intr = nve0_graph_intr;
-        nv_engine(priv)->cclass = &nve0_graph_cclass;
-        nv_engine(priv)->sclass = nve0_graph_sclass;
-
-        priv->base.units = nvc0_graph_units;
-
-        if (nouveau_boolopt(device->cfgopt, "NvGrUseFW", false)) {
-                nv_info(priv, "using external firmware\n");
-                if (nvc0_graph_ctor_fw(priv, "fuc409c", &priv->fuc409c) ||
-                    nvc0_graph_ctor_fw(priv, "fuc409d", &priv->fuc409d) ||
-                    nvc0_graph_ctor_fw(priv, "fuc41ac", &priv->fuc41ac) ||
-                    nvc0_graph_ctor_fw(priv, "fuc41ad", &priv->fuc41ad))
-                        return -EINVAL;
-                priv->firmware = true;
-        }
-
-        ret = nouveau_gpuobj_new(nv_object(priv), NULL, 0x1000, 256, 0,
-                                &priv->unk4188b4);
-        if (ret)
-                return ret;
-
-        ret = nouveau_gpuobj_new(nv_object(priv), NULL, 0x1000, 256, 0,
-                                &priv->unk4188b8);
-        if (ret)
-                return ret;
-
-        for (i = 0; i < 0x1000; i += 4) {
-                nv_wo32(priv->unk4188b4, i, 0x00000010);
-                nv_wo32(priv->unk4188b8, i, 0x00000010);
-        }
-
-        priv->gpc_nr =  nv_rd32(priv, 0x409604) & 0x0000001f;
-        priv->rop_nr = (nv_rd32(priv, 0x409604) & 0x001f0000) >> 16;
-        for (i = 0; i < priv->gpc_nr; i++) {
-                priv->tpc_nr[i] = nv_rd32(priv, GPC_UNIT(i, 0x2608));
-                priv->tpc_total += priv->tpc_nr[i];
-        }
-
-        switch (nv_device(priv)->chipset) {
-        case 0xe4:
-                if (priv->tpc_total == 8)
-                        priv->magic_not_rop_nr = 3;
-                else
-                if (priv->tpc_total == 7)
-                        priv->magic_not_rop_nr = 1;
-                break;
-        case 0xe7:
-        case 0xe6:
-                priv->magic_not_rop_nr = 1;
-                break;
-        default:
-                break;
-        }
-
-        return 0;
-}
-
-static void
-nve0_graph_init_obj418880(struct nvc0_graph_priv *priv)
-{
-        int i;
-
-        nv_wr32(priv, GPC_BCAST(0x0880), 0x00000000);
-        nv_wr32(priv, GPC_BCAST(0x08a4), 0x00000000);
-        for (i = 0; i < 4; i++)
-                nv_wr32(priv, GPC_BCAST(0x0888) + (i * 4), 0x00000000);
-        nv_wr32(priv, GPC_BCAST(0x08b4), priv->unk4188b4->addr >> 8);
-        nv_wr32(priv, GPC_BCAST(0x08b8), priv->unk4188b8->addr >> 8);
-}
-
-static void
-nve0_graph_init_regs(struct nvc0_graph_priv *priv)
-{
-        nv_wr32(priv, 0x400080, 0x003083c2);
-        nv_wr32(priv, 0x400088, 0x0001ffe7);
-        nv_wr32(priv, 0x40008c, 0x00000000);
-        nv_wr32(priv, 0x400090, 0x00000030);
-        nv_wr32(priv, 0x40013c, 0x003901f7);
-        nv_wr32(priv, 0x400140, 0x00000100);
-        nv_wr32(priv, 0x400144, 0x00000000);
-        nv_wr32(priv, 0x400148, 0x00000110);
-        nv_wr32(priv, 0x400138, 0x00000000);
-        nv_wr32(priv, 0x400130, 0x00000000);
-        nv_wr32(priv, 0x400134, 0x00000000);
-        nv_wr32(priv, 0x400124, 0x00000002);
-}
-
-static void
-nve0_graph_init_units(struct nvc0_graph_priv *priv)
-{
-        nv_wr32(priv, 0x409ffc, 0x00000000);
-        nv_wr32(priv, 0x409c14, 0x00003e3e);
-        nv_wr32(priv, 0x409c24, 0x000f0000);
-
-        nv_wr32(priv, 0x404000, 0xc0000000);
-        nv_wr32(priv, 0x404600, 0xc0000000);
-        nv_wr32(priv, 0x408030, 0xc0000000);
-        nv_wr32(priv, 0x404490, 0xc0000000);
-        nv_wr32(priv, 0x406018, 0xc0000000);
-        nv_wr32(priv, 0x407020, 0xc0000000);
-        nv_wr32(priv, 0x405840, 0xc0000000);
-        nv_wr32(priv, 0x405844, 0x00ffffff);
-
-        nv_mask(priv, 0x419cc0, 0x00000008, 0x00000008);
-        nv_mask(priv, 0x419eb4, 0x00001000, 0x00001000);
-
-}
-
-static void
-nve0_graph_init_gpc_0(struct nvc0_graph_priv *priv)
-{
-        const u32 magicgpc918 = DIV_ROUND_UP(0x00800000, priv->tpc_total);
-        u32 data[TPC_MAX / 8];
-        u8  tpcnr[GPC_MAX];
-        int i, gpc, tpc;
-
-        nv_wr32(priv, GPC_UNIT(0, 0x3018), 0x00000001);
-
-        memset(data, 0x00, sizeof(data));
-        memcpy(tpcnr, priv->tpc_nr, sizeof(priv->tpc_nr));
-        for (i = 0, gpc = -1; i < priv->tpc_total; i++) {
-                do {
-                        gpc = (gpc + 1) % priv->gpc_nr;
-                } while (!tpcnr[gpc]);
-                tpc = priv->tpc_nr[gpc] - tpcnr[gpc]--;
-
-                data[i / 8] |= tpc << ((i % 8) * 4);
-        }
-
-        nv_wr32(priv, GPC_BCAST(0x0980), data[0]);
-        nv_wr32(priv, GPC_BCAST(0x0984), data[1]);
-        nv_wr32(priv, GPC_BCAST(0x0988), data[2]);
-        nv_wr32(priv, GPC_BCAST(0x098c), data[3]);
-
-        for (gpc = 0; gpc < priv->gpc_nr; gpc++) {
-                nv_wr32(priv, GPC_UNIT(gpc, 0x0914), priv->magic_not_rop_nr << 8 |
-                                                  priv->tpc_nr[gpc]);
-                nv_wr32(priv, GPC_UNIT(gpc, 0x0910), 0x00040000 | priv->tpc_total);
-                nv_wr32(priv, GPC_UNIT(gpc, 0x0918), magicgpc918);
-        }
-
-        nv_wr32(priv, GPC_BCAST(0x3fd4), magicgpc918);
-        nv_wr32(priv, GPC_BCAST(0x08ac), nv_rd32(priv, 0x100800));
-}
-
-static void
-nve0_graph_init_gpc_1(struct nvc0_graph_priv *priv)
-{
-        int gpc, tpc;
-
-        for (gpc = 0; gpc < priv->gpc_nr; gpc++) {
-                nv_wr32(priv, GPC_UNIT(gpc, 0x3038), 0xc0000000);
-                nv_wr32(priv, GPC_UNIT(gpc, 0x0420), 0xc0000000);
-                nv_wr32(priv, GPC_UNIT(gpc, 0x0900), 0xc0000000);
-                nv_wr32(priv, GPC_UNIT(gpc, 0x1028), 0xc0000000);
-                nv_wr32(priv, GPC_UNIT(gpc, 0x0824), 0xc0000000);
-                for (tpc = 0; tpc < priv->tpc_nr[gpc]; tpc++) {
-                        nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x508), 0xffffffff);
-                        nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x50c), 0xffffffff);
-                        nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x224), 0xc0000000);
-                        nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x48c), 0xc0000000);
-                        nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x084), 0xc0000000);
-                        nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x644), 0x001ffffe);
-                        nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x64c), 0x0000000f);
-                }
-                nv_wr32(priv, GPC_UNIT(gpc, 0x2c90), 0xffffffff);
-                nv_wr32(priv, GPC_UNIT(gpc, 0x2c94), 0xffffffff);
-        }
-}
-
-static void
-nve0_graph_init_rop(struct nvc0_graph_priv *priv)
-{
-        int rop;
-
-        for (rop = 0; rop < priv->rop_nr; rop++) {
-                nv_wr32(priv, ROP_UNIT(rop, 0x144), 0xc0000000);
-                nv_wr32(priv, ROP_UNIT(rop, 0x070), 0xc0000000);
-                nv_wr32(priv, ROP_UNIT(rop, 0x204), 0xffffffff);
-                nv_wr32(priv, ROP_UNIT(rop, 0x208), 0xffffffff);
-        }
-}
-
-static int
-nve0_graph_init_ctxctl(struct nvc0_graph_priv *priv)
-{
-        u32 r000260;
-        int i;
-
-        if (priv->firmware) {
-                /* load fuc microcode */
-                r000260 = nv_mask(priv, 0x000260, 0x00000001, 0x00000000);
-                nvc0_graph_init_fw(priv, 0x409000, &priv->fuc409c, &priv->fuc409d);
-                nvc0_graph_init_fw(priv, 0x41a000, &priv->fuc41ac, &priv->fuc41ad);
-                nv_wr32(priv, 0x000260, r000260);
-
-                /* start both of them running */
-                nv_wr32(priv, 0x409840, 0xffffffff);
-                nv_wr32(priv, 0x41a10c, 0x00000000);
-                nv_wr32(priv, 0x40910c, 0x00000000);
-                nv_wr32(priv, 0x41a100, 0x00000002);
-                nv_wr32(priv, 0x409100, 0x00000002);
-                if (!nv_wait(priv, 0x409800, 0x00000001, 0x00000001))
-                        nv_error(priv, "0x409800 wait failed\n");
-
-                nv_wr32(priv, 0x409840, 0xffffffff);
-                nv_wr32(priv, 0x409500, 0x7fffffff);
-                nv_wr32(priv, 0x409504, 0x00000021);
-
-                nv_wr32(priv, 0x409840, 0xffffffff);
-                nv_wr32(priv, 0x409500, 0x00000000);
-                nv_wr32(priv, 0x409504, 0x00000010);
-                if (!nv_wait_ne(priv, 0x409800, 0xffffffff, 0x00000000)) {
-                        nv_error(priv, "fuc09 req 0x10 timeout\n");
-                        return -EBUSY;
-                }
-                priv->size = nv_rd32(priv, 0x409800);
-
-                nv_wr32(priv, 0x409840, 0xffffffff);
-                nv_wr32(priv, 0x409500, 0x00000000);
-                nv_wr32(priv, 0x409504, 0x00000016);
-                if (!nv_wait_ne(priv, 0x409800, 0xffffffff, 0x00000000)) {
-                        nv_error(priv, "fuc09 req 0x16 timeout\n");
-                        return -EBUSY;
-                }
-
-                nv_wr32(priv, 0x409840, 0xffffffff);
-                nv_wr32(priv, 0x409500, 0x00000000);
-                nv_wr32(priv, 0x409504, 0x00000025);
-                if (!nv_wait_ne(priv, 0x409800, 0xffffffff, 0x00000000)) {
-                        nv_error(priv, "fuc09 req 0x25 timeout\n");
-                        return -EBUSY;
-                }
-
-                nv_wr32(priv, 0x409800, 0x00000000);
-                nv_wr32(priv, 0x409500, 0x00000001);
-                nv_wr32(priv, 0x409504, 0x00000030);
-                if (!nv_wait_ne(priv, 0x409800, 0xffffffff, 0x00000000)) {
-                        nv_error(priv, "fuc09 req 0x30 timeout\n");
-                        return -EBUSY;
-                }
-
-                nv_wr32(priv, 0x409810, 0xb00095c8);
-                nv_wr32(priv, 0x409800, 0x00000000);
-                nv_wr32(priv, 0x409500, 0x00000001);
-                nv_wr32(priv, 0x409504, 0x00000031);
-                if (!nv_wait_ne(priv, 0x409800, 0xffffffff, 0x00000000)) {
-                        nv_error(priv, "fuc09 req 0x31 timeout\n");
-                        return -EBUSY;
-                }
-
-                nv_wr32(priv, 0x409810, 0x00080420);
-                nv_wr32(priv, 0x409800, 0x00000000);
-                nv_wr32(priv, 0x409500, 0x00000001);
-                nv_wr32(priv, 0x409504, 0x00000032);
-                if (!nv_wait_ne(priv, 0x409800, 0xffffffff, 0x00000000)) {
-                        nv_error(priv, "fuc09 req 0x32 timeout\n");
-                        return -EBUSY;
-                }
-
-                nv_wr32(priv, 0x409614, 0x00000070);
-                nv_wr32(priv, 0x409614, 0x00000770);
-                nv_wr32(priv, 0x40802c, 0x00000001);
-
-                if (priv->data == NULL) {
-                        int ret = nve0_grctx_generate(priv);
-                        if (ret) {
-                                nv_error(priv, "failed to construct context\n");
-                                return ret;
-                        }
-                }
-
-                return 0;
-        }
-
-        /* load HUB microcode */
-        r000260 = nv_mask(priv, 0x000260, 0x00000001, 0x00000000);
-        nv_wr32(priv, 0x4091c0, 0x01000000);
-        for (i = 0; i < sizeof(nve0_grhub_data) / 4; i++)
-                nv_wr32(priv, 0x4091c4, nve0_grhub_data[i]);
-
-        nv_wr32(priv, 0x409180, 0x01000000);
-        for (i = 0; i < sizeof(nve0_grhub_code) / 4; i++) {
-                if ((i & 0x3f) == 0)
-                        nv_wr32(priv, 0x409188, i >> 6);
-                nv_wr32(priv, 0x409184, nve0_grhub_code[i]);
-        }
-
-        /* load GPC microcode */
-        nv_wr32(priv, 0x41a1c0, 0x01000000);
-        for (i = 0; i < sizeof(nve0_grgpc_data) / 4; i++)
-                nv_wr32(priv, 0x41a1c4, nve0_grgpc_data[i]);
-
-        nv_wr32(priv, 0x41a180, 0x01000000);
-        for (i = 0; i < sizeof(nve0_grgpc_code) / 4; i++) {
-                if ((i & 0x3f) == 0)
-                        nv_wr32(priv, 0x41a188, i >> 6);
-                nv_wr32(priv, 0x41a184, nve0_grgpc_code[i]);
-        }
-        nv_wr32(priv, 0x000260, r000260);
-
-        /* start HUB ucode running, it'll init the GPCs */
-        nv_wr32(priv, 0x409800, nv_device(priv)->chipset);
-        nv_wr32(priv, 0x40910c, 0x00000000);
-        nv_wr32(priv, 0x409100, 0x00000002);
-        if (!nv_wait(priv, 0x409800, 0x80000000, 0x80000000)) {
-                nv_error(priv, "HUB_INIT timed out\n");
-                nvc0_graph_ctxctl_debug(priv);
-                return -EBUSY;
-        }
-
-        priv->size = nv_rd32(priv, 0x409804);
-        if (priv->data == NULL) {
-                int ret = nve0_grctx_generate(priv);
-                if (ret) {
-                        nv_error(priv, "failed to construct context\n");
-                        return ret;
-                }
-        }
-
-        return 0;
-}
-
-static int
-nve0_graph_init(struct nouveau_object *object)
-{
-        struct nvc0_graph_priv *priv = (void *)object;
-        int ret;
-
-        ret = nouveau_graph_init(&priv->base);
-        if (ret)
-                return ret;
-
-        nve0_graph_init_obj418880(priv);
-        nve0_graph_init_regs(priv);
-        nve0_graph_init_gpc_0(priv);
-
-        nv_wr32(priv, 0x400500, 0x00010001);
-        nv_wr32(priv, 0x400100, 0xffffffff);
-        nv_wr32(priv, 0x40013c, 0xffffffff);
-
-        nve0_graph_init_units(priv);
-        nve0_graph_init_gpc_1(priv);
-        nve0_graph_init_rop(priv);
-
-        nv_wr32(priv, 0x400108, 0xffffffff);
-        nv_wr32(priv, 0x400138, 0xffffffff);
-        nv_wr32(priv, 0x400118, 0xffffffff);
-        nv_wr32(priv, 0x400130, 0xffffffff);
-        nv_wr32(priv, 0x40011c, 0xffffffff);
-        nv_wr32(priv, 0x400134, 0xffffffff);
-        nv_wr32(priv, 0x400054, 0x34ce3464);
-
-        ret = nve0_graph_init_ctxctl(priv);
-        if (ret)
-                return ret;
-
-        return 0;
-}
-
-struct nouveau_oclass
-nve0_graph_oclass = {
-        .handle = NV_ENGINE(GR, 0xe0),
-        .ofuncs = &(struct nouveau_ofuncs) {
-                .ctor = nve0_graph_ctor,
-                .dtor = nvc0_graph_dtor,
-                .init = nve0_graph_init,
-                .fini = _nouveau_graph_fini,
-        },
-};
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/nve4.c b/drivers/gpu/drm/nouveau/core/engine/graph/nve4.c
new file mode 100644
index 000000000000..05ec09c88517
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/core/engine/graph/nve4.c
@@ -0,0 +1,354 @@
+/*
+ * Copyright 2013 Red Hat Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Ben Skeggs <bskeggs@redhat.com>
+ */
+
+#include "nvc0.h"
+
+/*******************************************************************************
+ * Graphics object classes
+ ******************************************************************************/
+
+static struct nouveau_oclass
+nve4_graph_sclass[] = {
+        { 0x902d, &nouveau_object_ofuncs },
+        { 0xa040, &nouveau_object_ofuncs },
+        { 0xa097, &nouveau_object_ofuncs },
+        { 0xa0c0, &nouveau_object_ofuncs },
+        {}
+};
+
+/*******************************************************************************
+ * PGRAPH engine/subdev functions
+ ******************************************************************************/
+
+struct nvc0_graph_init
+nve4_graph_init_regs[] = {
+        { 0x400080,   1, 0x04, 0x003083c2 },
+        { 0x400088,   1, 0x04, 0x0001ffe7 },
+        { 0x40008c,   1, 0x04, 0x00000000 },
+        { 0x400090,   1, 0x04, 0x00000030 },
+        { 0x40013c,   1, 0x04, 0x003901f7 },
+        { 0x400140,   1, 0x04, 0x00000100 },
+        { 0x400144,   1, 0x04, 0x00000000 },
+        { 0x400148,   1, 0x04, 0x00000110 },
+        { 0x400138,   1, 0x04, 0x00000000 },
+        { 0x400130,   2, 0x04, 0x00000000 },
+        { 0x400124,   1, 0x04, 0x00000002 },
+        {}
+};
+
+static struct nvc0_graph_init
+nve4_graph_init_unk58xx[] = {
+        { 0x405844,   1, 0x04, 0x00ffffff },
+        { 0x405850,   1, 0x04, 0x00000000 },
+        { 0x405900,   1, 0x04, 0x0000ff34 },
+        { 0x405908,   1, 0x04, 0x00000000 },
+        { 0x405928,   1, 0x04, 0x00000000 },
+        { 0x40592c,   1, 0x04, 0x00000000 },
+        {}
+};
+
+static struct nvc0_graph_init
+nve4_graph_init_unk70xx[] = {
+        { 0x407010,   1, 0x04, 0x00000000 },
+        {}
+};
+
+struct nvc0_graph_init
+nve4_graph_init_unk5bxx[] = {
+        { 0x405b50,   1, 0x04, 0x00000000 },
+        {}
+};
+
+static struct nvc0_graph_init
+nve4_graph_init_gpc[] = {
+        { 0x418408,   1, 0x04, 0x00000000 },
+        { 0x4184a0,   1, 0x04, 0x00000000 },
+        { 0x4184a4,   2, 0x04, 0x00000000 },
+        { 0x418604,   1, 0x04, 0x00000000 },
+        { 0x418680,   1, 0x04, 0x00000000 },
+        { 0x418714,   1, 0x04, 0x00000000 },
+        { 0x418384,   1, 0x04, 0x00000000 },
+        { 0x418814,   3, 0x04, 0x00000000 },
+        { 0x418b04,   1, 0x04, 0x00000000 },
+        { 0x4188c8,   2, 0x04, 0x00000000 },
+        { 0x4188d0,   1, 0x04, 0x00010000 },
+        { 0x4188d4,   1, 0x04, 0x00000001 },
+        { 0x418910,   1, 0x04, 0x00010001 },
+        { 0x418914,   1, 0x04, 0x00000301 },
+        { 0x418918,   1, 0x04, 0x00800000 },
+        { 0x418980,   1, 0x04, 0x77777770 },
+        { 0x418984,   3, 0x04, 0x77777777 },
+        { 0x418c04,   1, 0x04, 0x00000000 },
+        { 0x418c64,   1, 0x04, 0x00000000 },
+        { 0x418c68,   1, 0x04, 0x00000000 },
+        { 0x418c88,   1, 0x04, 0x00000000 },
+        { 0x418cb4,   2, 0x04, 0x00000000 },
+        { 0x418d00,   1, 0x04, 0x00000000 },
+        { 0x418d28,   1, 0x04, 0x00000000 },
+        { 0x418d2c,   1, 0x04, 0x00000000 },
+        { 0x418f00,   1, 0x04, 0x00000000 },
+        { 0x418f08,   1, 0x04, 0x00000000 },
+        { 0x418f20,   2, 0x04, 0x00000000 },
+        { 0x418e00,   1, 0x04, 0x00000060 },
+        { 0x418e08,   1, 0x04, 0x00000000 },
+        { 0x418e1c,   1, 0x04, 0x00000000 },
+        { 0x418e20,   1, 0x04, 0x00000000 },
+        { 0x41900c,   1, 0x04, 0x00000000 },
+        { 0x419018,   1, 0x04, 0x00000000 },
+        {}
+};
+
+static struct nvc0_graph_init
+nve4_graph_init_tpc[] = {
+        { 0x419d0c,   1, 0x04, 0x00000000 },
+        { 0x419d10,   1, 0x04, 0x00000014 },
+        { 0x419ab0,   1, 0x04, 0x00000000 },
+        { 0x419ac8,   1, 0x04, 0x00000000 },
+        { 0x419ab8,   1, 0x04, 0x000000e7 },
+        { 0x419abc,   2, 0x04, 0x00000000 },
+        { 0x419ab4,   1, 0x04, 0x00000000 },
+        { 0x41980c,   1, 0x04, 0x00000010 },
+        { 0x419844,   1, 0x04, 0x00000000 },
+        { 0x419850,   1, 0x04, 0x00000004 },
+        { 0x419854,   2, 0x04, 0x00000000 },
+        { 0x419c98,   1, 0x04, 0x00000000 },
+        { 0x419ca8,   1, 0x04, 0x00000000 },
+        { 0x419cb0,   1, 0x04, 0x01000000 },
+        { 0x419cb4,   1, 0x04, 0x00000000 },
+        { 0x419cb8,   1, 0x04, 0x00b08bea },
+        { 0x419c84,   1, 0x04, 0x00010384 },
+        { 0x419cbc,   1, 0x04, 0x28137646 },
+        { 0x419cc0,   2, 0x04, 0x00000000 },
+        { 0x419c80,   1, 0x04, 0x00020232 },
+        { 0x419c0c,   1, 0x04, 0x00000000 },
+        { 0x419e00,   1, 0x04, 0x00000000 },
+        { 0x419ea0,   1, 0x04, 0x00000000 },
+        { 0x419ee4,   1, 0x04, 0x00000000 },
+        { 0x419ea4,   1, 0x04, 0x00000100 },
+        { 0x419ea8,   1, 0x04, 0x00000000 },
+        { 0x419eb4,   1, 0x04, 0x00000000 },
+        { 0x419eb8,   3, 0x04, 0x00000000 },
+        { 0x419edc,   1, 0x04, 0x00000000 },
+        { 0x419f00,   1, 0x04, 0x00000000 },
+        { 0x419f74,   1, 0x04, 0x00000555 },
+        {}
+};
+
+struct nvc0_graph_init
+nve4_graph_init_unk[] = {
+        { 0x41be04,   1, 0x04, 0x00000000 },
+        { 0x41be08,   1, 0x04, 0x00000004 },
+        { 0x41be0c,   1, 0x04, 0x00000000 },
+        { 0x41be10,   1, 0x04, 0x003b8bc7 },
+        { 0x41be14,   2, 0x04, 0x00000000 },
+        { 0x41bfd4,   1, 0x04, 0x00800000 },
+        { 0x41bfdc,   1, 0x04, 0x00000000 },
+        { 0x41bff8,   1, 0x04, 0x00000000 },
+        { 0x41bffc,   1, 0x04, 0x00000000 },
+        { 0x41becc,   1, 0x04, 0x00000000 },
+        { 0x41bee8,   1, 0x04, 0x00000000 },
+        { 0x41beec,   1, 0x04, 0x00000000 },
+        {}
+};
+
+struct nvc0_graph_init
+nve4_graph_init_unk88xx[] = {
+        { 0x40880c,   1, 0x04, 0x00000000 },
+        { 0x408850,   1, 0x04, 0x00000004 },
+        { 0x408910,   9, 0x04, 0x00000000 },
+        { 0x408950,   1, 0x04, 0x00000000 },
+        { 0x408954,   1, 0x04, 0x0000ffff },
+        { 0x408958,   1, 0x04, 0x00000034 },
+        { 0x408984,   1, 0x04, 0x00000000 },
+        { 0x408988,   1, 0x04, 0x08040201 },
+        { 0x40898c,   1, 0x04, 0x80402010 },
+        {}
+};
+
+int
+nve4_graph_init(struct nouveau_object *object)
+{
+        struct nvc0_graph_oclass *oclass = (void *)object->oclass;
+        struct nvc0_graph_priv *priv = (void *)object;
+        const u32 magicgpc918 = DIV_ROUND_UP(0x00800000, priv->tpc_total);
+        u32 data[TPC_MAX / 8] = {};
+        u8  tpcnr[GPC_MAX];
+        int gpc, tpc, rop;
+        int ret, i;
+
+        ret = nouveau_graph_init(&priv->base);
+        if (ret)
+                return ret;
+
+        nv_wr32(priv, GPC_BCAST(0x0880), 0x00000000);
+        nv_wr32(priv, GPC_BCAST(0x08a4), 0x00000000);
+        nv_wr32(priv, GPC_BCAST(0x0888), 0x00000000);
+        nv_wr32(priv, GPC_BCAST(0x088c), 0x00000000);
+        nv_wr32(priv, GPC_BCAST(0x0890), 0x00000000);
+        nv_wr32(priv, GPC_BCAST(0x0894), 0x00000000);
+        nv_wr32(priv, GPC_BCAST(0x08b4), priv->unk4188b4->addr >> 8);
+        nv_wr32(priv, GPC_BCAST(0x08b8), priv->unk4188b8->addr >> 8);
+
+        for (i = 0; oclass->mmio[i]; i++)
+                nvc0_graph_mmio(priv, oclass->mmio[i]);
+
+        nv_wr32(priv, GPC_UNIT(0, 0x3018), 0x00000001);
+
+        memset(data, 0x00, sizeof(data));
+        memcpy(tpcnr, priv->tpc_nr, sizeof(priv->tpc_nr));
+        for (i = 0, gpc = -1; i < priv->tpc_total; i++) {
+                do {
+                        gpc = (gpc + 1) % priv->gpc_nr;
+                } while (!tpcnr[gpc]);
+                tpc = priv->tpc_nr[gpc] - tpcnr[gpc]--;
+
+                data[i / 8] |= tpc << ((i % 8) * 4);
+        }
+
+        nv_wr32(priv, GPC_BCAST(0x0980), data[0]);
+        nv_wr32(priv, GPC_BCAST(0x0984), data[1]);
+        nv_wr32(priv, GPC_BCAST(0x0988), data[2]);
+        nv_wr32(priv, GPC_BCAST(0x098c), data[3]);
+
+        for (gpc = 0; gpc < priv->gpc_nr; gpc++) {
+                nv_wr32(priv, GPC_UNIT(gpc, 0x0914),
+                        priv->magic_not_rop_nr << 8 | priv->tpc_nr[gpc]);
+                nv_wr32(priv, GPC_UNIT(gpc, 0x0910), 0x00040000 |
+                        priv->tpc_total);
+                nv_wr32(priv, GPC_UNIT(gpc, 0x0918), magicgpc918);
+        }
+
+        nv_wr32(priv, GPC_BCAST(0x3fd4), magicgpc918);
+        nv_wr32(priv, GPC_BCAST(0x08ac), nv_rd32(priv, 0x100800));
+
+        nv_wr32(priv, 0x400500, 0x00010001);
+
+        nv_wr32(priv, 0x400100, 0xffffffff);
+        nv_wr32(priv, 0x40013c, 0xffffffff);
+
+        nv_wr32(priv, 0x409ffc, 0x00000000);
+        nv_wr32(priv, 0x409c14, 0x00003e3e);
+        nv_wr32(priv, 0x409c24, 0x000f0001);
+        nv_wr32(priv, 0x404000, 0xc0000000);
+        nv_wr32(priv, 0x404600, 0xc0000000);
+        nv_wr32(priv, 0x408030, 0xc0000000);
+        nv_wr32(priv, 0x404490, 0xc0000000);
+        nv_wr32(priv, 0x406018, 0xc0000000);
+        nv_wr32(priv, 0x407020, 0x40000000);
+        nv_wr32(priv, 0x405840, 0xc0000000);
+        nv_wr32(priv, 0x405844, 0x00ffffff);
+        nv_mask(priv, 0x419cc0, 0x00000008, 0x00000008);
+        nv_mask(priv, 0x419eb4, 0x00001000, 0x00001000);
+
+        for (gpc = 0; gpc < priv->gpc_nr; gpc++) {
+                nv_wr32(priv, GPC_UNIT(gpc, 0x3038), 0xc0000000);
+                nv_wr32(priv, GPC_UNIT(gpc, 0x0420), 0xc0000000);
+                nv_wr32(priv, GPC_UNIT(gpc, 0x0900), 0xc0000000);
+                nv_wr32(priv, GPC_UNIT(gpc, 0x1028), 0xc0000000);
+                nv_wr32(priv, GPC_UNIT(gpc, 0x0824), 0xc0000000);
+                for (tpc = 0; tpc < priv->tpc_nr[gpc]; tpc++) {
+                        nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x508), 0xffffffff);
+                        nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x50c), 0xffffffff);
+                        nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x224), 0xc0000000);
+                        nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x48c), 0xc0000000);
+                        nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x084), 0xc0000000);
+                        nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x644), 0x001ffffe);
+                        nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x64c), 0x0000000f);
+                }
+                nv_wr32(priv, GPC_UNIT(gpc, 0x2c90), 0xffffffff);
+                nv_wr32(priv, GPC_UNIT(gpc, 0x2c94), 0xffffffff);
+        }
+
+        for (rop = 0; rop < priv->rop_nr; rop++) {
+                nv_wr32(priv, ROP_UNIT(rop, 0x144), 0xc0000000);
+                nv_wr32(priv, ROP_UNIT(rop, 0x070), 0xc0000000);
+                nv_wr32(priv, ROP_UNIT(rop, 0x204), 0xffffffff);
+                nv_wr32(priv, ROP_UNIT(rop, 0x208), 0xffffffff);
+        }
+
+        nv_wr32(priv, 0x400108, 0xffffffff);
+        nv_wr32(priv, 0x400138, 0xffffffff);
+        nv_wr32(priv, 0x400118, 0xffffffff);
+        nv_wr32(priv, 0x400130, 0xffffffff);
+        nv_wr32(priv, 0x40011c, 0xffffffff);
+        nv_wr32(priv, 0x400134, 0xffffffff);
+
+        nv_wr32(priv, 0x400054, 0x34ce3464);
+        return nvc0_graph_init_ctxctl(priv);
+}
+
+static struct nvc0_graph_init *
+nve4_graph_init_mmio[] = {
+        nve4_graph_init_regs,
+        nvc0_graph_init_unk40xx,
+        nvc0_graph_init_unk44xx,
+        nvc0_graph_init_unk78xx,
+        nvc0_graph_init_unk60xx,
+        nvd9_graph_init_unk64xx,
+        nve4_graph_init_unk58xx,
+        nvc0_graph_init_unk80xx,
+        nve4_graph_init_unk70xx,
+        nve4_graph_init_unk5bxx,
+        nve4_graph_init_gpc,
+        nve4_graph_init_tpc,
+        nve4_graph_init_unk,
+        nve4_graph_init_unk88xx,
+        NULL
+};
+
+#include "fuc/hubnve0.fuc.h"
+
+static struct nvc0_graph_ucode
+nve4_graph_fecs_ucode = {
+        .code.data = nve0_grhub_code,
+        .code.size = sizeof(nve0_grhub_code),
+        .data.data = nve0_grhub_data,
+        .data.size = sizeof(nve0_grhub_data),
+};
+
+#include "fuc/gpcnve0.fuc.h"
+
+static struct nvc0_graph_ucode
+nve4_graph_gpccs_ucode = {
+        .code.data = nve0_grgpc_code,
+        .code.size = sizeof(nve0_grgpc_code),
+        .data.data = nve0_grgpc_data,
+        .data.size = sizeof(nve0_grgpc_data),
+};
+
+struct nouveau_oclass *
+nve4_graph_oclass = &(struct nvc0_graph_oclass) {
+        .base.handle = NV_ENGINE(GR, 0xe4),
+        .base.ofuncs = &(struct nouveau_ofuncs) {
+                .ctor = nvc0_graph_ctor,
+                .dtor = nvc0_graph_dtor,
+                .init = nve4_graph_init,
+                .fini = _nouveau_graph_fini,
+        },
+        .cclass = &nve4_grctx_oclass,
+        .sclass = nve4_graph_sclass,
+        .mmio = nve4_graph_init_mmio,
+        .fecs.ucode = &nve4_graph_fecs_ucode,
+        .gpccs.ucode = &nve4_graph_gpccs_ucode,
+}.base;
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/nvf0.c b/drivers/gpu/drm/nouveau/core/engine/graph/nvf0.c
new file mode 100644
index 000000000000..2f0ac7832234
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/core/engine/graph/nvf0.c
@@ -0,0 +1,248 @@
+/*
+ * Copyright 2013 Red Hat Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Ben Skeggs <bskeggs@redhat.com>
+ */
+
+#include "nvc0.h"
+
+/*******************************************************************************
+ * Graphics object classes
+ ******************************************************************************/
+
+static struct nouveau_oclass
+nvf0_graph_sclass[] = {
+        { 0x902d, &nouveau_object_ofuncs },
+        { 0xa140, &nouveau_object_ofuncs },
+        { 0xa197, &nouveau_object_ofuncs },
+        { 0xa1c0, &nouveau_object_ofuncs },
+        {}
+};
+
+/*******************************************************************************
+ * PGRAPH engine/subdev functions
+ ******************************************************************************/
+
+static struct nvc0_graph_init
+nvf0_graph_init_unk40xx[] = {
+        { 0x40415c,   1, 0x04, 0x00000000 },
+        { 0x404170,   1, 0x04, 0x00000000 },
+        { 0x4041b4,   1, 0x04, 0x00000000 },
+        {}
+};
+
+static struct nvc0_graph_init
+nvf0_graph_init_unk58xx[] = {
+        { 0x405844,   1, 0x04, 0x00ffffff },
+        { 0x405850,   1, 0x04, 0x00000000 },
+        { 0x405900,   1, 0x04, 0x0000ff00 },
+        { 0x405908,   1, 0x04, 0x00000000 },
+        { 0x405928,   1, 0x04, 0x00000000 },
+        { 0x40592c,   1, 0x04, 0x00000000 },
+        {}
+};
+
+static struct nvc0_graph_init
+nvf0_graph_init_unk70xx[] = {
+        { 0x407010,   1, 0x04, 0x00000000 },
+        { 0x407040,   1, 0x04, 0x80440424 },
+        { 0x407048,   1, 0x04, 0x0000000a },
+        {}
+};
+
+static struct nvc0_graph_init
+nvf0_graph_init_unk5bxx[] = {
+        { 0x405b44,   1, 0x04, 0x00000000 },
+        { 0x405b50,   1, 0x04, 0x00000000 },
+        {}
+};
+
+static struct nvc0_graph_init
+nvf0_graph_init_gpc[] = {
+        { 0x418408,   1, 0x04, 0x00000000 },
+        { 0x4184a0,   1, 0x04, 0x00000000 },
+        { 0x4184a4,   2, 0x04, 0x00000000 },
+        { 0x418604,   1, 0x04, 0x00000000 },
+        { 0x418680,   1, 0x04, 0x00000000 },
+        { 0x418714,   1, 0x04, 0x00000000 },
+        { 0x418384,   1, 0x04, 0x00000000 },
+        { 0x418814,   3, 0x04, 0x00000000 },
+        { 0x418b04,   1, 0x04, 0x00000000 },
+        { 0x4188c8,   2, 0x04, 0x00000000 },
+        { 0x4188d0,   1, 0x04, 0x00010000 },
+        { 0x4188d4,   1, 0x04, 0x00000001 },
+        { 0x418910,   1, 0x04, 0x00010001 },
+        { 0x418914,   1, 0x04, 0x00000301 },
+        { 0x418918,   1, 0x04, 0x00800000 },
+        { 0x418980,   1, 0x04, 0x77777770 },
+        { 0x418984,   3, 0x04, 0x77777777 },
+        { 0x418c04,   1, 0x04, 0x00000000 },
+        { 0x418c64,   1, 0x04, 0x00000000 },
+        { 0x418c68,   1, 0x04, 0x00000000 },
+        { 0x418c88,   1, 0x04, 0x00000000 },
+        { 0x418cb4,   2, 0x04, 0x00000000 },
+        { 0x418d00,   1, 0x04, 0x00000000 },
+        { 0x418d28,   1, 0x04, 0x00000000 },
+        { 0x418d2c,   1, 0x04, 0x00000000 },
+        { 0x418f00,   1, 0x04, 0x00000400 },
+        { 0x418f08,   1, 0x04, 0x00000000 },
+        { 0x418f20,   1, 0x04, 0x00000000 },
+        { 0x418f24,   1, 0x04, 0x00000000 },
+        { 0x418e00,   1, 0x04, 0x00000000 },
+        { 0x418e08,   1, 0x04, 0x00000000 },
+        { 0x418e1c,   2, 0x04, 0x00000000 },
+        { 0x41900c,   1, 0x04, 0x00000000 },
+        { 0x419018,   1, 0x04, 0x00000000 },
+        {}
+};
+
+static struct nvc0_graph_init
+nvf0_graph_init_tpc[] = {
+        { 0x419d0c,   1, 0x04, 0x00000000 },
+        { 0x419d10,   1, 0x04, 0x00000014 },
+        { 0x419ab0,   1, 0x04, 0x00000000 },
+        { 0x419ac8,   1, 0x04, 0x00000000 },
+        { 0x419ab8,   1, 0x04, 0x000000e7 },
+        { 0x419aec,   1, 0x04, 0x00000000 },
+        { 0x419abc,   2, 0x04, 0x00000000 },
+        { 0x419ab4,   1, 0x04, 0x00000000 },
+        { 0x419aa8,   2, 0x04, 0x00000000 },
+        { 0x41980c,   1, 0x04, 0x00000010 },
+        { 0x419844,   1, 0x04, 0x00000000 },
+        { 0x419850,   1, 0x04, 0x00000004 },
+        { 0x419854,   2, 0x04, 0x00000000 },
+        { 0x419c98,   1, 0x04, 0x00000000 },
+        { 0x419ca8,   1, 0x04, 0x00000000 },
+        { 0x419cb0,   1, 0x04, 0x01000000 },
+        { 0x419cb4,   1, 0x04, 0x00000000 },
+        { 0x419cb8,   1, 0x04, 0x00b08bea },
+        { 0x419c84,   1, 0x04, 0x00010384 },
+        { 0x419cbc,   1, 0x04, 0x281b3646 },
+        { 0x419cc0,   2, 0x04, 0x00000000 },
+        { 0x419c80,   1, 0x04, 0x00020230 },
+        { 0x419ccc,   2, 0x04, 0x00000000 },
+        { 0x419c0c,   1, 0x04, 0x00000000 },
+        { 0x419e00,   1, 0x04, 0x00000080 },
+        { 0x419ea0,   1, 0x04, 0x00000000 },
+        { 0x419ee4,   1, 0x04, 0x00000000 },
+        { 0x419ea4,   1, 0x04, 0x00000100 },
+        { 0x419ea8,   1, 0x04, 0x00000000 },
+        { 0x419eb4,   1, 0x04, 0x00000000 },
+        { 0x419ebc,   2, 0x04, 0x00000000 },
+        { 0x419edc,   1, 0x04, 0x00000000 },
+        { 0x419f00,   1, 0x04, 0x00000000 },
+        { 0x419ed0,   1, 0x04, 0x00003234 },
+        { 0x419f74,   1, 0x04, 0x00015555 },
+        { 0x419f80,   4, 0x04, 0x00000000 },
+        {}
+};
+
+static int
+nvf0_graph_fini(struct nouveau_object *object, bool suspend)
+{
+        struct nvc0_graph_priv *priv = (void *)object;
+        static const struct {
+                u32 addr;
+                u32 data;
+        } magic[] = {
+                { 0x020520, 0xfffffffc },
+                { 0x020524, 0xfffffffe },
+                { 0x020524, 0xfffffffc },
+                { 0x020524, 0xfffffff8 },
+                { 0x020524, 0xffffffe0 },
+                { 0x020530, 0xfffffffe },
+                { 0x02052c, 0xfffffffa },
+                { 0x02052c, 0xfffffff0 },
+                { 0x02052c, 0xffffffc0 },
+                { 0x02052c, 0xffffff00 },
+                { 0x02052c, 0xfffffc00 },
+                { 0x02052c, 0xfffcfc00 },
+                { 0x02052c, 0xfff0fc00 },
+                { 0x02052c, 0xff80fc00 },
+                { 0x020528, 0xfffffffe },
+                { 0x020528, 0xfffffffc },
+        };
+        int i;
+
+        nv_mask(priv, 0x000200, 0x08001000, 0x00000000);
+        nv_mask(priv, 0x0206b4, 0x00000000, 0x00000000);
+        for (i = 0; i < ARRAY_SIZE(magic); i++) {
+                nv_wr32(priv, magic[i].addr, magic[i].data);
+                nv_wait(priv, magic[i].addr, 0x80000000, 0x00000000);
+        }
+
+        return nouveau_graph_fini(&priv->base, suspend);
+}
+
+static struct nvc0_graph_init *
+nvf0_graph_init_mmio[] = {
+        nve4_graph_init_regs,
+        nvf0_graph_init_unk40xx,
+        nvc0_graph_init_unk44xx,
+        nvc0_graph_init_unk78xx,
+        nvc0_graph_init_unk60xx,
+        nvd9_graph_init_unk64xx,
+        nvf0_graph_init_unk58xx,
+        nvc0_graph_init_unk80xx,
+        nvf0_graph_init_unk70xx,
+        nvf0_graph_init_unk5bxx,
+        nvf0_graph_init_gpc,
+        nvf0_graph_init_tpc,
+        nve4_graph_init_unk,
+        nve4_graph_init_unk88xx,
+        NULL
+};
+
+#include "fuc/hubnvf0.fuc.h"
+
+static struct nvc0_graph_ucode
+nvf0_graph_fecs_ucode = {
+        .code.data = nvf0_grhub_code,
+        .code.size = sizeof(nvf0_grhub_code),
+        .data.data = nvf0_grhub_data,
+        .data.size = sizeof(nvf0_grhub_data),
+};
+
+#include "fuc/gpcnvf0.fuc.h"
+
+static struct nvc0_graph_ucode
+nvf0_graph_gpccs_ucode = {
+        .code.data = nvf0_grgpc_code,
+        .code.size = sizeof(nvf0_grgpc_code),
+        .data.data = nvf0_grgpc_data,
+        .data.size = sizeof(nvf0_grgpc_data),
+};
+
+struct nouveau_oclass *
+nvf0_graph_oclass = &(struct nvc0_graph_oclass) {
+        .base.handle = NV_ENGINE(GR, 0xf0),
+        .base.ofuncs = &(struct nouveau_ofuncs) {
+                .ctor = nvc0_graph_ctor,
+                .dtor = nvc0_graph_dtor,
+                .init = nve4_graph_init,
+                .fini = nvf0_graph_fini,
+        },
+        .cclass = &nvf0_grctx_oclass,
+        .sclass =  nvf0_graph_sclass,
+        .mmio = nvf0_graph_init_mmio,
+        .fecs.ucode = 0 ? &nvf0_graph_fecs_ucode : NULL,
+        .gpccs.ucode = &nvf0_graph_gpccs_ucode,
+}.base;
diff --git a/drivers/gpu/drm/nouveau/core/engine/mpeg/nv50.c b/drivers/gpu/drm/nouveau/core/engine/mpeg/nv50.c
index bc7d12b30fc1..37a2bd9e8078 100644
--- a/drivers/gpu/drm/nouveau/core/engine/mpeg/nv50.c
+++ b/drivers/gpu/drm/nouveau/core/engine/mpeg/nv50.c
@@ -125,13 +125,6 @@ nv50_mpeg_cclass = {
  * PMPEG engine/subdev functions
  ******************************************************************************/
 
-int
-nv50_mpeg_tlb_flush(struct nouveau_engine *engine)
-{
-        nv50_vm_flush_engine(&engine->base, 0x08);
-        return 0;
-}
-
 void
 nv50_mpeg_intr(struct nouveau_subdev *subdev)
 {
@@ -191,7 +184,6 @@ nv50_mpeg_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
         nv_subdev(priv)->intr = nv50_vpe_intr;
         nv_engine(priv)->cclass = &nv50_mpeg_cclass;
         nv_engine(priv)->sclass = nv50_mpeg_sclass;
-        nv_engine(priv)->tlb_flush = nv50_mpeg_tlb_flush;
         return 0;
 }
 
diff --git a/drivers/gpu/drm/nouveau/core/engine/mpeg/nv84.c b/drivers/gpu/drm/nouveau/core/engine/mpeg/nv84.c
index 8f805b44d59e..96f5aa92677b 100644
--- a/drivers/gpu/drm/nouveau/core/engine/mpeg/nv84.c
+++ b/drivers/gpu/drm/nouveau/core/engine/mpeg/nv84.c
@@ -88,7 +88,6 @@ nv84_mpeg_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
         nv_subdev(priv)->intr = nv50_mpeg_intr;
         nv_engine(priv)->cclass = &nv84_mpeg_cclass;
         nv_engine(priv)->sclass = nv84_mpeg_sclass;
-        nv_engine(priv)->tlb_flush = nv50_mpeg_tlb_flush;
         return 0;
 }
 
diff --git a/drivers/gpu/drm/nouveau/core/engine/ppp/nvc0.c b/drivers/gpu/drm/nouveau/core/engine/ppp/nvc0.c
index ebf0d860e2dd..98072c1ff360 100644
--- a/drivers/gpu/drm/nouveau/core/engine/ppp/nvc0.c
+++ b/drivers/gpu/drm/nouveau/core/engine/ppp/nvc0.c
@@ -22,8 +22,7 @@
  * Authors: Maarten Lankhorst
  */
 
-#include <core/falcon.h>
-
+#include <engine/falcon.h>
 #include <engine/ppp.h>
 
 struct nvc0_ppp_priv {
diff --git a/drivers/gpu/drm/nouveau/core/engine/vp/nv84.c b/drivers/gpu/drm/nouveau/core/engine/vp/nv84.c
index 261cd96e6951..fd6272b8cdb2 100644
--- a/drivers/gpu/drm/nouveau/core/engine/vp/nv84.c
+++ b/drivers/gpu/drm/nouveau/core/engine/vp/nv84.c
@@ -19,24 +19,19 @@
  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  * OTHER DEALINGS IN THE SOFTWARE.
  *
- * Authors: Ben Skeggs
+ * Authors: Ben Skeggs, Ilia Mirkin
  */
 
-#include <core/engctx.h>
-#include <core/class.h>
-
+#include <engine/xtensa.h>
 #include <engine/vp.h>
 
-struct nv84_vp_priv {
-        struct nouveau_engine base;
-};
-
 /*******************************************************************************
  * VP object classes
  ******************************************************************************/
 
 static struct nouveau_oclass
 nv84_vp_sclass[] = {
+        { 0x7476, &nouveau_object_ofuncs },
         {},
 };
 
@@ -48,7 +43,7 @@ static struct nouveau_oclass
 nv84_vp_cclass = {
         .handle = NV_ENGCTX(VP, 0x84),
         .ofuncs = &(struct nouveau_ofuncs) {
-                .ctor = _nouveau_engctx_ctor,
+                .ctor = _nouveau_xtensa_engctx_ctor,
                 .dtor = _nouveau_engctx_dtor,
                 .init = _nouveau_engctx_init,
                 .fini = _nouveau_engctx_fini,
@@ -66,10 +61,10 @@ nv84_vp_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
              struct nouveau_oclass *oclass, void *data, u32 size,
              struct nouveau_object **pobject)
 {
-        struct nv84_vp_priv *priv;
+        struct nouveau_xtensa *priv;
         int ret;
 
-        ret = nouveau_engine_create(parent, engine, oclass, true,
+        ret = nouveau_xtensa_create(parent, engine, oclass, 0xf000, true,
                                     "PVP", "vp", &priv);
         *pobject = nv_object(priv);
         if (ret)
@@ -78,6 +73,8 @@ nv84_vp_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
         nv_subdev(priv)->unit = 0x01020000;
         nv_engine(priv)->cclass = &nv84_vp_cclass;
         nv_engine(priv)->sclass = nv84_vp_sclass;
+        priv->fifo_val = 0x111;
+        priv->unkd28 = 0x9c544;
         return 0;
 }
 
@@ -86,8 +83,10 @@ nv84_vp_oclass = {
         .handle = NV_ENGINE(VP, 0x84),
         .ofuncs = &(struct nouveau_ofuncs) {
                 .ctor = nv84_vp_ctor,
-                .dtor = _nouveau_engine_dtor,
-                .init = _nouveau_engine_init,
-                .fini = _nouveau_engine_fini,
+                .dtor = _nouveau_xtensa_dtor,
+                .init = _nouveau_xtensa_init,
+                .fini = _nouveau_xtensa_fini,
+                .rd32 = _nouveau_xtensa_rd32,
+                .wr32 = _nouveau_xtensa_wr32,
         },
 };
diff --git a/drivers/gpu/drm/nouveau/core/engine/vp/nv98.c b/drivers/gpu/drm/nouveau/core/engine/vp/nv98.c
new file mode 100644
index 000000000000..8a8236bc84de
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/core/engine/vp/nv98.c
@@ -0,0 +1,93 @@
+/*
+ * Copyright 2012 Red Hat Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Ben Skeggs
+ */
+
+#include <core/engctx.h>
+#include <core/class.h>
+
+#include <engine/vp.h>
+
+struct nv98_vp_priv {
+        struct nouveau_engine base;
+};
+
+/*******************************************************************************
+ * VP object classes
+ ******************************************************************************/
+
+static struct nouveau_oclass
+nv98_vp_sclass[] = {
+        {},
+};
+
+/*******************************************************************************
+ * PVP context
+ ******************************************************************************/
+
+static struct nouveau_oclass
+nv98_vp_cclass = {
+        .handle = NV_ENGCTX(VP, 0x98),
+        .ofuncs = &(struct nouveau_ofuncs) {
+                .ctor = _nouveau_engctx_ctor,
+                .dtor = _nouveau_engctx_dtor,
+                .init = _nouveau_engctx_init,
+                .fini = _nouveau_engctx_fini,
+                .rd32 = _nouveau_engctx_rd32,
+                .wr32 = _nouveau_engctx_wr32,
+        },
+};
+
+/*******************************************************************************
+ * PVP engine/subdev functions
+ ******************************************************************************/
+
+static int
+nv98_vp_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
+             struct nouveau_oclass *oclass, void *data, u32 size,
+             struct nouveau_object **pobject)
+{
+        struct nv98_vp_priv *priv;
+        int ret;
+
+        ret = nouveau_engine_create(parent, engine, oclass, true,
+                                    "PVP", "vp", &priv);
+        *pobject = nv_object(priv);
+        if (ret)
+                return ret;
+
+        nv_subdev(priv)->unit = 0x01020000;
+        nv_engine(priv)->cclass = &nv98_vp_cclass;
+        nv_engine(priv)->sclass = nv98_vp_sclass;
+        return 0;
+}
+
+struct nouveau_oclass
+nv98_vp_oclass = {
+        .handle = NV_ENGINE(VP, 0x98),
+        .ofuncs = &(struct nouveau_ofuncs) {
+                .ctor = nv98_vp_ctor,
+                .dtor = _nouveau_engine_dtor,
+                .init = _nouveau_engine_init,
+                .fini = _nouveau_engine_fini,
+        },
+};
diff --git a/drivers/gpu/drm/nouveau/core/engine/vp/nvc0.c b/drivers/gpu/drm/nouveau/core/engine/vp/nvc0.c
index f761949d7039..1879229b60eb 100644
--- a/drivers/gpu/drm/nouveau/core/engine/vp/nvc0.c
+++ b/drivers/gpu/drm/nouveau/core/engine/vp/nvc0.c
@@ -22,8 +22,7 @@
  * Authors: Maarten Lankhorst
  */
 
-#include <core/falcon.h>
-
+#include <engine/falcon.h>
 #include <engine/vp.h>
 
 struct nvc0_vp_priv {
diff --git a/drivers/gpu/drm/nouveau/core/engine/vp/nve0.c b/drivers/gpu/drm/nouveau/core/engine/vp/nve0.c
index 2384ce5dbe16..d28ecbf7bc49 100644
--- a/drivers/gpu/drm/nouveau/core/engine/vp/nve0.c
+++ b/drivers/gpu/drm/nouveau/core/engine/vp/nve0.c
@@ -22,8 +22,7 @@
  * Authors: Ben Skeggs
  */
 
-#include <core/falcon.h>
-
+#include <engine/falcon.h>
 #include <engine/vp.h>
 
 struct nve0_vp_priv {
diff --git a/drivers/gpu/drm/nouveau/core/engine/xtensa.c b/drivers/gpu/drm/nouveau/core/engine/xtensa.c
new file mode 100644
index 000000000000..0639bc59d0a5
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/core/engine/xtensa.c
@@ -0,0 +1,170 @@
+/*
+ * Copyright 2013 Ilia Mirkin
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include <engine/xtensa.h>
+
+u32
+_nouveau_xtensa_rd32(struct nouveau_object *object, u64 addr)
+{
+        struct nouveau_xtensa *xtensa = (void *)object;
+        return nv_rd32(xtensa, xtensa->addr + addr);
+}
+
+void
+_nouveau_xtensa_wr32(struct nouveau_object *object, u64 addr, u32 data)
+{
+        struct nouveau_xtensa *xtensa = (void *)object;
+        nv_wr32(xtensa, xtensa->addr + addr, data);
+}
+
+int
+_nouveau_xtensa_engctx_ctor(struct nouveau_object *parent,
+                            struct nouveau_object *engine,
+                            struct nouveau_oclass *oclass, void *data, u32 size,
+                            struct nouveau_object **pobject)
+{
+        struct nouveau_engctx *engctx;
+        int ret;
+
+        ret = nouveau_engctx_create(parent, engine, oclass, NULL,
+                                    0x10000, 0x1000,
+                                    NVOBJ_FLAG_ZERO_ALLOC, &engctx);
+        *pobject = nv_object(engctx);
+        return ret;
+}
+
+void
+_nouveau_xtensa_intr(struct nouveau_subdev *subdev)
+{
+        struct nouveau_xtensa *xtensa = (void *)subdev;
+        u32 unk104 = nv_ro32(xtensa, 0xd04);
+        u32 intr = nv_ro32(xtensa, 0xc20);
+        u32 chan = nv_ro32(xtensa, 0xc28);
+        u32 unk10c = nv_ro32(xtensa, 0xd0c);
+
+        if (intr & 0x10)
+                nv_warn(xtensa, "Watchdog interrupt, engine hung.\n");
+        nv_wo32(xtensa, 0xc20, intr);
+        intr = nv_ro32(xtensa, 0xc20);
+        if (unk104 == 0x10001 && unk10c == 0x200 && chan && !intr) {
+                nv_debug(xtensa, "Enabling FIFO_CTRL\n");
+                nv_mask(xtensa, xtensa->addr + 0xd94, 0, xtensa->fifo_val);
+        }
+}
+
+int
+nouveau_xtensa_create_(struct nouveau_object *parent,
+                       struct nouveau_object *engine,
+                       struct nouveau_oclass *oclass, u32 addr, bool enable,
+                       const char *iname, const char *fname,
+                       int length, void **pobject)
+{
+        struct nouveau_xtensa *xtensa;
+        int ret;
+
+        ret = nouveau_engine_create_(parent, engine, oclass, enable, iname,
+                                     fname, length, pobject);
+        xtensa = *pobject;
+        if (ret)
+                return ret;
+
+        nv_subdev(xtensa)->intr = _nouveau_xtensa_intr;
+
+        xtensa->addr = addr;
+
+        return 0;
+}
+
+int
+_nouveau_xtensa_init(struct nouveau_object *object)
+{
+        struct nouveau_device *device = nv_device(object);
+        struct nouveau_xtensa *xtensa = (void *)object;
+        const struct firmware *fw;
+        char name[32];
+        int i, ret;
+        u32 tmp;
+
+        ret = nouveau_engine_init(&xtensa->base);
+        if (ret)
+                return ret;
+
+        if (!xtensa->gpu_fw) {
+                snprintf(name, sizeof(name), "nouveau/nv84_xuc%03x",
+                         xtensa->addr >> 12);
+
+                ret = request_firmware(&fw, name, &device->pdev->dev);
+                if (ret) {
+                        nv_warn(xtensa, "unable to load firmware %s\n", name);
+                        return ret;
+                }
+
+                ret = nouveau_gpuobj_new(object, NULL, fw->size, 0x1000, 0,
+                                         &xtensa->gpu_fw);
+                if (ret) {
+                        release_firmware(fw);
+                        return ret;
+                }
+
+                nv_debug(xtensa, "Loading firmware to address: 0x%llx\n",
+                         xtensa->gpu_fw->addr);
+
+                for (i = 0; i < fw->size / 4; i++)
+                        nv_wo32(xtensa->gpu_fw, i * 4, *((u32 *)fw->data + i));
+                release_firmware(fw);
+        }
+
+        nv_wo32(xtensa, 0xd10, 0x1fffffff); /* ?? */
+        nv_wo32(xtensa, 0xd08, 0x0fffffff); /* ?? */
+
+        nv_wo32(xtensa, 0xd28, xtensa->unkd28); /* ?? */
+        nv_wo32(xtensa, 0xc20, 0x3f); /* INTR */
+        nv_wo32(xtensa, 0xd84, 0x3f); /* INTR_EN */
+
+        nv_wo32(xtensa, 0xcc0, xtensa->gpu_fw->addr >> 8); /* XT_REGION_BASE */
+        nv_wo32(xtensa, 0xcc4, 0x1c); /* XT_REGION_SETUP */
+        nv_wo32(xtensa, 0xcc8, xtensa->gpu_fw->size >> 8); /* XT_REGION_LIMIT */
+
+        tmp = nv_rd32(xtensa, 0x0);
+        nv_wo32(xtensa, 0xde0, tmp); /* SCRATCH_H2X */
+
+        nv_wo32(xtensa, 0xce8, 0xf); /* XT_REGION_SETUP */
+
+        nv_wo32(xtensa, 0xc20, 0x3f); /* INTR */
+        nv_wo32(xtensa, 0xd84, 0x3f); /* INTR_EN */
+
+        return 0;
+}
+
+int
+_nouveau_xtensa_fini(struct nouveau_object *object, bool suspend)
+{
+        struct nouveau_xtensa *xtensa = (void *)object;
+
+        nv_wo32(xtensa, 0xd84, 0); /* INTR_EN */
+        nv_wo32(xtensa, 0xd94, 0); /* FIFO_CTRL */
+
+        if (!suspend)
+                nouveau_gpuobj_ref(NULL, &xtensa->gpu_fw);
+
+        return nouveau_engine_fini(&xtensa->base, suspend);
+}
diff --git a/drivers/gpu/drm/nouveau/core/include/core/device.h b/drivers/gpu/drm/nouveau/core/include/core/device.h
index 05840f3eee98..99b6600fe80a 100644
--- a/drivers/gpu/drm/nouveau/core/include/core/device.h
+++ b/drivers/gpu/drm/nouveau/core/include/core/device.h
@@ -17,8 +17,7 @@ enum nv_subdev_type {
         NVDEV_SUBDEV_DEVINIT,
         NVDEV_SUBDEV_GPIO,
         NVDEV_SUBDEV_I2C,
-        NVDEV_SUBDEV_CLOCK,
-        NVDEV_SUBDEV_DEVINIT_LAST = NVDEV_SUBDEV_CLOCK,
+        NVDEV_SUBDEV_DEVINIT_LAST = NVDEV_SUBDEV_I2C,
 
         /* This grouping of subdevs are initialised right after they've
          * been created, and are allowed to assume any subdevs in the
@@ -35,6 +34,7 @@ enum nv_subdev_type {
         NVDEV_SUBDEV_VM,
         NVDEV_SUBDEV_BAR,
         NVDEV_SUBDEV_VOLT,
+        NVDEV_SUBDEV_CLOCK,
         NVDEV_SUBDEV_THERM,
 
         NVDEV_ENGINE_DMAOBJ,
@@ -49,6 +49,7 @@ enum nv_subdev_type {
         NVDEV_ENGINE_PPP,
         NVDEV_ENGINE_COPY0,
         NVDEV_ENGINE_COPY1,
+        NVDEV_ENGINE_COPY2,
         NVDEV_ENGINE_UNK1C1,
         NVDEV_ENGINE_VENC,
         NVDEV_ENGINE_DISP,
diff --git a/drivers/gpu/drm/nouveau/core/include/core/mm.h b/drivers/gpu/drm/nouveau/core/include/core/mm.h
index 2514e81ade02..2bf7d0e32261 100644
--- a/drivers/gpu/drm/nouveau/core/include/core/mm.h
+++ b/drivers/gpu/drm/nouveau/core/include/core/mm.h
@@ -15,8 +15,6 @@ struct nouveau_mm {
         struct list_head nodes;
         struct list_head free;
 
-        struct mutex mutex;
-
         u32 block_size;
         int heap_nodes;
 };
diff --git a/drivers/gpu/drm/nouveau/core/include/engine/bsp.h b/drivers/gpu/drm/nouveau/core/include/engine/bsp.h
index 13ccdf54dfad..67662e2c4547 100644
--- a/drivers/gpu/drm/nouveau/core/include/engine/bsp.h
+++ b/drivers/gpu/drm/nouveau/core/include/engine/bsp.h
@@ -2,6 +2,7 @@
 #define __NOUVEAU_BSP_H__
 
 extern struct nouveau_oclass nv84_bsp_oclass;
+extern struct nouveau_oclass nv98_bsp_oclass;
 extern struct nouveau_oclass nvc0_bsp_oclass;
 extern struct nouveau_oclass nve0_bsp_oclass;
 
diff --git a/drivers/gpu/drm/nouveau/core/include/engine/copy.h b/drivers/gpu/drm/nouveau/core/include/engine/copy.h
index 8cad2cf28cef..316a28ae5f5c 100644
--- a/drivers/gpu/drm/nouveau/core/include/engine/copy.h
+++ b/drivers/gpu/drm/nouveau/core/include/engine/copy.h
@@ -8,5 +8,6 @@ extern struct nouveau_oclass nvc0_copy0_oclass;
 extern struct nouveau_oclass nvc0_copy1_oclass;
 extern struct nouveau_oclass nve0_copy0_oclass;
 extern struct nouveau_oclass nve0_copy1_oclass;
+extern struct nouveau_oclass nve0_copy2_oclass;
 
 #endif
diff --git a/drivers/gpu/drm/nouveau/core/include/core/falcon.h b/drivers/gpu/drm/nouveau/core/include/engine/falcon.h
index 1edec386ab36..1edec386ab36 100644
--- a/drivers/gpu/drm/nouveau/core/include/core/falcon.h
+++ b/drivers/gpu/drm/nouveau/core/include/engine/falcon.h
diff --git a/drivers/gpu/drm/nouveau/core/include/engine/graph.h b/drivers/gpu/drm/nouveau/core/include/engine/graph.h
index 5d392439f2ac..8e1b52312ddc 100644
--- a/drivers/gpu/drm/nouveau/core/include/engine/graph.h
+++ b/drivers/gpu/drm/nouveau/core/include/engine/graph.h
@@ -61,8 +61,14 @@ extern struct nouveau_oclass nv34_graph_oclass;
 extern struct nouveau_oclass nv35_graph_oclass;
 extern struct nouveau_oclass nv40_graph_oclass;
 extern struct nouveau_oclass nv50_graph_oclass;
-extern struct nouveau_oclass nvc0_graph_oclass;
-extern struct nouveau_oclass nve0_graph_oclass;
+extern struct nouveau_oclass *nvc0_graph_oclass;
+extern struct nouveau_oclass *nvc1_graph_oclass;
+extern struct nouveau_oclass *nvc3_graph_oclass;
+extern struct nouveau_oclass *nvc8_graph_oclass;
+extern struct nouveau_oclass *nvd7_graph_oclass;
+extern struct nouveau_oclass *nvd9_graph_oclass;
+extern struct nouveau_oclass *nve4_graph_oclass;
+extern struct nouveau_oclass *nvf0_graph_oclass;
 
 extern const struct nouveau_bitfield nv04_graph_nsource[];
 extern struct nouveau_ofuncs nv04_graph_ofuncs;
diff --git a/drivers/gpu/drm/nouveau/core/include/engine/mpeg.h b/drivers/gpu/drm/nouveau/core/include/engine/mpeg.h
index bbf0d4a5bbd7..1d1a89a06ee4 100644
--- a/drivers/gpu/drm/nouveau/core/include/engine/mpeg.h
+++ b/drivers/gpu/drm/nouveau/core/include/engine/mpeg.h
@@ -54,7 +54,6 @@ extern struct nouveau_ofuncs nv50_mpeg_ofuncs;
 int  nv50_mpeg_context_ctor(struct nouveau_object *, struct nouveau_object *,
                             struct nouveau_oclass *, void *, u32,
                             struct nouveau_object **);
-int  nv50_mpeg_tlb_flush(struct nouveau_engine *);
 void nv50_mpeg_intr(struct nouveau_subdev *);
 int  nv50_mpeg_init(struct nouveau_object *);
 
diff --git a/drivers/gpu/drm/nouveau/core/include/engine/vp.h b/drivers/gpu/drm/nouveau/core/include/engine/vp.h
index d7b287b115bf..39baebec7fbb 100644
--- a/drivers/gpu/drm/nouveau/core/include/engine/vp.h
+++ b/drivers/gpu/drm/nouveau/core/include/engine/vp.h
@@ -2,6 +2,7 @@
 #define __NOUVEAU_VP_H__
 
 extern struct nouveau_oclass nv84_vp_oclass;
+extern struct nouveau_oclass nv98_vp_oclass;
 extern struct nouveau_oclass nvc0_vp_oclass;
 extern struct nouveau_oclass nve0_vp_oclass;
 
diff --git a/drivers/gpu/drm/nouveau/core/include/engine/xtensa.h b/drivers/gpu/drm/nouveau/core/include/engine/xtensa.h
new file mode 100644
index 000000000000..306100f31f02
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/core/include/engine/xtensa.h
@@ -0,0 +1,38 @@
+#ifndef __NOUVEAU_XTENSA_H__
+#define __NOUVEAU_XTENSA_H__
+
+#include <core/engine.h>
+#include <core/engctx.h>
+#include <core/gpuobj.h>
+
+struct nouveau_xtensa {
+        struct nouveau_engine base;
+
+        u32 addr;
+        struct nouveau_gpuobj *gpu_fw;
+        u32 fifo_val;
+        u32 unkd28;
+};
+
+#define nouveau_xtensa_create(p,e,c,b,d,i,f,r)                          \
+        nouveau_xtensa_create_((p), (e), (c), (b), (d), (i), (f),       \
+                               sizeof(**r),(void **)r)
+
+int _nouveau_xtensa_engctx_ctor(struct nouveau_object *,
+                                struct nouveau_object *,
+                                struct nouveau_oclass *, void *, u32,
+                                struct nouveau_object **);
+
+void _nouveau_xtensa_intr(struct nouveau_subdev *);
+int nouveau_xtensa_create_(struct nouveau_object *,
+                           struct nouveau_object *,
+                           struct nouveau_oclass *, u32, bool,
+                           const char *, const char *,
+                           int, void **);
+#define _nouveau_xtensa_dtor _nouveau_engine_dtor
+int _nouveau_xtensa_init(struct nouveau_object *);
+int _nouveau_xtensa_fini(struct nouveau_object *, bool);
+u32  _nouveau_xtensa_rd32(struct nouveau_object *, u64);
+void _nouveau_xtensa_wr32(struct nouveau_object *, u64, u32);
+
+#endif
diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/clock.h b/drivers/gpu/drm/nouveau/core/include/subdev/clock.h
index 41b7a6a76f19..89ee289097a6 100644
--- a/drivers/gpu/drm/nouveau/core/include/subdev/clock.h
+++ b/drivers/gpu/drm/nouveau/core/include/subdev/clock.h
@@ -10,8 +10,6 @@ struct nvbios_pll;
 struct nouveau_clock {
         struct nouveau_subdev base;
 
-        int (*pll_set)(struct nouveau_clock *, u32 type, u32 freq);
-
         /*XXX: die, these are here *only* to support the completely
          *     bat-shit insane what-was-nouveau_hw.c code
          */
diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/devinit.h b/drivers/gpu/drm/nouveau/core/include/subdev/devinit.h
index 29e4cc1f6cc0..685c9b12ee4c 100644
--- a/drivers/gpu/drm/nouveau/core/include/subdev/devinit.h
+++ b/drivers/gpu/drm/nouveau/core/include/subdev/devinit.h
@@ -8,6 +8,8 @@ struct nouveau_devinit {
         struct nouveau_subdev base;
         bool post;
         void (*meminit)(struct nouveau_devinit *);
+        int  (*pll_set)(struct nouveau_devinit *, u32 type, u32 freq);
+
 };
 
 static inline struct nouveau_devinit *
@@ -20,11 +22,20 @@ nouveau_devinit(void *obj)
         nouveau_devinit_create_((p), (e), (o), sizeof(**d), (void **)d)
 #define nouveau_devinit_destroy(p)                                             \
         nouveau_subdev_destroy(&(p)->base)
+#define nouveau_devinit_init(p) ({                                             \
+        struct nouveau_devinit *d = (p);                                       \
+        _nouveau_devinit_init(nv_object(d));                                   \
+})
+#define nouveau_devinit_fini(p,s) ({                                           \
+        struct nouveau_devinit *d = (p);                                       \
+        _nouveau_devinit_fini(nv_object(d), (s));                              \
+})
 
 int nouveau_devinit_create_(struct nouveau_object *, struct nouveau_object *,
                             struct nouveau_oclass *, int, void **);
-int nouveau_devinit_init(struct nouveau_devinit *);
-int nouveau_devinit_fini(struct nouveau_devinit *, bool suspend);
+#define _nouveau_devinit_dtor _nouveau_subdev_dtor
+int _nouveau_devinit_init(struct nouveau_object *);
+int _nouveau_devinit_fini(struct nouveau_object *, bool suspend);
 
 extern struct nouveau_oclass nv04_devinit_oclass;
 extern struct nouveau_oclass nv05_devinit_oclass;
@@ -32,9 +43,7 @@ extern struct nouveau_oclass nv10_devinit_oclass;
 extern struct nouveau_oclass nv1a_devinit_oclass;
 extern struct nouveau_oclass nv20_devinit_oclass;
 extern struct nouveau_oclass nv50_devinit_oclass;
-
-void nv04_devinit_dtor(struct nouveau_object *);
-int  nv04_devinit_init(struct nouveau_object *);
-int  nv04_devinit_fini(struct nouveau_object *, bool);
+extern struct nouveau_oclass nva3_devinit_oclass;
+extern struct nouveau_oclass nvc0_devinit_oclass;
 
 #endif
diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/fb.h b/drivers/gpu/drm/nouveau/core/include/subdev/fb.h
index da470e6851b1..2e7405084261 100644
--- a/drivers/gpu/drm/nouveau/core/include/subdev/fb.h
+++ b/drivers/gpu/drm/nouveau/core/include/subdev/fb.h
@@ -53,31 +53,7 @@ struct nouveau_fb {
 
         bool (*memtype_valid)(struct nouveau_fb *, u32 memtype);
 
-        struct {
-                enum {
-                        NV_MEM_TYPE_UNKNOWN = 0,
-                        NV_MEM_TYPE_STOLEN,
-                        NV_MEM_TYPE_SGRAM,
-                        NV_MEM_TYPE_SDRAM,
-                        NV_MEM_TYPE_DDR1,
-                        NV_MEM_TYPE_DDR2,
-                        NV_MEM_TYPE_DDR3,
-                        NV_MEM_TYPE_GDDR2,
-                        NV_MEM_TYPE_GDDR3,
-                        NV_MEM_TYPE_GDDR4,
-                        NV_MEM_TYPE_GDDR5
-                } type;
-                u64 stolen;
-                u64 size;
-
-                int ranks;
-                int parts;
-
-                int  (*init)(struct nouveau_fb *);
-                int  (*get)(struct nouveau_fb *, u64 size, u32 align,
-                            u32 size_nc, u32 type, struct nouveau_mem **);
-                void (*put)(struct nouveau_fb *, struct nouveau_mem **);
-        } ram;
+        struct nouveau_ram *ram;
 
         struct nouveau_mm vram;
         struct nouveau_mm tags;
@@ -102,18 +78,6 @@ nouveau_fb(void *obj)
         return (void *)nv_device(obj)->subdev[NVDEV_SUBDEV_FB];
 }
 
-#define nouveau_fb_create(p,e,c,d)                                             \
-        nouveau_subdev_create((p), (e), (c), 0, "PFB", "fb", (d))
-int  nouveau_fb_preinit(struct nouveau_fb *);
-void nouveau_fb_destroy(struct nouveau_fb *);
-int  nouveau_fb_init(struct nouveau_fb *);
-#define nouveau_fb_fini(p,s)                                                   \
-        nouveau_subdev_fini(&(p)->base, (s))
-
-void _nouveau_fb_dtor(struct nouveau_object *);
-int  _nouveau_fb_init(struct nouveau_object *);
-#define _nouveau_fb_fini _nouveau_subdev_fini
-
 extern struct nouveau_oclass nv04_fb_oclass;
 extern struct nouveau_oclass nv10_fb_oclass;
 extern struct nouveau_oclass nv1a_fb_oclass;
@@ -132,40 +96,31 @@ extern struct nouveau_oclass nv4e_fb_oclass;
 extern struct nouveau_oclass nv50_fb_oclass;
 extern struct nouveau_oclass nvc0_fb_oclass;
 
-struct nouveau_bios;
-int  nouveau_fb_bios_memtype(struct nouveau_bios *);
-
-bool nv04_fb_memtype_valid(struct nouveau_fb *, u32 memtype);
-
-void nv10_fb_tile_init(struct nouveau_fb *, int i, u32 addr, u32 size,
-                       u32 pitch, u32 flags, struct nouveau_fb_tile *);
-void nv10_fb_tile_fini(struct nouveau_fb *, int i, struct nouveau_fb_tile *);
-void nv10_fb_tile_prog(struct nouveau_fb *, int, struct nouveau_fb_tile *);
-
-int  nv20_fb_vram_init(struct nouveau_fb *);
-void nv20_fb_tile_init(struct nouveau_fb *, int i, u32 addr, u32 size,
-                       u32 pitch, u32 flags, struct nouveau_fb_tile *);
-void nv20_fb_tile_fini(struct nouveau_fb *, int i, struct nouveau_fb_tile *);
-void nv20_fb_tile_prog(struct nouveau_fb *, int, struct nouveau_fb_tile *);
-
-int  nv30_fb_init(struct nouveau_object *);
-void nv30_fb_tile_init(struct nouveau_fb *, int i, u32 addr, u32 size,
-                       u32 pitch, u32 flags, struct nouveau_fb_tile *);
-
-void nv40_fb_tile_comp(struct nouveau_fb *, int i, u32 size, u32 flags,
-                       struct nouveau_fb_tile *);
-
-int  nv41_fb_vram_init(struct nouveau_fb *);
-int  nv41_fb_init(struct nouveau_object *);
-void nv41_fb_tile_prog(struct nouveau_fb *, int, struct nouveau_fb_tile *);
-
-int  nv44_fb_vram_init(struct nouveau_fb *);
-int  nv44_fb_init(struct nouveau_object *);
-void nv44_fb_tile_prog(struct nouveau_fb *, int, struct nouveau_fb_tile *);
+struct nouveau_ram {
+        struct nouveau_object base;
+        enum {
+                NV_MEM_TYPE_UNKNOWN = 0,
+                NV_MEM_TYPE_STOLEN,
+                NV_MEM_TYPE_SGRAM,
+                NV_MEM_TYPE_SDRAM,
+                NV_MEM_TYPE_DDR1,
+                NV_MEM_TYPE_DDR2,
+                NV_MEM_TYPE_DDR3,
+                NV_MEM_TYPE_GDDR2,
+                NV_MEM_TYPE_GDDR3,
+                NV_MEM_TYPE_GDDR4,
+                NV_MEM_TYPE_GDDR5
+        } type;
+        u64 stolen;
+        u64 size;
+        u32 tags;
 
-void nv46_fb_tile_init(struct nouveau_fb *, int i, u32 addr, u32 size,
-                       u32 pitch, u32 flags, struct nouveau_fb_tile *);
+        int ranks;
+        int parts;
 
-void nv50_fb_vram_del(struct nouveau_fb *, struct nouveau_mem **);
+        int  (*get)(struct nouveau_fb *, u64 size, u32 align,
+                    u32 size_nc, u32 type, struct nouveau_mem **);
+        void (*put)(struct nouveau_fb *, struct nouveau_mem **);
+};
 
 #endif
diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/vm.h b/drivers/gpu/drm/nouveau/core/include/subdev/vm.h
index 9d595efe667a..f2e87b105666 100644
--- a/drivers/gpu/drm/nouveau/core/include/subdev/vm.h
+++ b/drivers/gpu/drm/nouveau/core/include/subdev/vm.h
@@ -58,7 +58,7 @@ struct nouveau_vm {
         int refcount;
 
         struct list_head pgd_list;
-        atomic_t engref[64]; //NVDEV_SUBDEV_NR];
+        atomic_t engref[NVDEV_SUBDEV_NR];
 
         struct nouveau_vm_pgt *pgt;
         u32 fpde;
@@ -117,9 +117,6 @@ int  nv04_vm_create(struct nouveau_vmmgr *, u64, u64, u64,
                     struct nouveau_vm **);
 void nv04_vmmgr_dtor(struct nouveau_object *);
 
-void nv50_vm_flush_engine(struct nouveau_subdev *, int engine);
-void nvc0_vm_flush_engine(struct nouveau_subdev *, u64 addr, int type);
-
 /* nouveau_vm.c */
 int  nouveau_vm_create(struct nouveau_vmmgr *, u64 offset, u64 length,
                        u64 mm_offset, u32 block, struct nouveau_vm **);
diff --git a/drivers/gpu/drm/nouveau/core/subdev/bar/nv50.c b/drivers/gpu/drm/nouveau/core/subdev/bar/nv50.c
index 649f1ced1fe0..160d27f3c7b4 100644
--- a/drivers/gpu/drm/nouveau/core/subdev/bar/nv50.c
+++ b/drivers/gpu/drm/nouveau/core/subdev/bar/nv50.c
@@ -53,7 +53,6 @@ nv50_bar_kmap(struct nouveau_bar *bar, struct nouveau_mem *mem,
                 return ret;
 
         nouveau_vm_map(vma, mem);
-        nv50_vm_flush_engine(nv_subdev(bar), 6);
         return 0;
 }
 
@@ -69,7 +68,6 @@ nv50_bar_umap(struct nouveau_bar *bar, struct nouveau_mem *mem,
                 return ret;
 
         nouveau_vm_map(vma, mem);
-        nv50_vm_flush_engine(nv_subdev(bar), 6);
         return 0;
 }
 
@@ -77,7 +75,6 @@ static void
 nv50_bar_unmap(struct nouveau_bar *bar, struct nouveau_vma *vma)
 {
         nouveau_vm_unmap(vma);
-        nv50_vm_flush_engine(nv_subdev(bar), 6);
         nouveau_vm_put(vma);
 }
 
@@ -147,6 +144,8 @@ nv50_bar_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
         if (ret)
                 return ret;
 
+        atomic_inc(&vm->engref[NVDEV_SUBDEV_BAR]);
+
         ret = nouveau_gpuobj_new(nv_object(priv), heap,
                                  ((limit-- - start) >> 12) * 8, 0x1000,
                                  NVOBJ_FLAG_ZERO_ALLOC, &vm->pgt[0].obj[0]);
@@ -179,6 +178,8 @@ nv50_bar_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
         if (ret)
                 return ret;
 
+        atomic_inc(&vm->engref[NVDEV_SUBDEV_BAR]);
+
         ret = nouveau_vm_ref(vm, &priv->bar1_vm, priv->pgd);
         nouveau_vm_ref(NULL, &vm, NULL);
         if (ret)
@@ -237,7 +238,11 @@ nv50_bar_init(struct nouveau_object *object)
 
         nv_mask(priv, 0x000200, 0x00000100, 0x00000000);
         nv_mask(priv, 0x000200, 0x00000100, 0x00000100);
-        nv50_vm_flush_engine(nv_subdev(priv), 6);
+        nv_wr32(priv, 0x100c80, 0x00060001);
+        if (!nv_wait(priv, 0x100c80, 0x00000001, 0x00000000)) {
+                nv_error(priv, "vm flush timeout\n");
+                return -EBUSY;
+        }
 
         nv_wr32(priv, 0x001704, 0x00000000 | priv->mem->addr >> 12);
         nv_wr32(priv, 0x001704, 0x40000000 | priv->mem->addr >> 12);
diff --git a/drivers/gpu/drm/nouveau/core/subdev/bar/nvc0.c b/drivers/gpu/drm/nouveau/core/subdev/bar/nvc0.c
index f8a44956dec1..b2ec7411eb2e 100644
--- a/drivers/gpu/drm/nouveau/core/subdev/bar/nvc0.c
+++ b/drivers/gpu/drm/nouveau/core/subdev/bar/nvc0.c
@@ -51,7 +51,6 @@ nvc0_bar_kmap(struct nouveau_bar *bar, struct nouveau_mem *mem,
                 return ret;
 
         nouveau_vm_map(vma, mem);
-        nvc0_vm_flush_engine(nv_subdev(bar), priv->bar[0].pgd->addr, 5);
         return 0;
 }
 
@@ -68,18 +67,13 @@ nvc0_bar_umap(struct nouveau_bar *bar, struct nouveau_mem *mem,
                 return ret;
 
         nouveau_vm_map(vma, mem);
-        nvc0_vm_flush_engine(nv_subdev(bar), priv->bar[1].pgd->addr, 5);
         return 0;
 }
 
 static void
 nvc0_bar_unmap(struct nouveau_bar *bar, struct nouveau_vma *vma)
 {
-        struct nvc0_bar_priv *priv = (void *)bar;
-        int i = !(vma->vm == priv->bar[0].vm);
-
         nouveau_vm_unmap(vma);
-        nvc0_vm_flush_engine(nv_subdev(bar), priv->bar[i].pgd->addr, 5);
         nouveau_vm_put(vma);
 }
 
@@ -116,6 +110,8 @@ nvc0_bar_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
         if (ret)
                 return ret;
 
+        atomic_inc(&vm->engref[NVDEV_SUBDEV_BAR]);
+
         ret = nouveau_gpuobj_new(nv_object(priv), NULL,
                                  (pci_resource_len(pdev, 3) >> 12) * 8,
                                  0x1000, NVOBJ_FLAG_ZERO_ALLOC,
@@ -150,6 +146,8 @@ nvc0_bar_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
         if (ret)
                 return ret;
 
+        atomic_inc(&vm->engref[NVDEV_SUBDEV_BAR]);
+
         ret = nouveau_vm_ref(vm, &priv->bar[1].vm, priv->bar[1].pgd);
         nouveau_vm_ref(NULL, &vm, NULL);
         if (ret)
diff --git a/drivers/gpu/drm/nouveau/core/subdev/bios/base.c b/drivers/gpu/drm/nouveau/core/subdev/bios/base.c
index 0e2c1a4f1659..aa0fbbec7f08 100644
--- a/drivers/gpu/drm/nouveau/core/subdev/bios/base.c
+++ b/drivers/gpu/drm/nouveau/core/subdev/bios/base.c
@@ -85,11 +85,15 @@ static void
 nouveau_bios_shadow_pramin(struct nouveau_bios *bios)
 {
         struct nouveau_device *device = nv_device(bios);
+        u64 addr = 0;
         u32 bar0 = 0;
         int i;
 
         if (device->card_type >= NV_50) {
-                u64 addr = (u64)(nv_rd32(bios, 0x619f04) & 0xffffff00) << 8;
+                if (  device->card_type < NV_C0 ||
+                    !(nv_rd32(bios, 0x022500) & 0x00000001))
+                        addr = (u64)(nv_rd32(bios, 0x619f04) & 0xffffff00) << 8;
+
                 if (!addr) {
                         addr  = (u64)nv_rd32(bios, 0x001700) << 16;
                         addr += 0xf0000;
diff --git a/drivers/gpu/drm/nouveau/core/subdev/bios/init.c b/drivers/gpu/drm/nouveau/core/subdev/bios/init.c
index c434d398d16f..0687e6481438 100644
--- a/drivers/gpu/drm/nouveau/core/subdev/bios/init.c
+++ b/drivers/gpu/drm/nouveau/core/subdev/bios/init.c
@@ -10,7 +10,6 @@
 #include <subdev/bios/gpio.h>
 #include <subdev/bios/init.h>
 #include <subdev/devinit.h>
-#include <subdev/clock.h>
 #include <subdev/i2c.h>
 #include <subdev/vga.h>
 #include <subdev/gpio.h>
@@ -300,9 +299,9 @@ init_wrauxr(struct nvbios_init *init, u32 addr, u8 data)
 static void
 init_prog_pll(struct nvbios_init *init, u32 id, u32 freq)
 {
-        struct nouveau_clock *clk = nouveau_clock(init->bios);
-        if (clk && clk->pll_set && init_exec(init)) {
-                int ret = clk->pll_set(clk, id, freq);
+        struct nouveau_devinit *devinit = nouveau_devinit(init->bios);
+        if (devinit->pll_set && init_exec(init)) {
+                int ret = devinit->pll_set(devinit, id, freq);
                 if (ret)
                         warn("failed to prog pll 0x%08x to %dkHz\n", id, freq);
         }
diff --git a/drivers/gpu/drm/nouveau/core/subdev/clock/nv04.c b/drivers/gpu/drm/nouveau/core/subdev/clock/nv04.c
index b7fd1151166e..a14277586595 100644
--- a/drivers/gpu/drm/nouveau/core/subdev/clock/nv04.c
+++ b/drivers/gpu/drm/nouveau/core/subdev/clock/nv04.c
@@ -22,9 +22,10 @@
  * Authors: Ben Skeggs
  */
 
-#include <subdev/clock.h>
 #include <subdev/bios.h>
 #include <subdev/bios/pll.h>
+#include <subdev/clock.h>
+#include <subdev/devinit/priv.h>
 
 #include "pll.h"
 
@@ -32,272 +33,12 @@ struct nv04_clock_priv {
         struct nouveau_clock base;
 };
 
-static int
-powerctrl_1_shift(int chip_version, int reg)
-{
-        int shift = -4;
-
-        if (chip_version < 0x17 || chip_version == 0x1a || chip_version == 0x20)
-                return shift;
-
-        switch (reg) {
-        case 0x680520:
-                shift += 4;
-        case 0x680508:
-                shift += 4;
-        case 0x680504:
-                shift += 4;
-        case 0x680500:
-                shift += 4;
-        }
-
-        /*
-         * the shift for vpll regs is only used for nv3x chips with a single
-         * stage pll
-         */
-        if (shift > 4 && (chip_version < 0x32 || chip_version == 0x35 ||
-                          chip_version == 0x36 || chip_version >= 0x40))
-                shift = -4;
-
-        return shift;
-}
-
-static void
-setPLL_single(struct nv04_clock_priv *priv, u32 reg,
-              struct nouveau_pll_vals *pv)
-{
-        int chip_version = nouveau_bios(priv)->version.chip;
-        uint32_t oldpll = nv_rd32(priv, reg);
-        int oldN = (oldpll >> 8) & 0xff, oldM = oldpll & 0xff;
-        uint32_t pll = (oldpll & 0xfff80000) | pv->log2P << 16 | pv->NM1;
-        uint32_t saved_powerctrl_1 = 0;
-        int shift_powerctrl_1 = powerctrl_1_shift(chip_version, reg);
-
-        if (oldpll == pll)
-                return; /* already set */
-
-        if (shift_powerctrl_1 >= 0) {
-                saved_powerctrl_1 = nv_rd32(priv, 0x001584);
-                nv_wr32(priv, 0x001584,
-                        (saved_powerctrl_1 & ~(0xf << shift_powerctrl_1)) |
-                        1 << shift_powerctrl_1);
-        }
-
-        if (oldM && pv->M1 && (oldN / oldM < pv->N1 / pv->M1))
-                /* upclock -- write new post divider first */
-                nv_wr32(priv, reg, pv->log2P << 16 | (oldpll & 0xffff));
-        else
-                /* downclock -- write new NM first */
-                nv_wr32(priv, reg, (oldpll & 0xffff0000) | pv->NM1);
-
-        if (chip_version < 0x17 && chip_version != 0x11)
-                /* wait a bit on older chips */
-                msleep(64);
-        nv_rd32(priv, reg);
-
-        /* then write the other half as well */
-        nv_wr32(priv, reg, pll);
-
-        if (shift_powerctrl_1 >= 0)
-                nv_wr32(priv, 0x001584, saved_powerctrl_1);
-}
-
-static uint32_t
-new_ramdac580(uint32_t reg1, bool ss, uint32_t ramdac580)
-{
-        bool head_a = (reg1 == 0x680508);
-
-        if (ss) /* single stage pll mode */
-                ramdac580 |= head_a ? 0x00000100 : 0x10000000;
-        else
-                ramdac580 &= head_a ? 0xfffffeff : 0xefffffff;
-
-        return ramdac580;
-}
-
-static void
-setPLL_double_highregs(struct nv04_clock_priv *priv, u32 reg1,
-                       struct nouveau_pll_vals *pv)
-{
-        int chip_version = nouveau_bios(priv)->version.chip;
-        bool nv3035 = chip_version == 0x30 || chip_version == 0x35;
-        uint32_t reg2 = reg1 + ((reg1 == 0x680520) ? 0x5c : 0x70);
-        uint32_t oldpll1 = nv_rd32(priv, reg1);
-        uint32_t oldpll2 = !nv3035 ? nv_rd32(priv, reg2) : 0;
-        uint32_t pll1 = (oldpll1 & 0xfff80000) | pv->log2P << 16 | pv->NM1;
-        uint32_t pll2 = (oldpll2 & 0x7fff0000) | 1 << 31 | pv->NM2;
-        uint32_t oldramdac580 = 0, ramdac580 = 0;
-        bool single_stage = !pv->NM2 || pv->N2 == pv->M2;       /* nv41+ only */
-        uint32_t saved_powerctrl_1 = 0, savedc040 = 0;
-        int shift_powerctrl_1 = powerctrl_1_shift(chip_version, reg1);
-
-        /* model specific additions to generic pll1 and pll2 set up above */
-        if (nv3035) {
-                pll1 = (pll1 & 0xfcc7ffff) | (pv->N2 & 0x18) << 21 |
-                       (pv->N2 & 0x7) << 19 | 8 << 4 | (pv->M2 & 7) << 4;
-                pll2 = 0;
-        }
-        if (chip_version > 0x40 && reg1 >= 0x680508) { /* !nv40 */
-                oldramdac580 = nv_rd32(priv, 0x680580);
-                ramdac580 = new_ramdac580(reg1, single_stage, oldramdac580);
-                if (oldramdac580 != ramdac580)
-                        oldpll1 = ~0;   /* force mismatch */
-                if (single_stage)
-                        /* magic value used by nvidia in single stage mode */
-                        pll2 |= 0x011f;
-        }
-        if (chip_version > 0x70)
-                /* magic bits set by the blob (but not the bios) on g71-73 */
-                pll1 = (pll1 & 0x7fffffff) | (single_stage ? 0x4 : 0xc) << 28;
-
-        if (oldpll1 == pll1 && oldpll2 == pll2)
-                return; /* already set */
-
-        if (shift_powerctrl_1 >= 0) {
-                saved_powerctrl_1 = nv_rd32(priv, 0x001584);
-                nv_wr32(priv, 0x001584,
-                        (saved_powerctrl_1 & ~(0xf << shift_powerctrl_1)) |
-                        1 << shift_powerctrl_1);
-        }
-
-        if (chip_version >= 0x40) {
-                int shift_c040 = 14;
-
-                switch (reg1) {
-                case 0x680504:
-                        shift_c040 += 2;
-                case 0x680500:
-                        shift_c040 += 2;
-                case 0x680520:
-                        shift_c040 += 2;
-                case 0x680508:
-                        shift_c040 += 2;
-                }
-
-                savedc040 = nv_rd32(priv, 0xc040);
-                if (shift_c040 != 14)
-                        nv_wr32(priv, 0xc040, savedc040 & ~(3 << shift_c040));
-        }
-
-        if (oldramdac580 != ramdac580)
-                nv_wr32(priv, 0x680580, ramdac580);
-
-        if (!nv3035)
-                nv_wr32(priv, reg2, pll2);
-        nv_wr32(priv, reg1, pll1);
-
-        if (shift_powerctrl_1 >= 0)
-                nv_wr32(priv, 0x001584, saved_powerctrl_1);
-        if (chip_version >= 0x40)
-                nv_wr32(priv, 0xc040, savedc040);
-}
-
-static void
-setPLL_double_lowregs(struct nv04_clock_priv *priv, u32 NMNMreg,
-                      struct nouveau_pll_vals *pv)
-{
-        /* When setting PLLs, there is a merry game of disabling and enabling
-         * various bits of hardware during the process. This function is a
-         * synthesis of six nv4x traces, nearly each card doing a subtly
-         * different thing. With luck all the necessary bits for each card are
-         * combined herein. Without luck it deviates from each card's formula
-         * so as to not work on any :)
-         */
-
-        uint32_t Preg = NMNMreg - 4;
-        bool mpll = Preg == 0x4020;
-        uint32_t oldPval = nv_rd32(priv, Preg);
-        uint32_t NMNM = pv->NM2 << 16 | pv->NM1;
-        uint32_t Pval = (oldPval & (mpll ? ~(0x77 << 16) : ~(7 << 16))) |
-                        0xc << 28 | pv->log2P << 16;
-        uint32_t saved4600 = 0;
-        /* some cards have different maskc040s */
-        uint32_t maskc040 = ~(3 << 14), savedc040;
-        bool single_stage = !pv->NM2 || pv->N2 == pv->M2;
-
-        if (nv_rd32(priv, NMNMreg) == NMNM && (oldPval & 0xc0070000) == Pval)
-                return;
-
-        if (Preg == 0x4000)
-                maskc040 = ~0x333;
-        if (Preg == 0x4058)
-                maskc040 = ~(0xc << 24);
-
-        if (mpll) {
-                struct nvbios_pll info;
-                uint8_t Pval2;
-
-                if (nvbios_pll_parse(nouveau_bios(priv), Preg, &info))
-                        return;
-
-                Pval2 = pv->log2P + info.bias_p;
-                if (Pval2 > info.max_p)
-                        Pval2 = info.max_p;
-                Pval |= 1 << 28 | Pval2 << 20;
-
-                saved4600 = nv_rd32(priv, 0x4600);
-                nv_wr32(priv, 0x4600, saved4600 | 8 << 28);
-        }
-        if (single_stage)
-                Pval |= mpll ? 1 << 12 : 1 << 8;
-
-        nv_wr32(priv, Preg, oldPval | 1 << 28);
-        nv_wr32(priv, Preg, Pval & ~(4 << 28));
-        if (mpll) {
-                Pval |= 8 << 20;
-                nv_wr32(priv, 0x4020, Pval & ~(0xc << 28));
-                nv_wr32(priv, 0x4038, Pval & ~(0xc << 28));
-        }
-
-        savedc040 = nv_rd32(priv, 0xc040);
-        nv_wr32(priv, 0xc040, savedc040 & maskc040);
-
-        nv_wr32(priv, NMNMreg, NMNM);
-        if (NMNMreg == 0x4024)
-                nv_wr32(priv, 0x403c, NMNM);
-
-        nv_wr32(priv, Preg, Pval);
-        if (mpll) {
-                Pval &= ~(8 << 20);
-                nv_wr32(priv, 0x4020, Pval);
-                nv_wr32(priv, 0x4038, Pval);
-                nv_wr32(priv, 0x4600, saved4600);
-        }
-
-        nv_wr32(priv, 0xc040, savedc040);
-
-        if (mpll) {
-                nv_wr32(priv, 0x4020, Pval & ~(1 << 28));
-                nv_wr32(priv, 0x4038, Pval & ~(1 << 28));
-        }
-}
-
-int
-nv04_clock_pll_set(struct nouveau_clock *clk, u32 type, u32 freq)
-{
-        struct nv04_clock_priv *priv = (void *)clk;
-        struct nouveau_pll_vals pv;
-        struct nvbios_pll info;
-        int ret;
-
-        ret = nvbios_pll_parse(nouveau_bios(priv), type > 0x405c ?
-                               type : type - 4, &info);
-        if (ret)
-                return ret;
-
-        ret = clk->pll_calc(clk, &info, freq, &pv);
-        if (!ret)
-                return ret;
-
-        return clk->pll_prog(clk, type, &pv);
-}
-
 int
 nv04_clock_pll_calc(struct nouveau_clock *clock, struct nvbios_pll *info,
                     int clk, struct nouveau_pll_vals *pv)
 {
         int N1, M1, N2, M2, P;
-        int ret = nv04_pll_calc(clock, info, clk, &N1, &M1, &N2, &M2, &P);
+        int ret = nv04_pll_calc(nv_subdev(clock), info, clk, &N1, &M1, &N2, &M2, &P);
         if (ret) {
                 pv->refclk = info->refclk;
                 pv->N1 = N1;
@@ -313,17 +54,17 @@ int
 nv04_clock_pll_prog(struct nouveau_clock *clk, u32 reg1,
                     struct nouveau_pll_vals *pv)
 {
-        struct nv04_clock_priv *priv = (void *)clk;
+        struct nouveau_devinit *devinit = nouveau_devinit(clk);
         int cv = nouveau_bios(clk)->version.chip;
 
         if (cv == 0x30 || cv == 0x31 || cv == 0x35 || cv == 0x36 ||
             cv >= 0x40) {
                 if (reg1 > 0x405c)
-                        setPLL_double_highregs(priv, reg1, pv);
+                        setPLL_double_highregs(devinit, reg1, pv);
                 else
-                        setPLL_double_lowregs(priv, reg1, pv);
+                        setPLL_double_lowregs(devinit, reg1, pv);
         } else
-                setPLL_single(priv, reg1, pv);
+                setPLL_single(devinit, reg1, pv);
 
         return 0;
 }
@@ -341,7 +82,6 @@ nv04_clock_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
         if (ret)
                 return ret;
 
-        priv->base.pll_set = nv04_clock_pll_set;
         priv->base.pll_calc = nv04_clock_pll_calc;
         priv->base.pll_prog = nv04_clock_pll_prog;
         return 0;
diff --git a/drivers/gpu/drm/nouveau/core/subdev/clock/nv40.c b/drivers/gpu/drm/nouveau/core/subdev/clock/nv40.c
index a4b2b7ebf9af..0db5dbfd91b5 100644
--- a/drivers/gpu/drm/nouveau/core/subdev/clock/nv40.c
+++ b/drivers/gpu/drm/nouveau/core/subdev/clock/nv40.c
@@ -41,7 +41,6 @@ nv40_clock_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
         if (ret)
                 return ret;
 
-        priv->base.pll_set = nv04_clock_pll_set;
         priv->base.pll_calc = nv04_clock_pll_calc;
         priv->base.pll_prog = nv04_clock_pll_prog;
         return 0;
diff --git a/drivers/gpu/drm/nouveau/core/subdev/clock/nv50.c b/drivers/gpu/drm/nouveau/core/subdev/clock/nv50.c
index f4147f67eda6..d09d3e78040c 100644
--- a/drivers/gpu/drm/nouveau/core/subdev/clock/nv50.c
+++ b/drivers/gpu/drm/nouveau/core/subdev/clock/nv50.c
@@ -33,50 +33,6 @@ struct nv50_clock_priv {
 };
 
 static int
-nv50_clock_pll_set(struct nouveau_clock *clk, u32 type, u32 freq)
-{
-        struct nv50_clock_priv *priv = (void *)clk;
-        struct nouveau_bios *bios = nouveau_bios(priv);
-        struct nvbios_pll info;
-        int N1, M1, N2, M2, P;
-        int ret;
-
-        ret = nvbios_pll_parse(bios, type, &info);
-        if (ret) {
-                nv_error(clk, "failed to retrieve pll data, %d\n", ret);
-                return ret;
-        }
-
-        ret = nv04_pll_calc(clk, &info, freq, &N1, &M1, &N2, &M2, &P);
-        if (!ret) {
-                nv_error(clk, "failed pll calculation\n");
-                return ret;
-        }
-
-        switch (info.type) {
-        case PLL_VPLL0:
-        case PLL_VPLL1:
-                nv_wr32(priv, info.reg + 0, 0x10000611);
-                nv_mask(priv, info.reg + 4, 0x00ff00ff, (M1 << 16) | N1);
-                nv_mask(priv, info.reg + 8, 0x7fff00ff, (P  << 28) |
-                                                        (M2 << 16) | N2);
-                break;
-        case PLL_MEMORY:
-                nv_mask(priv, info.reg + 0, 0x01ff0000, (P << 22) |
-                                                        (info.bias_p << 19) |
-                                                        (P << 16));
-                nv_wr32(priv, info.reg + 4, (N1 << 8) | M1);
-                break;
-        default:
-                nv_mask(priv, info.reg + 0, 0x00070000, (P << 16));
-                nv_wr32(priv, info.reg + 4, (N1 << 8) | M1);
-                break;
-        }
-
-        return 0;
-}
-
-static int
 nv50_clock_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
                 struct nouveau_oclass *oclass, void *data, u32 size,
                 struct nouveau_object **pobject)
@@ -89,7 +45,6 @@ nv50_clock_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
         if (ret)
                 return ret;
 
-        priv->base.pll_set = nv50_clock_pll_set;
         priv->base.pll_calc = nv04_clock_pll_calc;
         return 0;
 }
diff --git a/drivers/gpu/drm/nouveau/core/subdev/clock/nva3.c b/drivers/gpu/drm/nouveau/core/subdev/clock/nva3.c
index 9068c98b96f6..f074cd20bc9c 100644
--- a/drivers/gpu/drm/nouveau/core/subdev/clock/nva3.c
+++ b/drivers/gpu/drm/nouveau/core/subdev/clock/nva3.c
@@ -32,47 +32,13 @@ struct nva3_clock_priv {
         struct nouveau_clock base;
 };
 
-static int
-nva3_clock_pll_set(struct nouveau_clock *clk, u32 type, u32 freq)
-{
-        struct nva3_clock_priv *priv = (void *)clk;
-        struct nouveau_bios *bios = nouveau_bios(priv);
-        struct nvbios_pll info;
-        int N, fN, M, P;
-        int ret;
-
-        ret = nvbios_pll_parse(bios, type, &info);
-        if (ret)
-                return ret;
-
-        ret = nva3_pll_calc(clk, &info, freq, &N, &fN, &M, &P);
-        if (ret < 0)
-                return ret;
-
-        switch (info.type) {
-        case PLL_VPLL0:
-        case PLL_VPLL1:
-                nv_wr32(priv, info.reg + 0, 0x50000610);
-                nv_mask(priv, info.reg + 4, 0x003fffff,
-                                            (P << 16) | (M << 8) | N);
-                nv_wr32(priv, info.reg + 8, fN);
-                break;
-        default:
-                nv_warn(priv, "0x%08x/%dKhz unimplemented\n", type, freq);
-                ret = -EINVAL;
-                break;
-        }
-
-        return ret;
-}
-
 int
 nva3_clock_pll_calc(struct nouveau_clock *clock, struct nvbios_pll *info,
                     int clk, struct nouveau_pll_vals *pv)
 {
         int ret, N, M, P;
 
-        ret = nva3_pll_calc(clock, info, clk, &N, NULL, &M, &P);
+        ret = nva3_pll_calc(nv_subdev(clock), info, clk, &N, NULL, &M, &P);
 
         if (ret > 0) {
                 pv->refclk = info->refclk;
@@ -97,7 +63,6 @@ nva3_clock_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
         if (ret)
                 return ret;
 
-        priv->base.pll_set = nva3_clock_pll_set;
         priv->base.pll_calc = nva3_clock_pll_calc;
         return 0;
 }
diff --git a/drivers/gpu/drm/nouveau/core/subdev/clock/nvc0.c b/drivers/gpu/drm/nouveau/core/subdev/clock/nvc0.c
index 7c9626258a46..439d81c26130 100644
--- a/drivers/gpu/drm/nouveau/core/subdev/clock/nvc0.c
+++ b/drivers/gpu/drm/nouveau/core/subdev/clock/nvc0.c
@@ -33,41 +33,6 @@ struct nvc0_clock_priv {
 };
 
 static int
-nvc0_clock_pll_set(struct nouveau_clock *clk, u32 type, u32 freq)
-{
-        struct nvc0_clock_priv *priv = (void *)clk;
-        struct nouveau_bios *bios = nouveau_bios(priv);
-        struct nvbios_pll info;
-        int N, fN, M, P;
-        int ret;
-
-        ret = nvbios_pll_parse(bios, type, &info);
-        if (ret)
-                return ret;
-
-        ret = nva3_pll_calc(clk, &info, freq, &N, &fN, &M, &P);
-        if (ret < 0)
-                return ret;
-
-        switch (info.type) {
-        case PLL_VPLL0:
-        case PLL_VPLL1:
-        case PLL_VPLL2:
-        case PLL_VPLL3:
-                nv_mask(priv, info.reg + 0x0c, 0x00000000, 0x00000100);
-                nv_wr32(priv, info.reg + 0x04, (P << 16) | (N << 8) | M);
-                nv_wr32(priv, info.reg + 0x10, fN << 16);
-                break;
-        default:
-                nv_warn(priv, "0x%08x/%dKhz unimplemented\n", type, freq);
-                ret = -EINVAL;
-                break;
-        }
-
-        return ret;
-}
-
-static int
 nvc0_clock_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
                 struct nouveau_oclass *oclass, void *data, u32 size,
                 struct nouveau_object **pobject)
@@ -80,7 +45,6 @@ nvc0_clock_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
         if (ret)
                 return ret;
 
-        priv->base.pll_set = nvc0_clock_pll_set;
         priv->base.pll_calc = nva3_clock_pll_calc;
         return 0;
 }
diff --git a/drivers/gpu/drm/nouveau/core/subdev/clock/pll.h b/drivers/gpu/drm/nouveau/core/subdev/clock/pll.h
index ef2c0078f337..445b14c33a98 100644
--- a/drivers/gpu/drm/nouveau/core/subdev/clock/pll.h
+++ b/drivers/gpu/drm/nouveau/core/subdev/clock/pll.h
@@ -1,9 +1,9 @@
 #ifndef __NOUVEAU_PLL_H__
 #define __NOUVEAU_PLL_H__
 
-int nv04_pll_calc(struct nouveau_clock *, struct nvbios_pll *, u32 freq,
+int nv04_pll_calc(struct nouveau_subdev *, struct nvbios_pll *, u32 freq,
                   int *N1, int *M1, int *N2, int *M2, int *P);
-int nva3_pll_calc(struct nouveau_clock *, struct nvbios_pll *, u32 freq,
+int nva3_pll_calc(struct nouveau_subdev *, struct nvbios_pll *, u32 freq,
                   int *N, int *fN, int *M, int *P);
 
 #endif
diff --git a/drivers/gpu/drm/nouveau/core/subdev/clock/pllnv04.c b/drivers/gpu/drm/nouveau/core/subdev/clock/pllnv04.c
index a2ab6d051ba8..cf1ed0dc9bc9 100644
--- a/drivers/gpu/drm/nouveau/core/subdev/clock/pllnv04.c
+++ b/drivers/gpu/drm/nouveau/core/subdev/clock/pllnv04.c
@@ -21,14 +21,13 @@
  * SOFTWARE.
  */
 
-#include <subdev/clock.h>
 #include <subdev/bios.h>
 #include <subdev/bios/pll.h>
 
 #include "pll.h"
 
 static int
-getMNP_single(struct nouveau_clock *clock, struct nvbios_pll *info, int clk,
+getMNP_single(struct nouveau_subdev *subdev, struct nvbios_pll *info, int clk,
               int *pN, int *pM, int *pP)
 {
         /* Find M, N and P for a single stage PLL
@@ -39,7 +38,7 @@ getMNP_single(struct nouveau_clock *clock, struct nvbios_pll *info, int clk,
          * "clk" parameter in kHz
          * returns calculated clock
          */
-        int cv = nouveau_bios(clock)->version.chip;
+        int cv = nouveau_bios(subdev)->version.chip;
         int minvco = info->vco1.min_freq, maxvco = info->vco1.max_freq;
         int minM = info->vco1.min_m, maxM = info->vco1.max_m;
         int minN = info->vco1.min_n, maxN = info->vco1.max_n;
@@ -124,7 +123,7 @@ getMNP_single(struct nouveau_clock *clock, struct nvbios_pll *info, int clk,
 }
 
 static int
-getMNP_double(struct nouveau_clock *clock, struct nvbios_pll *info, int clk,
+getMNP_double(struct nouveau_subdev *subdev, struct nvbios_pll *info, int clk,
               int *pN1, int *pM1, int *pN2, int *pM2, int *pP)
 {
         /* Find M, N and P for a two stage PLL
@@ -135,7 +134,7 @@ getMNP_double(struct nouveau_clock *clock, struct nvbios_pll *info, int clk,
          * "clk" parameter in kHz
          * returns calculated clock
          */
-        int chip_version = nouveau_bios(clock)->version.chip;
+        int chip_version = nouveau_bios(subdev)->version.chip;
         int minvco1 = info->vco1.min_freq, maxvco1 = info->vco1.max_freq;
         int minvco2 = info->vco2.min_freq, maxvco2 = info->vco2.max_freq;
         int minU1 = info->vco1.min_inputfreq, minU2 = info->vco2.min_inputfreq;
@@ -223,20 +222,20 @@ getMNP_double(struct nouveau_clock *clock, struct nvbios_pll *info, int clk,
 }
 
 int
-nv04_pll_calc(struct nouveau_clock *clk, struct nvbios_pll *info, u32 freq,
+nv04_pll_calc(struct nouveau_subdev *subdev, struct nvbios_pll *info, u32 freq,
               int *N1, int *M1, int *N2, int *M2, int *P)
 {
         int ret;
 
         if (!info->vco2.max_freq) {
-                ret = getMNP_single(clk, info, freq, N1, M1, P);
+                ret = getMNP_single(subdev, info, freq, N1, M1, P);
                 *N2 = 1;
                 *M2 = 1;
         } else {
-                ret = getMNP_double(clk, info, freq, N1, M1, N2, M2, P);
+                ret = getMNP_double(subdev, info, freq, N1, M1, N2, M2, P);
         }
 
         if (!ret)
-                nv_error(clk, "unable to compute acceptable pll values\n");
+                nv_error(subdev, "unable to compute acceptable pll values\n");
         return ret;
 }
diff --git a/drivers/gpu/drm/nouveau/core/subdev/clock/pllnva3.c b/drivers/gpu/drm/nouveau/core/subdev/clock/pllnva3.c
index eed5c16cf610..2fe1f712eefa 100644
--- a/drivers/gpu/drm/nouveau/core/subdev/clock/pllnva3.c
+++ b/drivers/gpu/drm/nouveau/core/subdev/clock/pllnva3.c
@@ -29,7 +29,7 @@
 #include "pll.h"
 
 int
-nva3_pll_calc(struct nouveau_clock *clock, struct nvbios_pll *info,
+nva3_pll_calc(struct nouveau_subdev *subdev, struct nvbios_pll *info,
               u32 freq, int *pN, int *pfN, int *pM, int *P)
 {
         u32 best_err = ~0, err;
@@ -50,8 +50,15 @@ nva3_pll_calc(struct nouveau_clock *clock, struct nvbios_pll *info,
                 u32 tmp = freq * *P * M;
                 N  = tmp / info->refclk;
                 fN = tmp % info->refclk;
-                if (!pfN && fN >= info->refclk / 2)
-                        N++;
+
+                if (!pfN) {
+                        if (fN >= info->refclk / 2)
+                                N++;
+                } else {
+                        if (fN <  info->refclk / 2)
+                                N--;
+                        fN = tmp - (N * info->refclk);
+                }
 
                 if (N < info->vco1.min_n)
                         continue;
@@ -66,13 +73,14 @@ nva3_pll_calc(struct nouveau_clock *clock, struct nvbios_pll *info,
                 }
 
                 if (pfN) {
-                        *pfN = (((fN << 13) / info->refclk) - 4096) & 0xffff;
+                        *pfN = ((fN << 13) + info->refclk / 2) / info->refclk;
+                        *pfN = (*pfN - 4096) & 0xffff;
                         return freq;
                 }
         }
 
         if (unlikely(best_err == ~0)) {
-                nv_error(clock, "unable to find matching pll values\n");
+                nv_error(subdev, "unable to find matching pll values\n");
                 return -EINVAL;
         }
 
diff --git a/drivers/gpu/drm/nouveau/core/subdev/devinit/base.c b/drivers/gpu/drm/nouveau/core/subdev/devinit/base.c
index 5a07a39c1735..79c81d3d9bac 100644
--- a/drivers/gpu/drm/nouveau/core/subdev/devinit/base.c
+++ b/drivers/gpu/drm/nouveau/core/subdev/devinit/base.c
@@ -29,18 +29,10 @@
 #include <subdev/bios/init.h>
 
 int
-nouveau_devinit_init(struct nouveau_devinit *devinit)
+_nouveau_devinit_fini(struct nouveau_object *object, bool suspend)
 {
-        int ret = nouveau_subdev_init(&devinit->base);
-        if (ret)
-                return ret;
+        struct nouveau_devinit *devinit = (void *)object;
 
-        return nvbios_init(&devinit->base, devinit->post);
-}
-
-int
-nouveau_devinit_fini(struct nouveau_devinit *devinit, bool suspend)
-{
         /* force full reinit on resume */
         if (suspend)
                 devinit->post = true;
@@ -49,6 +41,17 @@ nouveau_devinit_fini(struct nouveau_devinit *devinit, bool suspend)
 }
 
 int
+_nouveau_devinit_init(struct nouveau_object *object)
+{
+        struct nouveau_devinit *devinit = (void *)object;
+        int ret = nouveau_subdev_init(&devinit->base);
+        if (ret)
+                return ret;
+
+        return nvbios_init(&devinit->base, devinit->post);
+}
+
+int
 nouveau_devinit_create_(struct nouveau_object *parent,
                         struct nouveau_object *engine,
                         struct nouveau_oclass *oclass,
diff --git a/drivers/gpu/drm/nouveau/core/subdev/devinit/nv04.c b/drivers/gpu/drm/nouveau/core/subdev/devinit/nv04.c
index 7a72d9394340..b22357d9b821 100644
--- a/drivers/gpu/drm/nouveau/core/subdev/devinit/nv04.c
+++ b/drivers/gpu/drm/nouveau/core/subdev/devinit/nv04.c
@@ -24,10 +24,10 @@
  *
  */
 
-#include <subdev/devinit.h>
 #include <subdev/vga.h>
 
 #include "fbmem.h"
+#include "priv.h"
 
 struct nv04_devinit_priv {
         struct nouveau_devinit base;
@@ -111,33 +111,298 @@ nv04_devinit_meminit(struct nouveau_devinit *devinit)
 }
 
 static int
-nv04_devinit_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
-                  struct nouveau_oclass *oclass, void *data, u32 size,
-                  struct nouveau_object **pobject)
+powerctrl_1_shift(int chip_version, int reg)
 {
-        struct nv04_devinit_priv *priv;
+        int shift = -4;
+
+        if (chip_version < 0x17 || chip_version == 0x1a || chip_version == 0x20)
+                return shift;
+
+        switch (reg) {
+        case 0x680520:
+                shift += 4;
+        case 0x680508:
+                shift += 4;
+        case 0x680504:
+                shift += 4;
+        case 0x680500:
+                shift += 4;
+        }
+
+        /*
+         * the shift for vpll regs is only used for nv3x chips with a single
+         * stage pll
+         */
+        if (shift > 4 && (chip_version < 0x32 || chip_version == 0x35 ||
+                          chip_version == 0x36 || chip_version >= 0x40))
+                shift = -4;
+
+        return shift;
+}
+
+void
+setPLL_single(struct nouveau_devinit *devinit, u32 reg,
+              struct nouveau_pll_vals *pv)
+{
+        int chip_version = nouveau_bios(devinit)->version.chip;
+        uint32_t oldpll = nv_rd32(devinit, reg);
+        int oldN = (oldpll >> 8) & 0xff, oldM = oldpll & 0xff;
+        uint32_t pll = (oldpll & 0xfff80000) | pv->log2P << 16 | pv->NM1;
+        uint32_t saved_powerctrl_1 = 0;
+        int shift_powerctrl_1 = powerctrl_1_shift(chip_version, reg);
+
+        if (oldpll == pll)
+                return; /* already set */
+
+        if (shift_powerctrl_1 >= 0) {
+                saved_powerctrl_1 = nv_rd32(devinit, 0x001584);
+                nv_wr32(devinit, 0x001584,
+                        (saved_powerctrl_1 & ~(0xf << shift_powerctrl_1)) |
+                        1 << shift_powerctrl_1);
+        }
+
+        if (oldM && pv->M1 && (oldN / oldM < pv->N1 / pv->M1))
+                /* upclock -- write new post divider first */
+                nv_wr32(devinit, reg, pv->log2P << 16 | (oldpll & 0xffff));
+        else
+                /* downclock -- write new NM first */
+                nv_wr32(devinit, reg, (oldpll & 0xffff0000) | pv->NM1);
+
+        if (chip_version < 0x17 && chip_version != 0x11)
+                /* wait a bit on older chips */
+                msleep(64);
+        nv_rd32(devinit, reg);
+
+        /* then write the other half as well */
+        nv_wr32(devinit, reg, pll);
+
+        if (shift_powerctrl_1 >= 0)
+                nv_wr32(devinit, 0x001584, saved_powerctrl_1);
+}
+
+static uint32_t
+new_ramdac580(uint32_t reg1, bool ss, uint32_t ramdac580)
+{
+        bool head_a = (reg1 == 0x680508);
+
+        if (ss) /* single stage pll mode */
+                ramdac580 |= head_a ? 0x00000100 : 0x10000000;
+        else
+                ramdac580 &= head_a ? 0xfffffeff : 0xefffffff;
+
+        return ramdac580;
+}
+
+void
+setPLL_double_highregs(struct nouveau_devinit *devinit, u32 reg1,
+                       struct nouveau_pll_vals *pv)
+{
+        int chip_version = nouveau_bios(devinit)->version.chip;
+        bool nv3035 = chip_version == 0x30 || chip_version == 0x35;
+        uint32_t reg2 = reg1 + ((reg1 == 0x680520) ? 0x5c : 0x70);
+        uint32_t oldpll1 = nv_rd32(devinit, reg1);
+        uint32_t oldpll2 = !nv3035 ? nv_rd32(devinit, reg2) : 0;
+        uint32_t pll1 = (oldpll1 & 0xfff80000) | pv->log2P << 16 | pv->NM1;
+        uint32_t pll2 = (oldpll2 & 0x7fff0000) | 1 << 31 | pv->NM2;
+        uint32_t oldramdac580 = 0, ramdac580 = 0;
+        bool single_stage = !pv->NM2 || pv->N2 == pv->M2;       /* nv41+ only */
+        uint32_t saved_powerctrl_1 = 0, savedc040 = 0;
+        int shift_powerctrl_1 = powerctrl_1_shift(chip_version, reg1);
+
+        /* model specific additions to generic pll1 and pll2 set up above */
+        if (nv3035) {
+                pll1 = (pll1 & 0xfcc7ffff) | (pv->N2 & 0x18) << 21 |
+                       (pv->N2 & 0x7) << 19 | 8 << 4 | (pv->M2 & 7) << 4;
+                pll2 = 0;
+        }
+        if (chip_version > 0x40 && reg1 >= 0x680508) { /* !nv40 */
+                oldramdac580 = nv_rd32(devinit, 0x680580);
+                ramdac580 = new_ramdac580(reg1, single_stage, oldramdac580);
+                if (oldramdac580 != ramdac580)
+                        oldpll1 = ~0;   /* force mismatch */
+                if (single_stage)
+                        /* magic value used by nvidia in single stage mode */
+                        pll2 |= 0x011f;
+        }
+        if (chip_version > 0x70)
+                /* magic bits set by the blob (but not the bios) on g71-73 */
+                pll1 = (pll1 & 0x7fffffff) | (single_stage ? 0x4 : 0xc) << 28;
+
+        if (oldpll1 == pll1 && oldpll2 == pll2)
+                return; /* already set */
+
+        if (shift_powerctrl_1 >= 0) {
+                saved_powerctrl_1 = nv_rd32(devinit, 0x001584);
+                nv_wr32(devinit, 0x001584,
+                        (saved_powerctrl_1 & ~(0xf << shift_powerctrl_1)) |
+                        1 << shift_powerctrl_1);
+        }
+
+        if (chip_version >= 0x40) {
+                int shift_c040 = 14;
+
+                switch (reg1) {
+                case 0x680504:
+                        shift_c040 += 2;
+                case 0x680500:
+                        shift_c040 += 2;
+                case 0x680520:
+                        shift_c040 += 2;
+                case 0x680508:
+                        shift_c040 += 2;
+                }
+
+                savedc040 = nv_rd32(devinit, 0xc040);
+                if (shift_c040 != 14)
+                        nv_wr32(devinit, 0xc040, savedc040 & ~(3 << shift_c040));
+        }
+
+        if (oldramdac580 != ramdac580)
+                nv_wr32(devinit, 0x680580, ramdac580);
+
+        if (!nv3035)
+                nv_wr32(devinit, reg2, pll2);
+        nv_wr32(devinit, reg1, pll1);
+
+        if (shift_powerctrl_1 >= 0)
+                nv_wr32(devinit, 0x001584, saved_powerctrl_1);
+        if (chip_version >= 0x40)
+                nv_wr32(devinit, 0xc040, savedc040);
+}
+
+void
+setPLL_double_lowregs(struct nouveau_devinit *devinit, u32 NMNMreg,
+                      struct nouveau_pll_vals *pv)
+{
+        /* When setting PLLs, there is a merry game of disabling and enabling
+         * various bits of hardware during the process. This function is a
+         * synthesis of six nv4x traces, nearly each card doing a subtly
+         * different thing. With luck all the necessary bits for each card are
+         * combined herein. Without luck it deviates from each card's formula
+         * so as to not work on any :)
+         */
+
+        uint32_t Preg = NMNMreg - 4;
+        bool mpll = Preg == 0x4020;
+        uint32_t oldPval = nv_rd32(devinit, Preg);
+        uint32_t NMNM = pv->NM2 << 16 | pv->NM1;
+        uint32_t Pval = (oldPval & (mpll ? ~(0x77 << 16) : ~(7 << 16))) |
+                        0xc << 28 | pv->log2P << 16;
+        uint32_t saved4600 = 0;
+        /* some cards have different maskc040s */
+        uint32_t maskc040 = ~(3 << 14), savedc040;
+        bool single_stage = !pv->NM2 || pv->N2 == pv->M2;
+
+        if (nv_rd32(devinit, NMNMreg) == NMNM && (oldPval & 0xc0070000) == Pval)
+                return;
+
+        if (Preg == 0x4000)
+                maskc040 = ~0x333;
+        if (Preg == 0x4058)
+                maskc040 = ~(0xc << 24);
+
+        if (mpll) {
+                struct nvbios_pll info;
+                uint8_t Pval2;
+
+                if (nvbios_pll_parse(nouveau_bios(devinit), Preg, &info))
+                        return;
+
+                Pval2 = pv->log2P + info.bias_p;
+                if (Pval2 > info.max_p)
+                        Pval2 = info.max_p;
+                Pval |= 1 << 28 | Pval2 << 20;
+
+                saved4600 = nv_rd32(devinit, 0x4600);
+                nv_wr32(devinit, 0x4600, saved4600 | 8 << 28);
+        }
+        if (single_stage)
+                Pval |= mpll ? 1 << 12 : 1 << 8;
+
+        nv_wr32(devinit, Preg, oldPval | 1 << 28);
+        nv_wr32(devinit, Preg, Pval & ~(4 << 28));
+        if (mpll) {
+                Pval |= 8 << 20;
+                nv_wr32(devinit, 0x4020, Pval & ~(0xc << 28));
+                nv_wr32(devinit, 0x4038, Pval & ~(0xc << 28));
+        }
+
+        savedc040 = nv_rd32(devinit, 0xc040);
+        nv_wr32(devinit, 0xc040, savedc040 & maskc040);
+
+        nv_wr32(devinit, NMNMreg, NMNM);
+        if (NMNMreg == 0x4024)
+                nv_wr32(devinit, 0x403c, NMNM);
+
+        nv_wr32(devinit, Preg, Pval);
+        if (mpll) {
+                Pval &= ~(8 << 20);
+                nv_wr32(devinit, 0x4020, Pval);
+                nv_wr32(devinit, 0x4038, Pval);
+                nv_wr32(devinit, 0x4600, saved4600);
+        }
+
+        nv_wr32(devinit, 0xc040, savedc040);
+
+        if (mpll) {
+                nv_wr32(devinit, 0x4020, Pval & ~(1 << 28));
+                nv_wr32(devinit, 0x4038, Pval & ~(1 << 28));
+        }
+}
+
+int
+nv04_devinit_pll_set(struct nouveau_devinit *devinit, u32 type, u32 freq)
+{
+        struct nouveau_bios *bios = nouveau_bios(devinit);
+        struct nouveau_pll_vals pv;
+        struct nvbios_pll info;
+        int cv = bios->version.chip;
+        int N1, M1, N2, M2, P;
         int ret;
 
-        ret = nouveau_devinit_create(parent, engine, oclass, &priv);
-        *pobject = nv_object(priv);
+        ret = nvbios_pll_parse(bios, type > 0x405c ? type : type - 4, &info);
         if (ret)
                 return ret;
 
-        priv->base.meminit = nv04_devinit_meminit;
-        priv->owner = -1;
+        ret = nv04_pll_calc(nv_subdev(devinit), &info, freq,
+                           &N1, &M1, &N2, &M2, &P);
+        if (!ret)
+                return -EINVAL;
+
+        pv.refclk = info.refclk;
+        pv.N1 = N1;
+        pv.M1 = M1;
+        pv.N2 = N2;
+        pv.M2 = M2;
+        pv.log2P = P;
+
+        if (cv == 0x30 || cv == 0x31 || cv == 0x35 || cv == 0x36 ||
+            cv >= 0x40) {
+                if (type > 0x405c)
+                        setPLL_double_highregs(devinit, type, &pv);
+                else
+                        setPLL_double_lowregs(devinit, type, &pv);
+        } else
+                setPLL_single(devinit, type, &pv);
+
         return 0;
 }
 
-void
-nv04_devinit_dtor(struct nouveau_object *object)
+int
+nv04_devinit_fini(struct nouveau_object *object, bool suspend)
 {
         struct nv04_devinit_priv *priv = (void *)object;
 
-        /* restore vga owner saved at first init, and lock crtc regs  */
-        nv_wrvgaowner(priv, priv->owner);
-        nv_lockvgac(priv, true);
+        /* make i2c busses accessible */
+        nv_mask(priv, 0x000200, 0x00000001, 0x00000001);
 
-        nouveau_devinit_destroy(&priv->base);
+        /* unlock extended vga crtc regs, and unslave crtcs */
+        nv_lockvgac(priv, false);
+        if (priv->owner < 0)
+                priv->owner = nv_rdvgaowner(priv);
+        nv_wrvgaowner(priv, 0);
+
+        return nouveau_devinit_fini(&priv->base, suspend);
 }
 
 int
@@ -160,21 +425,35 @@ nv04_devinit_init(struct nouveau_object *object)
         return nouveau_devinit_init(&priv->base);
 }
 
-int
-nv04_devinit_fini(struct nouveau_object *object, bool suspend)
+void
+nv04_devinit_dtor(struct nouveau_object *object)
 {
         struct nv04_devinit_priv *priv = (void *)object;
 
-        /* make i2c busses accessible */
-        nv_mask(priv, 0x000200, 0x00000001, 0x00000001);
+        /* restore vga owner saved at first init, and lock crtc regs  */
+        nv_wrvgaowner(priv, priv->owner);
+        nv_lockvgac(priv, true);
 
-        /* unlock extended vga crtc regs, and unslave crtcs */
-        nv_lockvgac(priv, false);
-        if (priv->owner < 0)
-                priv->owner = nv_rdvgaowner(priv);
-        nv_wrvgaowner(priv, 0);
+        nouveau_devinit_destroy(&priv->base);
+}
 
-        return nouveau_devinit_fini(&priv->base, suspend);
+static int
+nv04_devinit_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
+                  struct nouveau_oclass *oclass, void *data, u32 size,
+                  struct nouveau_object **pobject)
+{
+        struct nv04_devinit_priv *priv;
+        int ret;
+
+        ret = nouveau_devinit_create(parent, engine, oclass, &priv);
+        *pobject = nv_object(priv);
+        if (ret)
+                return ret;
+
+        priv->base.meminit = nv04_devinit_meminit;
+        priv->base.pll_set = nv04_devinit_pll_set;
+        priv->owner = -1;
+        return 0;
 }
 
 struct nouveau_oclass
diff --git a/drivers/gpu/drm/nouveau/core/subdev/devinit/nv05.c b/drivers/gpu/drm/nouveau/core/subdev/devinit/nv05.c
index 191447d0d252..b1912a8a8942 100644
--- a/drivers/gpu/drm/nouveau/core/subdev/devinit/nv05.c
+++ b/drivers/gpu/drm/nouveau/core/subdev/devinit/nv05.c
@@ -24,12 +24,12 @@
  *
  */
 
-#include <subdev/devinit.h>
 #include <subdev/bios.h>
 #include <subdev/bios/bmp.h>
 #include <subdev/vga.h>
 
 #include "fbmem.h"
+#include "priv.h"
 
 struct nv05_devinit_priv {
         struct nouveau_devinit base;
@@ -144,6 +144,7 @@ nv05_devinit_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
                 return ret;
 
         priv->base.meminit = nv05_devinit_meminit;
+        priv->base.pll_set = nv04_devinit_pll_set;
         return 0;
 }
 
diff --git a/drivers/gpu/drm/nouveau/core/subdev/devinit/nv10.c b/drivers/gpu/drm/nouveau/core/subdev/devinit/nv10.c
index eb76ffab6b0c..463b08fa0968 100644
--- a/drivers/gpu/drm/nouveau/core/subdev/devinit/nv10.c
+++ b/drivers/gpu/drm/nouveau/core/subdev/devinit/nv10.c
@@ -24,10 +24,10 @@
  *
  */
 
-#include <subdev/devinit.h>
 #include <subdev/vga.h>
 
 #include "fbmem.h"
+#include "priv.h"
 
 struct nv10_devinit_priv {
         struct nouveau_devinit base;
@@ -109,6 +109,7 @@ nv10_devinit_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
                 return ret;
 
         priv->base.meminit = nv10_devinit_meminit;
+        priv->base.pll_set = nv04_devinit_pll_set;
         return 0;
 }
 
diff --git a/drivers/gpu/drm/nouveau/core/subdev/devinit/nv1a.c b/drivers/gpu/drm/nouveau/core/subdev/devinit/nv1a.c
index 5b2ba630d913..e9743cdabe75 100644
--- a/drivers/gpu/drm/nouveau/core/subdev/devinit/nv1a.c
+++ b/drivers/gpu/drm/nouveau/core/subdev/devinit/nv1a.c
@@ -22,8 +22,7 @@
  * Authors: Ben Skeggs
  */
 
-#include <subdev/devinit.h>
-#include <subdev/vga.h>
+#include "priv.h"
 
 struct nv1a_devinit_priv {
         struct nouveau_devinit base;
@@ -43,6 +42,7 @@ nv1a_devinit_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
         if (ret)
                 return ret;
 
+        priv->base.pll_set = nv04_devinit_pll_set;
         return 0;
 }
 
diff --git a/drivers/gpu/drm/nouveau/core/subdev/devinit/nv20.c b/drivers/gpu/drm/nouveau/core/subdev/devinit/nv20.c
index eb32e99005e4..6cc6080d3bc0 100644
--- a/drivers/gpu/drm/nouveau/core/subdev/devinit/nv20.c
+++ b/drivers/gpu/drm/nouveau/core/subdev/devinit/nv20.c
@@ -24,9 +24,7 @@
  *
  */
 
-#include <subdev/devinit.h>
-#include <subdev/vga.h>
-
+#include "priv.h"
 #include "fbmem.h"
 
 struct nv20_devinit_priv {
@@ -81,6 +79,7 @@ nv20_devinit_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
                 return ret;
 
         priv->base.meminit = nv20_devinit_meminit;
+        priv->base.pll_set = nv04_devinit_pll_set;
         return 0;
 }
 
diff --git a/drivers/gpu/drm/nouveau/core/subdev/devinit/nv50.c b/drivers/gpu/drm/nouveau/core/subdev/devinit/nv50.c
index 4a8577838417..6df72247c477 100644
--- a/drivers/gpu/drm/nouveau/core/subdev/devinit/nv50.c
+++ b/drivers/gpu/drm/nouveau/core/subdev/devinit/nv50.c
@@ -1,5 +1,5 @@
 /*
- * Copyright 2012 Red Hat Inc.
+ * Copyright 2013 Red Hat Inc.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -26,37 +26,55 @@
 #include <subdev/bios/dcb.h>
 #include <subdev/bios/disp.h>
 #include <subdev/bios/init.h>
-#include <subdev/devinit.h>
 #include <subdev/vga.h>
 
-struct nv50_devinit_priv {
-        struct nouveau_devinit base;
-};
+#include "priv.h"
 
 static int
-nv50_devinit_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
-                  struct nouveau_oclass *oclass, void *data, u32 size,
-                  struct nouveau_object **pobject)
+nv50_devinit_pll_set(struct nouveau_devinit *devinit, u32 type, u32 freq)
 {
-        struct nv50_devinit_priv *priv;
+        struct nv50_devinit_priv *priv = (void *)devinit;
+        struct nouveau_bios *bios = nouveau_bios(priv);
+        struct nvbios_pll info;
+        int N1, M1, N2, M2, P;
         int ret;
 
-        ret = nouveau_devinit_create(parent, engine, oclass, &priv);
-        *pobject = nv_object(priv);
-        if (ret)
+        ret = nvbios_pll_parse(bios, type, &info);
+        if (ret) {
+                nv_error(devinit, "failed to retrieve pll data, %d\n", ret);
                 return ret;
+        }
 
-        return 0;
-}
+        ret = nv04_pll_calc(nv_subdev(devinit), &info, freq, &N1, &M1, &N2, &M2, &P);
+        if (!ret) {
+                nv_error(devinit, "failed pll calculation\n");
+                return ret;
+        }
 
-static void
-nv50_devinit_dtor(struct nouveau_object *object)
-{
-        struct nv50_devinit_priv *priv = (void *)object;
-        nouveau_devinit_destroy(&priv->base);
+        switch (info.type) {
+        case PLL_VPLL0:
+        case PLL_VPLL1:
+                nv_wr32(priv, info.reg + 0, 0x10000611);
+                nv_mask(priv, info.reg + 4, 0x00ff00ff, (M1 << 16) | N1);
+                nv_mask(priv, info.reg + 8, 0x7fff00ff, (P  << 28) |
+                                                        (M2 << 16) | N2);
+                break;
+        case PLL_MEMORY:
+                nv_mask(priv, info.reg + 0, 0x01ff0000, (P << 22) |
+                                                        (info.bias_p << 19) |
+                                                        (P << 16));
+                nv_wr32(priv, info.reg + 4, (N1 << 8) | M1);
+                break;
+        default:
+                nv_mask(priv, info.reg + 0, 0x00070000, (P << 16));
+                nv_wr32(priv, info.reg + 4, (N1 << 8) | M1);
+                break;
+        }
+
+        return 0;
 }
 
-static int
+int
 nv50_devinit_init(struct nouveau_object *object)
 {
         struct nouveau_bios *bios = nouveau_bios(object);
@@ -103,10 +121,20 @@ nv50_devinit_init(struct nouveau_object *object)
 }
 
 static int
-nv50_devinit_fini(struct nouveau_object *object, bool suspend)
+nv50_devinit_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
+                  struct nouveau_oclass *oclass, void *data, u32 size,
+                  struct nouveau_object **pobject)
 {
-        struct nv50_devinit_priv *priv = (void *)object;
-        return nouveau_devinit_fini(&priv->base, suspend);
+        struct nv50_devinit_priv *priv;
+        int ret;
+
+        ret = nouveau_devinit_create(parent, engine, oclass, &priv);
+        *pobject = nv_object(priv);
+        if (ret)
+                return ret;
+
+        priv->base.pll_set = nv50_devinit_pll_set;
+        return 0;
 }
 
 struct nouveau_oclass
@@ -114,8 +142,8 @@ nv50_devinit_oclass = {
         .handle = NV_SUBDEV(DEVINIT, 0x50),
         .ofuncs = &(struct nouveau_ofuncs) {
                 .ctor = nv50_devinit_ctor,
-                .dtor = nv50_devinit_dtor,
+                .dtor = _nouveau_devinit_dtor,
                 .init = nv50_devinit_init,
-                .fini = nv50_devinit_fini,
+                .fini = _nouveau_devinit_fini,
         },
 };
diff --git a/drivers/gpu/drm/nouveau/core/subdev/devinit/nva3.c b/drivers/gpu/drm/nouveau/core/subdev/devinit/nva3.c
new file mode 100644
index 000000000000..76a68b290141
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/core/subdev/devinit/nva3.c
@@ -0,0 +1,87 @@
+/*
+ * Copyright 2013 Red Hat Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Ben Skeggs
+ */
+
+#include "priv.h"
+
+static int
+nva3_devinit_pll_set(struct nouveau_devinit *devinit, u32 type, u32 freq)
+{
+        struct nva3_devinit_priv *priv = (void *)devinit;
+        struct nouveau_bios *bios = nouveau_bios(priv);
+        struct nvbios_pll info;
+        int N, fN, M, P;
+        int ret;
+
+        ret = nvbios_pll_parse(bios, type, &info);
+        if (ret)
+                return ret;
+
+        ret = nva3_pll_calc(nv_subdev(devinit), &info, freq, &N, &fN, &M, &P);
+        if (ret < 0)
+                return ret;
+
+        switch (info.type) {
+        case PLL_VPLL0:
+        case PLL_VPLL1:
+                nv_wr32(priv, info.reg + 0, 0x50000610);
+                nv_mask(priv, info.reg + 4, 0x003fffff,
+                                            (P << 16) | (M << 8) | N);
+                nv_wr32(priv, info.reg + 8, fN);
+                break;
+        default:
+                nv_warn(priv, "0x%08x/%dKhz unimplemented\n", type, freq);
+                ret = -EINVAL;
+                break;
+        }
+
+        return ret;
+}
+
+static int
+nva3_devinit_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
+                  struct nouveau_oclass *oclass, void *data, u32 size,
+                  struct nouveau_object **pobject)
+{
+        struct nv50_devinit_priv *priv;
+        int ret;
+
+        ret = nouveau_devinit_create(parent, engine, oclass, &priv);
+        *pobject = nv_object(priv);
+        if (ret)
+                return ret;
+
+        priv->base.pll_set = nva3_devinit_pll_set;
+        return 0;
+}
+
+struct nouveau_oclass
+nva3_devinit_oclass = {
+        .handle = NV_SUBDEV(DEVINIT, 0xa3),
+        .ofuncs = &(struct nouveau_ofuncs) {
+                .ctor = nva3_devinit_ctor,
+                .dtor = _nouveau_devinit_dtor,
+                .init = nv50_devinit_init,
+                .fini = _nouveau_devinit_fini,
+        },
+};
diff --git a/drivers/gpu/drm/nouveau/core/subdev/devinit/nvc0.c b/drivers/gpu/drm/nouveau/core/subdev/devinit/nvc0.c
new file mode 100644
index 000000000000..19e265bf4574
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/core/subdev/devinit/nvc0.c
@@ -0,0 +1,90 @@
+/*
+ * Copyright 2013 Red Hat Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Ben Skeggs
+ */
+
+#include "priv.h"
+
+static int
+nvc0_devinit_pll_set(struct nouveau_devinit *devinit, u32 type, u32 freq)
+{
+        struct nvc0_devinit_priv *priv = (void *)devinit;
+        struct nouveau_bios *bios = nouveau_bios(priv);
+        struct nvbios_pll info;
+        int N, fN, M, P;
+        int ret;
+
+        ret = nvbios_pll_parse(bios, type, &info);
+        if (ret)
+                return ret;
+
+        ret = nva3_pll_calc(nv_subdev(devinit), &info, freq, &N, &fN, &M, &P);
+        if (ret < 0)
+                return ret;
+
+        switch (info.type) {
+        case PLL_VPLL0:
+        case PLL_VPLL1:
+        case PLL_VPLL2:
+        case PLL_VPLL3:
+                nv_mask(priv, info.reg + 0x0c, 0x00000000, 0x00000100);
+                nv_wr32(priv, info.reg + 0x04, (P << 16) | (N << 8) | M);
+                nv_wr32(priv, info.reg + 0x10, fN << 16);
+                break;
+        default:
+                nv_warn(priv, "0x%08x/%dKhz unimplemented\n", type, freq);
+                ret = -EINVAL;
+                break;
+        }
+
+        return ret;
+}
+
+static int
+nvc0_devinit_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
+                  struct nouveau_oclass *oclass, void *data, u32 size,
+                  struct nouveau_object **pobject)
+{
+        struct nv50_devinit_priv *priv;
+        int ret;
+
+        ret = nouveau_devinit_create(parent, engine, oclass, &priv);
+        *pobject = nv_object(priv);
+        if (ret)
+                return ret;
+
+        priv->base.pll_set = nvc0_devinit_pll_set;
+        if (nv_rd32(priv, 0x022500) & 0x00000001)
+                priv->base.post = true;
+        return 0;
+}
+
+struct nouveau_oclass
+nvc0_devinit_oclass = {
+        .handle = NV_SUBDEV(DEVINIT, 0xc0),
+        .ofuncs = &(struct nouveau_ofuncs) {
+                .ctor = nvc0_devinit_ctor,
+                .dtor = _nouveau_devinit_dtor,
+                .init = nv50_devinit_init,
+                .fini = _nouveau_devinit_fini,
+        },
+};
diff --git a/drivers/gpu/drm/nouveau/core/subdev/devinit/priv.h b/drivers/gpu/drm/nouveau/core/subdev/devinit/priv.h
new file mode 100644
index 000000000000..7d622e2b0171
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/core/subdev/devinit/priv.h
@@ -0,0 +1,25 @@
+#ifndef __NVKM_DEVINIT_PRIV_H__
+#define __NVKM_DEVINIT_PRIV_H__
+
+#include <subdev/bios.h>
+#include <subdev/bios/pll.h>
+#include <subdev/clock/pll.h>
+#include <subdev/devinit.h>
+
+void nv04_devinit_dtor(struct nouveau_object *);
+int  nv04_devinit_init(struct nouveau_object *);
+int  nv04_devinit_fini(struct nouveau_object *, bool);
+int  nv04_devinit_pll_set(struct nouveau_devinit *, u32, u32);
+
+void setPLL_single(struct nouveau_devinit *, u32, struct nouveau_pll_vals *);
+void setPLL_double_highregs(struct nouveau_devinit *, u32, struct nouveau_pll_vals *);
+void setPLL_double_lowregs(struct nouveau_devinit *, u32, struct nouveau_pll_vals *);
+
+
+struct nv50_devinit_priv {
+        struct nouveau_devinit base;
+};
+
+int  nv50_devinit_init(struct nouveau_object *);
+
+#endif
diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/base.c b/drivers/gpu/drm/nouveau/core/subdev/fb/base.c
index d62045f454b2..821cd75b86a3 100644
--- a/drivers/gpu/drm/nouveau/core/subdev/fb/base.c
+++ b/drivers/gpu/drm/nouveau/core/subdev/fb/base.c
@@ -57,7 +57,57 @@ nouveau_fb_bios_memtype(struct nouveau_bios *bios)
 }
 
 int
-nouveau_fb_preinit(struct nouveau_fb *pfb)
+_nouveau_fb_fini(struct nouveau_object *object, bool suspend)
+{
+        struct nouveau_fb *pfb = (void *)object;
+        int ret;
+
+        ret = nv_ofuncs(pfb->ram)->fini(nv_object(pfb->ram), suspend);
+        if (ret && suspend)
+                return ret;
+
+        return nouveau_subdev_fini(&pfb->base, suspend);
+}
+
+int
+_nouveau_fb_init(struct nouveau_object *object)
+{
+        struct nouveau_fb *pfb = (void *)object;
+        int ret, i;
+
+        ret = nouveau_subdev_init(&pfb->base);
+        if (ret)
+                return ret;
+
+        ret = nv_ofuncs(pfb->ram)->init(nv_object(pfb->ram));
+        if (ret)
+                return ret;
+
+        for (i = 0; i < pfb->tile.regions; i++)
+                pfb->tile.prog(pfb, i, &pfb->tile.region[i]);
+
+        return 0;
+}
+
+void
+_nouveau_fb_dtor(struct nouveau_object *object)
+{
+        struct nouveau_fb *pfb = (void *)object;
+        int i;
+
+        for (i = 0; i < pfb->tile.regions; i++)
+                pfb->tile.fini(pfb, i, &pfb->tile.region[i]);
+        nouveau_mm_fini(&pfb->tags);
+        nouveau_mm_fini(&pfb->vram);
+
+        nouveau_object_ref(NULL, (struct nouveau_object **)&pfb->ram);
+        nouveau_subdev_destroy(&pfb->base);
+}
+
+int
+nouveau_fb_create_(struct nouveau_object *parent, struct nouveau_object *engine,
+                   struct nouveau_oclass *oclass, struct nouveau_oclass *ramcls,
+                   int length, void **pobject)
 {
         static const char *name[] = {
                 [NV_MEM_TYPE_UNKNOWN] = "unknown",
@@ -72,69 +122,42 @@ nouveau_fb_preinit(struct nouveau_fb *pfb)
                 [NV_MEM_TYPE_GDDR4  ] = "GDDR4",
                 [NV_MEM_TYPE_GDDR5  ] = "GDDR5",
         };
-        int ret, tags;
+        struct nouveau_object *ram;
+        struct nouveau_fb *pfb;
+        int ret;
 
-        tags = pfb->ram.init(pfb);
-        if (tags < 0 || !pfb->ram.size) {
+        ret = nouveau_subdev_create_(parent, engine, oclass, 0, "PFB", "fb",
+                                     length, pobject);
+        pfb = *pobject;
+        if (ret)
+                return ret;
+
+        ret = nouveau_object_ctor(nv_object(pfb), nv_object(pfb),
+                                  ramcls, NULL, 0, &ram);
+        if (ret) {
                 nv_fatal(pfb, "error detecting memory configuration!!\n");
-                return (tags < 0) ? tags : -ERANGE;
+                return ret;
         }
 
+        atomic_dec(&ram->parent->refcount);
+        atomic_dec(&ram->engine->refcount);
+        pfb->ram = (void *)ram;
+
         if (!nouveau_mm_initialised(&pfb->vram)) {
-                ret = nouveau_mm_init(&pfb->vram, 0, pfb->ram.size >> 12, 1);
+                ret = nouveau_mm_init(&pfb->vram, 0, pfb->ram->size >> 12, 1);
                 if (ret)
                         return ret;
         }
 
         if (!nouveau_mm_initialised(&pfb->tags)) {
-                ret = nouveau_mm_init(&pfb->tags, 0, tags ? ++tags : 0, 1);
+                ret = nouveau_mm_init(&pfb->tags, 0, pfb->ram->tags ?
+                                     ++pfb->ram->tags : 0, 1);
                 if (ret)
                         return ret;
         }
 
-        nv_info(pfb, "RAM type: %s\n", name[pfb->ram.type]);
-        nv_info(pfb, "RAM size: %d MiB\n", (int)(pfb->ram.size >> 20));
-        nv_info(pfb, "   ZCOMP: %d tags\n", tags);
+        nv_info(pfb, "RAM type: %s\n", name[pfb->ram->type]);
+        nv_info(pfb, "RAM size: %d MiB\n", (int)(pfb->ram->size >> 20));
+        nv_info(pfb, "   ZCOMP: %d tags\n", pfb->ram->tags);
         return 0;
 }
-
-void
-nouveau_fb_destroy(struct nouveau_fb *pfb)
-{
-        int i;
-
-        for (i = 0; i < pfb->tile.regions; i++)
-                pfb->tile.fini(pfb, i, &pfb->tile.region[i]);
-        nouveau_mm_fini(&pfb->tags);
-        nouveau_mm_fini(&pfb->vram);
-
-        nouveau_subdev_destroy(&pfb->base);
-}
-
-void
-_nouveau_fb_dtor(struct nouveau_object *object)
-{
-        struct nouveau_fb *pfb = (void *)object;
-        nouveau_fb_destroy(pfb);
-}
-int
-nouveau_fb_init(struct nouveau_fb *pfb)
-{
-        int ret, i;
-
-        ret = nouveau_subdev_init(&pfb->base);
-        if (ret)
-                return ret;
-
-        for (i = 0; i < pfb->tile.regions; i++)
-                pfb->tile.prog(pfb, i, &pfb->tile.region[i]);
-
-        return 0;
-}
-
-int
-_nouveau_fb_init(struct nouveau_object *object)
-{
-        struct nouveau_fb *pfb = (void *)object;
-        return nouveau_fb_init(pfb);
-}
diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/nv04.c b/drivers/gpu/drm/nouveau/core/subdev/fb/nv04.c
index 6e369f85361e..1f103c7b89fa 100644
--- a/drivers/gpu/drm/nouveau/core/subdev/fb/nv04.c
+++ b/drivers/gpu/drm/nouveau/core/subdev/fb/nv04.c
@@ -22,24 +22,8 @@
  * Authors: Ben Skeggs
  */
 
-#include <subdev/fb.h>
+#include "priv.h"
 
-#define NV04_PFB_BOOT_0                                         0x00100000
-#       define NV04_PFB_BOOT_0_RAM_AMOUNT                       0x00000003
-#       define NV04_PFB_BOOT_0_RAM_AMOUNT_32MB                  0x00000000
-#       define NV04_PFB_BOOT_0_RAM_AMOUNT_4MB                   0x00000001
-#       define NV04_PFB_BOOT_0_RAM_AMOUNT_8MB                   0x00000002
-#       define NV04_PFB_BOOT_0_RAM_AMOUNT_16MB                  0x00000003
-#       define NV04_PFB_BOOT_0_RAM_WIDTH_128                    0x00000004
-#       define NV04_PFB_BOOT_0_RAM_TYPE                         0x00000028
-#       define NV04_PFB_BOOT_0_RAM_TYPE_SGRAM_8MBIT             0x00000000
-#       define NV04_PFB_BOOT_0_RAM_TYPE_SGRAM_16MBIT            0x00000008
-#       define NV04_PFB_BOOT_0_RAM_TYPE_SGRAM_16MBIT_4BANK      0x00000010
-#       define NV04_PFB_BOOT_0_RAM_TYPE_SDRAM_16MBIT            0x00000018
-#       define NV04_PFB_BOOT_0_RAM_TYPE_SDRAM_64MBIT            0x00000020
-#       define NV04_PFB_BOOT_0_RAM_TYPE_SDRAM_64MBITX16         0x00000028
-#       define NV04_PFB_BOOT_0_UMA_ENABLE                       0x00000100
-#       define NV04_PFB_BOOT_0_UMA_SIZE                         0x0000f000
 #define NV04_PFB_CFG0                                           0x00100200
 
 struct nv04_fb_priv {
@@ -56,37 +40,6 @@ nv04_fb_memtype_valid(struct nouveau_fb *pfb, u32 tile_flags)
 }
 
 static int
-nv04_fb_vram_init(struct nouveau_fb *pfb)
-{
-        u32 boot0 = nv_rd32(pfb, NV04_PFB_BOOT_0);
-        if (boot0 & 0x00000100) {
-                pfb->ram.size  = ((boot0 >> 12) & 0xf) * 2 + 2;
-                pfb->ram.size *= 1024 * 1024;
-        } else {
-                switch (boot0 & NV04_PFB_BOOT_0_RAM_AMOUNT) {
-                case NV04_PFB_BOOT_0_RAM_AMOUNT_32MB:
-                        pfb->ram.size = 32 * 1024 * 1024;
-                        break;
-                case NV04_PFB_BOOT_0_RAM_AMOUNT_16MB:
-                        pfb->ram.size = 16 * 1024 * 1024;
-                        break;
-                case NV04_PFB_BOOT_0_RAM_AMOUNT_8MB:
-                        pfb->ram.size = 8 * 1024 * 1024;
-                        break;
-                case NV04_PFB_BOOT_0_RAM_AMOUNT_4MB:
-                        pfb->ram.size = 4 * 1024 * 1024;
-                        break;
-                }
-        }
-
-        if ((boot0 & 0x00000038) <= 0x10)
-                pfb->ram.type = NV_MEM_TYPE_SGRAM;
-        else
-                pfb->ram.type = NV_MEM_TYPE_SDRAM;
-        return 0;
-}
-
-static int
 nv04_fb_init(struct nouveau_object *object)
 {
         struct nv04_fb_priv *priv = (void *)object;
@@ -112,14 +65,13 @@ nv04_fb_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
         struct nv04_fb_priv *priv;
         int ret;
 
-        ret = nouveau_fb_create(parent, engine, oclass, &priv);
+        ret = nouveau_fb_create(parent, engine, oclass, &nv04_ram_oclass, &priv);
         *pobject = nv_object(priv);
         if (ret)
                 return ret;
 
         priv->base.memtype_valid = nv04_fb_memtype_valid;
-        priv->base.ram.init = nv04_fb_vram_init;
-        return nouveau_fb_preinit(&priv->base);
+        return 0;
 }
 
 struct nouveau_oclass
diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/nv10.c b/drivers/gpu/drm/nouveau/core/subdev/fb/nv10.c
index edbbe26e858d..be069b5306b6 100644
--- a/drivers/gpu/drm/nouveau/core/subdev/fb/nv10.c
+++ b/drivers/gpu/drm/nouveau/core/subdev/fb/nv10.c
@@ -24,25 +24,12 @@
  *
  */
 
-#include <subdev/fb.h>
+#include "priv.h"
 
 struct nv10_fb_priv {
         struct nouveau_fb base;
 };
 
-static int
-nv10_fb_vram_init(struct nouveau_fb *pfb)
-{
-        u32 cfg0 = nv_rd32(pfb, 0x100200);
-        if (cfg0 & 0x00000001)
-                pfb->ram.type = NV_MEM_TYPE_DDR1;
-        else
-                pfb->ram.type = NV_MEM_TYPE_SDRAM;
-
-        pfb->ram.size = nv_rd32(pfb, 0x10020c) & 0xff000000;
-        return 0;
-}
-
 void
 nv10_fb_tile_init(struct nouveau_fb *pfb, int i, u32 addr, u32 size, u32 pitch,
                   u32 flags, struct nouveau_fb_tile *tile)
@@ -78,18 +65,17 @@ nv10_fb_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
         struct nv10_fb_priv *priv;
         int ret;
 
-        ret = nouveau_fb_create(parent, engine, oclass, &priv);
+        ret = nouveau_fb_create(parent, engine, oclass, &nv10_ram_oclass, &priv);
         *pobject = nv_object(priv);
         if (ret)
                 return ret;
 
         priv->base.memtype_valid = nv04_fb_memtype_valid;
-        priv->base.ram.init = nv10_fb_vram_init;
         priv->base.tile.regions = 8;
         priv->base.tile.init = nv10_fb_tile_init;
         priv->base.tile.fini = nv10_fb_tile_fini;
         priv->base.tile.prog = nv10_fb_tile_prog;
-        return nouveau_fb_preinit(&priv->base);
+        return 0;
 }
 
 struct nouveau_oclass
diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/nv1a.c b/drivers/gpu/drm/nouveau/core/subdev/fb/nv1a.c
index 48366841db4a..57a2af0079b3 100644
--- a/drivers/gpu/drm/nouveau/core/subdev/fb/nv1a.c
+++ b/drivers/gpu/drm/nouveau/core/subdev/fb/nv1a.c
@@ -24,38 +24,13 @@
  *
  */
 
-#include <subdev/fb.h>
+#include "priv.h"
 
 struct nv1a_fb_priv {
         struct nouveau_fb base;
 };
 
 static int
-nv1a_fb_vram_init(struct nouveau_fb *pfb)
-{
-        struct pci_dev *bridge;
-        u32 mem, mib;
-
-        bridge = pci_get_bus_and_slot(0, PCI_DEVFN(0, 1));
-        if (!bridge) {
-                nv_fatal(pfb, "no bridge device\n");
-                return -ENODEV;
-        }
-
-        if (nv_device(pfb)->chipset == 0x1a) {
-                pci_read_config_dword(bridge, 0x7c, &mem);
-                mib = ((mem >> 6) & 31) + 1;
-        } else {
-                pci_read_config_dword(bridge, 0x84, &mem);
-                mib = ((mem >> 4) & 127) + 1;
-        }
-
-        pfb->ram.type = NV_MEM_TYPE_STOLEN;
-        pfb->ram.size = mib * 1024 * 1024;
-        return 0;
-}
-
-static int
 nv1a_fb_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
              struct nouveau_oclass *oclass, void *data, u32 size,
              struct nouveau_object **pobject)
@@ -63,18 +38,17 @@ nv1a_fb_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
         struct nv1a_fb_priv *priv;
         int ret;
 
-        ret = nouveau_fb_create(parent, engine, oclass, &priv);
+        ret = nouveau_fb_create(parent, engine, oclass, &nv1a_ram_oclass, &priv);
         *pobject = nv_object(priv);
         if (ret)
                 return ret;
 
         priv->base.memtype_valid = nv04_fb_memtype_valid;
-        priv->base.ram.init = nv1a_fb_vram_init;
         priv->base.tile.regions = 8;
         priv->base.tile.init = nv10_fb_tile_init;
         priv->base.tile.fini = nv10_fb_tile_fini;
         priv->base.tile.prog = nv10_fb_tile_prog;
-        return nouveau_fb_preinit(&priv->base);
+        return 0;
 }
 
 struct nouveau_oclass
diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/nv20.c b/drivers/gpu/drm/nouveau/core/subdev/fb/nv20.c
index 5d14612a2c8e..b18c4e63bb47 100644
--- a/drivers/gpu/drm/nouveau/core/subdev/fb/nv20.c
+++ b/drivers/gpu/drm/nouveau/core/subdev/fb/nv20.c
@@ -24,29 +24,12 @@
  *
  */
 
-#include <subdev/fb.h>
+#include "priv.h"
 
 struct nv20_fb_priv {
         struct nouveau_fb base;
 };
 
-int
-nv20_fb_vram_init(struct nouveau_fb *pfb)
-{
-        u32 pbus1218 = nv_rd32(pfb, 0x001218);
-
-        switch (pbus1218 & 0x00000300) {
-        case 0x00000000: pfb->ram.type = NV_MEM_TYPE_SDRAM; break;
-        case 0x00000100: pfb->ram.type = NV_MEM_TYPE_DDR1; break;
-        case 0x00000200: pfb->ram.type = NV_MEM_TYPE_GDDR3; break;
-        case 0x00000300: pfb->ram.type = NV_MEM_TYPE_GDDR2; break;
-        }
-        pfb->ram.size  = (nv_rd32(pfb, 0x10020c) & 0xff000000);
-        pfb->ram.parts = (nv_rd32(pfb, 0x100200) & 0x00000003) + 1;
-
-        return nv_rd32(pfb, 0x100320);
-}
-
 void
 nv20_fb_tile_init(struct nouveau_fb *pfb, int i, u32 addr, u32 size, u32 pitch,
                   u32 flags, struct nouveau_fb_tile *tile)
@@ -65,7 +48,7 @@ nv20_fb_tile_comp(struct nouveau_fb *pfb, int i, u32 size, u32 flags,
                   struct nouveau_fb_tile *tile)
 {
         u32 tiles = DIV_ROUND_UP(size, 0x40);
-        u32 tags  = round_up(tiles / pfb->ram.parts, 0x40);
+        u32 tags  = round_up(tiles / pfb->ram->parts, 0x40);
         if (!nouveau_mm_head(&pfb->tags, 1, tags, tags, 1, &tile->tag)) {
                 if (!(flags & 2)) tile->zcomp = 0x00000000; /* Z16 */
                 else              tile->zcomp = 0x04000000; /* Z24S8 */
@@ -105,19 +88,18 @@ nv20_fb_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
         struct nv20_fb_priv *priv;
         int ret;
 
-        ret = nouveau_fb_create(parent, engine, oclass, &priv);
+        ret = nouveau_fb_create(parent, engine, oclass, &nv20_ram_oclass, &priv);
         *pobject = nv_object(priv);
         if (ret)
                 return ret;
 
         priv->base.memtype_valid = nv04_fb_memtype_valid;
-        priv->base.ram.init = nv20_fb_vram_init;
         priv->base.tile.regions = 8;
         priv->base.tile.init = nv20_fb_tile_init;
         priv->base.tile.comp = nv20_fb_tile_comp;
         priv->base.tile.fini = nv20_fb_tile_fini;
         priv->base.tile.prog = nv20_fb_tile_prog;
-        return nouveau_fb_preinit(&priv->base);
+        return 0;
 }
 
 struct nouveau_oclass
diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/nv25.c b/drivers/gpu/drm/nouveau/core/subdev/fb/nv25.c
index 0042ace6bef9..32ccabf10c45 100644
--- a/drivers/gpu/drm/nouveau/core/subdev/fb/nv25.c
+++ b/drivers/gpu/drm/nouveau/core/subdev/fb/nv25.c
@@ -24,7 +24,7 @@
  *
  */
 
-#include <subdev/fb.h>
+#include "priv.h"
 
 struct nv25_fb_priv {
         struct nouveau_fb base;
@@ -35,7 +35,7 @@ nv25_fb_tile_comp(struct nouveau_fb *pfb, int i, u32 size, u32 flags,
                   struct nouveau_fb_tile *tile)
 {
         u32 tiles = DIV_ROUND_UP(size, 0x40);
-        u32 tags  = round_up(tiles / pfb->ram.parts, 0x40);
+        u32 tags  = round_up(tiles / pfb->ram->parts, 0x40);
         if (!nouveau_mm_head(&pfb->tags, 1, tags, tags, 1, &tile->tag)) {
                 if (!(flags & 2)) tile->zcomp = 0x00100000; /* Z16 */
                 else              tile->zcomp = 0x00200000; /* Z24S8 */
@@ -54,19 +54,18 @@ nv25_fb_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
         struct nv25_fb_priv *priv;
         int ret;
 
-        ret = nouveau_fb_create(parent, engine, oclass, &priv);
+        ret = nouveau_fb_create(parent, engine, oclass, &nv20_ram_oclass, &priv);
         *pobject = nv_object(priv);
         if (ret)
                 return ret;
 
         priv->base.memtype_valid = nv04_fb_memtype_valid;
-        priv->base.ram.init = nv20_fb_vram_init;
         priv->base.tile.regions = 8;
         priv->base.tile.init = nv20_fb_tile_init;
         priv->base.tile.comp = nv25_fb_tile_comp;
         priv->base.tile.fini = nv20_fb_tile_fini;
         priv->base.tile.prog = nv20_fb_tile_prog;
-        return nouveau_fb_preinit(&priv->base);
+        return 0;
 }
 
 struct nouveau_oclass
diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/nv30.c b/drivers/gpu/drm/nouveau/core/subdev/fb/nv30.c
index a7ba0d048aec..bef756d43d33 100644
--- a/drivers/gpu/drm/nouveau/core/subdev/fb/nv30.c
+++ b/drivers/gpu/drm/nouveau/core/subdev/fb/nv30.c
@@ -24,7 +24,7 @@
  *
  */
 
-#include <subdev/fb.h>
+#include "priv.h"
 
 struct nv30_fb_priv {
         struct nouveau_fb base;
@@ -54,7 +54,7 @@ nv30_fb_tile_comp(struct nouveau_fb *pfb, int i, u32 size, u32 flags,
                   struct nouveau_fb_tile *tile)
 {
         u32 tiles = DIV_ROUND_UP(size, 0x40);
-        u32 tags  = round_up(tiles / pfb->ram.parts, 0x40);
+        u32 tags  = round_up(tiles / pfb->ram->parts, 0x40);
         if (!nouveau_mm_head(&pfb->tags, 1, tags, tags, 1, &tile->tag)) {
                 if (flags & 2) tile->zcomp |= 0x01000000; /* Z16 */
                 else           tile->zcomp |= 0x02000000; /* Z24S8 */
@@ -132,19 +132,18 @@ nv30_fb_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
         struct nv30_fb_priv *priv;
         int ret;
 
-        ret = nouveau_fb_create(parent, engine, oclass, &priv);
+        ret = nouveau_fb_create(parent, engine, oclass, &nv20_ram_oclass, &priv);
         *pobject = nv_object(priv);
         if (ret)
                 return ret;
 
         priv->base.memtype_valid = nv04_fb_memtype_valid;
-        priv->base.ram.init = nv20_fb_vram_init;
         priv->base.tile.regions = 8;
         priv->base.tile.init = nv30_fb_tile_init;
         priv->base.tile.comp = nv30_fb_tile_comp;
         priv->base.tile.fini = nv20_fb_tile_fini;
         priv->base.tile.prog = nv20_fb_tile_prog;
-        return nouveau_fb_preinit(&priv->base);
+        return 0;
 }
 
 struct nouveau_oclass
diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/nv35.c b/drivers/gpu/drm/nouveau/core/subdev/fb/nv35.c
index 092f6f4f3521..097d8e3824f2 100644
--- a/drivers/gpu/drm/nouveau/core/subdev/fb/nv35.c
+++ b/drivers/gpu/drm/nouveau/core/subdev/fb/nv35.c
@@ -24,7 +24,7 @@
  *
  */
 
-#include <subdev/fb.h>
+#include "priv.h"
 
 struct nv35_fb_priv {
         struct nouveau_fb base;
@@ -35,7 +35,7 @@ nv35_fb_tile_comp(struct nouveau_fb *pfb, int i, u32 size, u32 flags,
                   struct nouveau_fb_tile *tile)
 {
         u32 tiles = DIV_ROUND_UP(size, 0x40);
-        u32 tags  = round_up(tiles / pfb->ram.parts, 0x40);
+        u32 tags  = round_up(tiles / pfb->ram->parts, 0x40);
         if (!nouveau_mm_head(&pfb->tags, 1, tags, tags, 1, &tile->tag)) {
                 if (flags & 2) tile->zcomp |= 0x04000000; /* Z16 */
                 else           tile->zcomp |= 0x08000000; /* Z24S8 */
@@ -55,19 +55,18 @@ nv35_fb_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
         struct nv35_fb_priv *priv;
         int ret;
 
-        ret = nouveau_fb_create(parent, engine, oclass, &priv);
+        ret = nouveau_fb_create(parent, engine, oclass, &nv20_ram_oclass, &priv);
         *pobject = nv_object(priv);
         if (ret)
                 return ret;
 
         priv->base.memtype_valid = nv04_fb_memtype_valid;
-        priv->base.ram.init = nv20_fb_vram_init;
         priv->base.tile.regions = 8;
         priv->base.tile.init = nv30_fb_tile_init;
         priv->base.tile.comp = nv35_fb_tile_comp;
         priv->base.tile.fini = nv20_fb_tile_fini;
         priv->base.tile.prog = nv20_fb_tile_prog;
-        return nouveau_fb_preinit(&priv->base);
+        return 0;
 }
 
 struct nouveau_oclass
diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/nv36.c b/drivers/gpu/drm/nouveau/core/subdev/fb/nv36.c
index 797ab3b821b9..9d6d9df896d9 100644
--- a/drivers/gpu/drm/nouveau/core/subdev/fb/nv36.c
+++ b/drivers/gpu/drm/nouveau/core/subdev/fb/nv36.c
@@ -24,7 +24,7 @@
  *
  */
 
-#include <subdev/fb.h>
+#include "priv.h"
 
 struct nv36_fb_priv {
         struct nouveau_fb base;
@@ -35,7 +35,7 @@ nv36_fb_tile_comp(struct nouveau_fb *pfb, int i, u32 size, u32 flags,
                   struct nouveau_fb_tile *tile)
 {
         u32 tiles = DIV_ROUND_UP(size, 0x40);
-        u32 tags  = round_up(tiles / pfb->ram.parts, 0x40);
+        u32 tags  = round_up(tiles / pfb->ram->parts, 0x40);
         if (!nouveau_mm_head(&pfb->tags, 1, tags, tags, 1, &tile->tag)) {
                 if (flags & 2) tile->zcomp |= 0x10000000; /* Z16 */
                 else           tile->zcomp |= 0x20000000; /* Z24S8 */
@@ -55,19 +55,18 @@ nv36_fb_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
         struct nv36_fb_priv *priv;
         int ret;
 
-        ret = nouveau_fb_create(parent, engine, oclass, &priv);
+        ret = nouveau_fb_create(parent, engine, oclass, &nv20_ram_oclass, &priv);
         *pobject = nv_object(priv);
         if (ret)
                 return ret;
 
         priv->base.memtype_valid = nv04_fb_memtype_valid;
-        priv->base.ram.init = nv20_fb_vram_init;
         priv->base.tile.regions = 8;
         priv->base.tile.init = nv30_fb_tile_init;
         priv->base.tile.comp = nv36_fb_tile_comp;
         priv->base.tile.fini = nv20_fb_tile_fini;
         priv->base.tile.prog = nv20_fb_tile_prog;
-        return nouveau_fb_preinit(&priv->base);
+        return 0;
 }
 
 struct nouveau_oclass
diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/nv40.c b/drivers/gpu/drm/nouveau/core/subdev/fb/nv40.c
index 65e131b90f37..33b4393a7829 100644
--- a/drivers/gpu/drm/nouveau/core/subdev/fb/nv40.c
+++ b/drivers/gpu/drm/nouveau/core/subdev/fb/nv40.c
@@ -24,34 +24,18 @@
  *
  */
 
-#include <subdev/fb.h>
+#include "priv.h"
 
 struct nv40_fb_priv {
         struct nouveau_fb base;
 };
 
-static int
-nv40_fb_vram_init(struct nouveau_fb *pfb)
-{
-        u32 pbus1218 = nv_rd32(pfb, 0x001218);
-        switch (pbus1218 & 0x00000300) {
-        case 0x00000000: pfb->ram.type = NV_MEM_TYPE_SDRAM; break;
-        case 0x00000100: pfb->ram.type = NV_MEM_TYPE_DDR1; break;
-        case 0x00000200: pfb->ram.type = NV_MEM_TYPE_GDDR3; break;
-        case 0x00000300: pfb->ram.type = NV_MEM_TYPE_DDR2; break;
-        }
-
-        pfb->ram.size  =  nv_rd32(pfb, 0x10020c) & 0xff000000;
-        pfb->ram.parts = (nv_rd32(pfb, 0x100200) & 0x00000003) + 1;
-        return nv_rd32(pfb, 0x100320);
-}
-
 void
 nv40_fb_tile_comp(struct nouveau_fb *pfb, int i, u32 size, u32 flags,
                   struct nouveau_fb_tile *tile)
 {
         u32 tiles = DIV_ROUND_UP(size, 0x80);
-        u32 tags  = round_up(tiles / pfb->ram.parts, 0x100);
+        u32 tags  = round_up(tiles / pfb->ram->parts, 0x100);
         if ( (flags & 2) &&
             !nouveau_mm_head(&pfb->tags, 1, tags, tags, 1, &tile->tag)) {
                 tile->zcomp  = 0x28000000; /* Z24S8_SPLIT_GRAD */
@@ -85,19 +69,18 @@ nv40_fb_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
         struct nv40_fb_priv *priv;
         int ret;
 
-        ret = nouveau_fb_create(parent, engine, oclass, &priv);
+        ret = nouveau_fb_create(parent, engine, oclass, &nv40_ram_oclass, &priv);
         *pobject = nv_object(priv);
         if (ret)
                 return ret;
 
         priv->base.memtype_valid = nv04_fb_memtype_valid;
-        priv->base.ram.init = nv40_fb_vram_init;
         priv->base.tile.regions = 8;
         priv->base.tile.init = nv30_fb_tile_init;
         priv->base.tile.comp = nv40_fb_tile_comp;
         priv->base.tile.fini = nv20_fb_tile_fini;
         priv->base.tile.prog = nv20_fb_tile_prog;
-        return nouveau_fb_preinit(&priv->base);
+        return 0;
 }
 
 
diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/nv41.c b/drivers/gpu/drm/nouveau/core/subdev/fb/nv41.c
index e9e5a08c41a1..02cd83789cd4 100644
--- a/drivers/gpu/drm/nouveau/core/subdev/fb/nv41.c
+++ b/drivers/gpu/drm/nouveau/core/subdev/fb/nv41.c
@@ -24,28 +24,12 @@
  *
  */
 
-#include <subdev/fb.h>
+#include "priv.h"
 
 struct nv41_fb_priv {
         struct nouveau_fb base;
 };
 
-int
-nv41_fb_vram_init(struct nouveau_fb *pfb)
-{
-        u32 pfb474 = nv_rd32(pfb, 0x100474);
-        if (pfb474 & 0x00000004)
-                pfb->ram.type = NV_MEM_TYPE_GDDR3;
-        if (pfb474 & 0x00000002)
-                pfb->ram.type = NV_MEM_TYPE_DDR2;
-        if (pfb474 & 0x00000001)
-                pfb->ram.type = NV_MEM_TYPE_DDR1;
-
-        pfb->ram.size =   nv_rd32(pfb, 0x10020c) & 0xff000000;
-        pfb->ram.parts = (nv_rd32(pfb, 0x100200) & 0x00000003) + 1;
-        return nv_rd32(pfb, 0x100320);
-}
-
 void
 nv41_fb_tile_prog(struct nouveau_fb *pfb, int i, struct nouveau_fb_tile *tile)
 {
@@ -78,19 +62,18 @@ nv41_fb_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
         struct nv41_fb_priv *priv;
         int ret;
 
-        ret = nouveau_fb_create(parent, engine, oclass, &priv);
+        ret = nouveau_fb_create(parent, engine, oclass, &nv41_ram_oclass, &priv);
         *pobject = nv_object(priv);
         if (ret)
                 return ret;
 
         priv->base.memtype_valid = nv04_fb_memtype_valid;
-        priv->base.ram.init = nv41_fb_vram_init;
         priv->base.tile.regions = 12;
         priv->base.tile.init = nv30_fb_tile_init;
         priv->base.tile.comp = nv40_fb_tile_comp;
         priv->base.tile.fini = nv20_fb_tile_fini;
         priv->base.tile.prog = nv41_fb_tile_prog;
-        return nouveau_fb_preinit(&priv->base);
+        return 0;
 }
 
 
diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/nv44.c b/drivers/gpu/drm/nouveau/core/subdev/fb/nv44.c
index ae89b5006f7a..c5246c29f293 100644
--- a/drivers/gpu/drm/nouveau/core/subdev/fb/nv44.c
+++ b/drivers/gpu/drm/nouveau/core/subdev/fb/nv44.c
@@ -24,27 +24,12 @@
  *
  */
 
-#include <subdev/fb.h>
+#include "priv.h"
 
 struct nv44_fb_priv {
         struct nouveau_fb base;
 };
 
-int
-nv44_fb_vram_init(struct nouveau_fb *pfb)
-{
-        u32 pfb474 = nv_rd32(pfb, 0x100474);
-        if (pfb474 & 0x00000004)
-                pfb->ram.type = NV_MEM_TYPE_GDDR3;
-        if (pfb474 & 0x00000002)
-                pfb->ram.type = NV_MEM_TYPE_DDR2;
-        if (pfb474 & 0x00000001)
-                pfb->ram.type = NV_MEM_TYPE_DDR1;
-
-        pfb->ram.size = nv_rd32(pfb, 0x10020c) & 0xff000000;
-        return 0;
-}
-
 static void
 nv44_fb_tile_init(struct nouveau_fb *pfb, int i, u32 addr, u32 size, u32 pitch,
                   u32 flags, struct nouveau_fb_tile *tile)
@@ -87,18 +72,17 @@ nv44_fb_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
         struct nv44_fb_priv *priv;
         int ret;
 
-        ret = nouveau_fb_create(parent, engine, oclass, &priv);
+        ret = nouveau_fb_create(parent, engine, oclass, &nv44_ram_oclass, &priv);
         *pobject = nv_object(priv);
         if (ret)
                 return ret;
 
         priv->base.memtype_valid = nv04_fb_memtype_valid;
-        priv->base.ram.init = nv44_fb_vram_init;
         priv->base.tile.regions = 12;
         priv->base.tile.init = nv44_fb_tile_init;
         priv->base.tile.fini = nv20_fb_tile_fini;
         priv->base.tile.prog = nv44_fb_tile_prog;
-        return nouveau_fb_preinit(&priv->base);
+        return 0;
 }
 
 
diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/nv46.c b/drivers/gpu/drm/nouveau/core/subdev/fb/nv46.c
index 589b93ea2994..e2b57909bfca 100644
--- a/drivers/gpu/drm/nouveau/core/subdev/fb/nv46.c
+++ b/drivers/gpu/drm/nouveau/core/subdev/fb/nv46.c
@@ -24,7 +24,7 @@
  *
  */
 
-#include <subdev/fb.h>
+#include "priv.h"
 
 struct nv46_fb_priv {
         struct nouveau_fb base;
@@ -52,18 +52,17 @@ nv46_fb_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
         struct nv46_fb_priv *priv;
         int ret;
 
-        ret = nouveau_fb_create(parent, engine, oclass, &priv);
+        ret = nouveau_fb_create(parent, engine, oclass, &nv44_ram_oclass, &priv);
         *pobject = nv_object(priv);
         if (ret)
                 return ret;
 
         priv->base.memtype_valid = nv04_fb_memtype_valid;
-        priv->base.ram.init = nv44_fb_vram_init;
         priv->base.tile.regions = 15;
         priv->base.tile.init = nv46_fb_tile_init;
         priv->base.tile.fini = nv20_fb_tile_fini;
         priv->base.tile.prog = nv44_fb_tile_prog;
-        return nouveau_fb_preinit(&priv->base);
+        return 0;
 }
 
 
diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/nv47.c b/drivers/gpu/drm/nouveau/core/subdev/fb/nv47.c
index 818bba35b368..fe6a2278621d 100644
--- a/drivers/gpu/drm/nouveau/core/subdev/fb/nv47.c
+++ b/drivers/gpu/drm/nouveau/core/subdev/fb/nv47.c
@@ -24,7 +24,7 @@
  *
  */
 
-#include <subdev/fb.h>
+#include "priv.h"
 
 struct nv47_fb_priv {
         struct nouveau_fb base;
@@ -38,19 +38,18 @@ nv47_fb_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
         struct nv47_fb_priv *priv;
         int ret;
 
-        ret = nouveau_fb_create(parent, engine, oclass, &priv);
+        ret = nouveau_fb_create(parent, engine, oclass, &nv41_ram_oclass, &priv);
         *pobject = nv_object(priv);
         if (ret)
                 return ret;
 
         priv->base.memtype_valid = nv04_fb_memtype_valid;
-        priv->base.ram.init = nv41_fb_vram_init;
         priv->base.tile.regions = 15;
         priv->base.tile.init = nv30_fb_tile_init;
         priv->base.tile.comp = nv40_fb_tile_comp;
         priv->base.tile.fini = nv20_fb_tile_fini;
         priv->base.tile.prog = nv41_fb_tile_prog;
-        return nouveau_fb_preinit(&priv->base);
+        return 0;
 }
 
 
diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/nv49.c b/drivers/gpu/drm/nouveau/core/subdev/fb/nv49.c
index 84a31af16ab4..5eca99b8c7e2 100644
--- a/drivers/gpu/drm/nouveau/core/subdev/fb/nv49.c
+++ b/drivers/gpu/drm/nouveau/core/subdev/fb/nv49.c
@@ -24,30 +24,13 @@
  *
  */
 
-#include <subdev/fb.h>
+#include "priv.h"
 
 struct nv49_fb_priv {
         struct nouveau_fb base;
 };
 
 static int
-nv49_fb_vram_init(struct nouveau_fb *pfb)
-{
-        u32 pfb914 = nv_rd32(pfb, 0x100914);
-
-        switch (pfb914 & 0x00000003) {
-        case 0x00000000: pfb->ram.type = NV_MEM_TYPE_DDR1; break;
-        case 0x00000001: pfb->ram.type = NV_MEM_TYPE_DDR2; break;
-        case 0x00000002: pfb->ram.type = NV_MEM_TYPE_GDDR3; break;
-        case 0x00000003: break;
-        }
-
-        pfb->ram.size =   nv_rd32(pfb, 0x10020c) & 0xff000000;
-        pfb->ram.parts = (nv_rd32(pfb, 0x100200) & 0x00000003) + 1;
-        return nv_rd32(pfb, 0x100320);
-}
-
-static int
 nv49_fb_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
              struct nouveau_oclass *oclass, void *data, u32 size,
              struct nouveau_object **pobject)
@@ -55,20 +38,18 @@ nv49_fb_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
         struct nv49_fb_priv *priv;
         int ret;
 
-        ret = nouveau_fb_create(parent, engine, oclass, &priv);
+        ret = nouveau_fb_create(parent, engine, oclass, &nv49_ram_oclass, &priv);
         *pobject = nv_object(priv);
         if (ret)
                 return ret;
 
         priv->base.memtype_valid = nv04_fb_memtype_valid;
-        priv->base.ram.init = nv49_fb_vram_init;
         priv->base.tile.regions = 15;
         priv->base.tile.init = nv30_fb_tile_init;
         priv->base.tile.comp = nv40_fb_tile_comp;
         priv->base.tile.fini = nv20_fb_tile_fini;
         priv->base.tile.prog = nv41_fb_tile_prog;
-
-        return nouveau_fb_preinit(&priv->base);
+        return 0;
 }
 
 
diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/nv4e.c b/drivers/gpu/drm/nouveau/core/subdev/fb/nv4e.c
index 797fd558170b..1190b78a1e91 100644
--- a/drivers/gpu/drm/nouveau/core/subdev/fb/nv4e.c
+++ b/drivers/gpu/drm/nouveau/core/subdev/fb/nv4e.c
@@ -24,21 +24,13 @@
  *
  */
 
-#include <subdev/fb.h>
+#include "priv.h"
 
 struct nv4e_fb_priv {
         struct nouveau_fb base;
 };
 
 static int
-nv4e_fb_vram_init(struct nouveau_fb *pfb)
-{
-        pfb->ram.size = nv_rd32(pfb, 0x10020c) & 0xff000000;
-        pfb->ram.type = NV_MEM_TYPE_STOLEN;
-        return 0;
-}
-
-static int
 nv4e_fb_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
              struct nouveau_oclass *oclass, void *data, u32 size,
              struct nouveau_object **pobject)
@@ -46,18 +38,17 @@ nv4e_fb_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
         struct nv4e_fb_priv *priv;
         int ret;
 
-        ret = nouveau_fb_create(parent, engine, oclass, &priv);
+        ret = nouveau_fb_create(parent, engine, oclass, &nv4e_ram_oclass, &priv);
         *pobject = nv_object(priv);
         if (ret)
                 return ret;
 
         priv->base.memtype_valid = nv04_fb_memtype_valid;
-        priv->base.ram.init = nv4e_fb_vram_init;
         priv->base.tile.regions = 12;
         priv->base.tile.init = nv46_fb_tile_init;
         priv->base.tile.fini = nv20_fb_tile_fini;
         priv->base.tile.prog = nv44_fb_tile_prog;
-        return nouveau_fb_preinit(&priv->base);
+        return 0;
 }
 
 struct nouveau_oclass
diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/nv50.c b/drivers/gpu/drm/nouveau/core/subdev/fb/nv50.c
index 0772ec978165..da614ec5564b 100644
--- a/drivers/gpu/drm/nouveau/core/subdev/fb/nv50.c
+++ b/drivers/gpu/drm/nouveau/core/subdev/fb/nv50.c
@@ -27,7 +27,7 @@
 #include <core/engctx.h>
 #include <core/object.h>
 
-#include <subdev/fb.h>
+#include "priv.h"
 #include <subdev/bios.h>
 
 struct nv50_fb_priv {
@@ -36,7 +36,8 @@ struct nv50_fb_priv {
         dma_addr_t r100c08;
 };
 
-static int types[0x80] = {
+int
+nv50_fb_memtype[0x80] = {
         1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
         1, 1, 1, 1, 0, 0, 0, 0, 2, 2, 2, 2, 0, 0, 0, 0,
         1, 1, 1, 1, 1, 1, 1, 0, 2, 2, 2, 2, 2, 2, 2, 0,
@@ -50,192 +51,7 @@ static int types[0x80] = {
 static bool
 nv50_fb_memtype_valid(struct nouveau_fb *pfb, u32 memtype)
 {
-        return types[(memtype & 0xff00) >> 8] != 0;
-}
-
-static u32
-nv50_fb_vram_rblock(struct nouveau_fb *pfb)
-{
-        int i, parts, colbits, rowbitsa, rowbitsb, banks;
-        u64 rowsize, predicted;
-        u32 r0, r4, rt, ru, rblock_size;
-
-        r0 = nv_rd32(pfb, 0x100200);
-        r4 = nv_rd32(pfb, 0x100204);
-        rt = nv_rd32(pfb, 0x100250);
-        ru = nv_rd32(pfb, 0x001540);
-        nv_debug(pfb, "memcfg 0x%08x 0x%08x 0x%08x 0x%08x\n", r0, r4, rt, ru);
-
-        for (i = 0, parts = 0; i < 8; i++) {
-                if (ru & (0x00010000 << i))
-                        parts++;
-        }
-
-        colbits  =  (r4 & 0x0000f000) >> 12;
-        rowbitsa = ((r4 & 0x000f0000) >> 16) + 8;
-        rowbitsb = ((r4 & 0x00f00000) >> 20) + 8;
-        banks    = 1 << (((r4 & 0x03000000) >> 24) + 2);
-
-        rowsize = parts * banks * (1 << colbits) * 8;
-        predicted = rowsize << rowbitsa;
-        if (r0 & 0x00000004)
-                predicted += rowsize << rowbitsb;
-
-        if (predicted != pfb->ram.size) {
-                nv_warn(pfb, "memory controller reports %d MiB VRAM\n",
-                        (u32)(pfb->ram.size >> 20));
-        }
-
-        rblock_size = rowsize;
-        if (rt & 1)
-                rblock_size *= 3;
-
-        nv_debug(pfb, "rblock %d bytes\n", rblock_size);
-        return rblock_size;
-}
-
-static int
-nv50_fb_vram_init(struct nouveau_fb *pfb)
-{
-        struct nouveau_device *device = nv_device(pfb);
-        struct nouveau_bios *bios = nouveau_bios(device);
-        const u32 rsvd_head = ( 256 * 1024) >> 12; /* vga memory */
-        const u32 rsvd_tail = (1024 * 1024) >> 12; /* vbios etc */
-        u32 size, tags = 0;
-        int ret;
-
-        pfb->ram.size = nv_rd32(pfb, 0x10020c);
-        pfb->ram.size = (pfb->ram.size & 0xffffff00) |
-                       ((pfb->ram.size & 0x000000ff) << 32);
-
-        size = (pfb->ram.size >> 12) - rsvd_head - rsvd_tail;
-        switch (device->chipset) {
-        case 0xaa:
-        case 0xac:
-        case 0xaf: /* IGPs, no reordering, no real VRAM */
-                ret = nouveau_mm_init(&pfb->vram, rsvd_head, size, 1);
-                if (ret)
-                        return ret;
-
-                pfb->ram.type   = NV_MEM_TYPE_STOLEN;
-                pfb->ram.stolen = (u64)nv_rd32(pfb, 0x100e10) << 12;
-                break;
-        default:
-                switch (nv_rd32(pfb, 0x100714) & 0x00000007) {
-                case 0: pfb->ram.type = NV_MEM_TYPE_DDR1; break;
-                case 1:
-                        if (nouveau_fb_bios_memtype(bios) == NV_MEM_TYPE_DDR3)
-                                pfb->ram.type = NV_MEM_TYPE_DDR3;
-                        else
-                                pfb->ram.type = NV_MEM_TYPE_DDR2;
-                        break;
-                case 2: pfb->ram.type = NV_MEM_TYPE_GDDR3; break;
-                case 3: pfb->ram.type = NV_MEM_TYPE_GDDR4; break;
-                case 4: pfb->ram.type = NV_MEM_TYPE_GDDR5; break;
-                default:
-                        break;
-                }
-
-                ret = nouveau_mm_init(&pfb->vram, rsvd_head, size,
-                                      nv50_fb_vram_rblock(pfb) >> 12);
-                if (ret)
-                        return ret;
-
-                pfb->ram.ranks = (nv_rd32(pfb, 0x100200) & 0x4) ? 2 : 1;
-                tags = nv_rd32(pfb, 0x100320);
-                break;
-        }
-
-        return tags;
-}
-
-static int
-nv50_fb_vram_new(struct nouveau_fb *pfb, u64 size, u32 align, u32 ncmin,
-                 u32 memtype, struct nouveau_mem **pmem)
-{
-        struct nv50_fb_priv *priv = (void *)pfb;
-        struct nouveau_mm *heap = &priv->base.vram;
-        struct nouveau_mm *tags = &priv->base.tags;
-        struct nouveau_mm_node *r;
-        struct nouveau_mem *mem;
-        int comp = (memtype & 0x300) >> 8;
-        int type = (memtype & 0x07f);
-        int back = (memtype & 0x800);
-        int min, max, ret;
-
-        max = (size >> 12);
-        min = ncmin ? (ncmin >> 12) : max;
-        align >>= 12;
-
-        mem = kzalloc(sizeof(*mem), GFP_KERNEL);
-        if (!mem)
-                return -ENOMEM;
-
-        mutex_lock(&pfb->base.mutex);
-        if (comp) {
-                if (align == 16) {
-                        int n = (max >> 4) * comp;
-
-                        ret = nouveau_mm_head(tags, 1, n, n, 1, &mem->tag);
-                        if (ret)
-                                mem->tag = NULL;
-                }
-
-                if (unlikely(!mem->tag))
-                        comp = 0;
-        }
-
-        INIT_LIST_HEAD(&mem->regions);
-        mem->memtype = (comp << 7) | type;
-        mem->size = max;
-
-        type = types[type];
-        do {
-                if (back)
-                        ret = nouveau_mm_tail(heap, type, max, min, align, &r);
-                else
-                        ret = nouveau_mm_head(heap, type, max, min, align, &r);
-                if (ret) {
-                        mutex_unlock(&pfb->base.mutex);
-                        pfb->ram.put(pfb, &mem);
-                        return ret;
-                }
-
-                list_add_tail(&r->rl_entry, &mem->regions);
-                max -= r->length;
-        } while (max);
-        mutex_unlock(&pfb->base.mutex);
-
-        r = list_first_entry(&mem->regions, struct nouveau_mm_node, rl_entry);
-        mem->offset = (u64)r->offset << 12;
-        *pmem = mem;
-        return 0;
-}
-
-void
-nv50_fb_vram_del(struct nouveau_fb *pfb, struct nouveau_mem **pmem)
-{
-        struct nv50_fb_priv *priv = (void *)pfb;
-        struct nouveau_mm_node *this;
-        struct nouveau_mem *mem;
-
-        mem = *pmem;
-        *pmem = NULL;
-        if (unlikely(mem == NULL))
-                return;
-
-        mutex_lock(&pfb->base.mutex);
-        while (!list_empty(&mem->regions)) {
-                this = list_first_entry(&mem->regions, typeof(*this), rl_entry);
-
-                list_del(&this->rl_entry);
-                nouveau_mm_free(&priv->base.vram, &this);
-        }
-
-        nouveau_mm_free(&priv->base.tags, &mem->tag);
-        mutex_unlock(&pfb->base.mutex);
-
-        kfree(mem);
+        return nv50_fb_memtype[(memtype & 0xff00) >> 8] != 0;
 }
 
 static const struct nouveau_enum vm_dispatch_subclients[] = {
@@ -432,7 +248,7 @@ nv50_fb_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
         struct nv50_fb_priv *priv;
         int ret;
 
-        ret = nouveau_fb_create(parent, engine, oclass, &priv);
+        ret = nouveau_fb_create(parent, engine, oclass, &nv50_ram_oclass, &priv);
         *pobject = nv_object(priv);
         if (ret)
                 return ret;
@@ -449,11 +265,8 @@ nv50_fb_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
         }
 
         priv->base.memtype_valid = nv50_fb_memtype_valid;
-        priv->base.ram.init = nv50_fb_vram_init;
-        priv->base.ram.get = nv50_fb_vram_new;
-        priv->base.ram.put = nv50_fb_vram_del;
         nv_subdev(priv)->intr = nv50_fb_intr;
-        return nouveau_fb_preinit(&priv->base);
+        return 0;
 }
 
 static void
diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/nvc0.c b/drivers/gpu/drm/nouveau/core/subdev/fb/nvc0.c
index 86ad59203c8b..f35d76fd746d 100644
--- a/drivers/gpu/drm/nouveau/core/subdev/fb/nvc0.c
+++ b/drivers/gpu/drm/nouveau/core/subdev/fb/nvc0.c
@@ -22,9 +22,7 @@
  * Authors: Ben Skeggs
  */
 
-#include <subdev/fb.h>
-#include <subdev/ltcg.h>
-#include <subdev/bios.h>
+#include "priv.h"
 
 struct nvc0_fb_priv {
         struct nouveau_fb base;
@@ -34,7 +32,6 @@ struct nvc0_fb_priv {
 
 extern const u8 nvc0_pte_storage_type_map[256];
 
-
 static bool
 nvc0_fb_memtype_valid(struct nouveau_fb *pfb, u32 tile_flags)
 {
@@ -43,137 +40,6 @@ nvc0_fb_memtype_valid(struct nouveau_fb *pfb, u32 tile_flags)
 }
 
 static int
-nvc0_fb_vram_init(struct nouveau_fb *pfb)
-{
-        struct nouveau_bios *bios = nouveau_bios(pfb);
-        const u32 rsvd_head = ( 256 * 1024) >> 12; /* vga memory */
-        const u32 rsvd_tail = (1024 * 1024) >> 12; /* vbios etc */
-        u32 parts = nv_rd32(pfb, 0x022438);
-        u32 pmask = nv_rd32(pfb, 0x022554);
-        u32 bsize = nv_rd32(pfb, 0x10f20c);
-        u32 offset, length;
-        bool uniform = true;
-        int ret, part;
-
-        nv_debug(pfb, "0x100800: 0x%08x\n", nv_rd32(pfb, 0x100800));
-        nv_debug(pfb, "parts 0x%08x mask 0x%08x\n", parts, pmask);
-
-        pfb->ram.type = nouveau_fb_bios_memtype(bios);
-        pfb->ram.ranks = (nv_rd32(pfb, 0x10f200) & 0x00000004) ? 2 : 1;
-
-        /* read amount of vram attached to each memory controller */
-        for (part = 0; part < parts; part++) {
-                if (!(pmask & (1 << part))) {
-                        u32 psize = nv_rd32(pfb, 0x11020c + (part * 0x1000));
-                        if (psize != bsize) {
-                                if (psize < bsize)
-                                        bsize = psize;
-                                uniform = false;
-                        }
-
-                        nv_debug(pfb, "%d: mem_amount 0x%08x\n", part, psize);
-                        pfb->ram.size += (u64)psize << 20;
-                }
-        }
-
-        /* if all controllers have the same amount attached, there's no holes */
-        if (uniform) {
-                offset = rsvd_head;
-                length = (pfb->ram.size >> 12) - rsvd_head - rsvd_tail;
-                return nouveau_mm_init(&pfb->vram, offset, length, 1);
-        }
-
-        /* otherwise, address lowest common amount from 0GiB */
-        ret = nouveau_mm_init(&pfb->vram, rsvd_head, (bsize << 8) * parts, 1);
-        if (ret)
-                return ret;
-
-        /* and the rest starting from (8GiB + common_size) */
-        offset = (0x0200000000ULL >> 12) + (bsize << 8);
-        length = (pfb->ram.size >> 12) - (bsize << 8) - rsvd_tail;
-
-        ret = nouveau_mm_init(&pfb->vram, offset, length, 0);
-        if (ret) {
-                nouveau_mm_fini(&pfb->vram);
-                return ret;
-        }
-
-        return 0;
-}
-
-static int
-nvc0_fb_vram_new(struct nouveau_fb *pfb, u64 size, u32 align, u32 ncmin,
-                 u32 memtype, struct nouveau_mem **pmem)
-{
-        struct nouveau_mm *mm = &pfb->vram;
-        struct nouveau_mm_node *r;
-        struct nouveau_mem *mem;
-        int type = (memtype & 0x0ff);
-        int back = (memtype & 0x800);
-        int ret;
-        const bool comp = nvc0_pte_storage_type_map[type] != type;
-
-        size  >>= 12;
-        align >>= 12;
-        ncmin >>= 12;
-        if (!ncmin)
-                ncmin = size;
-
-        mem = kzalloc(sizeof(*mem), GFP_KERNEL);
-        if (!mem)
-                return -ENOMEM;
-
-        INIT_LIST_HEAD(&mem->regions);
-        mem->size = size;
-
-        mutex_lock(&pfb->base.mutex);
-        if (comp) {
-                struct nouveau_ltcg *ltcg = nouveau_ltcg(pfb->base.base.parent);
-
-                /* compression only works with lpages */
-                if (align == (1 << (17 - 12))) {
-                        int n = size >> 5;
-                        ltcg->tags_alloc(ltcg, n, &mem->tag);
-                }
-                if (unlikely(!mem->tag))
-                        type = nvc0_pte_storage_type_map[type];
-        }
-        mem->memtype = type;
-
-        do {
-                if (back)
-                        ret = nouveau_mm_tail(mm, 1, size, ncmin, align, &r);
-                else
-                        ret = nouveau_mm_head(mm, 1, size, ncmin, align, &r);
-                if (ret) {
-                        mutex_unlock(&pfb->base.mutex);
-                        pfb->ram.put(pfb, &mem);
-                        return ret;
-                }
-
-                list_add_tail(&r->rl_entry, &mem->regions);
-                size -= r->length;
-        } while (size);
-        mutex_unlock(&pfb->base.mutex);
-
-        r = list_first_entry(&mem->regions, struct nouveau_mm_node, rl_entry);
-        mem->offset = (u64)r->offset << 12;
-        *pmem = mem;
-        return 0;
-}
-
-static void
-nvc0_fb_vram_del(struct nouveau_fb *pfb, struct nouveau_mem **pmem)
-{
-        struct nouveau_ltcg *ltcg = nouveau_ltcg(pfb->base.base.parent);
-
-        if ((*pmem)->tag)
-                ltcg->tags_free(ltcg, &(*pmem)->tag);
-
-        nv50_fb_vram_del(pfb, pmem);
-}
-
-static int
 nvc0_fb_init(struct nouveau_object *object)
 {
         struct nvc0_fb_priv *priv = (void *)object;
@@ -212,15 +78,12 @@ nvc0_fb_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
         struct nvc0_fb_priv *priv;
         int ret;
 
-        ret = nouveau_fb_create(parent, engine, oclass, &priv);
+        ret = nouveau_fb_create(parent, engine, oclass, &nvc0_ram_oclass, &priv);
         *pobject = nv_object(priv);
         if (ret)
                 return ret;
 
         priv->base.memtype_valid = nvc0_fb_memtype_valid;
-        priv->base.ram.init = nvc0_fb_vram_init;
-        priv->base.ram.get = nvc0_fb_vram_new;
-        priv->base.ram.put = nvc0_fb_vram_del;
 
         priv->r100c10_page = alloc_page(GFP_KERNEL | __GFP_ZERO);
         if (priv->r100c10_page) {
@@ -231,7 +94,7 @@ nvc0_fb_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
                         return -EFAULT;
         }
 
-        return nouveau_fb_preinit(&priv->base);
+        return 0;
 }
 
 
diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/priv.h b/drivers/gpu/drm/nouveau/core/subdev/fb/priv.h
new file mode 100644
index 000000000000..6c974dd83e8b
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/core/subdev/fb/priv.h
@@ -0,0 +1,87 @@
+#ifndef __NVKM_FB_PRIV_H__
+#define __NVKM_FB_PRIV_H__
+
+#include <subdev/fb.h>
+
+#define nouveau_ram_create(p,e,o,d)                                            \
+        nouveau_object_create_((p), (e), (o), 0, sizeof(**d), (void **)d)
+#define nouveau_ram_destroy(p)                                                 \
+        nouveau_object_destroy(&(p)->base)
+#define nouveau_ram_init(p)                                                    \
+        nouveau_object_init(&(p)->base)
+#define nouveau_ram_fini(p,s)                                                  \
+        nouveau_object_fini(&(p)->base, (s))
+
+#define _nouveau_ram_dtor nouveau_object_destroy
+#define _nouveau_ram_init nouveau_object_init
+#define _nouveau_ram_fini nouveau_object_fini
+
+extern struct nouveau_oclass nv04_ram_oclass;
+extern struct nouveau_oclass nv10_ram_oclass;
+extern struct nouveau_oclass nv1a_ram_oclass;
+extern struct nouveau_oclass nv20_ram_oclass;
+extern struct nouveau_oclass nv40_ram_oclass;
+extern struct nouveau_oclass nv41_ram_oclass;
+extern struct nouveau_oclass nv44_ram_oclass;
+extern struct nouveau_oclass nv49_ram_oclass;
+extern struct nouveau_oclass nv4e_ram_oclass;
+extern struct nouveau_oclass nv50_ram_oclass;
+extern struct nouveau_oclass nvc0_ram_oclass;
+
+#define nouveau_fb_create(p,e,c,r,d)                                           \
+        nouveau_fb_create_((p), (e), (c), (r), sizeof(**d), (void **)d)
+#define nouveau_fb_destroy(p) ({                                               \
+        struct nouveau_fb *pfb = (p);                                          \
+        _nouveau_fb_dtor(nv_object(pfb));                                      \
+})
+#define nouveau_fb_init(p) ({                                                  \
+        struct nouveau_fb *pfb = (p);                                          \
+        _nouveau_fb_init(nv_object(pfb));                                      \
+})
+#define nouveau_fb_fini(p,s) ({                                                \
+        struct nouveau_fb *pfb = (p);                                          \
+        _nouveau_fb_fini(nv_object(pfb), (s));                                 \
+})
+
+int nouveau_fb_create_(struct nouveau_object *, struct nouveau_object *,
+                       struct nouveau_oclass *, struct nouveau_oclass *,
+                       int length, void **pobject);
+void _nouveau_fb_dtor(struct nouveau_object *);
+int  _nouveau_fb_init(struct nouveau_object *);
+int  _nouveau_fb_fini(struct nouveau_object *, bool);
+
+struct nouveau_bios;
+int  nouveau_fb_bios_memtype(struct nouveau_bios *);
+
+bool nv04_fb_memtype_valid(struct nouveau_fb *, u32 memtype);
+
+void nv10_fb_tile_init(struct nouveau_fb *, int i, u32 addr, u32 size,
+                       u32 pitch, u32 flags, struct nouveau_fb_tile *);
+void nv10_fb_tile_fini(struct nouveau_fb *, int i, struct nouveau_fb_tile *);
+void nv10_fb_tile_prog(struct nouveau_fb *, int, struct nouveau_fb_tile *);
+
+void nv20_fb_tile_init(struct nouveau_fb *, int i, u32 addr, u32 size,
+                       u32 pitch, u32 flags, struct nouveau_fb_tile *);
+void nv20_fb_tile_fini(struct nouveau_fb *, int i, struct nouveau_fb_tile *);
+void nv20_fb_tile_prog(struct nouveau_fb *, int, struct nouveau_fb_tile *);
+
+int  nv30_fb_init(struct nouveau_object *);
+void nv30_fb_tile_init(struct nouveau_fb *, int i, u32 addr, u32 size,
+                       u32 pitch, u32 flags, struct nouveau_fb_tile *);
+
+void nv40_fb_tile_comp(struct nouveau_fb *, int i, u32 size, u32 flags,
+                       struct nouveau_fb_tile *);
+
+int  nv41_fb_init(struct nouveau_object *);
+void nv41_fb_tile_prog(struct nouveau_fb *, int, struct nouveau_fb_tile *);
+
+int  nv44_fb_init(struct nouveau_object *);
+void nv44_fb_tile_prog(struct nouveau_fb *, int, struct nouveau_fb_tile *);
+
+void nv46_fb_tile_init(struct nouveau_fb *, int i, u32 addr, u32 size,
+                       u32 pitch, u32 flags, struct nouveau_fb_tile *);
+
+void nv50_ram_put(struct nouveau_fb *, struct nouveau_mem **);
+extern int nv50_fb_memtype[0x80];
+
+#endif
diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/ramnv04.c b/drivers/gpu/drm/nouveau/core/subdev/fb/ramnv04.c
new file mode 100644
index 000000000000..e781080d3327
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/core/subdev/fb/ramnv04.c
@@ -0,0 +1,95 @@
+/*
+ * Copyright 2013 Red Hat Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Ben Skeggs
+ */
+
+#define NV04_PFB_BOOT_0                                         0x00100000
+#       define NV04_PFB_BOOT_0_RAM_AMOUNT                       0x00000003
+#       define NV04_PFB_BOOT_0_RAM_AMOUNT_32MB                  0x00000000
+#       define NV04_PFB_BOOT_0_RAM_AMOUNT_4MB                   0x00000001
+#       define NV04_PFB_BOOT_0_RAM_AMOUNT_8MB                   0x00000002
+#       define NV04_PFB_BOOT_0_RAM_AMOUNT_16MB                  0x00000003
+#       define NV04_PFB_BOOT_0_RAM_WIDTH_128                    0x00000004
+#       define NV04_PFB_BOOT_0_RAM_TYPE                         0x00000028
+#       define NV04_PFB_BOOT_0_RAM_TYPE_SGRAM_8MBIT             0x00000000
+#       define NV04_PFB_BOOT_0_RAM_TYPE_SGRAM_16MBIT            0x00000008
+#       define NV04_PFB_BOOT_0_RAM_TYPE_SGRAM_16MBIT_4BANK      0x00000010
+#       define NV04_PFB_BOOT_0_RAM_TYPE_SDRAM_16MBIT            0x00000018
+#       define NV04_PFB_BOOT_0_RAM_TYPE_SDRAM_64MBIT            0x00000020
+#       define NV04_PFB_BOOT_0_RAM_TYPE_SDRAM_64MBITX16         0x00000028
+#       define NV04_PFB_BOOT_0_UMA_ENABLE                       0x00000100
+#       define NV04_PFB_BOOT_0_UMA_SIZE                         0x0000f000
+
+#include "priv.h"
+
+static int
+nv04_ram_create(struct nouveau_object *parent, struct nouveau_object *engine,
+                struct nouveau_oclass *oclass, void *data, u32 size,
+                struct nouveau_object **pobject)
+{
+        struct nouveau_fb *pfb = nouveau_fb(parent);
+        struct nouveau_ram *ram;
+        u32 boot0 = nv_rd32(pfb, NV04_PFB_BOOT_0);
+        int ret;
+
+        ret = nouveau_ram_create(parent, engine, oclass, &ram);
+        *pobject = nv_object(ram);
+        if (ret)
+                return ret;
+
+        if (boot0 & 0x00000100) {
+                ram->size  = ((boot0 >> 12) & 0xf) * 2 + 2;
+                ram->size *= 1024 * 1024;
+        } else {
+                switch (boot0 & NV04_PFB_BOOT_0_RAM_AMOUNT) {
+                case NV04_PFB_BOOT_0_RAM_AMOUNT_32MB:
+                        ram->size = 32 * 1024 * 1024;
+                        break;
+                case NV04_PFB_BOOT_0_RAM_AMOUNT_16MB:
+                        ram->size = 16 * 1024 * 1024;
+                        break;
+                case NV04_PFB_BOOT_0_RAM_AMOUNT_8MB:
+                        ram->size = 8 * 1024 * 1024;
+                        break;
+                case NV04_PFB_BOOT_0_RAM_AMOUNT_4MB:
+                        ram->size = 4 * 1024 * 1024;
+                        break;
+                }
+        }
+
+        if ((boot0 & 0x00000038) <= 0x10)
+                ram->type = NV_MEM_TYPE_SGRAM;
+        else
+                ram->type = NV_MEM_TYPE_SDRAM;
+        return 0;
+}
+
+struct nouveau_oclass
+nv04_ram_oclass = {
+        .handle = 0,
+        .ofuncs = &(struct nouveau_ofuncs) {
+                .ctor = nv04_ram_create,
+                .dtor = _nouveau_ram_dtor,
+                .init = _nouveau_ram_init,
+                .fini = _nouveau_ram_fini,
+        }
+};
diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/ramnv10.c b/drivers/gpu/drm/nouveau/core/subdev/fb/ramnv10.c
new file mode 100644
index 000000000000..8311f3774edf
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/core/subdev/fb/ramnv10.c
@@ -0,0 +1,61 @@
+/*
+ * Copyright 2013 Red Hat Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Ben Skeggs
+ */
+
+#include "priv.h"
+
+static int
+nv10_ram_create(struct nouveau_object *parent, struct nouveau_object *engine,
+                struct nouveau_oclass *oclass, void *data, u32 size,
+                struct nouveau_object **pobject)
+{
+        struct nouveau_fb *pfb = nouveau_fb(parent);
+        struct nouveau_ram *ram;
+        u32 cfg0 = nv_rd32(pfb, 0x100200);
+        int ret;
+
+        ret = nouveau_ram_create(parent, engine, oclass, &ram);
+        *pobject = nv_object(ram);
+        if (ret)
+                return ret;
+
+        if (cfg0 & 0x00000001)
+                ram->type = NV_MEM_TYPE_DDR1;
+        else
+                ram->type = NV_MEM_TYPE_SDRAM;
+
+        ram->size = nv_rd32(pfb, 0x10020c) & 0xff000000;
+        return 0;
+}
+
+
+struct nouveau_oclass
+nv10_ram_oclass = {
+        .handle = 0,
+        .ofuncs = &(struct nouveau_ofuncs) {
+                .ctor = nv10_ram_create,
+                .dtor = _nouveau_ram_dtor,
+                .init = _nouveau_ram_init,
+                .fini = _nouveau_ram_fini,
+        }
+};
diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/ramnv1a.c b/drivers/gpu/drm/nouveau/core/subdev/fb/ramnv1a.c
new file mode 100644
index 000000000000..d0caddfb9db0
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/core/subdev/fb/ramnv1a.c
@@ -0,0 +1,71 @@
+/*
+ * Copyright 2013 Red Hat Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Ben Skeggs
+ */
+
+#include "priv.h"
+
+static int
+nv1a_ram_create(struct nouveau_object *parent, struct nouveau_object *engine,
+                struct nouveau_oclass *oclass, void *data, u32 size,
+                struct nouveau_object **pobject)
+{
+        struct nouveau_fb *pfb = nouveau_fb(parent);
+        struct nouveau_ram *ram;
+        struct pci_dev *bridge;
+        u32 mem, mib;
+        int ret;
+
+        bridge = pci_get_bus_and_slot(0, PCI_DEVFN(0, 1));
+        if (!bridge) {
+                nv_fatal(pfb, "no bridge device\n");
+                return -ENODEV;
+        }
+
+        ret = nouveau_ram_create(parent, engine, oclass, &ram);
+        *pobject = nv_object(ram);
+        if (ret)
+                return ret;
+
+        if (nv_device(pfb)->chipset == 0x1a) {
+                pci_read_config_dword(bridge, 0x7c, &mem);
+                mib = ((mem >> 6) & 31) + 1;
+        } else {
+                pci_read_config_dword(bridge, 0x84, &mem);
+                mib = ((mem >> 4) & 127) + 1;
+        }
+
+        ram->type = NV_MEM_TYPE_STOLEN;
+        ram->size = mib * 1024 * 1024;
+        return 0;
+}
+
+struct nouveau_oclass
+nv1a_ram_oclass = {
+        .handle = 0,
+        .ofuncs = &(struct nouveau_ofuncs) {
+                .ctor = nv1a_ram_create,
+                .dtor = _nouveau_ram_dtor,
+                .init = _nouveau_ram_init,
+                .fini = _nouveau_ram_fini,
+        }
+};
diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/ramnv20.c b/drivers/gpu/drm/nouveau/core/subdev/fb/ramnv20.c
new file mode 100644
index 000000000000..fdc11bba226d
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/core/subdev/fb/ramnv20.c
@@ -0,0 +1,63 @@
+/*
+ * Copyright 2013 Red Hat Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Ben Skeggs
+ */
+
+#include "priv.h"
+
+static int
+nv20_ram_create(struct nouveau_object *parent, struct nouveau_object *engine,
+                struct nouveau_oclass *oclass, void *data, u32 size,
+                struct nouveau_object **pobject)
+{
+        struct nouveau_fb *pfb = nouveau_fb(parent);
+        struct nouveau_ram *ram;
+        u32 pbus1218 = nv_rd32(pfb, 0x001218);
+        int ret;
+
+        ret = nouveau_ram_create(parent, engine, oclass, &ram);
+        *pobject = nv_object(ram);
+        if (ret)
+                return ret;
+
+        switch (pbus1218 & 0x00000300) {
+        case 0x00000000: ram->type = NV_MEM_TYPE_SDRAM; break;
+        case 0x00000100: ram->type = NV_MEM_TYPE_DDR1; break;
+        case 0x00000200: ram->type = NV_MEM_TYPE_GDDR3; break;
+        case 0x00000300: ram->type = NV_MEM_TYPE_GDDR2; break;
+        }
+        ram->size  = (nv_rd32(pfb, 0x10020c) & 0xff000000);
+        ram->parts = (nv_rd32(pfb, 0x100200) & 0x00000003) + 1;
+        ram->tags  = nv_rd32(pfb, 0x100320);
+        return 0;
+}
+
+struct nouveau_oclass
+nv20_ram_oclass = {
+        .handle = 0,
+        .ofuncs = &(struct nouveau_ofuncs) {
+                .ctor = nv20_ram_create,
+                .dtor = _nouveau_ram_dtor,
+                .init = _nouveau_ram_init,
+                .fini = _nouveau_ram_fini,
+        }
+};
diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/ramnv40.c b/drivers/gpu/drm/nouveau/core/subdev/fb/ramnv40.c
new file mode 100644
index 000000000000..ee49ac4dbdb6
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/core/subdev/fb/ramnv40.c
@@ -0,0 +1,65 @@
+/*
+ * Copyright 2013 Red Hat Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Ben Skeggs
+ */
+
+#include "priv.h"
+
+static int
+nv40_ram_create(struct nouveau_object *parent, struct nouveau_object *engine,
+                struct nouveau_oclass *oclass, void *data, u32 size,
+                struct nouveau_object **pobject)
+{
+        struct nouveau_fb *pfb = nouveau_fb(parent);
+        struct nouveau_ram *ram;
+        u32 pbus1218 = nv_rd32(pfb, 0x001218);
+        int ret;
+
+        ret = nouveau_ram_create(parent, engine, oclass, &ram);
+        *pobject = nv_object(ram);
+        if (ret)
+                return ret;
+
+        switch (pbus1218 & 0x00000300) {
+        case 0x00000000: ram->type = NV_MEM_TYPE_SDRAM; break;
+        case 0x00000100: ram->type = NV_MEM_TYPE_DDR1; break;
+        case 0x00000200: ram->type = NV_MEM_TYPE_GDDR3; break;
+        case 0x00000300: ram->type = NV_MEM_TYPE_DDR2; break;
+        }
+
+        ram->size  =  nv_rd32(pfb, 0x10020c) & 0xff000000;
+        ram->parts = (nv_rd32(pfb, 0x100200) & 0x00000003) + 1;
+        ram->tags  =  nv_rd32(pfb, 0x100320);
+        return 0;
+}
+
+
+struct nouveau_oclass
+nv40_ram_oclass = {
+        .handle = 0,
+        .ofuncs = &(struct nouveau_ofuncs) {
+                .ctor = nv40_ram_create,
+                .dtor = _nouveau_ram_dtor,
+                .init = _nouveau_ram_init,
+                .fini = _nouveau_ram_fini,
+        }
+};
diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/ramnv41.c b/drivers/gpu/drm/nouveau/core/subdev/fb/ramnv41.c
new file mode 100644
index 000000000000..1dab7e12abab
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/core/subdev/fb/ramnv41.c
@@ -0,0 +1,64 @@
+/*
+ * Copyright 2013 Red Hat Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Ben Skeggs
+ */
+
+#include "priv.h"
+
+static int
+nv41_ram_create(struct nouveau_object *parent, struct nouveau_object *engine,
+                struct nouveau_oclass *oclass, void *data, u32 size,
+                struct nouveau_object **pobject)
+{
+        struct nouveau_fb *pfb = nouveau_fb(parent);
+        struct nouveau_ram *ram;
+        u32 pfb474 = nv_rd32(pfb, 0x100474);
+        int ret;
+
+        ret = nouveau_ram_create(parent, engine, oclass, &ram);
+        *pobject = nv_object(ram);
+        if (ret)
+                return ret;
+
+        if (pfb474 & 0x00000004)
+                ram->type = NV_MEM_TYPE_GDDR3;
+        if (pfb474 & 0x00000002)
+                ram->type = NV_MEM_TYPE_DDR2;
+        if (pfb474 & 0x00000001)
+                ram->type = NV_MEM_TYPE_DDR1;
+
+        ram->size  =  nv_rd32(pfb, 0x10020c) & 0xff000000;
+        ram->parts = (nv_rd32(pfb, 0x100200) & 0x00000003) + 1;
+        ram->tags  =  nv_rd32(pfb, 0x100320);
+        return 0;
+}
+
+struct nouveau_oclass
+nv41_ram_oclass = {
+        .handle = 0,
+        .ofuncs = &(struct nouveau_ofuncs) {
+                .ctor = nv41_ram_create,
+                .dtor = _nouveau_ram_dtor,
+                .init = _nouveau_ram_init,
+                .fini = _nouveau_ram_fini,
+        }
+};
diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/ramnv44.c b/drivers/gpu/drm/nouveau/core/subdev/fb/ramnv44.c
new file mode 100644
index 000000000000..25fff842e5c1
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/core/subdev/fb/ramnv44.c
@@ -0,0 +1,62 @@
+/*
+ * Copyright 2013 Red Hat Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Ben Skeggs
+ */
+
+#include "priv.h"
+
+static int
+nv44_ram_create(struct nouveau_object *parent, struct nouveau_object *engine,
+                struct nouveau_oclass *oclass, void *data, u32 size,
+                struct nouveau_object **pobject)
+{
+        struct nouveau_fb *pfb = nouveau_fb(parent);
+        struct nouveau_ram *ram;
+        u32 pfb474 = nv_rd32(pfb, 0x100474);
+        int ret;
+
+        ret = nouveau_ram_create(parent, engine, oclass, &ram);
+        *pobject = nv_object(ram);
+        if (ret)
+                return ret;
+
+        if (pfb474 & 0x00000004)
+                ram->type = NV_MEM_TYPE_GDDR3;
+        if (pfb474 & 0x00000002)
+                ram->type = NV_MEM_TYPE_DDR2;
+        if (pfb474 & 0x00000001)
+                ram->type = NV_MEM_TYPE_DDR1;
+
+        ram->size = nv_rd32(pfb, 0x10020c) & 0xff000000;
+        return 0;
+}
+
+struct nouveau_oclass
+nv44_ram_oclass = {
+        .handle = 0,
+        .ofuncs = &(struct nouveau_ofuncs) {
+                .ctor = nv44_ram_create,
+                .dtor = _nouveau_ram_dtor,
+                .init = _nouveau_ram_init,
+                .fini = _nouveau_ram_fini,
+        }
+};
diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/ramnv49.c b/drivers/gpu/drm/nouveau/core/subdev/fb/ramnv49.c
new file mode 100644
index 000000000000..19e3a9a63a02
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/core/subdev/fb/ramnv49.c
@@ -0,0 +1,64 @@
+/*
+ * Copyright 2013 Red Hat Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Ben Skeggs
+ */
+
+#include "priv.h"
+
+static int
+nv49_ram_create(struct nouveau_object *parent, struct nouveau_object *engine,
+                struct nouveau_oclass *oclass, void *data, u32 size,
+                struct nouveau_object **pobject)
+{
+        struct nouveau_fb *pfb = nouveau_fb(parent);
+        struct nouveau_ram *ram;
+        u32 pfb914 = nv_rd32(pfb, 0x100914);
+        int ret;
+
+        ret = nouveau_ram_create(parent, engine, oclass, &ram);
+        *pobject = nv_object(ram);
+        if (ret)
+                return ret;
+
+        switch (pfb914 & 0x00000003) {
+        case 0x00000000: pfb->ram->type = NV_MEM_TYPE_DDR1; break;
+        case 0x00000001: pfb->ram->type = NV_MEM_TYPE_DDR2; break;
+        case 0x00000002: pfb->ram->type = NV_MEM_TYPE_GDDR3; break;
+        case 0x00000003: break;
+        }
+
+        pfb->ram->size  =  nv_rd32(pfb, 0x10020c) & 0xff000000;
+        pfb->ram->parts = (nv_rd32(pfb, 0x100200) & 0x00000003) + 1;
+        pfb->ram->tags  =  nv_rd32(pfb, 0x100320);
+        return 0;
+}
+
+struct nouveau_oclass
+nv49_ram_oclass = {
+        .handle = 0,
+        .ofuncs = &(struct nouveau_ofuncs) {
+                .ctor = nv49_ram_create,
+                .dtor = _nouveau_ram_dtor,
+                .init = _nouveau_ram_init,
+                .fini = _nouveau_ram_fini,
+        }
+};
diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/ramnv4e.c b/drivers/gpu/drm/nouveau/core/subdev/fb/ramnv4e.c
new file mode 100644
index 000000000000..7192aa6e5577
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/core/subdev/fb/ramnv4e.c
@@ -0,0 +1,55 @@
+/*
+ * Copyright 2013 Red Hat Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Ben Skeggs
+ */
+
+#include "priv.h"
+
+static int
+nv4e_ram_create(struct nouveau_object *parent, struct nouveau_object *engine,
+                struct nouveau_oclass *oclass, void *data, u32 size,
+                struct nouveau_object **pobject)
+{
+        struct nouveau_fb *pfb = nouveau_fb(parent);
+        struct nouveau_ram *ram;
+        int ret;
+
+        ret = nouveau_ram_create(parent, engine, oclass, &ram);
+        *pobject = nv_object(ram);
+        if (ret)
+                return ret;
+
+        pfb->ram->size = nv_rd32(pfb, 0x10020c) & 0xff000000;
+        pfb->ram->type = NV_MEM_TYPE_STOLEN;
+        return 0;
+}
+
+struct nouveau_oclass
+nv4e_ram_oclass = {
+        .handle = 0,
+        .ofuncs = &(struct nouveau_ofuncs) {
+                .ctor = nv4e_ram_create,
+                .dtor = _nouveau_ram_dtor,
+                .init = _nouveau_ram_init,
+                .fini = _nouveau_ram_fini,
+        }
+};
diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/ramnv50.c b/drivers/gpu/drm/nouveau/core/subdev/fb/ramnv50.c
new file mode 100644
index 000000000000..af5aa7ee8ad9
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/core/subdev/fb/ramnv50.c
@@ -0,0 +1,232 @@
+/*
+ * Copyright 2013 Red Hat Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Ben Skeggs
+ */
+
+#include <subdev/bios.h>
+#include <core/mm.h>
+#include "priv.h"
+
+void
+nv50_ram_put(struct nouveau_fb *pfb, struct nouveau_mem **pmem)
+{
+        struct nouveau_mm_node *this;
+        struct nouveau_mem *mem;
+
+        mem = *pmem;
+        *pmem = NULL;
+        if (unlikely(mem == NULL))
+                return;
+
+        mutex_lock(&pfb->base.mutex);
+        while (!list_empty(&mem->regions)) {
+                this = list_first_entry(&mem->regions, typeof(*this), rl_entry);
+
+                list_del(&this->rl_entry);
+                nouveau_mm_free(&pfb->vram, &this);
+        }
+
+        nouveau_mm_free(&pfb->tags, &mem->tag);
+        mutex_unlock(&pfb->base.mutex);
+
+        kfree(mem);
+}
+
+static int
+nv50_ram_get(struct nouveau_fb *pfb, u64 size, u32 align, u32 ncmin,
+             u32 memtype, struct nouveau_mem **pmem)
+{
+        struct nouveau_mm *heap = &pfb->vram;
+        struct nouveau_mm *tags = &pfb->tags;
+        struct nouveau_mm_node *r;
+        struct nouveau_mem *mem;
+        int comp = (memtype & 0x300) >> 8;
+        int type = (memtype & 0x07f);
+        int back = (memtype & 0x800);
+        int min, max, ret;
+
+        max = (size >> 12);
+        min = ncmin ? (ncmin >> 12) : max;
+        align >>= 12;
+
+        mem = kzalloc(sizeof(*mem), GFP_KERNEL);
+        if (!mem)
+                return -ENOMEM;
+
+        mutex_lock(&pfb->base.mutex);
+        if (comp) {
+                if (align == 16) {
+                        int n = (max >> 4) * comp;
+
+                        ret = nouveau_mm_head(tags, 1, n, n, 1, &mem->tag);
+                        if (ret)
+                                mem->tag = NULL;
+                }
+
+                if (unlikely(!mem->tag))
+                        comp = 0;
+        }
+
+        INIT_LIST_HEAD(&mem->regions);
+        mem->memtype = (comp << 7) | type;
+        mem->size = max;
+
+        type = nv50_fb_memtype[type];
+        do {
+                if (back)
+                        ret = nouveau_mm_tail(heap, type, max, min, align, &r);
+                else
+                        ret = nouveau_mm_head(heap, type, max, min, align, &r);
+                if (ret) {
+                        mutex_unlock(&pfb->base.mutex);
+                        pfb->ram->put(pfb, &mem);
+                        return ret;
+                }
+
+                list_add_tail(&r->rl_entry, &mem->regions);
+                max -= r->length;
+        } while (max);
+        mutex_unlock(&pfb->base.mutex);
+
+        r = list_first_entry(&mem->regions, struct nouveau_mm_node, rl_entry);
+        mem->offset = (u64)r->offset << 12;
+        *pmem = mem;
+        return 0;
+}
+
+static u32
+nv50_fb_vram_rblock(struct nouveau_fb *pfb, struct nouveau_ram *ram)
+{
+        int i, parts, colbits, rowbitsa, rowbitsb, banks;
+        u64 rowsize, predicted;
+        u32 r0, r4, rt, ru, rblock_size;
+
+        r0 = nv_rd32(pfb, 0x100200);
+        r4 = nv_rd32(pfb, 0x100204);
+        rt = nv_rd32(pfb, 0x100250);
+        ru = nv_rd32(pfb, 0x001540);
+        nv_debug(pfb, "memcfg 0x%08x 0x%08x 0x%08x 0x%08x\n", r0, r4, rt, ru);
+
+        for (i = 0, parts = 0; i < 8; i++) {
+                if (ru & (0x00010000 << i))
+                        parts++;
+        }
+
+        colbits  =  (r4 & 0x0000f000) >> 12;
+        rowbitsa = ((r4 & 0x000f0000) >> 16) + 8;
+        rowbitsb = ((r4 & 0x00f00000) >> 20) + 8;
+        banks    = 1 << (((r4 & 0x03000000) >> 24) + 2);
+
+        rowsize = parts * banks * (1 << colbits) * 8;
+        predicted = rowsize << rowbitsa;
+        if (r0 & 0x00000004)
+                predicted += rowsize << rowbitsb;
+
+        if (predicted != ram->size) {
+                nv_warn(pfb, "memory controller reports %d MiB VRAM\n",
+                        (u32)(ram->size >> 20));
+        }
+
+        rblock_size = rowsize;
+        if (rt & 1)
+                rblock_size *= 3;
+
+        nv_debug(pfb, "rblock %d bytes\n", rblock_size);
+        return rblock_size;
+}
+
+static int
+nv50_ram_create(struct nouveau_object *parent, struct nouveau_object *engine,
+                struct nouveau_oclass *oclass, void *data, u32 datasize,
+                struct nouveau_object **pobject)
+{
+        struct nouveau_fb *pfb = nouveau_fb(parent);
+        struct nouveau_device *device = nv_device(pfb);
+        struct nouveau_bios *bios = nouveau_bios(device);
+        struct nouveau_ram *ram;
+        const u32 rsvd_head = ( 256 * 1024) >> 12; /* vga memory */
+        const u32 rsvd_tail = (1024 * 1024) >> 12; /* vbios etc */
+        u32 size;
+        int ret;
+
+        ret = nouveau_ram_create(parent, engine, oclass, &ram);
+        *pobject = nv_object(ram);
+        if (ret)
+                return ret;
+
+        ram->size = nv_rd32(pfb, 0x10020c);
+        ram->size = (ram->size & 0xffffff00) |
+                       ((ram->size & 0x000000ff) << 32);
+
+        size = (ram->size >> 12) - rsvd_head - rsvd_tail;
+        switch (device->chipset) {
+        case 0xaa:
+        case 0xac:
+        case 0xaf: /* IGPs, no reordering, no real VRAM */
+                ret = nouveau_mm_init(&pfb->vram, rsvd_head, size, 1);
+                if (ret)
+                        return ret;
+
+                ram->type   = NV_MEM_TYPE_STOLEN;
+                ram->stolen = (u64)nv_rd32(pfb, 0x100e10) << 12;
+                break;
+        default:
+                switch (nv_rd32(pfb, 0x100714) & 0x00000007) {
+                case 0: ram->type = NV_MEM_TYPE_DDR1; break;
+                case 1:
+                        if (nouveau_fb_bios_memtype(bios) == NV_MEM_TYPE_DDR3)
+                                ram->type = NV_MEM_TYPE_DDR3;
+                        else
+                                ram->type = NV_MEM_TYPE_DDR2;
+                        break;
+                case 2: ram->type = NV_MEM_TYPE_GDDR3; break;
+                case 3: ram->type = NV_MEM_TYPE_GDDR4; break;
+                case 4: ram->type = NV_MEM_TYPE_GDDR5; break;
+                default:
+                        break;
+                }
+
+                ret = nouveau_mm_init(&pfb->vram, rsvd_head, size,
+                                      nv50_fb_vram_rblock(pfb, ram) >> 12);
+                if (ret)
+                        return ret;
+
+                ram->ranks = (nv_rd32(pfb, 0x100200) & 0x4) ? 2 : 1;
+                ram->tags  =  nv_rd32(pfb, 0x100320);
+                break;
+        }
+
+        ram->get = nv50_ram_get;
+        ram->put = nv50_ram_put;
+        return 0;
+}
+
+struct nouveau_oclass
+nv50_ram_oclass = {
+        .handle = 0,
+        .ofuncs = &(struct nouveau_ofuncs) {
+                .ctor = nv50_ram_create,
+                .dtor = _nouveau_ram_dtor,
+                .init = _nouveau_ram_init,
+                .fini = _nouveau_ram_fini,
+        }
+};
diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/ramnvc0.c b/drivers/gpu/drm/nouveau/core/subdev/fb/ramnvc0.c
new file mode 100644
index 000000000000..9c3634acbb9d
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/core/subdev/fb/ramnvc0.c
@@ -0,0 +1,186 @@
+/*
+ * Copyright 2013 Red Hat Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Ben Skeggs
+ */
+
+#include <subdev/bios.h>
+#include <subdev/ltcg.h>
+
+#include "priv.h"
+
+extern const u8 nvc0_pte_storage_type_map[256];
+
+void
+nvc0_ram_put(struct nouveau_fb *pfb, struct nouveau_mem **pmem)
+{
+        struct nouveau_ltcg *ltcg = nouveau_ltcg(pfb);
+
+        if ((*pmem)->tag)
+                ltcg->tags_free(ltcg, &(*pmem)->tag);
+
+        nv50_ram_put(pfb, pmem);
+}
+
+int
+nvc0_ram_get(struct nouveau_fb *pfb, u64 size, u32 align, u32 ncmin,
+             u32 memtype, struct nouveau_mem **pmem)
+{
+        struct nouveau_mm *mm = &pfb->vram;
+        struct nouveau_mm_node *r;
+        struct nouveau_mem *mem;
+        int type = (memtype & 0x0ff);
+        int back = (memtype & 0x800);
+        const bool comp = nvc0_pte_storage_type_map[type] != type;
+        int ret;
+
+        size  >>= 12;
+        align >>= 12;
+        ncmin >>= 12;
+        if (!ncmin)
+                ncmin = size;
+
+        mem = kzalloc(sizeof(*mem), GFP_KERNEL);
+        if (!mem)
+                return -ENOMEM;
+
+        INIT_LIST_HEAD(&mem->regions);
+        mem->size = size;
+
+        mutex_lock(&pfb->base.mutex);
+        if (comp) {
+                struct nouveau_ltcg *ltcg = nouveau_ltcg(pfb);
+
+                /* compression only works with lpages */
+                if (align == (1 << (17 - 12))) {
+                        int n = size >> 5;
+                        ltcg->tags_alloc(ltcg, n, &mem->tag);
+                }
+
+                if (unlikely(!mem->tag))
+                        type = nvc0_pte_storage_type_map[type];
+        }
+        mem->memtype = type;
+
+        do {
+                if (back)
+                        ret = nouveau_mm_tail(mm, 1, size, ncmin, align, &r);
+                else
+                        ret = nouveau_mm_head(mm, 1, size, ncmin, align, &r);
+                if (ret) {
+                        mutex_unlock(&pfb->base.mutex);
+                        pfb->ram->put(pfb, &mem);
+                        return ret;
+                }
+
+                list_add_tail(&r->rl_entry, &mem->regions);
+                size -= r->length;
+        } while (size);
+        mutex_unlock(&pfb->base.mutex);
+
+        r = list_first_entry(&mem->regions, struct nouveau_mm_node, rl_entry);
+        mem->offset = (u64)r->offset << 12;
+        *pmem = mem;
+        return 0;
+}
+
+static int
+nvc0_ram_create(struct nouveau_object *parent, struct nouveau_object *engine,
+                struct nouveau_oclass *oclass, void *data, u32 size,
+                struct nouveau_object **pobject)
+{
+        struct nouveau_fb *pfb = nouveau_fb(parent);
+        struct nouveau_bios *bios = nouveau_bios(pfb);
+        struct nouveau_ram *ram;
+        const u32 rsvd_head = ( 256 * 1024) >> 12; /* vga memory */
+        const u32 rsvd_tail = (1024 * 1024) >> 12; /* vbios etc */
+        u32 parts = nv_rd32(pfb, 0x022438);
+        u32 pmask = nv_rd32(pfb, 0x022554);
+        u32 bsize = nv_rd32(pfb, 0x10f20c);
+        u32 offset, length;
+        bool uniform = true;
+        int ret, part;
+
+        ret = nouveau_ram_create(parent, engine, oclass, &ram);
+        *pobject = nv_object(ram);
+        if (ret)
+                return ret;
+
+        nv_debug(pfb, "0x100800: 0x%08x\n", nv_rd32(pfb, 0x100800));
+        nv_debug(pfb, "parts 0x%08x mask 0x%08x\n", parts, pmask);
+
+        ram->type = nouveau_fb_bios_memtype(bios);
+        ram->ranks = (nv_rd32(pfb, 0x10f200) & 0x00000004) ? 2 : 1;
+
+        /* read amount of vram attached to each memory controller */
+        for (part = 0; part < parts; part++) {
+                if (!(pmask & (1 << part))) {
+                        u32 psize = nv_rd32(pfb, 0x11020c + (part * 0x1000));
+                        if (psize != bsize) {
+                                if (psize < bsize)
+                                        bsize = psize;
+                                uniform = false;
+                        }
+
+                        nv_debug(pfb, "%d: mem_amount 0x%08x\n", part, psize);
+                        ram->size += (u64)psize << 20;
+                }
+        }
+
+        /* if all controllers have the same amount attached, there's no holes */
+        if (uniform) {
+                offset = rsvd_head;
+                length = (ram->size >> 12) - rsvd_head - rsvd_tail;
+                ret = nouveau_mm_init(&pfb->vram, offset, length, 1);
+        } else {
+                /* otherwise, address lowest common amount from 0GiB */
+                ret = nouveau_mm_init(&pfb->vram, rsvd_head,
+                                      (bsize << 8) * parts, 1);
+                if (ret)
+                        return ret;
+
+                /* and the rest starting from (8GiB + common_size) */
+                offset = (0x0200000000ULL >> 12) + (bsize << 8);
+                length = (ram->size >> 12) - (bsize << 8) - rsvd_tail;
+
+                ret = nouveau_mm_init(&pfb->vram, offset, length, 0);
+                if (ret)
+                        nouveau_mm_fini(&pfb->vram);
+        }
+
+        if (ret)
+                return ret;
+
+        ram->get = nvc0_ram_get;
+        ram->put = nvc0_ram_put;
+        return 0;
+}
+
+struct nouveau_oclass
+nvc0_ram_oclass = {
+        .handle = 0,
+        .ofuncs = &(struct nouveau_ofuncs) {
+                .ctor = nvc0_ram_create,
+                .dtor = _nouveau_ram_dtor,
+                .init = _nouveau_ram_init,
+                .fini = _nouveau_ram_fini,
+        }
+};
diff --git a/drivers/gpu/drm/nouveau/core/subdev/instmem/nv50.c b/drivers/gpu/drm/nouveau/core/subdev/instmem/nv50.c
index cfc7e31461de..97bc5dff93e7 100644
--- a/drivers/gpu/drm/nouveau/core/subdev/instmem/nv50.c
+++ b/drivers/gpu/drm/nouveau/core/subdev/instmem/nv50.c
@@ -56,7 +56,7 @@ nv50_instobj_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
         if (ret)
                 return ret;
 
-        ret = pfb->ram.get(pfb, size, align, 0, 0x800, &node->mem);
+        ret = pfb->ram->get(pfb, size, align, 0, 0x800, &node->mem);
         if (ret)
                 return ret;
 
@@ -71,7 +71,7 @@ nv50_instobj_dtor(struct nouveau_object *object)
 {
         struct nv50_instobj_priv *node = (void *)object;
         struct nouveau_fb *pfb = nouveau_fb(object);
-        pfb->ram.put(pfb, &node->mem);
+        pfb->ram->put(pfb, &node->mem);
         nouveau_instobj_destroy(&node->base);
 }
 
diff --git a/drivers/gpu/drm/nouveau/core/subdev/ltcg/nvc0.c b/drivers/gpu/drm/nouveau/core/subdev/ltcg/nvc0.c
index fb794e997fbc..bcca883018f4 100644
--- a/drivers/gpu/drm/nouveau/core/subdev/ltcg/nvc0.c
+++ b/drivers/gpu/drm/nouveau/core/subdev/ltcg/nvc0.c
@@ -122,7 +122,7 @@ nvc0_ltcg_init_tag_ram(struct nouveau_fb *pfb, struct nvc0_ltcg_priv *priv)
                 nv_wr32(priv, 0x17e000, priv->part_nr);
 
         /* tags for 1/4 of VRAM should be enough (8192/4 per GiB of VRAM) */
-        priv->num_tags = (pfb->ram.size >> 17) / 4;
+        priv->num_tags = (pfb->ram->size >> 17) / 4;
         if (priv->num_tags > (1 << 17))
                 priv->num_tags = 1 << 17; /* we have 17 bits in PTE */
         priv->num_tags = (priv->num_tags + 63) & ~63; /* round up to 64 */
diff --git a/drivers/gpu/drm/nouveau/core/subdev/mc/nv50.c b/drivers/gpu/drm/nouveau/core/subdev/mc/nv50.c
index d796924f9930..0cb322a5e72c 100644
--- a/drivers/gpu/drm/nouveau/core/subdev/mc/nv50.c
+++ b/drivers/gpu/drm/nouveau/core/subdev/mc/nv50.c
@@ -35,6 +35,7 @@ nv50_mc_intr[] = {
         { 0x00001000, NVDEV_ENGINE_GR },
         { 0x00004000, NVDEV_ENGINE_CRYPT },     /* NV84- */
         { 0x00008000, NVDEV_ENGINE_BSP },       /* NV84- */
+        { 0x00020000, NVDEV_ENGINE_VP },        /* NV84- */
         { 0x00100000, NVDEV_SUBDEV_TIMER },
         { 0x00200000, NVDEV_SUBDEV_GPIO },
         { 0x04000000, NVDEV_ENGINE_DISP },
diff --git a/drivers/gpu/drm/nouveau/core/subdev/mc/nvc0.c b/drivers/gpu/drm/nouveau/core/subdev/mc/nvc0.c
index 737bd4b682e1..c5da3babbc62 100644
--- a/drivers/gpu/drm/nouveau/core/subdev/mc/nvc0.c
+++ b/drivers/gpu/drm/nouveau/core/subdev/mc/nvc0.c
@@ -33,6 +33,7 @@ nvc0_mc_intr[] = {
         { 0x00000001, NVDEV_ENGINE_PPP },
         { 0x00000020, NVDEV_ENGINE_COPY0 },
         { 0x00000040, NVDEV_ENGINE_COPY1 },
+        { 0x00000080, NVDEV_ENGINE_COPY2 },
         { 0x00000100, NVDEV_ENGINE_FIFO },
         { 0x00001000, NVDEV_ENGINE_GR },
         { 0x00008000, NVDEV_ENGINE_BSP },
diff --git a/drivers/gpu/drm/nouveau/core/subdev/vm/base.c b/drivers/gpu/drm/nouveau/core/subdev/vm/base.c
index 77c67fc970e6..67fcb6c852ac 100644
--- a/drivers/gpu/drm/nouveau/core/subdev/vm/base.c
+++ b/drivers/gpu/drm/nouveau/core/subdev/vm/base.c
@@ -236,9 +236,9 @@ nouveau_vm_unmap_pgt(struct nouveau_vm *vm, int big, u32 fpde, u32 lpde)
                         vmm->map_pgt(vpgd->obj, pde, vpgt->obj);
                 }
 
-                mutex_unlock(&vm->mm.mutex);
+                mutex_unlock(&nv_subdev(vmm)->mutex);
                 nouveau_gpuobj_ref(NULL, &pgt);
-                mutex_lock(&vm->mm.mutex);
+                mutex_lock(&nv_subdev(vmm)->mutex);
         }
 }
 
@@ -256,18 +256,18 @@ nouveau_vm_map_pgt(struct nouveau_vm *vm, u32 pde, u32 type)
         pgt_size  = (1 << (vmm->pgt_bits + 12)) >> type;
         pgt_size *= 8;
 
-        mutex_unlock(&vm->mm.mutex);
+        mutex_unlock(&nv_subdev(vmm)->mutex);
         ret = nouveau_gpuobj_new(nv_object(vm->vmm), NULL, pgt_size, 0x1000,
                                  NVOBJ_FLAG_ZERO_ALLOC, &pgt);
-        mutex_lock(&vm->mm.mutex);
+        mutex_lock(&nv_subdev(vmm)->mutex);
         if (unlikely(ret))
                 return ret;
 
         /* someone beat us to filling the PDE while we didn't have the lock */
         if (unlikely(vpgt->refcount[big]++)) {
-                mutex_unlock(&vm->mm.mutex);
+                mutex_unlock(&nv_subdev(vmm)->mutex);
                 nouveau_gpuobj_ref(NULL, &pgt);
-                mutex_lock(&vm->mm.mutex);
+                mutex_lock(&nv_subdev(vmm)->mutex);
                 return 0;
         }
 
@@ -289,11 +289,11 @@ nouveau_vm_get(struct nouveau_vm *vm, u64 size, u32 page_shift,
         u32 fpde, lpde, pde;
         int ret;
 
-        mutex_lock(&vm->mm.mutex);
+        mutex_lock(&nv_subdev(vmm)->mutex);
         ret = nouveau_mm_head(&vm->mm, page_shift, msize, msize, align,
                              &vma->node);
         if (unlikely(ret != 0)) {
-                mutex_unlock(&vm->mm.mutex);
+                mutex_unlock(&nv_subdev(vmm)->mutex);
                 return ret;
         }
 
@@ -314,13 +314,14 @@ nouveau_vm_get(struct nouveau_vm *vm, u64 size, u32 page_shift,
                         if (pde != fpde)
                                 nouveau_vm_unmap_pgt(vm, big, fpde, pde - 1);
                         nouveau_mm_free(&vm->mm, &vma->node);
-                        mutex_unlock(&vm->mm.mutex);
+                        mutex_unlock(&nv_subdev(vmm)->mutex);
                         return ret;
                 }
         }
-        mutex_unlock(&vm->mm.mutex);
+        mutex_unlock(&nv_subdev(vmm)->mutex);
 
-        vma->vm     = vm;
+        vma->vm = NULL;
+        nouveau_vm_ref(vm, &vma->vm, NULL);
         vma->offset = (u64)vma->node->offset << 12;
         vma->access = access;
         return 0;
@@ -338,10 +339,12 @@ nouveau_vm_put(struct nouveau_vma *vma)
         fpde = (vma->node->offset >> vmm->pgt_bits);
         lpde = (vma->node->offset + vma->node->length - 1) >> vmm->pgt_bits;
 
-        mutex_lock(&vm->mm.mutex);
+        mutex_lock(&nv_subdev(vmm)->mutex);
         nouveau_vm_unmap_pgt(vm, vma->node->type != vmm->spg_shift, fpde, lpde);
         nouveau_mm_free(&vm->mm, &vma->node);
-        mutex_unlock(&vm->mm.mutex);
+        mutex_unlock(&nv_subdev(vmm)->mutex);
+
+        nouveau_vm_ref(NULL, &vma->vm, NULL);
 }
 
 int
@@ -362,7 +365,7 @@ nouveau_vm_create(struct nouveau_vmmgr *vmm, u64 offset, u64 length,
         vm->fpde = offset >> (vmm->pgt_bits + 12);
         vm->lpde = (offset + length - 1) >> (vmm->pgt_bits + 12);
 
-        vm->pgt  = kcalloc(vm->lpde - vm->fpde + 1, sizeof(*vm->pgt), GFP_KERNEL);
+        vm->pgt  = vzalloc((vm->lpde - vm->fpde + 1) * sizeof(*vm->pgt));
         if (!vm->pgt) {
                 kfree(vm);
                 return -ENOMEM;
@@ -371,7 +374,7 @@ nouveau_vm_create(struct nouveau_vmmgr *vmm, u64 offset, u64 length,
         ret = nouveau_mm_init(&vm->mm, mm_offset >> 12, mm_length >> 12,
                               block >> 12);
         if (ret) {
-                kfree(vm->pgt);
+                vfree(vm->pgt);
                 kfree(vm);
                 return ret;
         }
@@ -405,24 +408,25 @@ nouveau_vm_link(struct nouveau_vm *vm, struct nouveau_gpuobj *pgd)
 
         nouveau_gpuobj_ref(pgd, &vpgd->obj);
 
-        mutex_lock(&vm->mm.mutex);
+        mutex_lock(&nv_subdev(vmm)->mutex);
         for (i = vm->fpde; i <= vm->lpde; i++)
                 vmm->map_pgt(pgd, i, vm->pgt[i - vm->fpde].obj);
         list_add(&vpgd->head, &vm->pgd_list);
-        mutex_unlock(&vm->mm.mutex);
+        mutex_unlock(&nv_subdev(vmm)->mutex);
         return 0;
 }
 
 static void
 nouveau_vm_unlink(struct nouveau_vm *vm, struct nouveau_gpuobj *mpgd)
 {
+        struct nouveau_vmmgr *vmm = vm->vmm;
         struct nouveau_vm_pgd *vpgd, *tmp;
         struct nouveau_gpuobj *pgd = NULL;
 
         if (!mpgd)
                 return;
 
-        mutex_lock(&vm->mm.mutex);
+        mutex_lock(&nv_subdev(vmm)->mutex);
         list_for_each_entry_safe(vpgd, tmp, &vm->pgd_list, head) {
                 if (vpgd->obj == mpgd) {
                         pgd = vpgd->obj;
@@ -431,7 +435,7 @@ nouveau_vm_unlink(struct nouveau_vm *vm, struct nouveau_gpuobj *mpgd)
                         break;
                 }
         }
-        mutex_unlock(&vm->mm.mutex);
+        mutex_unlock(&nv_subdev(vmm)->mutex);
 
         nouveau_gpuobj_ref(NULL, &pgd);
 }
@@ -446,7 +450,7 @@ nouveau_vm_del(struct nouveau_vm *vm)
         }
 
         nouveau_mm_fini(&vm->mm);
-        kfree(vm->pgt);
+        vfree(vm->pgt);
         kfree(vm);
 }
 
diff --git a/drivers/gpu/drm/nouveau/core/subdev/vm/nv50.c b/drivers/gpu/drm/nouveau/core/subdev/vm/nv50.c
index e067f81c97b3..07dd1fe2d6fb 100644
--- a/drivers/gpu/drm/nouveau/core/subdev/vm/nv50.c
+++ b/drivers/gpu/drm/nouveau/core/subdev/vm/nv50.c
@@ -27,11 +27,11 @@
 
 #include <subdev/timer.h>
 #include <subdev/fb.h>
+#include <subdev/bar.h>
 #include <subdev/vm.h>
 
 struct nv50_vmmgr_priv {
         struct nouveau_vmmgr base;
-        spinlock_t lock;
 };
 
 static void
@@ -86,8 +86,8 @@ nv50_vm_map(struct nouveau_vma *vma, struct nouveau_gpuobj *pgt,
 
         /* IGPs don't have real VRAM, re-target to stolen system memory */
         target = 0;
-        if (nouveau_fb(vma->vm->vmm)->ram.stolen) {
-                phys += nouveau_fb(vma->vm->vmm)->ram.stolen;
+        if (nouveau_fb(vma->vm->vmm)->ram->stolen) {
+                phys += nouveau_fb(vma->vm->vmm)->ram->stolen;
                 target = 3;
         }
 
@@ -151,29 +151,42 @@ nv50_vm_unmap(struct nouveau_gpuobj *pgt, u32 pte, u32 cnt)
 static void
 nv50_vm_flush(struct nouveau_vm *vm)
 {
+        struct nv50_vmmgr_priv *priv = (void *)vm->vmm;
+        struct nouveau_bar *bar = nouveau_bar(priv);
         struct nouveau_engine *engine;
-        int i;
+        int i, vme;
+
+        bar->flush(bar);
 
+        mutex_lock(&nv_subdev(priv)->mutex);
         for (i = 0; i < NVDEV_SUBDEV_NR; i++) {
-                if (atomic_read(&vm->engref[i])) {
-                        engine = nouveau_engine(vm->vmm, i);
-                        if (engine && engine->tlb_flush)
-                                engine->tlb_flush(engine);
+                if (!atomic_read(&vm->engref[i]))
+                        continue;
+
+                /* unfortunate hw bug workaround... */
+                engine = nouveau_engine(priv, i);
+                if (engine && engine->tlb_flush) {
+                        engine->tlb_flush(engine);
+                        continue;
                 }
-        }
-}
 
-void
-nv50_vm_flush_engine(struct nouveau_subdev *subdev, int engine)
-{
-        struct nv50_vmmgr_priv *priv = (void *)nouveau_vmmgr(subdev);
-        unsigned long flags;
-
-        spin_lock_irqsave(&priv->lock, flags);
-        nv_wr32(subdev, 0x100c80, (engine << 16) | 1);
-        if (!nv_wait(subdev, 0x100c80, 0x00000001, 0x00000000))
-                nv_error(subdev, "vm flush timeout: engine %d\n", engine);
-        spin_unlock_irqrestore(&priv->lock, flags);
+                switch (i) {
+                case NVDEV_ENGINE_GR   : vme = 0x00; break;
+                case NVDEV_ENGINE_VP   : vme = 0x01; break;
+                case NVDEV_SUBDEV_BAR  : vme = 0x06; break;
+                case NVDEV_ENGINE_MPEG : vme = 0x08; break;
+                case NVDEV_ENGINE_BSP  : vme = 0x09; break;
+                case NVDEV_ENGINE_CRYPT: vme = 0x0a; break;
+                case NVDEV_ENGINE_COPY0: vme = 0x0d; break;
+                default:
+                        continue;
+                }
+
+                nv_wr32(priv, 0x100c80, (vme << 16) | 1);
+                if (!nv_wait(priv, 0x100c80, 0x00000001, 0x00000000))
+                        nv_error(priv, "vm flush timeout: engine %d\n", vme);
+        }
+        mutex_unlock(&nv_subdev(priv)->mutex);
 }
 
 static int
@@ -211,7 +224,6 @@ nv50_vmmgr_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
         priv->base.map_sg = nv50_vm_map_sg;
         priv->base.unmap = nv50_vm_unmap;
         priv->base.flush = nv50_vm_flush;
-        spin_lock_init(&priv->lock);
         return 0;
 }
 
diff --git a/drivers/gpu/drm/nouveau/core/subdev/vm/nvc0.c b/drivers/gpu/drm/nouveau/core/subdev/vm/nvc0.c
index 4c3b0a23b9d6..668cf964e4a9 100644
--- a/drivers/gpu/drm/nouveau/core/subdev/vm/nvc0.c
+++ b/drivers/gpu/drm/nouveau/core/subdev/vm/nvc0.c
@@ -29,10 +29,10 @@
 #include <subdev/fb.h>
 #include <subdev/vm.h>
 #include <subdev/ltcg.h>
+#include <subdev/bar.h>
 
 struct nvc0_vmmgr_priv {
         struct nouveau_vmmgr base;
-        spinlock_t lock;
 };
 
 
@@ -160,40 +160,40 @@ nvc0_vm_unmap(struct nouveau_gpuobj *pgt, u32 pte, u32 cnt)
         }
 }
 
-void
-nvc0_vm_flush_engine(struct nouveau_subdev *subdev, u64 addr, int type)
-{
-        struct nvc0_vmmgr_priv *priv = (void *)nouveau_vmmgr(subdev);
-        unsigned long flags;
-
-        /* looks like maybe a "free flush slots" counter, the
-         * faster you write to 0x100cbc to more it decreases
-         */
-        spin_lock_irqsave(&priv->lock, flags);
-        if (!nv_wait_ne(subdev, 0x100c80, 0x00ff0000, 0x00000000)) {
-                nv_error(subdev, "vm timeout 0: 0x%08x %d\n",
-                         nv_rd32(subdev, 0x100c80), type);
-        }
-
-        nv_wr32(subdev, 0x100cb8, addr >> 8);
-        nv_wr32(subdev, 0x100cbc, 0x80000000 | type);
-
-        /* wait for flush to be queued? */
-        if (!nv_wait(subdev, 0x100c80, 0x00008000, 0x00008000)) {
-                nv_error(subdev, "vm timeout 1: 0x%08x %d\n",
-                         nv_rd32(subdev, 0x100c80), type);
-        }
-        spin_unlock_irqrestore(&priv->lock, flags);
-}
-
 static void
 nvc0_vm_flush(struct nouveau_vm *vm)
 {
+        struct nvc0_vmmgr_priv *priv = (void *)vm->vmm;
+        struct nouveau_bar *bar = nouveau_bar(priv);
         struct nouveau_vm_pgd *vpgd;
+        u32 type;
+
+        bar->flush(bar);
+
+        type = 0x00000001; /* PAGE_ALL */
+        if (atomic_read(&vm->engref[NVDEV_SUBDEV_BAR]))
+                type |= 0x00000004; /* HUB_ONLY */
 
+        mutex_lock(&nv_subdev(priv)->mutex);
         list_for_each_entry(vpgd, &vm->pgd_list, head) {
-                nvc0_vm_flush_engine(nv_subdev(vm->vmm), vpgd->obj->addr, 1);
+                /* looks like maybe a "free flush slots" counter, the
+                 * faster you write to 0x100cbc to more it decreases
+                 */
+                if (!nv_wait_ne(priv, 0x100c80, 0x00ff0000, 0x00000000)) {
+                        nv_error(priv, "vm timeout 0: 0x%08x %d\n",
+                                 nv_rd32(priv, 0x100c80), type);
+                }
+
+                nv_wr32(priv, 0x100cb8, vpgd->obj->addr >> 8);
+                nv_wr32(priv, 0x100cbc, 0x80000000 | type);
+
+                /* wait for flush to be queued? */
+                if (!nv_wait(priv, 0x100c80, 0x00008000, 0x00008000)) {
+                        nv_error(priv, "vm timeout 1: 0x%08x %d\n",
+                                 nv_rd32(priv, 0x100c80), type);
+                }
         }
+        mutex_unlock(&nv_subdev(priv)->mutex);
 }
 
 static int
@@ -227,7 +227,6 @@ nvc0_vmmgr_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
         priv->base.map_sg = nvc0_vm_map_sg;
         priv->base.unmap = nvc0_vm_unmap;
         priv->base.flush = nvc0_vm_flush;
-        spin_lock_init(&priv->lock);
         return 0;
 }
 
diff --git a/drivers/gpu/drm/nouveau/nouveau_abi16.c b/drivers/gpu/drm/nouveau/nouveau_abi16.c
index 1c4c6c9161ac..8f467e7bfd19 100644
--- a/drivers/gpu/drm/nouveau/nouveau_abi16.c
+++ b/drivers/gpu/drm/nouveau/nouveau_abi16.c
@@ -129,6 +129,7 @@ nouveau_abi16_chan_fini(struct nouveau_abi16 *abi16,
 
         if (chan->ntfy) {
                 nouveau_bo_vma_del(chan->ntfy, &chan->ntfy_vma);
+                nouveau_bo_unpin(chan->ntfy);
                 drm_gem_object_unreference_unlocked(chan->ntfy->gem);
         }
 
diff --git a/drivers/gpu/drm/nouveau/nouveau_bios.c b/drivers/gpu/drm/nouveau/nouveau_bios.c
index 6aa2137e093a..3e7287675ecf 100644
--- a/drivers/gpu/drm/nouveau/nouveau_bios.c
+++ b/drivers/gpu/drm/nouveau/nouveau_bios.c
@@ -1878,9 +1878,6 @@ parse_dcb_table(struct drm_device *dev, struct nvbios *bios)
         if (dcb->version < 0x21)
                 merge_like_dcb_entries(dev, dcb);
 
-        if (!dcb->entries)
-                return -ENXIO;
-
         /* dump connector table entries to log, if any exist */
         idx = -1;
         while ((conn = olddcb_conn(dev, ++idx))) {
@@ -2054,19 +2051,14 @@ nouveau_bios_posted(struct drm_device *dev)
         struct nouveau_drm *drm = nouveau_drm(dev);
         unsigned htotal;
 
-        if (nv_device(drm->device)->card_type >= NV_50) {
-                if (NVReadVgaCrtc(dev, 0, 0x00) == 0 &&
-                    NVReadVgaCrtc(dev, 0, 0x1a) == 0)
-                        return false;
+        if (nv_device(drm->device)->card_type >= NV_50)
                 return true;
-        }
 
         htotal  = NVReadVgaCrtc(dev, 0, 0x06);
         htotal |= (NVReadVgaCrtc(dev, 0, 0x07) & 0x01) << 8;
         htotal |= (NVReadVgaCrtc(dev, 0, 0x07) & 0x20) << 4;
         htotal |= (NVReadVgaCrtc(dev, 0, 0x25) & 0x01) << 10;
         htotal |= (NVReadVgaCrtc(dev, 0, 0x41) & 0x01) << 11;
-
         return (htotal != 0);
 }
 
diff --git a/drivers/gpu/drm/nouveau/nouveau_bo.c b/drivers/gpu/drm/nouveau/nouveau_bo.c
index 7ff10711a4d0..4b1afb131380 100644
--- a/drivers/gpu/drm/nouveau/nouveau_bo.c
+++ b/drivers/gpu/drm/nouveau/nouveau_bo.c
@@ -255,7 +255,7 @@ set_placement_range(struct nouveau_bo *nvbo, uint32_t type)
 {
         struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev);
         struct nouveau_fb *pfb = nouveau_fb(drm->device);
-        u32 vram_pages = pfb->ram.size >> PAGE_SHIFT;
+        u32 vram_pages = pfb->ram->size >> PAGE_SHIFT;
 
         if (nv_device(drm->device)->card_type == NV_10 &&
             nvbo->tile_mode && (type & TTM_PL_FLAG_VRAM) &&
@@ -968,7 +968,7 @@ nouveau_bo_move_m2mf(struct ttm_buffer_object *bo, int evict, bool intr,
                      bool no_wait_gpu, struct ttm_mem_reg *new_mem)
 {
         struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
-        struct nouveau_channel *chan = chan = drm->channel;
+        struct nouveau_channel *chan = chan = drm->ttm.chan;
         struct nouveau_bo *nvbo = nouveau_bo(bo);
         struct ttm_mem_reg *old_mem = &bo->mem;
         int ret;
@@ -1052,6 +1052,7 @@ nouveau_bo_move_init(struct nouveau_drm *drm)
                         }
 
                         drm->ttm.move = mthd->exec;
+                        drm->ttm.chan = chan;
                         name = mthd->name;
                         break;
                 }
@@ -1550,13 +1551,8 @@ void
 nouveau_bo_vma_del(struct nouveau_bo *nvbo, struct nouveau_vma *vma)
 {
         if (vma->node) {
-                if (nvbo->bo.mem.mem_type != TTM_PL_SYSTEM) {
-                        spin_lock(&nvbo->bo.bdev->fence_lock);
-                        ttm_bo_wait(&nvbo->bo, false, false, false);
-                        spin_unlock(&nvbo->bo.bdev->fence_lock);
+                if (nvbo->bo.mem.mem_type != TTM_PL_SYSTEM)
                         nouveau_vm_unmap(vma);
-                }
-
                 nouveau_vm_put(vma);
                 list_del(&vma->head);
         }
diff --git a/drivers/gpu/drm/nouveau/nouveau_chan.c b/drivers/gpu/drm/nouveau/nouveau_chan.c
index eaa80a2b81ee..e84f4c32331b 100644
--- a/drivers/gpu/drm/nouveau/nouveau_chan.c
+++ b/drivers/gpu/drm/nouveau/nouveau_chan.c
@@ -147,7 +147,7 @@ nouveau_channel_prep(struct nouveau_drm *drm, struct nouveau_cli *cli,
                 args.limit = client->vm->vmm->limit - 1;
         } else
         if (chan->push.buffer->bo.mem.mem_type == TTM_PL_VRAM) {
-                u64 limit = pfb->ram.size - imem->reserved - 1;
+                u64 limit = pfb->ram->size - imem->reserved - 1;
                 if (device->card_type == NV_04) {
                         /* nv04 vram pushbuf hack, retarget to its location in
                          * the framebuffer bar rather than direct vram access..
@@ -282,7 +282,7 @@ nouveau_channel_init(struct nouveau_channel *chan, u32 vram, u32 gart)
                 } else {
                         args.flags = NV_DMA_TARGET_VRAM | NV_DMA_ACCESS_RDWR;
                         args.start = 0;
-                        args.limit = pfb->ram.size - imem->reserved - 1;
+                        args.limit = pfb->ram->size - imem->reserved - 1;
                 }
 
                 ret = nouveau_object_new(nv_object(client), chan->handle, vram,
diff --git a/drivers/gpu/drm/nouveau/nouveau_display.c b/drivers/gpu/drm/nouveau/nouveau_display.c
index f17dc2ab03ec..708b2d1c0037 100644
--- a/drivers/gpu/drm/nouveau/nouveau_display.c
+++ b/drivers/gpu/drm/nouveau/nouveau_display.c
@@ -26,6 +26,7 @@
 
 #include <drm/drmP.h>
 #include <drm/drm_crtc_helper.h>
+#include <drm/ttm/ttm_execbuf_util.h>
 
 #include "nouveau_fbcon.h"
 #include "dispnv04/hw.h"
@@ -332,10 +333,15 @@ nouveau_display_create(struct drm_device *dev)
 
         if (nouveau_modeset == 1 ||
             (nouveau_modeset < 0 && pclass == PCI_CLASS_DISPLAY_VGA)) {
-                if (nv_device(drm->device)->card_type < NV_50)
-                        ret = nv04_display_create(dev);
-                else
-                        ret = nv50_display_create(dev);
+                if (drm->vbios.dcb.entries) {
+                        if (nv_device(drm->device)->card_type < NV_50)
+                                ret = nv04_display_create(dev);
+                        else
+                                ret = nv50_display_create(dev);
+                } else {
+                        ret = 0;
+                }
+
                 if (ret)
                         goto disp_create_err;
 
@@ -457,51 +463,6 @@ nouveau_display_resume(struct drm_device *dev)
 }
 
 static int
-nouveau_page_flip_reserve(struct nouveau_bo *old_bo,
-                          struct nouveau_bo *new_bo)
-{
-        int ret;
-
-        ret = nouveau_bo_pin(new_bo, TTM_PL_FLAG_VRAM);
-        if (ret)
-                return ret;
-
-        ret = ttm_bo_reserve(&new_bo->bo, false, false, false, 0);
-        if (ret)
-                goto fail;
-
-        if (likely(old_bo != new_bo)) {
-                ret = ttm_bo_reserve(&old_bo->bo, false, false, false, 0);
-                if (ret)
-                        goto fail_unreserve;
-        }
-
-        return 0;
-
-fail_unreserve:
-        ttm_bo_unreserve(&new_bo->bo);
-fail:
-        nouveau_bo_unpin(new_bo);
-        return ret;
-}
-
-static void
-nouveau_page_flip_unreserve(struct nouveau_bo *old_bo,
-                            struct nouveau_bo *new_bo,
-                            struct nouveau_fence *fence)
-{
-        nouveau_bo_fence(new_bo, fence);
-        ttm_bo_unreserve(&new_bo->bo);
-
-        if (likely(old_bo != new_bo)) {
-                nouveau_bo_fence(old_bo, fence);
-                ttm_bo_unreserve(&old_bo->bo);
-        }
-
-        nouveau_bo_unpin(old_bo);
-}
-
-static int
 nouveau_page_flip_emit(struct nouveau_channel *chan,
                        struct nouveau_bo *old_bo,
                        struct nouveau_bo *new_bo,
@@ -563,6 +524,9 @@ nouveau_crtc_page_flip(struct drm_crtc *crtc, struct drm_framebuffer *fb,
         struct nouveau_page_flip_state *s;
         struct nouveau_channel *chan = NULL;
         struct nouveau_fence *fence;
+        struct list_head res;
+        struct ttm_validate_buffer res_val[2];
+        struct ww_acquire_ctx ticket;
         int ret;
 
         if (!drm->channel)
@@ -572,25 +536,43 @@ nouveau_crtc_page_flip(struct drm_crtc *crtc, struct drm_framebuffer *fb,
         if (!s)
                 return -ENOMEM;
 
-        /* Don't let the buffers go away while we flip */
-        ret = nouveau_page_flip_reserve(old_bo, new_bo);
-        if (ret)
-                goto fail_free;
-
-        /* Initialize a page flip struct */
-        *s = (struct nouveau_page_flip_state)
-                { { }, event, nouveau_crtc(crtc)->index,
-                  fb->bits_per_pixel, fb->pitches[0], crtc->x, crtc->y,
-                  new_bo->bo.offset };
-
         /* Choose the channel the flip will be handled in */
+        spin_lock(&old_bo->bo.bdev->fence_lock);
         fence = new_bo->bo.sync_obj;
         if (fence)
                 chan = fence->channel;
         if (!chan)
                 chan = drm->channel;
+        spin_unlock(&old_bo->bo.bdev->fence_lock);
+
         mutex_lock(&chan->cli->mutex);
 
+        if (new_bo != old_bo) {
+                ret = nouveau_bo_pin(new_bo, TTM_PL_FLAG_VRAM);
+                if (likely(!ret)) {
+                        res_val[0].bo = &old_bo->bo;
+                        res_val[1].bo = &new_bo->bo;
+                        INIT_LIST_HEAD(&res);
+                        list_add_tail(&res_val[0].head, &res);
+                        list_add_tail(&res_val[1].head, &res);
+                        ret = ttm_eu_reserve_buffers(&ticket, &res);
+                        if (ret)
+                                nouveau_bo_unpin(new_bo);
+                }
+        } else
+                ret = ttm_bo_reserve(&new_bo->bo, false, false, false, 0);
+
+        if (ret) {
+                mutex_unlock(&chan->cli->mutex);
+                goto fail_free;
+        }
+
+        /* Initialize a page flip struct */
+        *s = (struct nouveau_page_flip_state)
+                { { }, event, nouveau_crtc(crtc)->index,
+                  fb->bits_per_pixel, fb->pitches[0], crtc->x, crtc->y,
+                  new_bo->bo.offset };
+
         /* Emit a page flip */
         if (nv_device(drm->device)->card_type >= NV_50) {
                 ret = nv50_display_flip_next(crtc, fb, chan, 0);
@@ -608,12 +590,22 @@ nouveau_crtc_page_flip(struct drm_crtc *crtc, struct drm_framebuffer *fb,
         /* Update the crtc struct and cleanup */
         crtc->fb = fb;
 
-        nouveau_page_flip_unreserve(old_bo, new_bo, fence);
+        if (old_bo != new_bo) {
+                ttm_eu_fence_buffer_objects(&ticket, &res, fence);
+                nouveau_bo_unpin(old_bo);
+        } else {
+                nouveau_bo_fence(new_bo, fence);
+                ttm_bo_unreserve(&new_bo->bo);
+        }
         nouveau_fence_unref(&fence);
         return 0;
 
 fail_unreserve:
-        nouveau_page_flip_unreserve(old_bo, new_bo, NULL);
+        if (old_bo != new_bo) {
+                ttm_eu_backoff_reservation(&ticket, &res);
+                nouveau_bo_unpin(new_bo);
+        } else
+                ttm_bo_unreserve(&new_bo->bo);
 fail_free:
         kfree(s);
         return ret;
diff --git a/drivers/gpu/drm/nouveau/nouveau_drm.c b/drivers/gpu/drm/nouveau/nouveau_drm.c
index 383f4e6ea9d1..218a4b522fe5 100644
--- a/drivers/gpu/drm/nouveau/nouveau_drm.c
+++ b/drivers/gpu/drm/nouveau/nouveau_drm.c
@@ -702,6 +702,7 @@ driver = {
         .gem_prime_export = drm_gem_prime_export,
         .gem_prime_import = drm_gem_prime_import,
         .gem_prime_pin = nouveau_gem_prime_pin,
+        .gem_prime_unpin = nouveau_gem_prime_unpin,
         .gem_prime_get_sg_table = nouveau_gem_prime_get_sg_table,
         .gem_prime_import_sg_table = nouveau_gem_prime_import_sg_table,
         .gem_prime_vmap = nouveau_gem_prime_vmap,
diff --git a/drivers/gpu/drm/nouveau/nouveau_drm.h b/drivers/gpu/drm/nouveau/nouveau_drm.h
index f2b30f89dee0..41ff7e0d403a 100644
--- a/drivers/gpu/drm/nouveau/nouveau_drm.h
+++ b/drivers/gpu/drm/nouveau/nouveau_drm.h
@@ -96,6 +96,7 @@ struct nouveau_drm {
                 int (*move)(struct nouveau_channel *,
                             struct ttm_buffer_object *,
                             struct ttm_mem_reg *, struct ttm_mem_reg *);
+                struct nouveau_channel *chan;
                 int mtrr;
         } ttm;
 
diff --git a/drivers/gpu/drm/nouveau/nouveau_fbcon.c b/drivers/gpu/drm/nouveau/nouveau_fbcon.c
index b03531781580..9352010030e9 100644
--- a/drivers/gpu/drm/nouveau/nouveau_fbcon.c
+++ b/drivers/gpu/drm/nouveau/nouveau_fbcon.c
@@ -289,16 +289,13 @@ nouveau_fbcon_create(struct drm_fb_helper *helper,
         ret = nouveau_bo_pin(nvbo, TTM_PL_FLAG_VRAM);
         if (ret) {
                 NV_ERROR(drm, "failed to pin fb: %d\n", ret);
-                nouveau_bo_ref(NULL, &nvbo);
-                goto out;
+                goto out_unref;
         }
 
         ret = nouveau_bo_map(nvbo);
         if (ret) {
                 NV_ERROR(drm, "failed to map fb: %d\n", ret);
-                nouveau_bo_unpin(nvbo);
-                nouveau_bo_ref(NULL, &nvbo);
-                goto out;
+                goto out_unpin;
         }
 
         chan = nouveau_nofbaccel ? NULL : drm->channel;
@@ -316,13 +313,14 @@ nouveau_fbcon_create(struct drm_fb_helper *helper,
         info = framebuffer_alloc(0, &pdev->dev);
         if (!info) {
                 ret = -ENOMEM;
-                goto out_unref;
+                goto out_unlock;
         }
 
         ret = fb_alloc_cmap(&info->cmap, 256, 0);
         if (ret) {
                 ret = -ENOMEM;
-                goto out_unref;
+                framebuffer_release(info);
+                goto out_unlock;
         }
 
         info->par = fbcon;
@@ -337,7 +335,7 @@ nouveau_fbcon_create(struct drm_fb_helper *helper,
         fbcon->helper.fbdev = info;
 
         strcpy(info->fix.id, "nouveaufb");
-        if (nouveau_nofbaccel)
+        if (!chan)
                 info->flags = FBINFO_DEFAULT | FBINFO_HWACCEL_DISABLED;
         else
                 info->flags = FBINFO_DEFAULT | FBINFO_HWACCEL_COPYAREA |
@@ -383,8 +381,14 @@ nouveau_fbcon_create(struct drm_fb_helper *helper,
         vga_switcheroo_client_fb_set(dev->pdev, info);
         return 0;
 
-out_unref:
+out_unlock:
         mutex_unlock(&dev->struct_mutex);
+        if (chan)
+                nouveau_bo_vma_del(nvbo, &fbcon->nouveau_fb.vma);
+out_unpin:
+        nouveau_bo_unpin(nvbo);
+out_unref:
+        nouveau_bo_ref(NULL, &nvbo);
 out:
         return ret;
 }
@@ -413,6 +417,7 @@ nouveau_fbcon_destroy(struct drm_device *dev, struct nouveau_fbdev *fbcon)
         if (nouveau_fb->nvbo) {
                 nouveau_bo_unmap(nouveau_fb->nvbo);
                 nouveau_bo_vma_del(nouveau_fb->nvbo, &nouveau_fb->vma);
+                nouveau_bo_unpin(nouveau_fb->nvbo);
                 drm_gem_object_unreference_unlocked(nouveau_fb->nvbo->gem);
                 nouveau_fb->nvbo = NULL;
         }
@@ -467,10 +472,10 @@ nouveau_fbcon_init(struct drm_device *dev)
 
         drm_fb_helper_single_add_all_connectors(&fbcon->helper);
 
-        if (pfb->ram.size <= 32 * 1024 * 1024)
+        if (pfb->ram->size <= 32 * 1024 * 1024)
                 preferred_bpp = 8;
         else
-        if (pfb->ram.size <= 64 * 1024 * 1024)
+        if (pfb->ram->size <= 64 * 1024 * 1024)
                 preferred_bpp = 16;
         else
                 preferred_bpp = 32;
diff --git a/drivers/gpu/drm/nouveau/nouveau_fence.c b/drivers/gpu/drm/nouveau/nouveau_fence.c
index 6c946837a0aa..1680d9187bab 100644
--- a/drivers/gpu/drm/nouveau/nouveau_fence.c
+++ b/drivers/gpu/drm/nouveau/nouveau_fence.c
@@ -35,15 +35,34 @@
 
 #include <engine/fifo.h>
 
+struct fence_work {
+        struct work_struct base;
+        struct list_head head;
+        void (*func)(void *);
+        void *data;
+};
+
+static void
+nouveau_fence_signal(struct nouveau_fence *fence)
+{
+        struct fence_work *work, *temp;
+
+        list_for_each_entry_safe(work, temp, &fence->work, head) {
+                schedule_work(&work->base);
+                list_del(&work->head);
+        }
+
+        fence->channel = NULL;
+        list_del(&fence->head);
+}
+
 void
 nouveau_fence_context_del(struct nouveau_fence_chan *fctx)
 {
         struct nouveau_fence *fence, *fnext;
         spin_lock(&fctx->lock);
         list_for_each_entry_safe(fence, fnext, &fctx->pending, head) {
-                fence->channel = NULL;
-                list_del(&fence->head);
-                nouveau_fence_unref(&fence);
+                nouveau_fence_signal(fence);
         }
         spin_unlock(&fctx->lock);
 }
@@ -57,6 +76,50 @@ nouveau_fence_context_new(struct nouveau_fence_chan *fctx)
 }
 
 static void
+nouveau_fence_work_handler(struct work_struct *kwork)
+{
+        struct fence_work *work = container_of(kwork, typeof(*work), base);
+        work->func(work->data);
+        kfree(work);
+}
+
+void
+nouveau_fence_work(struct nouveau_fence *fence,
+                   void (*func)(void *), void *data)
+{
+        struct nouveau_channel *chan = fence->channel;
+        struct nouveau_fence_chan *fctx;
+        struct fence_work *work = NULL;
+
+        if (nouveau_fence_done(fence)) {
+                func(data);
+                return;
+        }
+
+        fctx = chan->fence;
+        work = kmalloc(sizeof(*work), GFP_KERNEL);
+        if (!work) {
+                WARN_ON(nouveau_fence_wait(fence, false, false));
+                func(data);
+                return;
+        }
+
+        spin_lock(&fctx->lock);
+        if (!fence->channel) {
+                spin_unlock(&fctx->lock);
+                kfree(work);
+                func(data);
+                return;
+        }
+
+        INIT_WORK(&work->base, nouveau_fence_work_handler);
+        work->func = func;
+        work->data = data;
+        list_add(&work->head, &fence->work);
+        spin_unlock(&fctx->lock);
+}
+
+static void
 nouveau_fence_update(struct nouveau_channel *chan)
 {
         struct nouveau_fence_chan *fctx = chan->fence;
@@ -67,8 +130,7 @@ nouveau_fence_update(struct nouveau_channel *chan)
                 if (fctx->read(chan) < fence->sequence)
                         break;
 
-                fence->channel = NULL;
-                list_del(&fence->head);
+                nouveau_fence_signal(fence);
                 nouveau_fence_unref(&fence);
         }
         spin_unlock(&fctx->lock);
@@ -265,6 +327,7 @@ nouveau_fence_new(struct nouveau_channel *chan, bool sysmem,
         if (!fence)
                 return -ENOMEM;
 
+        INIT_LIST_HEAD(&fence->work);
         fence->sysmem = sysmem;
         kref_init(&fence->kref);
 
diff --git a/drivers/gpu/drm/nouveau/nouveau_fence.h b/drivers/gpu/drm/nouveau/nouveau_fence.h
index c89943407b52..c57bb61da58c 100644
--- a/drivers/gpu/drm/nouveau/nouveau_fence.h
+++ b/drivers/gpu/drm/nouveau/nouveau_fence.h
@@ -5,6 +5,7 @@ struct nouveau_drm;
 
 struct nouveau_fence {
         struct list_head head;
+        struct list_head work;
         struct kref kref;
 
         bool sysmem;
@@ -22,6 +23,7 @@ void nouveau_fence_unref(struct nouveau_fence **);
 
 int  nouveau_fence_emit(struct nouveau_fence *, struct nouveau_channel *);
 bool nouveau_fence_done(struct nouveau_fence *);
+void nouveau_fence_work(struct nouveau_fence *, void (*)(void *), void *);
 int  nouveau_fence_wait(struct nouveau_fence *, bool lazy, bool intr);
 int  nouveau_fence_sync(struct nouveau_fence *, struct nouveau_channel *);
 
diff --git a/drivers/gpu/drm/nouveau/nouveau_gem.c b/drivers/gpu/drm/nouveau/nouveau_gem.c
index b4b4d0c1f4af..e72d09c068a8 100644
--- a/drivers/gpu/drm/nouveau/nouveau_gem.c
+++ b/drivers/gpu/drm/nouveau/nouveau_gem.c
@@ -50,7 +50,8 @@ nouveau_gem_object_del(struct drm_gem_object *gem)
                 return;
         nvbo->gem = NULL;
 
-        if (unlikely(nvbo->pin_refcnt)) {
+        /* Lockdep hates you for doing reserve with gem object lock held */
+        if (WARN_ON_ONCE(nvbo->pin_refcnt)) {
                 nvbo->pin_refcnt = 1;
                 nouveau_bo_unpin(nvbo);
         }
@@ -101,6 +102,41 @@ out:
         return ret;
 }
 
+static void
+nouveau_gem_object_delete(void *data)
+{
+        struct nouveau_vma *vma = data;
+        nouveau_vm_unmap(vma);
+        nouveau_vm_put(vma);
+        kfree(vma);
+}
+
+static void
+nouveau_gem_object_unmap(struct nouveau_bo *nvbo, struct nouveau_vma *vma)
+{
+        const bool mapped = nvbo->bo.mem.mem_type != TTM_PL_SYSTEM;
+        struct nouveau_fence *fence = NULL;
+
+        list_del(&vma->head);
+
+        if (mapped) {
+                spin_lock(&nvbo->bo.bdev->fence_lock);
+                if (nvbo->bo.sync_obj)
+                        fence = nouveau_fence_ref(nvbo->bo.sync_obj);
+                spin_unlock(&nvbo->bo.bdev->fence_lock);
+        }
+
+        if (fence) {
+                nouveau_fence_work(fence, nouveau_gem_object_delete, vma);
+        } else {
+                if (mapped)
+                        nouveau_vm_unmap(vma);
+                nouveau_vm_put(vma);
+                kfree(vma);
+        }
+        nouveau_fence_unref(&fence);
+}
+
 void
 nouveau_gem_object_close(struct drm_gem_object *gem, struct drm_file *file_priv)
 {
@@ -118,10 +154,8 @@ nouveau_gem_object_close(struct drm_gem_object *gem, struct drm_file *file_priv)
 
         vma = nouveau_bo_vma_find(nvbo, cli->base.vm);
         if (vma) {
-                if (--vma->refcount == 0) {
-                        nouveau_bo_vma_del(nvbo, vma);
-                        kfree(vma);
-                }
+                if (--vma->refcount == 0)
+                        nouveau_gem_object_unmap(nvbo, vma);
         }
         ttm_bo_unreserve(&nvbo->bo);
 }
@@ -276,10 +310,12 @@ struct validate_op {
         struct list_head vram_list;
         struct list_head gart_list;
         struct list_head both_list;
+        struct ww_acquire_ctx ticket;
 };
 
 static void
-validate_fini_list(struct list_head *list, struct nouveau_fence *fence)
+validate_fini_list(struct list_head *list, struct nouveau_fence *fence,
+                   struct ww_acquire_ctx *ticket)
 {
         struct list_head *entry, *tmp;
         struct nouveau_bo *nvbo;
@@ -296,17 +332,24 @@ validate_fini_list(struct list_head *list, struct nouveau_fence *fence)
 
                 list_del(&nvbo->entry);
                 nvbo->reserved_by = NULL;
-                ttm_bo_unreserve(&nvbo->bo);
+                ttm_bo_unreserve_ticket(&nvbo->bo, ticket);
                 drm_gem_object_unreference_unlocked(nvbo->gem);
         }
 }
 
 static void
-validate_fini(struct validate_op *op, struct nouveau_fence* fence)
+validate_fini_no_ticket(struct validate_op *op, struct nouveau_fence *fence)
 {
-        validate_fini_list(&op->vram_list, fence);
-        validate_fini_list(&op->gart_list, fence);
-        validate_fini_list(&op->both_list, fence);
+        validate_fini_list(&op->vram_list, fence, &op->ticket);
+        validate_fini_list(&op->gart_list, fence, &op->ticket);
+        validate_fini_list(&op->both_list, fence, &op->ticket);
+}
+
+static void
+validate_fini(struct validate_op *op, struct nouveau_fence *fence)
+{
+        validate_fini_no_ticket(op, fence);
+        ww_acquire_fini(&op->ticket);
 }
 
 static int
@@ -316,13 +359,11 @@ validate_init(struct nouveau_channel *chan, struct drm_file *file_priv,
 {
         struct nouveau_cli *cli = nouveau_cli(file_priv);
         struct drm_device *dev = chan->drm->dev;
-        struct nouveau_drm *drm = nouveau_drm(dev);
-        uint32_t sequence;
         int trycnt = 0;
         int ret, i;
         struct nouveau_bo *res_bo = NULL;
 
-        sequence = atomic_add_return(1, &drm->ttm.validate_sequence);
+        ww_acquire_init(&op->ticket, &reservation_ww_class);
 retry:
         if (++trycnt > 100000) {
                 NV_ERROR(cli, "%s failed and gave up.\n", __func__);
@@ -337,6 +378,7 @@ retry:
                 gem = drm_gem_object_lookup(dev, file_priv, b->handle);
                 if (!gem) {
                         NV_ERROR(cli, "Unknown handle 0x%08x\n", b->handle);
+                        ww_acquire_done(&op->ticket);
                         validate_fini(op, NULL);
                         return -ENOENT;
                 }
@@ -351,21 +393,23 @@ retry:
                         NV_ERROR(cli, "multiple instances of buffer %d on "
                                       "validation list\n", b->handle);
                         drm_gem_object_unreference_unlocked(gem);
+                        ww_acquire_done(&op->ticket);
                         validate_fini(op, NULL);
                         return -EINVAL;
                 }
 
-                ret = ttm_bo_reserve(&nvbo->bo, true, false, true, sequence);
+                ret = ttm_bo_reserve(&nvbo->bo, true, false, true, &op->ticket);
                 if (ret) {
-                        validate_fini(op, NULL);
-                        if (unlikely(ret == -EAGAIN)) {
-                                sequence = atomic_add_return(1, &drm->ttm.validate_sequence);
+                        validate_fini_no_ticket(op, NULL);
+                        if (unlikely(ret == -EDEADLK)) {
                                 ret = ttm_bo_reserve_slowpath(&nvbo->bo, true,
-                                                              sequence);
+                                                              &op->ticket);
                                 if (!ret)
                                         res_bo = nvbo;
                         }
                         if (unlikely(ret)) {
+                                ww_acquire_done(&op->ticket);
+                                ww_acquire_fini(&op->ticket);
                                 drm_gem_object_unreference_unlocked(gem);
                                 if (ret != -ERESTARTSYS)
                                         NV_ERROR(cli, "fail reserve\n");
@@ -389,6 +433,7 @@ retry:
                         NV_ERROR(cli, "invalid valid domains: 0x%08x\n",
                                  b->valid_domains);
                         list_add_tail(&nvbo->entry, &op->both_list);
+                        ww_acquire_done(&op->ticket);
                         validate_fini(op, NULL);
                         return -EINVAL;
                 }
@@ -396,6 +441,7 @@ retry:
                         goto retry;
         }
 
+        ww_acquire_done(&op->ticket);
         return 0;
 }
 
diff --git a/drivers/gpu/drm/nouveau/nouveau_gem.h b/drivers/gpu/drm/nouveau/nouveau_gem.h
index 8d7a3f0aeb86..502e4290aa8f 100644
--- a/drivers/gpu/drm/nouveau/nouveau_gem.h
+++ b/drivers/gpu/drm/nouveau/nouveau_gem.h
@@ -36,6 +36,7 @@ extern int nouveau_gem_ioctl_info(struct drm_device *, void *,
                                   struct drm_file *);
 
 extern int nouveau_gem_prime_pin(struct drm_gem_object *);
+extern void nouveau_gem_prime_unpin(struct drm_gem_object *);
 extern struct sg_table *nouveau_gem_prime_get_sg_table(struct drm_gem_object *);
 extern struct drm_gem_object *nouveau_gem_prime_import_sg_table(
         struct drm_device *, size_t size, struct sg_table *);
diff --git a/drivers/gpu/drm/nouveau/nouveau_mem.c b/drivers/gpu/drm/nouveau/nouveau_mem.c
index 7e0ff10a2759..4f6a572f2258 100644
--- a/drivers/gpu/drm/nouveau/nouveau_mem.c
+++ b/drivers/gpu/drm/nouveau/nouveau_mem.c
@@ -125,7 +125,7 @@ nv50_mem_timing_calc(struct drm_device *dev, u32 freq,
                 t->reg[7] = 0x4000202 | (e->tCL - 1) << 16;
 
                 /* XXX: P.version == 1 only has DDR2 and GDDR3? */
-                if (pfb->ram.type == NV_MEM_TYPE_DDR2) {
+                if (pfb->ram->type == NV_MEM_TYPE_DDR2) {
                         t->reg[5] |= (e->tCL + 3) << 8;
                         t->reg[6] |= (t->tCWL - 2) << 8;
                         t->reg[8] |= (e->tCL - 4);
@@ -428,7 +428,7 @@ nouveau_mem_timing_calc(struct drm_device *dev, u32 freq,
                 break;
         }
 
-        switch (pfb->ram.type * !ret) {
+        switch (pfb->ram->type * !ret) {
         case NV_MEM_TYPE_GDDR3:
                 ret = nouveau_mem_gddr3_mr(dev, freq, e, len, boot, t);
                 break;
@@ -455,7 +455,7 @@ nouveau_mem_timing_calc(struct drm_device *dev, u32 freq,
                 else
                         dll_off = !!(ramcfg[2] & 0x40);
 
-                switch (pfb->ram.type) {
+                switch (pfb->ram->type) {
                 case NV_MEM_TYPE_GDDR3:
                         t->mr[1] &= ~0x00000040;
                         t->mr[1] |=  0x00000040 * dll_off;
@@ -522,7 +522,7 @@ nouveau_mem_timing_read(struct drm_device *dev, struct nouveau_pm_memtiming *t)
         t->odt = 0;
         t->drive_strength = 0;
 
-        switch (pfb->ram.type) {
+        switch (pfb->ram->type) {
         case NV_MEM_TYPE_DDR3:
                 t->odt |= (t->mr[1] & 0x200) >> 7;
         case NV_MEM_TYPE_DDR2:
@@ -551,7 +551,7 @@ nouveau_mem_exec(struct nouveau_mem_exec_func *exec,
         u32 mr[3] = { info->mr[0], info->mr[1], info->mr[2] };
         u32 mr1_dlloff;
 
-        switch (pfb->ram.type) {
+        switch (pfb->ram->type) {
         case NV_MEM_TYPE_DDR2:
                 tDLLK = 2000;
                 mr1_dlloff = 0x00000001;
@@ -572,7 +572,7 @@ nouveau_mem_exec(struct nouveau_mem_exec_func *exec,
         }
 
         /* fetch current MRs */
-        switch (pfb->ram.type) {
+        switch (pfb->ram->type) {
         case NV_MEM_TYPE_GDDR3:
         case NV_MEM_TYPE_DDR3:
                 mr[2] = exec->mrg(exec, 2);
@@ -639,7 +639,7 @@ nouveau_mem_exec(struct nouveau_mem_exec_func *exec,
                 exec->mrs (exec, 0, info->mr[0] | 0x00000000);
                 exec->wait(exec, tMRD);
                 exec->wait(exec, tDLLK);
-                if (pfb->ram.type == NV_MEM_TYPE_GDDR3)
+                if (pfb->ram->type == NV_MEM_TYPE_GDDR3)
                         exec->precharge(exec);
         }
 
diff --git a/drivers/gpu/drm/nouveau/nouveau_prime.c b/drivers/gpu/drm/nouveau/nouveau_prime.c
index f53e10874cae..e90468d5e5c0 100644
--- a/drivers/gpu/drm/nouveau/nouveau_prime.c
+++ b/drivers/gpu/drm/nouveau/nouveau_prime.c
@@ -84,7 +84,7 @@ struct drm_gem_object *nouveau_gem_prime_import_sg_table(struct drm_device *dev,
 int nouveau_gem_prime_pin(struct drm_gem_object *obj)
 {
         struct nouveau_bo *nvbo = nouveau_gem_object(obj);
-        int ret = 0;
+        int ret;
 
         /* pin buffer into GTT */
         ret = nouveau_bo_pin(nvbo, TTM_PL_FLAG_TT);
@@ -93,3 +93,10 @@ int nouveau_gem_prime_pin(struct drm_gem_object *obj)
 
         return 0;
 }
+
+void nouveau_gem_prime_unpin(struct drm_gem_object *obj)
+{
+        struct nouveau_bo *nvbo = nouveau_gem_object(obj);
+
+        nouveau_bo_unpin(nvbo);
+}
diff --git a/drivers/gpu/drm/nouveau/nouveau_ttm.c b/drivers/gpu/drm/nouveau/nouveau_ttm.c
index f19a15a3bc03..19e3757291fb 100644
--- a/drivers/gpu/drm/nouveau/nouveau_ttm.c
+++ b/drivers/gpu/drm/nouveau/nouveau_ttm.c
@@ -69,7 +69,7 @@ nouveau_vram_manager_del(struct ttm_mem_type_manager *man,
         struct nouveau_drm *drm = nouveau_bdev(man->bdev);
         struct nouveau_fb *pfb = nouveau_fb(drm->device);
         nouveau_mem_node_cleanup(mem->mm_node);
-        pfb->ram.put(pfb, (struct nouveau_mem **)&mem->mm_node);
+        pfb->ram->put(pfb, (struct nouveau_mem **)&mem->mm_node);
 }
 
 static int
@@ -88,7 +88,7 @@ nouveau_vram_manager_new(struct ttm_mem_type_manager *man,
         if (nvbo->tile_flags & NOUVEAU_GEM_TILE_NONCONTIG)
                 size_nc = 1 << nvbo->page_shift;
 
-        ret = pfb->ram.get(pfb, mem->num_pages << PAGE_SHIFT,
+        ret = pfb->ram->get(pfb, mem->num_pages << PAGE_SHIFT,
                            mem->page_alignment << PAGE_SHIFT, size_nc,
                            (nvbo->tile_flags >> 8) & 0x3ff, &node);
         if (ret) {
@@ -111,7 +111,7 @@ nouveau_vram_manager_debug(struct ttm_mem_type_manager *man, const char *prefix)
         struct nouveau_mm_node *r;
         u32 total = 0, free = 0;
 
-        mutex_lock(&mm->mutex);
+        mutex_lock(&nv_subdev(pfb)->mutex);
         list_for_each_entry(r, &mm->nodes, nl_entry) {
                 printk(KERN_DEBUG "%s %d: 0x%010llx 0x%010llx\n",
                        prefix, r->type, ((u64)r->offset << 12),
@@ -121,7 +121,7 @@ nouveau_vram_manager_debug(struct ttm_mem_type_manager *man, const char *prefix)
                 if (!r->type)
                         free += r->length;
         }
-        mutex_unlock(&mm->mutex);
+        mutex_unlock(&nv_subdev(pfb)->mutex);
 
         printk(KERN_DEBUG "%s  total: 0x%010llx free: 0x%010llx\n",
                prefix, (u64)total << 12, (u64)free << 12);
@@ -168,9 +168,6 @@ nouveau_gart_manager_new(struct ttm_mem_type_manager *man,
         struct nouveau_bo *nvbo = nouveau_bo(bo);
         struct nouveau_mem *node;
 
-        if (unlikely((mem->num_pages << PAGE_SHIFT) >= 512 * 1024 * 1024))
-                return -ENOMEM;
-
         node = kzalloc(sizeof(*node), GFP_KERNEL);
         if (!node)
                 return -ENOMEM;
@@ -386,7 +383,7 @@ nouveau_ttm_init(struct nouveau_drm *drm)
         }
 
         /* VRAM init */
-        drm->gem.vram_available  = nouveau_fb(drm->device)->ram.size;
+        drm->gem.vram_available  = nouveau_fb(drm->device)->ram->size;
         drm->gem.vram_available -= nouveau_instmem(drm->device)->reserved;
 
         ret = ttm_bo_init_mm(&drm->ttm.bdev, TTM_PL_VRAM,
@@ -396,15 +393,12 @@ nouveau_ttm_init(struct nouveau_drm *drm)
                 return ret;
         }
 
-        drm->ttm.mtrr = drm_mtrr_add(pci_resource_start(dev->pdev, 1),
-                                     pci_resource_len(dev->pdev, 1),
-                                     DRM_MTRR_WC);
+        drm->ttm.mtrr = arch_phys_wc_add(pci_resource_start(dev->pdev, 1),
+                                         pci_resource_len(dev->pdev, 1));
 
         /* GART init */
         if (drm->agp.stat != ENABLED) {
                 drm->gem.gart_available = nouveau_vmmgr(drm->device)->limit;
-                if (drm->gem.gart_available > 512 * 1024 * 1024)
-                        drm->gem.gart_available = 512 * 1024 * 1024;
         } else {
                 drm->gem.gart_available = drm->agp.size;
         }
@@ -433,10 +427,6 @@ nouveau_ttm_fini(struct nouveau_drm *drm)
 
         nouveau_ttm_global_release(drm);
 
-        if (drm->ttm.mtrr >= 0) {
-                drm_mtrr_del(drm->ttm.mtrr,
-                             pci_resource_start(drm->dev->pdev, 1),
-                             pci_resource_len(drm->dev->pdev, 1), DRM_MTRR_WC);
-                drm->ttm.mtrr = -1;
-        }
+        arch_phys_wc_del(drm->ttm.mtrr);
+        drm->ttm.mtrr = 0;
 }
diff --git a/drivers/gpu/drm/nouveau/nv50_display.c b/drivers/gpu/drm/nouveau/nv50_display.c
index dd5e01f89f28..54dc6355b0c2 100644
--- a/drivers/gpu/drm/nouveau/nv50_display.c
+++ b/drivers/gpu/drm/nouveau/nv50_display.c
@@ -159,7 +159,7 @@ nv50_dmac_create_fbdma(struct nouveau_object *core, u32 parent)
                                         .flags = NV_DMA_TARGET_VRAM |
                                                  NV_DMA_ACCESS_RDWR,
                                         .start = 0,
-                                        .limit = pfb->ram.size - 1,
+                                        .limit = pfb->ram->size - 1,
                                         .conf0 = NV50_DMA_CONF0_ENABLE |
                                                  NV50_DMA_CONF0_PART_256,
                                      }, sizeof(struct nv_dma_class), &object);
@@ -172,7 +172,7 @@ nv50_dmac_create_fbdma(struct nouveau_object *core, u32 parent)
                                         .flags = NV_DMA_TARGET_VRAM |
                                                  NV_DMA_ACCESS_RDWR,
                                         .start = 0,
-                                        .limit = pfb->ram.size - 1,
+                                        .limit = pfb->ram->size - 1,
                                         .conf0 = NV50_DMA_CONF0_ENABLE | 0x70 |
                                                  NV50_DMA_CONF0_PART_256,
                                  }, sizeof(struct nv_dma_class), &object);
@@ -185,7 +185,7 @@ nv50_dmac_create_fbdma(struct nouveau_object *core, u32 parent)
                                         .flags = NV_DMA_TARGET_VRAM |
                                                  NV_DMA_ACCESS_RDWR,
                                         .start = 0,
-                                        .limit = pfb->ram.size - 1,
+                                        .limit = pfb->ram->size - 1,
                                         .conf0 = NV50_DMA_CONF0_ENABLE | 0x7a |
                                                  NV50_DMA_CONF0_PART_256,
                                  }, sizeof(struct nv_dma_class), &object);
@@ -204,7 +204,7 @@ nvc0_dmac_create_fbdma(struct nouveau_object *core, u32 parent)
                                         .flags = NV_DMA_TARGET_VRAM |
                                                  NV_DMA_ACCESS_RDWR,
                                         .start = 0,
-                                        .limit = pfb->ram.size - 1,
+                                        .limit = pfb->ram->size - 1,
                                         .conf0 = NVC0_DMA_CONF0_ENABLE,
                                      }, sizeof(struct nv_dma_class), &object);
         if (ret)
@@ -216,7 +216,7 @@ nvc0_dmac_create_fbdma(struct nouveau_object *core, u32 parent)
                                         .flags = NV_DMA_TARGET_VRAM |
                                                  NV_DMA_ACCESS_RDWR,
                                         .start = 0,
-                                        .limit = pfb->ram.size - 1,
+                                        .limit = pfb->ram->size - 1,
                                         .conf0 = NVC0_DMA_CONF0_ENABLE | 0xfe,
                                  }, sizeof(struct nv_dma_class), &object);
         if (ret)
@@ -228,7 +228,7 @@ nvc0_dmac_create_fbdma(struct nouveau_object *core, u32 parent)
                                         .flags = NV_DMA_TARGET_VRAM |
                                                  NV_DMA_ACCESS_RDWR,
                                         .start = 0,
-                                        .limit = pfb->ram.size - 1,
+                                        .limit = pfb->ram->size - 1,
                                         .conf0 = NVC0_DMA_CONF0_ENABLE | 0xfe,
                                  }, sizeof(struct nv_dma_class), &object);
         return ret;
@@ -246,7 +246,7 @@ nvd0_dmac_create_fbdma(struct nouveau_object *core, u32 parent)
                                         .flags = NV_DMA_TARGET_VRAM |
                                                  NV_DMA_ACCESS_RDWR,
                                         .start = 0,
-                                        .limit = pfb->ram.size - 1,
+                                        .limit = pfb->ram->size - 1,
                                         .conf0 = NVD0_DMA_CONF0_ENABLE |
                                                  NVD0_DMA_CONF0_PAGE_LP,
                                      }, sizeof(struct nv_dma_class), &object);
@@ -259,7 +259,7 @@ nvd0_dmac_create_fbdma(struct nouveau_object *core, u32 parent)
                                         .flags = NV_DMA_TARGET_VRAM |
                                                  NV_DMA_ACCESS_RDWR,
                                         .start = 0,
-                                        .limit = pfb->ram.size - 1,
+                                        .limit = pfb->ram->size - 1,
                                         .conf0 = NVD0_DMA_CONF0_ENABLE | 0xfe |
                                                  NVD0_DMA_CONF0_PAGE_LP,
                                  }, sizeof(struct nv_dma_class), &object);
@@ -316,7 +316,7 @@ nv50_dmac_create(struct nouveau_object *core, u32 bclass, u8 head,
                                         .flags = NV_DMA_TARGET_VRAM |
                                                  NV_DMA_ACCESS_RDWR,
                                         .start = 0,
-                                        .limit = pfb->ram.size - 1,
+                                        .limit = pfb->ram->size - 1,
                                  }, sizeof(struct nv_dma_class), &object);
         if (ret)
                 return ret;
diff --git a/drivers/gpu/drm/nouveau/nv50_pm.c b/drivers/gpu/drm/nouveau/nv50_pm.c
index 69620e39c90c..4efc33fa73fc 100644
--- a/drivers/gpu/drm/nouveau/nv50_pm.c
+++ b/drivers/gpu/drm/nouveau/nv50_pm.c
@@ -493,12 +493,12 @@ mclk_mrs(struct nouveau_mem_exec_func *exec, int mr, u32 data)
         struct hwsq_ucode *hwsq = &info->mclk_hwsq;
 
         if (mr <= 1) {
-                if (pfb->ram.ranks > 1)
+                if (pfb->ram->ranks > 1)
                         hwsq_wr32(hwsq, 0x1002c8 + ((mr - 0) * 4), data);
                 hwsq_wr32(hwsq, 0x1002c0 + ((mr - 0) * 4), data);
         } else
         if (mr <= 3) {
-                if (pfb->ram.ranks > 1)
+                if (pfb->ram->ranks > 1)
                         hwsq_wr32(hwsq, 0x1002e8 + ((mr - 2) * 4), data);
                 hwsq_wr32(hwsq, 0x1002e0 + ((mr - 2) * 4), data);
         }
diff --git a/drivers/gpu/drm/nouveau/nva3_pm.c b/drivers/gpu/drm/nouveau/nva3_pm.c
index 863f010fafeb..0d0ed597fea8 100644
--- a/drivers/gpu/drm/nouveau/nva3_pm.c
+++ b/drivers/gpu/drm/nouveau/nva3_pm.c
@@ -389,12 +389,12 @@ mclk_mrs(struct nouveau_mem_exec_func *exec, int mr, u32 data)
         struct nouveau_device *device = nouveau_dev(exec->dev);
         struct nouveau_fb *pfb = nouveau_fb(device);
         if (mr <= 1) {
-                if (pfb->ram.ranks > 1)
+                if (pfb->ram->ranks > 1)
                         nv_wr32(device, 0x1002c8 + ((mr - 0) * 4), data);
                 nv_wr32(device, 0x1002c0 + ((mr - 0) * 4), data);
         } else
         if (mr <= 3) {
-                if (pfb->ram.ranks > 1)
+                if (pfb->ram->ranks > 1)
                         nv_wr32(device, 0x1002e8 + ((mr - 2) * 4), data);
                 nv_wr32(device, 0x1002e0 + ((mr - 2) * 4), data);
         }
diff --git a/drivers/gpu/drm/nouveau/nvc0_pm.c b/drivers/gpu/drm/nouveau/nvc0_pm.c
index 0d34eb581179..3b7041cb013f 100644
--- a/drivers/gpu/drm/nouveau/nvc0_pm.c
+++ b/drivers/gpu/drm/nouveau/nvc0_pm.c
@@ -477,7 +477,7 @@ mclk_mrg(struct nouveau_mem_exec_func *exec, int mr)
 {
         struct nouveau_device *device = nouveau_dev(exec->dev);
         struct nouveau_fb *pfb = nouveau_fb(device);
-        if (pfb->ram.type != NV_MEM_TYPE_GDDR5) {
+        if (pfb->ram->type != NV_MEM_TYPE_GDDR5) {
                 if (mr <= 1)
                         return nv_rd32(device, 0x10f300 + ((mr - 0) * 4));
                 return nv_rd32(device, 0x10f320 + ((mr - 2) * 4));
@@ -496,15 +496,15 @@ mclk_mrs(struct nouveau_mem_exec_func *exec, int mr, u32 data)
 {
         struct nouveau_device *device = nouveau_dev(exec->dev);
         struct nouveau_fb *pfb = nouveau_fb(device);
-        if (pfb->ram.type != NV_MEM_TYPE_GDDR5) {
+        if (pfb->ram->type != NV_MEM_TYPE_GDDR5) {
                 if (mr <= 1) {
                         nv_wr32(device, 0x10f300 + ((mr - 0) * 4), data);
-                        if (pfb->ram.ranks > 1)
+                        if (pfb->ram->ranks > 1)
                                 nv_wr32(device, 0x10f308 + ((mr - 0) * 4), data);
                 } else
                 if (mr <= 3) {
                         nv_wr32(device, 0x10f320 + ((mr - 2) * 4), data);
-                        if (pfb->ram.ranks > 1)
+                        if (pfb->ram->ranks > 1)
                                 nv_wr32(device, 0x10f328 + ((mr - 2) * 4), data);
                 }
         } else {