diff options
Diffstat (limited to 'drivers/gpu/drm/nouveau')
24 files changed, 429 insertions, 241 deletions
diff --git a/drivers/gpu/drm/nouveau/Makefile b/drivers/gpu/drm/nouveau/Makefile index 7f0d807a0d0d..453df3f6053f 100644 --- a/drivers/gpu/drm/nouveau/Makefile +++ b/drivers/gpu/drm/nouveau/Makefile | |||
@@ -22,7 +22,7 @@ nouveau-y := nouveau_drv.o nouveau_state.o nouveau_channel.o nouveau_mem.o \ | |||
22 | nv50_cursor.o nv50_display.o nv50_fbcon.o \ | 22 | nv50_cursor.o nv50_display.o nv50_fbcon.o \ |
23 | nv04_dac.o nv04_dfp.o nv04_tv.o nv17_tv.o nv17_tv_modes.o \ | 23 | nv04_dac.o nv04_dfp.o nv04_tv.o nv17_tv.o nv17_tv_modes.o \ |
24 | nv04_crtc.o nv04_display.o nv04_cursor.o nv04_fbcon.o \ | 24 | nv04_crtc.o nv04_display.o nv04_cursor.o nv04_fbcon.o \ |
25 | nv17_gpio.o | 25 | nv17_gpio.o nv50_gpio.o |
26 | 26 | ||
27 | nouveau-$(CONFIG_DRM_NOUVEAU_DEBUG) += nouveau_debugfs.o | 27 | nouveau-$(CONFIG_DRM_NOUVEAU_DEBUG) += nouveau_debugfs.o |
28 | nouveau-$(CONFIG_COMPAT) += nouveau_ioc32.o | 28 | nouveau-$(CONFIG_COMPAT) += nouveau_ioc32.o |
diff --git a/drivers/gpu/drm/nouveau/nouveau_bios.c b/drivers/gpu/drm/nouveau/nouveau_bios.c index b5a9336a2e88..abc382a9918b 100644 --- a/drivers/gpu/drm/nouveau/nouveau_bios.c +++ b/drivers/gpu/drm/nouveau/nouveau_bios.c | |||
@@ -2573,48 +2573,34 @@ init_gpio(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) | |||
2573 | * each GPIO according to various values listed in each entry | 2573 | * each GPIO according to various values listed in each entry |
2574 | */ | 2574 | */ |
2575 | 2575 | ||
2576 | const uint32_t nv50_gpio_reg[4] = { 0xe104, 0xe108, 0xe280, 0xe284 }; | 2576 | struct drm_nouveau_private *dev_priv = bios->dev->dev_private; |
2577 | const uint32_t nv50_gpio_ctl[2] = { 0xe100, 0xe28c }; | 2577 | const uint32_t nv50_gpio_ctl[2] = { 0xe100, 0xe28c }; |
2578 | const uint8_t *gpio_table = &bios->data[bios->dcb.gpio_table_ptr]; | ||
2579 | const uint8_t *gpio_entry; | ||
2580 | int i; | 2578 | int i; |
2581 | 2579 | ||
2582 | if (!iexec->execute) | 2580 | if (dev_priv->card_type != NV_50) { |
2583 | return 1; | 2581 | NV_ERROR(bios->dev, "INIT_GPIO on unsupported chipset\n"); |
2584 | 2582 | return -ENODEV; | |
2585 | if (bios->dcb.version != 0x40) { | ||
2586 | NV_ERROR(bios->dev, "DCB table not version 4.0\n"); | ||
2587 | return 0; | ||
2588 | } | ||
2589 | |||
2590 | if (!bios->dcb.gpio_table_ptr) { | ||
2591 | NV_WARN(bios->dev, "Invalid pointer to INIT_8E table\n"); | ||
2592 | return 0; | ||
2593 | } | 2583 | } |
2594 | 2584 | ||
2595 | gpio_entry = gpio_table + gpio_table[1]; | 2585 | if (!iexec->execute) |
2596 | for (i = 0; i < gpio_table[2]; i++, gpio_entry += gpio_table[3]) { | 2586 | return 1; |
2597 | uint32_t entry = ROM32(gpio_entry[0]), r, s, v; | ||
2598 | int line = (entry & 0x0000001f); | ||
2599 | 2587 | ||
2600 | BIOSLOG(bios, "0x%04X: Entry: 0x%08X\n", offset, entry); | 2588 | for (i = 0; i < bios->dcb.gpio.entries; i++) { |
2589 | struct dcb_gpio_entry *gpio = &bios->dcb.gpio.entry[i]; | ||
2590 | uint32_t r, s, v; | ||
2601 | 2591 | ||
2602 | if ((entry & 0x0000ff00) == 0x0000ff00) | 2592 | BIOSLOG(bios, "0x%04X: Entry: 0x%08X\n", offset, gpio->entry); |
2603 | continue; | ||
2604 | 2593 | ||
2605 | r = nv50_gpio_reg[line >> 3]; | 2594 | nv50_gpio_set(bios->dev, gpio->tag, gpio->state_default); |
2606 | s = (line & 0x07) << 2; | ||
2607 | v = bios_rd32(bios, r) & ~(0x00000003 << s); | ||
2608 | if (entry & 0x01000000) | ||
2609 | v |= (((entry & 0x60000000) >> 29) ^ 2) << s; | ||
2610 | else | ||
2611 | v |= (((entry & 0x18000000) >> 27) ^ 2) << s; | ||
2612 | bios_wr32(bios, r, v); | ||
2613 | 2595 | ||
2614 | r = nv50_gpio_ctl[line >> 4]; | 2596 | /* The NVIDIA binary driver doesn't appear to actually do |
2615 | s = (line & 0x0f); | 2597 | * any of this, my VBIOS does however. |
2598 | */ | ||
2599 | /* Not a clue, needs de-magicing */ | ||
2600 | r = nv50_gpio_ctl[gpio->line >> 4]; | ||
2601 | s = (gpio->line & 0x0f); | ||
2616 | v = bios_rd32(bios, r) & ~(0x00010001 << s); | 2602 | v = bios_rd32(bios, r) & ~(0x00010001 << s); |
2617 | switch ((entry & 0x06000000) >> 25) { | 2603 | switch ((gpio->entry & 0x06000000) >> 25) { |
2618 | case 1: | 2604 | case 1: |
2619 | v |= (0x00000001 << s); | 2605 | v |= (0x00000001 << s); |
2620 | break; | 2606 | break; |
@@ -3198,7 +3184,6 @@ static int run_lvds_table(struct drm_device *dev, struct dcb_entry *dcbent, int | |||
3198 | struct nvbios *bios = &dev_priv->vbios; | 3184 | struct nvbios *bios = &dev_priv->vbios; |
3199 | unsigned int outputset = (dcbent->or == 4) ? 1 : 0; | 3185 | unsigned int outputset = (dcbent->or == 4) ? 1 : 0; |
3200 | uint16_t scriptptr = 0, clktable; | 3186 | uint16_t scriptptr = 0, clktable; |
3201 | uint8_t clktableptr = 0; | ||
3202 | 3187 | ||
3203 | /* | 3188 | /* |
3204 | * For now we assume version 3.0 table - g80 support will need some | 3189 | * For now we assume version 3.0 table - g80 support will need some |
@@ -3217,26 +3202,29 @@ static int run_lvds_table(struct drm_device *dev, struct dcb_entry *dcbent, int | |||
3217 | scriptptr = ROM16(bios->data[bios->fp.lvdsmanufacturerpointer + 11 + outputset * 2]); | 3202 | scriptptr = ROM16(bios->data[bios->fp.lvdsmanufacturerpointer + 11 + outputset * 2]); |
3218 | break; | 3203 | break; |
3219 | case LVDS_RESET: | 3204 | case LVDS_RESET: |
3205 | clktable = bios->fp.lvdsmanufacturerpointer + 15; | ||
3206 | if (dcbent->or == 4) | ||
3207 | clktable += 8; | ||
3208 | |||
3220 | if (dcbent->lvdsconf.use_straps_for_mode) { | 3209 | if (dcbent->lvdsconf.use_straps_for_mode) { |
3221 | if (bios->fp.dual_link) | 3210 | if (bios->fp.dual_link) |
3222 | clktableptr += 2; | 3211 | clktable += 4; |
3223 | if (bios->fp.BITbit1) | 3212 | if (bios->fp.if_is_24bit) |
3224 | clktableptr++; | 3213 | clktable += 2; |
3225 | } else { | 3214 | } else { |
3226 | /* using EDID */ | 3215 | /* using EDID */ |
3227 | uint8_t fallback = bios->data[bios->fp.lvdsmanufacturerpointer + 4]; | 3216 | int cmpval_24bit = (dcbent->or == 4) ? 4 : 1; |
3228 | int fallbackcmpval = (dcbent->or == 4) ? 4 : 1; | ||
3229 | 3217 | ||
3230 | if (bios->fp.dual_link) { | 3218 | if (bios->fp.dual_link) { |
3231 | clktableptr += 2; | 3219 | clktable += 4; |
3232 | fallbackcmpval *= 2; | 3220 | cmpval_24bit <<= 1; |
3233 | } | 3221 | } |
3234 | if (fallbackcmpval & fallback) | 3222 | |
3235 | clktableptr++; | 3223 | if (bios->fp.strapless_is_24bit & cmpval_24bit) |
3224 | clktable += 2; | ||
3236 | } | 3225 | } |
3237 | 3226 | ||
3238 | /* adding outputset * 8 may not be correct */ | 3227 | clktable = ROM16(bios->data[clktable]); |
3239 | clktable = ROM16(bios->data[bios->fp.lvdsmanufacturerpointer + 15 + clktableptr * 2 + outputset * 8]); | ||
3240 | if (!clktable) { | 3228 | if (!clktable) { |
3241 | NV_ERROR(dev, "Pixel clock comparison table not found\n"); | 3229 | NV_ERROR(dev, "Pixel clock comparison table not found\n"); |
3242 | return -ENOENT; | 3230 | return -ENOENT; |
@@ -3638,37 +3626,40 @@ int nouveau_bios_parse_lvds_table(struct drm_device *dev, int pxclk, bool *dl, b | |||
3638 | *if_is_24bit = bios->data[lvdsofs] & 16; | 3626 | *if_is_24bit = bios->data[lvdsofs] & 16; |
3639 | break; | 3627 | break; |
3640 | case 0x30: | 3628 | case 0x30: |
3641 | /* | 3629 | case 0x40: |
3642 | * My money would be on there being a 24 bit interface bit in | ||
3643 | * this table, but I have no example of a laptop bios with a | ||
3644 | * 24 bit panel to confirm that. Hence we shout loudly if any | ||
3645 | * bit other than bit 0 is set (I've not even seen bit 1) | ||
3646 | */ | ||
3647 | if (bios->data[lvdsofs] > 1) | ||
3648 | NV_ERROR(dev, | ||
3649 | "You have a very unusual laptop display; please report it\n"); | ||
3650 | /* | 3630 | /* |
3651 | * No sign of the "power off for reset" or "reset for panel | 3631 | * No sign of the "power off for reset" or "reset for panel |
3652 | * on" bits, but it's safer to assume we should | 3632 | * on" bits, but it's safer to assume we should |
3653 | */ | 3633 | */ |
3654 | bios->fp.power_off_for_reset = true; | 3634 | bios->fp.power_off_for_reset = true; |
3655 | bios->fp.reset_after_pclk_change = true; | 3635 | bios->fp.reset_after_pclk_change = true; |
3636 | |||
3656 | /* | 3637 | /* |
3657 | * It's ok lvdsofs is wrong for nv4x edid case; dual_link is | 3638 | * It's ok lvdsofs is wrong for nv4x edid case; dual_link is |
3658 | * over-written, and BITbit1 isn't used | 3639 | * over-written, and if_is_24bit isn't used |
3659 | */ | 3640 | */ |
3660 | bios->fp.dual_link = bios->data[lvdsofs] & 1; | 3641 | bios->fp.dual_link = bios->data[lvdsofs] & 1; |
3661 | bios->fp.BITbit1 = bios->data[lvdsofs] & 2; | ||
3662 | bios->fp.duallink_transition_clk = ROM16(bios->data[bios->fp.lvdsmanufacturerpointer + 5]) * 10; | ||
3663 | break; | ||
3664 | case 0x40: | ||
3665 | bios->fp.dual_link = bios->data[lvdsofs] & 1; | ||
3666 | bios->fp.if_is_24bit = bios->data[lvdsofs] & 2; | 3642 | bios->fp.if_is_24bit = bios->data[lvdsofs] & 2; |
3667 | bios->fp.strapless_is_24bit = bios->data[bios->fp.lvdsmanufacturerpointer + 4]; | 3643 | bios->fp.strapless_is_24bit = bios->data[bios->fp.lvdsmanufacturerpointer + 4]; |
3668 | bios->fp.duallink_transition_clk = ROM16(bios->data[bios->fp.lvdsmanufacturerpointer + 5]) * 10; | 3644 | bios->fp.duallink_transition_clk = ROM16(bios->data[bios->fp.lvdsmanufacturerpointer + 5]) * 10; |
3669 | break; | 3645 | break; |
3670 | } | 3646 | } |
3671 | 3647 | ||
3648 | /* Dell Latitude D620 reports a too-high value for the dual-link | ||
3649 | * transition freq, causing us to program the panel incorrectly. | ||
3650 | * | ||
3651 | * It doesn't appear the VBIOS actually uses its transition freq | ||
3652 | * (90000kHz), instead it uses the "Number of LVDS channels" field | ||
3653 | * out of the panel ID structure (http://www.spwg.org/). | ||
3654 | * | ||
3655 | * For the moment, a quirk will do :) | ||
3656 | */ | ||
3657 | if ((dev->pdev->device == 0x01d7) && | ||
3658 | (dev->pdev->subsystem_vendor == 0x1028) && | ||
3659 | (dev->pdev->subsystem_device == 0x01c2)) { | ||
3660 | bios->fp.duallink_transition_clk = 80000; | ||
3661 | } | ||
3662 | |||
3672 | /* set dual_link flag for EDID case */ | 3663 | /* set dual_link flag for EDID case */ |
3673 | if (pxclk && (chip_version < 0x25 || chip_version > 0x28)) | 3664 | if (pxclk && (chip_version < 0x25 || chip_version > 0x28)) |
3674 | bios->fp.dual_link = (pxclk >= bios->fp.duallink_transition_clk); | 3665 | bios->fp.dual_link = (pxclk >= bios->fp.duallink_transition_clk); |
@@ -5077,25 +5068,25 @@ parse_dcb30_gpio_entry(struct nvbios *bios, uint16_t offset) | |||
5077 | gpio->tag = tag; | 5068 | gpio->tag = tag; |
5078 | gpio->line = line; | 5069 | gpio->line = line; |
5079 | gpio->invert = flags != 4; | 5070 | gpio->invert = flags != 4; |
5071 | gpio->entry = ent; | ||
5080 | } | 5072 | } |
5081 | 5073 | ||
5082 | static void | 5074 | static void |
5083 | parse_dcb40_gpio_entry(struct nvbios *bios, uint16_t offset) | 5075 | parse_dcb40_gpio_entry(struct nvbios *bios, uint16_t offset) |
5084 | { | 5076 | { |
5077 | uint32_t entry = ROM32(bios->data[offset]); | ||
5085 | struct dcb_gpio_entry *gpio; | 5078 | struct dcb_gpio_entry *gpio; |
5086 | uint32_t ent = ROM32(bios->data[offset]); | ||
5087 | uint8_t line = ent & 0x1f, | ||
5088 | tag = ent >> 8 & 0xff; | ||
5089 | 5079 | ||
5090 | if (tag == 0xff) | 5080 | if ((entry & 0x0000ff00) == 0x0000ff00) |
5091 | return; | 5081 | return; |
5092 | 5082 | ||
5093 | gpio = new_gpio_entry(bios); | 5083 | gpio = new_gpio_entry(bios); |
5094 | 5084 | gpio->tag = (entry & 0x0000ff00) >> 8; | |
5095 | /* Currently unused, we may need more fields parsed at some | 5085 | gpio->line = (entry & 0x0000001f) >> 0; |
5096 | * point. */ | 5086 | gpio->state_default = (entry & 0x01000000) >> 24; |
5097 | gpio->tag = tag; | 5087 | gpio->state[0] = (entry & 0x18000000) >> 27; |
5098 | gpio->line = line; | 5088 | gpio->state[1] = (entry & 0x60000000) >> 29; |
5089 | gpio->entry = entry; | ||
5099 | } | 5090 | } |
5100 | 5091 | ||
5101 | static void | 5092 | static void |
diff --git a/drivers/gpu/drm/nouveau/nouveau_bios.h b/drivers/gpu/drm/nouveau/nouveau_bios.h index 4f88e6924d27..c0d7b0a3ece0 100644 --- a/drivers/gpu/drm/nouveau/nouveau_bios.h +++ b/drivers/gpu/drm/nouveau/nouveau_bios.h | |||
@@ -49,6 +49,9 @@ struct dcb_gpio_entry { | |||
49 | enum dcb_gpio_tag tag; | 49 | enum dcb_gpio_tag tag; |
50 | int line; | 50 | int line; |
51 | bool invert; | 51 | bool invert; |
52 | uint32_t entry; | ||
53 | uint8_t state_default; | ||
54 | uint8_t state[2]; | ||
52 | }; | 55 | }; |
53 | 56 | ||
54 | struct dcb_gpio_table { | 57 | struct dcb_gpio_table { |
@@ -267,7 +270,6 @@ struct nvbios { | |||
267 | bool reset_after_pclk_change; | 270 | bool reset_after_pclk_change; |
268 | bool dual_link; | 271 | bool dual_link; |
269 | bool link_c_increment; | 272 | bool link_c_increment; |
270 | bool BITbit1; | ||
271 | bool if_is_24bit; | 273 | bool if_is_24bit; |
272 | int duallink_transition_clk; | 274 | int duallink_transition_clk; |
273 | uint8_t strapless_is_24bit; | 275 | uint8_t strapless_is_24bit; |
diff --git a/drivers/gpu/drm/nouveau/nouveau_bo.c b/drivers/gpu/drm/nouveau/nouveau_bo.c index 9042dd7fb058..957d17629840 100644 --- a/drivers/gpu/drm/nouveau/nouveau_bo.c +++ b/drivers/gpu/drm/nouveau/nouveau_bo.c | |||
@@ -72,7 +72,7 @@ nouveau_bo_fixup_align(struct drm_device *dev, | |||
72 | * many small buffers. | 72 | * many small buffers. |
73 | */ | 73 | */ |
74 | if (dev_priv->card_type == NV_50) { | 74 | if (dev_priv->card_type == NV_50) { |
75 | uint32_t block_size = nouveau_mem_fb_amount(dev) >> 15; | 75 | uint32_t block_size = dev_priv->vram_size >> 15; |
76 | int i; | 76 | int i; |
77 | 77 | ||
78 | switch (tile_flags) { | 78 | switch (tile_flags) { |
@@ -154,7 +154,7 @@ nouveau_bo_new(struct drm_device *dev, struct nouveau_channel *chan, | |||
154 | 154 | ||
155 | nvbo->placement.fpfn = 0; | 155 | nvbo->placement.fpfn = 0; |
156 | nvbo->placement.lpfn = mappable ? dev_priv->fb_mappable_pages : 0; | 156 | nvbo->placement.lpfn = mappable ? dev_priv->fb_mappable_pages : 0; |
157 | nouveau_bo_placement_set(nvbo, flags); | 157 | nouveau_bo_placement_set(nvbo, flags, 0); |
158 | 158 | ||
159 | nvbo->channel = chan; | 159 | nvbo->channel = chan; |
160 | ret = ttm_bo_init(&dev_priv->ttm.bdev, &nvbo->bo, size, | 160 | ret = ttm_bo_init(&dev_priv->ttm.bdev, &nvbo->bo, size, |
@@ -173,26 +173,33 @@ nouveau_bo_new(struct drm_device *dev, struct nouveau_channel *chan, | |||
173 | return 0; | 173 | return 0; |
174 | } | 174 | } |
175 | 175 | ||
176 | static void | ||
177 | set_placement_list(uint32_t *pl, unsigned *n, uint32_t type, uint32_t flags) | ||
178 | { | ||
179 | *n = 0; | ||
180 | |||
181 | if (type & TTM_PL_FLAG_VRAM) | ||
182 | pl[(*n)++] = TTM_PL_FLAG_VRAM | flags; | ||
183 | if (type & TTM_PL_FLAG_TT) | ||
184 | pl[(*n)++] = TTM_PL_FLAG_TT | flags; | ||
185 | if (type & TTM_PL_FLAG_SYSTEM) | ||
186 | pl[(*n)++] = TTM_PL_FLAG_SYSTEM | flags; | ||
187 | } | ||
188 | |||
176 | void | 189 | void |
177 | nouveau_bo_placement_set(struct nouveau_bo *nvbo, uint32_t memtype) | 190 | nouveau_bo_placement_set(struct nouveau_bo *nvbo, uint32_t type, uint32_t busy) |
178 | { | 191 | { |
179 | int n = 0; | 192 | struct ttm_placement *pl = &nvbo->placement; |
180 | 193 | uint32_t flags = TTM_PL_MASK_CACHING | | |
181 | if (memtype & TTM_PL_FLAG_VRAM) | 194 | (nvbo->pin_refcnt ? TTM_PL_FLAG_NO_EVICT : 0); |
182 | nvbo->placements[n++] = TTM_PL_FLAG_VRAM | TTM_PL_MASK_CACHING; | 195 | |
183 | if (memtype & TTM_PL_FLAG_TT) | 196 | pl->placement = nvbo->placements; |
184 | nvbo->placements[n++] = TTM_PL_FLAG_TT | TTM_PL_MASK_CACHING; | 197 | set_placement_list(nvbo->placements, &pl->num_placement, |
185 | if (memtype & TTM_PL_FLAG_SYSTEM) | 198 | type, flags); |
186 | nvbo->placements[n++] = TTM_PL_FLAG_SYSTEM | TTM_PL_MASK_CACHING; | 199 | |
187 | nvbo->placement.placement = nvbo->placements; | 200 | pl->busy_placement = nvbo->busy_placements; |
188 | nvbo->placement.busy_placement = nvbo->placements; | 201 | set_placement_list(nvbo->busy_placements, &pl->num_busy_placement, |
189 | nvbo->placement.num_placement = n; | 202 | type | busy, flags); |
190 | nvbo->placement.num_busy_placement = n; | ||
191 | |||
192 | if (nvbo->pin_refcnt) { | ||
193 | while (n--) | ||
194 | nvbo->placements[n] |= TTM_PL_FLAG_NO_EVICT; | ||
195 | } | ||
196 | } | 203 | } |
197 | 204 | ||
198 | int | 205 | int |
@@ -200,7 +207,7 @@ nouveau_bo_pin(struct nouveau_bo *nvbo, uint32_t memtype) | |||
200 | { | 207 | { |
201 | struct drm_nouveau_private *dev_priv = nouveau_bdev(nvbo->bo.bdev); | 208 | struct drm_nouveau_private *dev_priv = nouveau_bdev(nvbo->bo.bdev); |
202 | struct ttm_buffer_object *bo = &nvbo->bo; | 209 | struct ttm_buffer_object *bo = &nvbo->bo; |
203 | int ret, i; | 210 | int ret; |
204 | 211 | ||
205 | if (nvbo->pin_refcnt && !(memtype & (1 << bo->mem.mem_type))) { | 212 | if (nvbo->pin_refcnt && !(memtype & (1 << bo->mem.mem_type))) { |
206 | NV_ERROR(nouveau_bdev(bo->bdev)->dev, | 213 | NV_ERROR(nouveau_bdev(bo->bdev)->dev, |
@@ -216,9 +223,7 @@ nouveau_bo_pin(struct nouveau_bo *nvbo, uint32_t memtype) | |||
216 | if (ret) | 223 | if (ret) |
217 | goto out; | 224 | goto out; |
218 | 225 | ||
219 | nouveau_bo_placement_set(nvbo, memtype); | 226 | nouveau_bo_placement_set(nvbo, memtype, 0); |
220 | for (i = 0; i < nvbo->placement.num_placement; i++) | ||
221 | nvbo->placements[i] |= TTM_PL_FLAG_NO_EVICT; | ||
222 | 227 | ||
223 | ret = ttm_bo_validate(bo, &nvbo->placement, false, false); | 228 | ret = ttm_bo_validate(bo, &nvbo->placement, false, false); |
224 | if (ret == 0) { | 229 | if (ret == 0) { |
@@ -245,7 +250,7 @@ nouveau_bo_unpin(struct nouveau_bo *nvbo) | |||
245 | { | 250 | { |
246 | struct drm_nouveau_private *dev_priv = nouveau_bdev(nvbo->bo.bdev); | 251 | struct drm_nouveau_private *dev_priv = nouveau_bdev(nvbo->bo.bdev); |
247 | struct ttm_buffer_object *bo = &nvbo->bo; | 252 | struct ttm_buffer_object *bo = &nvbo->bo; |
248 | int ret, i; | 253 | int ret; |
249 | 254 | ||
250 | if (--nvbo->pin_refcnt) | 255 | if (--nvbo->pin_refcnt) |
251 | return 0; | 256 | return 0; |
@@ -254,8 +259,7 @@ nouveau_bo_unpin(struct nouveau_bo *nvbo) | |||
254 | if (ret) | 259 | if (ret) |
255 | return ret; | 260 | return ret; |
256 | 261 | ||
257 | for (i = 0; i < nvbo->placement.num_placement; i++) | 262 | nouveau_bo_placement_set(nvbo, bo->mem.placement, 0); |
258 | nvbo->placements[i] &= ~TTM_PL_FLAG_NO_EVICT; | ||
259 | 263 | ||
260 | ret = ttm_bo_validate(bo, &nvbo->placement, false, false); | 264 | ret = ttm_bo_validate(bo, &nvbo->placement, false, false); |
261 | if (ret == 0) { | 265 | if (ret == 0) { |
@@ -396,8 +400,8 @@ nouveau_bo_init_mem_type(struct ttm_bo_device *bdev, uint32_t type, | |||
396 | man->io_addr = NULL; | 400 | man->io_addr = NULL; |
397 | man->io_offset = drm_get_resource_start(dev, 1); | 401 | man->io_offset = drm_get_resource_start(dev, 1); |
398 | man->io_size = drm_get_resource_len(dev, 1); | 402 | man->io_size = drm_get_resource_len(dev, 1); |
399 | if (man->io_size > nouveau_mem_fb_amount(dev)) | 403 | if (man->io_size > dev_priv->vram_size) |
400 | man->io_size = nouveau_mem_fb_amount(dev); | 404 | man->io_size = dev_priv->vram_size; |
401 | 405 | ||
402 | man->gpu_offset = dev_priv->vm_vram_base; | 406 | man->gpu_offset = dev_priv->vm_vram_base; |
403 | break; | 407 | break; |
@@ -440,10 +444,11 @@ nouveau_bo_evict_flags(struct ttm_buffer_object *bo, struct ttm_placement *pl) | |||
440 | 444 | ||
441 | switch (bo->mem.mem_type) { | 445 | switch (bo->mem.mem_type) { |
442 | case TTM_PL_VRAM: | 446 | case TTM_PL_VRAM: |
443 | nouveau_bo_placement_set(nvbo, TTM_PL_FLAG_TT); | 447 | nouveau_bo_placement_set(nvbo, TTM_PL_FLAG_TT, |
448 | TTM_PL_FLAG_SYSTEM); | ||
444 | break; | 449 | break; |
445 | default: | 450 | default: |
446 | nouveau_bo_placement_set(nvbo, TTM_PL_FLAG_SYSTEM); | 451 | nouveau_bo_placement_set(nvbo, TTM_PL_FLAG_SYSTEM, 0); |
447 | break; | 452 | break; |
448 | } | 453 | } |
449 | 454 | ||
diff --git a/drivers/gpu/drm/nouveau/nouveau_channel.c b/drivers/gpu/drm/nouveau/nouveau_channel.c index 6dfb425cbae9..1fc57ef58295 100644 --- a/drivers/gpu/drm/nouveau/nouveau_channel.c +++ b/drivers/gpu/drm/nouveau/nouveau_channel.c | |||
@@ -142,7 +142,6 @@ nouveau_channel_alloc(struct drm_device *dev, struct nouveau_channel **chan_ret, | |||
142 | GFP_KERNEL); | 142 | GFP_KERNEL); |
143 | if (!dev_priv->fifos[channel]) | 143 | if (!dev_priv->fifos[channel]) |
144 | return -ENOMEM; | 144 | return -ENOMEM; |
145 | dev_priv->fifo_alloc_count++; | ||
146 | chan = dev_priv->fifos[channel]; | 145 | chan = dev_priv->fifos[channel]; |
147 | INIT_LIST_HEAD(&chan->nvsw.vbl_wait); | 146 | INIT_LIST_HEAD(&chan->nvsw.vbl_wait); |
148 | INIT_LIST_HEAD(&chan->fence.pending); | 147 | INIT_LIST_HEAD(&chan->fence.pending); |
@@ -321,7 +320,6 @@ nouveau_channel_free(struct nouveau_channel *chan) | |||
321 | iounmap(chan->user); | 320 | iounmap(chan->user); |
322 | 321 | ||
323 | dev_priv->fifos[chan->id] = NULL; | 322 | dev_priv->fifos[chan->id] = NULL; |
324 | dev_priv->fifo_alloc_count--; | ||
325 | kfree(chan); | 323 | kfree(chan); |
326 | } | 324 | } |
327 | 325 | ||
diff --git a/drivers/gpu/drm/nouveau/nouveau_debugfs.c b/drivers/gpu/drm/nouveau/nouveau_debugfs.c index 8ff9ef5d4b47..a251886a0ce6 100644 --- a/drivers/gpu/drm/nouveau/nouveau_debugfs.c +++ b/drivers/gpu/drm/nouveau/nouveau_debugfs.c | |||
@@ -137,10 +137,9 @@ nouveau_debugfs_memory_info(struct seq_file *m, void *data) | |||
137 | { | 137 | { |
138 | struct drm_info_node *node = (struct drm_info_node *) m->private; | 138 | struct drm_info_node *node = (struct drm_info_node *) m->private; |
139 | struct drm_minor *minor = node->minor; | 139 | struct drm_minor *minor = node->minor; |
140 | struct drm_device *dev = minor->dev; | 140 | struct drm_nouveau_private *dev_priv = minor->dev->dev_private; |
141 | 141 | ||
142 | seq_printf(m, "VRAM total: %dKiB\n", | 142 | seq_printf(m, "VRAM total: %dKiB\n", (int)(dev_priv->vram_size >> 10)); |
143 | (int)(nouveau_mem_fb_amount(dev) >> 10)); | ||
144 | return 0; | 143 | return 0; |
145 | } | 144 | } |
146 | 145 | ||
diff --git a/drivers/gpu/drm/nouveau/nouveau_dp.c b/drivers/gpu/drm/nouveau/nouveau_dp.c index f954ad93e81f..deeb21c6865c 100644 --- a/drivers/gpu/drm/nouveau/nouveau_dp.c +++ b/drivers/gpu/drm/nouveau/nouveau_dp.c | |||
@@ -483,7 +483,7 @@ nouveau_dp_auxch(struct nouveau_i2c_chan *auxch, int cmd, int addr, | |||
483 | ctrl |= (cmd << NV50_AUXCH_CTRL_CMD_SHIFT); | 483 | ctrl |= (cmd << NV50_AUXCH_CTRL_CMD_SHIFT); |
484 | ctrl |= ((data_nr - 1) << NV50_AUXCH_CTRL_LEN_SHIFT); | 484 | ctrl |= ((data_nr - 1) << NV50_AUXCH_CTRL_LEN_SHIFT); |
485 | 485 | ||
486 | for (;;) { | 486 | for (i = 0; i < 16; i++) { |
487 | nv_wr32(dev, NV50_AUXCH_CTRL(index), ctrl | 0x80000000); | 487 | nv_wr32(dev, NV50_AUXCH_CTRL(index), ctrl | 0x80000000); |
488 | nv_wr32(dev, NV50_AUXCH_CTRL(index), ctrl); | 488 | nv_wr32(dev, NV50_AUXCH_CTRL(index), ctrl); |
489 | nv_wr32(dev, NV50_AUXCH_CTRL(index), ctrl | 0x00010000); | 489 | nv_wr32(dev, NV50_AUXCH_CTRL(index), ctrl | 0x00010000); |
@@ -502,6 +502,12 @@ nouveau_dp_auxch(struct nouveau_i2c_chan *auxch, int cmd, int addr, | |||
502 | break; | 502 | break; |
503 | } | 503 | } |
504 | 504 | ||
505 | if (i == 16) { | ||
506 | NV_ERROR(dev, "auxch DEFER too many times, bailing\n"); | ||
507 | ret = -EREMOTEIO; | ||
508 | goto out; | ||
509 | } | ||
510 | |||
505 | if (cmd & 1) { | 511 | if (cmd & 1) { |
506 | if ((stat & NV50_AUXCH_STAT_COUNT) != data_nr) { | 512 | if ((stat & NV50_AUXCH_STAT_COUNT) != data_nr) { |
507 | ret = -EREMOTEIO; | 513 | ret = -EREMOTEIO; |
diff --git a/drivers/gpu/drm/nouveau/nouveau_drv.h b/drivers/gpu/drm/nouveau/nouveau_drv.h index d8b559011777..ace630aa89e1 100644 --- a/drivers/gpu/drm/nouveau/nouveau_drv.h +++ b/drivers/gpu/drm/nouveau/nouveau_drv.h | |||
@@ -76,6 +76,7 @@ struct nouveau_bo { | |||
76 | struct ttm_buffer_object bo; | 76 | struct ttm_buffer_object bo; |
77 | struct ttm_placement placement; | 77 | struct ttm_placement placement; |
78 | u32 placements[3]; | 78 | u32 placements[3]; |
79 | u32 busy_placements[3]; | ||
79 | struct ttm_bo_kmap_obj kmap; | 80 | struct ttm_bo_kmap_obj kmap; |
80 | struct list_head head; | 81 | struct list_head head; |
81 | 82 | ||
@@ -519,6 +520,7 @@ struct drm_nouveau_private { | |||
519 | 520 | ||
520 | struct workqueue_struct *wq; | 521 | struct workqueue_struct *wq; |
521 | struct work_struct irq_work; | 522 | struct work_struct irq_work; |
523 | struct work_struct hpd_work; | ||
522 | 524 | ||
523 | struct list_head vbl_waiting; | 525 | struct list_head vbl_waiting; |
524 | 526 | ||
@@ -533,7 +535,6 @@ struct drm_nouveau_private { | |||
533 | 535 | ||
534 | struct fb_info *fbdev_info; | 536 | struct fb_info *fbdev_info; |
535 | 537 | ||
536 | int fifo_alloc_count; | ||
537 | struct nouveau_channel *fifos[NOUVEAU_MAX_CHANNEL_NR]; | 538 | struct nouveau_channel *fifos[NOUVEAU_MAX_CHANNEL_NR]; |
538 | 539 | ||
539 | struct nouveau_engine engine; | 540 | struct nouveau_engine engine; |
@@ -553,12 +554,6 @@ struct drm_nouveau_private { | |||
553 | uint32_t ramro_offset; | 554 | uint32_t ramro_offset; |
554 | uint32_t ramro_size; | 555 | uint32_t ramro_size; |
555 | 556 | ||
556 | /* base physical addresses */ | ||
557 | uint64_t fb_phys; | ||
558 | uint64_t fb_available_size; | ||
559 | uint64_t fb_mappable_pages; | ||
560 | uint64_t fb_aper_free; | ||
561 | |||
562 | struct { | 557 | struct { |
563 | enum { | 558 | enum { |
564 | NOUVEAU_GART_NONE = 0, | 559 | NOUVEAU_GART_NONE = 0, |
@@ -572,10 +567,6 @@ struct drm_nouveau_private { | |||
572 | struct nouveau_gpuobj *sg_ctxdma; | 567 | struct nouveau_gpuobj *sg_ctxdma; |
573 | struct page *sg_dummy_page; | 568 | struct page *sg_dummy_page; |
574 | dma_addr_t sg_dummy_bus; | 569 | dma_addr_t sg_dummy_bus; |
575 | |||
576 | /* nottm hack */ | ||
577 | struct drm_ttm_backend *sg_be; | ||
578 | unsigned long sg_handle; | ||
579 | } gart_info; | 570 | } gart_info; |
580 | 571 | ||
581 | /* nv10-nv40 tiling regions */ | 572 | /* nv10-nv40 tiling regions */ |
@@ -584,6 +575,16 @@ struct drm_nouveau_private { | |||
584 | spinlock_t lock; | 575 | spinlock_t lock; |
585 | } tile; | 576 | } tile; |
586 | 577 | ||
578 | /* VRAM/fb configuration */ | ||
579 | uint64_t vram_size; | ||
580 | uint64_t vram_sys_base; | ||
581 | |||
582 | uint64_t fb_phys; | ||
583 | uint64_t fb_available_size; | ||
584 | uint64_t fb_mappable_pages; | ||
585 | uint64_t fb_aper_free; | ||
586 | int fb_mtrr; | ||
587 | |||
587 | /* G8x/G9x virtual address space */ | 588 | /* G8x/G9x virtual address space */ |
588 | uint64_t vm_gart_base; | 589 | uint64_t vm_gart_base; |
589 | uint64_t vm_gart_size; | 590 | uint64_t vm_gart_size; |
@@ -592,10 +593,6 @@ struct drm_nouveau_private { | |||
592 | uint64_t vm_end; | 593 | uint64_t vm_end; |
593 | struct nouveau_gpuobj *vm_vram_pt[NV50_VM_VRAM_NR]; | 594 | struct nouveau_gpuobj *vm_vram_pt[NV50_VM_VRAM_NR]; |
594 | int vm_vram_pt_nr; | 595 | int vm_vram_pt_nr; |
595 | uint64_t vram_sys_base; | ||
596 | |||
597 | /* the mtrr covering the FB */ | ||
598 | int fb_mtrr; | ||
599 | 596 | ||
600 | struct mem_block *ramin_heap; | 597 | struct mem_block *ramin_heap; |
601 | 598 | ||
@@ -614,11 +611,7 @@ struct drm_nouveau_private { | |||
614 | uint32_t dac_users[4]; | 611 | uint32_t dac_users[4]; |
615 | 612 | ||
616 | struct nouveau_suspend_resume { | 613 | struct nouveau_suspend_resume { |
617 | uint32_t fifo_mode; | ||
618 | uint32_t graph_ctx_control; | ||
619 | uint32_t graph_state; | ||
620 | uint32_t *ramin_copy; | 614 | uint32_t *ramin_copy; |
621 | uint64_t ramin_size; | ||
622 | } susres; | 615 | } susres; |
623 | 616 | ||
624 | struct backlight_device *backlight; | 617 | struct backlight_device *backlight; |
@@ -717,7 +710,7 @@ extern struct mem_block *nouveau_mem_alloc_block(struct mem_block *, | |||
717 | struct drm_file *, int tail); | 710 | struct drm_file *, int tail); |
718 | extern void nouveau_mem_takedown(struct mem_block **heap); | 711 | extern void nouveau_mem_takedown(struct mem_block **heap); |
719 | extern void nouveau_mem_free_block(struct mem_block *); | 712 | extern void nouveau_mem_free_block(struct mem_block *); |
720 | extern uint64_t nouveau_mem_fb_amount(struct drm_device *); | 713 | extern int nouveau_mem_detect(struct drm_device *dev); |
721 | extern void nouveau_mem_release(struct drm_file *, struct mem_block *heap); | 714 | extern void nouveau_mem_release(struct drm_file *, struct mem_block *heap); |
722 | extern int nouveau_mem_init(struct drm_device *); | 715 | extern int nouveau_mem_init(struct drm_device *); |
723 | extern int nouveau_mem_init_agp(struct drm_device *); | 716 | extern int nouveau_mem_init_agp(struct drm_device *); |
@@ -1124,7 +1117,8 @@ extern int nouveau_bo_pin(struct nouveau_bo *, uint32_t flags); | |||
1124 | extern int nouveau_bo_unpin(struct nouveau_bo *); | 1117 | extern int nouveau_bo_unpin(struct nouveau_bo *); |
1125 | extern int nouveau_bo_map(struct nouveau_bo *); | 1118 | extern int nouveau_bo_map(struct nouveau_bo *); |
1126 | extern void nouveau_bo_unmap(struct nouveau_bo *); | 1119 | extern void nouveau_bo_unmap(struct nouveau_bo *); |
1127 | extern void nouveau_bo_placement_set(struct nouveau_bo *, uint32_t memtype); | 1120 | extern void nouveau_bo_placement_set(struct nouveau_bo *, uint32_t type, |
1121 | uint32_t busy); | ||
1128 | extern u16 nouveau_bo_rd16(struct nouveau_bo *nvbo, unsigned index); | 1122 | extern u16 nouveau_bo_rd16(struct nouveau_bo *nvbo, unsigned index); |
1129 | extern void nouveau_bo_wr16(struct nouveau_bo *nvbo, unsigned index, u16 val); | 1123 | extern void nouveau_bo_wr16(struct nouveau_bo *nvbo, unsigned index, u16 val); |
1130 | extern u32 nouveau_bo_rd32(struct nouveau_bo *nvbo, unsigned index); | 1124 | extern u32 nouveau_bo_rd32(struct nouveau_bo *nvbo, unsigned index); |
@@ -1168,6 +1162,10 @@ extern int nouveau_gem_ioctl_info(struct drm_device *, void *, | |||
1168 | int nv17_gpio_get(struct drm_device *dev, enum dcb_gpio_tag tag); | 1162 | int nv17_gpio_get(struct drm_device *dev, enum dcb_gpio_tag tag); |
1169 | int nv17_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state); | 1163 | int nv17_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state); |
1170 | 1164 | ||
1165 | /* nv50_gpio.c */ | ||
1166 | int nv50_gpio_get(struct drm_device *dev, enum dcb_gpio_tag tag); | ||
1167 | int nv50_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state); | ||
1168 | |||
1171 | #ifndef ioread32_native | 1169 | #ifndef ioread32_native |
1172 | #ifdef __BIG_ENDIAN | 1170 | #ifdef __BIG_ENDIAN |
1173 | #define ioread16_native ioread16be | 1171 | #define ioread16_native ioread16be |
diff --git a/drivers/gpu/drm/nouveau/nouveau_encoder.h b/drivers/gpu/drm/nouveau/nouveau_encoder.h index bc4a24029ed1..9f28b94e479b 100644 --- a/drivers/gpu/drm/nouveau/nouveau_encoder.h +++ b/drivers/gpu/drm/nouveau/nouveau_encoder.h | |||
@@ -47,6 +47,7 @@ struct nouveau_encoder { | |||
47 | 47 | ||
48 | union { | 48 | union { |
49 | struct { | 49 | struct { |
50 | int mc_unknown; | ||
50 | int dpcd_version; | 51 | int dpcd_version; |
51 | int link_nr; | 52 | int link_nr; |
52 | int link_bw; | 53 | int link_bw; |
diff --git a/drivers/gpu/drm/nouveau/nouveau_gem.c b/drivers/gpu/drm/nouveau/nouveau_gem.c index 0d22f66f1c79..1bc0b38a5167 100644 --- a/drivers/gpu/drm/nouveau/nouveau_gem.c +++ b/drivers/gpu/drm/nouveau/nouveau_gem.c | |||
@@ -180,40 +180,35 @@ nouveau_gem_set_domain(struct drm_gem_object *gem, uint32_t read_domains, | |||
180 | { | 180 | { |
181 | struct nouveau_bo *nvbo = gem->driver_private; | 181 | struct nouveau_bo *nvbo = gem->driver_private; |
182 | struct ttm_buffer_object *bo = &nvbo->bo; | 182 | struct ttm_buffer_object *bo = &nvbo->bo; |
183 | uint64_t flags; | 183 | uint32_t domains = valid_domains & |
184 | (write_domains ? write_domains : read_domains); | ||
185 | uint32_t pref_flags = 0, valid_flags = 0; | ||
184 | 186 | ||
185 | if (!valid_domains || (!read_domains && !write_domains)) | 187 | if (!domains) |
186 | return -EINVAL; | 188 | return -EINVAL; |
187 | 189 | ||
188 | if (write_domains) { | 190 | if (valid_domains & NOUVEAU_GEM_DOMAIN_VRAM) |
189 | if ((valid_domains & NOUVEAU_GEM_DOMAIN_VRAM) && | 191 | valid_flags |= TTM_PL_FLAG_VRAM; |
190 | (write_domains & NOUVEAU_GEM_DOMAIN_VRAM)) | 192 | |
191 | flags = TTM_PL_FLAG_VRAM; | 193 | if (valid_domains & NOUVEAU_GEM_DOMAIN_GART) |
192 | else | 194 | valid_flags |= TTM_PL_FLAG_TT; |
193 | if ((valid_domains & NOUVEAU_GEM_DOMAIN_GART) && | 195 | |
194 | (write_domains & NOUVEAU_GEM_DOMAIN_GART)) | 196 | if ((domains & NOUVEAU_GEM_DOMAIN_VRAM) && |
195 | flags = TTM_PL_FLAG_TT; | 197 | bo->mem.mem_type == TTM_PL_VRAM) |
196 | else | 198 | pref_flags |= TTM_PL_FLAG_VRAM; |
197 | return -EINVAL; | 199 | |
198 | } else { | 200 | else if ((domains & NOUVEAU_GEM_DOMAIN_GART) && |
199 | if ((valid_domains & NOUVEAU_GEM_DOMAIN_VRAM) && | 201 | bo->mem.mem_type == TTM_PL_TT) |
200 | (read_domains & NOUVEAU_GEM_DOMAIN_VRAM) && | 202 | pref_flags |= TTM_PL_FLAG_TT; |
201 | bo->mem.mem_type == TTM_PL_VRAM) | 203 | |
202 | flags = TTM_PL_FLAG_VRAM; | 204 | else if (domains & NOUVEAU_GEM_DOMAIN_VRAM) |
203 | else | 205 | pref_flags |= TTM_PL_FLAG_VRAM; |
204 | if ((valid_domains & NOUVEAU_GEM_DOMAIN_GART) && | 206 | |
205 | (read_domains & NOUVEAU_GEM_DOMAIN_GART) && | 207 | else |
206 | bo->mem.mem_type == TTM_PL_TT) | 208 | pref_flags |= TTM_PL_FLAG_TT; |
207 | flags = TTM_PL_FLAG_TT; | 209 | |
208 | else | 210 | nouveau_bo_placement_set(nvbo, pref_flags, valid_flags); |
209 | if ((valid_domains & NOUVEAU_GEM_DOMAIN_VRAM) && | ||
210 | (read_domains & NOUVEAU_GEM_DOMAIN_VRAM)) | ||
211 | flags = TTM_PL_FLAG_VRAM; | ||
212 | else | ||
213 | flags = TTM_PL_FLAG_TT; | ||
214 | } | ||
215 | 211 | ||
216 | nouveau_bo_placement_set(nvbo, flags); | ||
217 | return 0; | 212 | return 0; |
218 | } | 213 | } |
219 | 214 | ||
diff --git a/drivers/gpu/drm/nouveau/nouveau_irq.c b/drivers/gpu/drm/nouveau/nouveau_irq.c index 2bd59a92fee5..13e73cee4c44 100644 --- a/drivers/gpu/drm/nouveau/nouveau_irq.c +++ b/drivers/gpu/drm/nouveau/nouveau_irq.c | |||
@@ -51,6 +51,7 @@ nouveau_irq_preinstall(struct drm_device *dev) | |||
51 | 51 | ||
52 | if (dev_priv->card_type == NV_50) { | 52 | if (dev_priv->card_type == NV_50) { |
53 | INIT_WORK(&dev_priv->irq_work, nv50_display_irq_handler_bh); | 53 | INIT_WORK(&dev_priv->irq_work, nv50_display_irq_handler_bh); |
54 | INIT_WORK(&dev_priv->hpd_work, nv50_display_irq_hotplug_bh); | ||
54 | INIT_LIST_HEAD(&dev_priv->vbl_waiting); | 55 | INIT_LIST_HEAD(&dev_priv->vbl_waiting); |
55 | } | 56 | } |
56 | } | 57 | } |
diff --git a/drivers/gpu/drm/nouveau/nouveau_mem.c b/drivers/gpu/drm/nouveau/nouveau_mem.c index 2dc09dbd817d..775a7017af64 100644 --- a/drivers/gpu/drm/nouveau/nouveau_mem.c +++ b/drivers/gpu/drm/nouveau/nouveau_mem.c | |||
@@ -347,6 +347,20 @@ nv50_mem_vm_bind_linear(struct drm_device *dev, uint64_t virt, uint32_t size, | |||
347 | return -EBUSY; | 347 | return -EBUSY; |
348 | } | 348 | } |
349 | 349 | ||
350 | nv_wr32(dev, 0x100c80, 0x00040001); | ||
351 | if (!nv_wait(0x100c80, 0x00000001, 0x00000000)) { | ||
352 | NV_ERROR(dev, "timeout: (0x100c80 & 1) == 0 (2)\n"); | ||
353 | NV_ERROR(dev, "0x100c80 = 0x%08x\n", nv_rd32(dev, 0x100c80)); | ||
354 | return -EBUSY; | ||
355 | } | ||
356 | |||
357 | nv_wr32(dev, 0x100c80, 0x00060001); | ||
358 | if (!nv_wait(0x100c80, 0x00000001, 0x00000000)) { | ||
359 | NV_ERROR(dev, "timeout: (0x100c80 & 1) == 0 (2)\n"); | ||
360 | NV_ERROR(dev, "0x100c80 = 0x%08x\n", nv_rd32(dev, 0x100c80)); | ||
361 | return -EBUSY; | ||
362 | } | ||
363 | |||
350 | return 0; | 364 | return 0; |
351 | } | 365 | } |
352 | 366 | ||
@@ -387,6 +401,20 @@ nv50_mem_vm_unbind(struct drm_device *dev, uint64_t virt, uint32_t size) | |||
387 | if (!nv_wait(0x100c80, 0x00000001, 0x00000000)) { | 401 | if (!nv_wait(0x100c80, 0x00000001, 0x00000000)) { |
388 | NV_ERROR(dev, "timeout: (0x100c80 & 1) == 0 (2)\n"); | 402 | NV_ERROR(dev, "timeout: (0x100c80 & 1) == 0 (2)\n"); |
389 | NV_ERROR(dev, "0x100c80 = 0x%08x\n", nv_rd32(dev, 0x100c80)); | 403 | NV_ERROR(dev, "0x100c80 = 0x%08x\n", nv_rd32(dev, 0x100c80)); |
404 | return; | ||
405 | } | ||
406 | |||
407 | nv_wr32(dev, 0x100c80, 0x00040001); | ||
408 | if (!nv_wait(0x100c80, 0x00000001, 0x00000000)) { | ||
409 | NV_ERROR(dev, "timeout: (0x100c80 & 1) == 0 (2)\n"); | ||
410 | NV_ERROR(dev, "0x100c80 = 0x%08x\n", nv_rd32(dev, 0x100c80)); | ||
411 | return; | ||
412 | } | ||
413 | |||
414 | nv_wr32(dev, 0x100c80, 0x00060001); | ||
415 | if (!nv_wait(0x100c80, 0x00000001, 0x00000000)) { | ||
416 | NV_ERROR(dev, "timeout: (0x100c80 & 1) == 0 (2)\n"); | ||
417 | NV_ERROR(dev, "0x100c80 = 0x%08x\n", nv_rd32(dev, 0x100c80)); | ||
390 | } | 418 | } |
391 | } | 419 | } |
392 | 420 | ||
@@ -449,9 +477,30 @@ void nouveau_mem_close(struct drm_device *dev) | |||
449 | } | 477 | } |
450 | } | 478 | } |
451 | 479 | ||
452 | /*XXX won't work on BSD because of pci_read_config_dword */ | ||
453 | static uint32_t | 480 | static uint32_t |
454 | nouveau_mem_fb_amount_igp(struct drm_device *dev) | 481 | nouveau_mem_detect_nv04(struct drm_device *dev) |
482 | { | ||
483 | uint32_t boot0 = nv_rd32(dev, NV03_BOOT_0); | ||
484 | |||
485 | if (boot0 & 0x00000100) | ||
486 | return (((boot0 >> 12) & 0xf) * 2 + 2) * 1024 * 1024; | ||
487 | |||
488 | switch (boot0 & NV03_BOOT_0_RAM_AMOUNT) { | ||
489 | case NV04_BOOT_0_RAM_AMOUNT_32MB: | ||
490 | return 32 * 1024 * 1024; | ||
491 | case NV04_BOOT_0_RAM_AMOUNT_16MB: | ||
492 | return 16 * 1024 * 1024; | ||
493 | case NV04_BOOT_0_RAM_AMOUNT_8MB: | ||
494 | return 8 * 1024 * 1024; | ||
495 | case NV04_BOOT_0_RAM_AMOUNT_4MB: | ||
496 | return 4 * 1024 * 1024; | ||
497 | } | ||
498 | |||
499 | return 0; | ||
500 | } | ||
501 | |||
502 | static uint32_t | ||
503 | nouveau_mem_detect_nforce(struct drm_device *dev) | ||
455 | { | 504 | { |
456 | struct drm_nouveau_private *dev_priv = dev->dev_private; | 505 | struct drm_nouveau_private *dev_priv = dev->dev_private; |
457 | struct pci_dev *bridge; | 506 | struct pci_dev *bridge; |
@@ -463,11 +512,11 @@ nouveau_mem_fb_amount_igp(struct drm_device *dev) | |||
463 | return 0; | 512 | return 0; |
464 | } | 513 | } |
465 | 514 | ||
466 | if (dev_priv->flags&NV_NFORCE) { | 515 | if (dev_priv->flags & NV_NFORCE) { |
467 | pci_read_config_dword(bridge, 0x7C, &mem); | 516 | pci_read_config_dword(bridge, 0x7C, &mem); |
468 | return (uint64_t)(((mem >> 6) & 31) + 1)*1024*1024; | 517 | return (uint64_t)(((mem >> 6) & 31) + 1)*1024*1024; |
469 | } else | 518 | } else |
470 | if (dev_priv->flags&NV_NFORCE2) { | 519 | if (dev_priv->flags & NV_NFORCE2) { |
471 | pci_read_config_dword(bridge, 0x84, &mem); | 520 | pci_read_config_dword(bridge, 0x84, &mem); |
472 | return (uint64_t)(((mem >> 4) & 127) + 1)*1024*1024; | 521 | return (uint64_t)(((mem >> 4) & 127) + 1)*1024*1024; |
473 | } | 522 | } |
@@ -477,50 +526,32 @@ nouveau_mem_fb_amount_igp(struct drm_device *dev) | |||
477 | } | 526 | } |
478 | 527 | ||
479 | /* returns the amount of FB ram in bytes */ | 528 | /* returns the amount of FB ram in bytes */ |
480 | uint64_t nouveau_mem_fb_amount(struct drm_device *dev) | 529 | int |
530 | nouveau_mem_detect(struct drm_device *dev) | ||
481 | { | 531 | { |
482 | struct drm_nouveau_private *dev_priv = dev->dev_private; | 532 | struct drm_nouveau_private *dev_priv = dev->dev_private; |
483 | uint32_t boot0; | 533 | |
484 | 534 | if (dev_priv->card_type == NV_04) { | |
485 | switch (dev_priv->card_type) { | 535 | dev_priv->vram_size = nouveau_mem_detect_nv04(dev); |
486 | case NV_04: | 536 | } else |
487 | boot0 = nv_rd32(dev, NV03_BOOT_0); | 537 | if (dev_priv->flags & (NV_NFORCE | NV_NFORCE2)) { |
488 | if (boot0 & 0x00000100) | 538 | dev_priv->vram_size = nouveau_mem_detect_nforce(dev); |
489 | return (((boot0 >> 12) & 0xf) * 2 + 2) * 1024 * 1024; | 539 | } else { |
490 | 540 | dev_priv->vram_size = nv_rd32(dev, NV04_FIFO_DATA); | |
491 | switch (boot0 & NV03_BOOT_0_RAM_AMOUNT) { | 541 | dev_priv->vram_size &= NV10_FIFO_DATA_RAM_AMOUNT_MB_MASK; |
492 | case NV04_BOOT_0_RAM_AMOUNT_32MB: | 542 | if (dev_priv->chipset == 0xaa || dev_priv->chipset == 0xac) |
493 | return 32 * 1024 * 1024; | 543 | dev_priv->vram_sys_base = nv_rd32(dev, 0x100e10) << 12; |
494 | case NV04_BOOT_0_RAM_AMOUNT_16MB: | ||
495 | return 16 * 1024 * 1024; | ||
496 | case NV04_BOOT_0_RAM_AMOUNT_8MB: | ||
497 | return 8 * 1024 * 1024; | ||
498 | case NV04_BOOT_0_RAM_AMOUNT_4MB: | ||
499 | return 4 * 1024 * 1024; | ||
500 | } | ||
501 | break; | ||
502 | case NV_10: | ||
503 | case NV_20: | ||
504 | case NV_30: | ||
505 | case NV_40: | ||
506 | case NV_50: | ||
507 | default: | ||
508 | if (dev_priv->flags & (NV_NFORCE | NV_NFORCE2)) { | ||
509 | return nouveau_mem_fb_amount_igp(dev); | ||
510 | } else { | ||
511 | uint64_t mem; | ||
512 | mem = (nv_rd32(dev, NV04_FIFO_DATA) & | ||
513 | NV10_FIFO_DATA_RAM_AMOUNT_MB_MASK) >> | ||
514 | NV10_FIFO_DATA_RAM_AMOUNT_MB_SHIFT; | ||
515 | return mem * 1024 * 1024; | ||
516 | } | ||
517 | break; | ||
518 | } | 544 | } |
519 | 545 | ||
520 | NV_ERROR(dev, | 546 | NV_INFO(dev, "Detected %dMiB VRAM\n", (int)(dev_priv->vram_size >> 20)); |
521 | "Unable to detect video ram size. Please report your setup to " | 547 | if (dev_priv->vram_sys_base) { |
522 | DRIVER_EMAIL "\n"); | 548 | NV_INFO(dev, "Stolen system memory at: 0x%010llx\n", |
523 | return 0; | 549 | dev_priv->vram_sys_base); |
550 | } | ||
551 | |||
552 | if (dev_priv->vram_size) | ||
553 | return 0; | ||
554 | return -ENOMEM; | ||
524 | } | 555 | } |
525 | 556 | ||
526 | #if __OS_HAS_AGP | 557 | #if __OS_HAS_AGP |
@@ -631,15 +662,12 @@ nouveau_mem_init(struct drm_device *dev) | |||
631 | spin_lock_init(&dev_priv->ttm.bo_list_lock); | 662 | spin_lock_init(&dev_priv->ttm.bo_list_lock); |
632 | spin_lock_init(&dev_priv->tile.lock); | 663 | spin_lock_init(&dev_priv->tile.lock); |
633 | 664 | ||
634 | dev_priv->fb_available_size = nouveau_mem_fb_amount(dev); | 665 | dev_priv->fb_available_size = dev_priv->vram_size; |
635 | |||
636 | dev_priv->fb_mappable_pages = dev_priv->fb_available_size; | 666 | dev_priv->fb_mappable_pages = dev_priv->fb_available_size; |
637 | if (dev_priv->fb_mappable_pages > drm_get_resource_len(dev, 1)) | 667 | if (dev_priv->fb_mappable_pages > drm_get_resource_len(dev, 1)) |
638 | dev_priv->fb_mappable_pages = drm_get_resource_len(dev, 1); | 668 | dev_priv->fb_mappable_pages = drm_get_resource_len(dev, 1); |
639 | dev_priv->fb_mappable_pages >>= PAGE_SHIFT; | 669 | dev_priv->fb_mappable_pages >>= PAGE_SHIFT; |
640 | 670 | ||
641 | NV_INFO(dev, "%d MiB VRAM\n", (int)(dev_priv->fb_available_size >> 20)); | ||
642 | |||
643 | /* remove reserved space at end of vram from available amount */ | 671 | /* remove reserved space at end of vram from available amount */ |
644 | dev_priv->fb_available_size -= dev_priv->ramin_rsvd_vram; | 672 | dev_priv->fb_available_size -= dev_priv->ramin_rsvd_vram; |
645 | dev_priv->fb_aper_free = dev_priv->fb_available_size; | 673 | dev_priv->fb_aper_free = dev_priv->fb_available_size; |
diff --git a/drivers/gpu/drm/nouveau/nouveau_sgdma.c b/drivers/gpu/drm/nouveau/nouveau_sgdma.c index 86785b8d42ed..1d6ee8b55154 100644 --- a/drivers/gpu/drm/nouveau/nouveau_sgdma.c +++ b/drivers/gpu/drm/nouveau/nouveau_sgdma.c | |||
@@ -172,6 +172,24 @@ nouveau_sgdma_unbind(struct ttm_backend *be) | |||
172 | } | 172 | } |
173 | dev_priv->engine.instmem.finish_access(nvbe->dev); | 173 | dev_priv->engine.instmem.finish_access(nvbe->dev); |
174 | 174 | ||
175 | if (dev_priv->card_type == NV_50) { | ||
176 | nv_wr32(dev, 0x100c80, 0x00050001); | ||
177 | if (!nv_wait(0x100c80, 0x00000001, 0x00000000)) { | ||
178 | NV_ERROR(dev, "timeout: (0x100c80 & 1) == 0 (2)\n"); | ||
179 | NV_ERROR(dev, "0x100c80 = 0x%08x\n", | ||
180 | nv_rd32(dev, 0x100c80)); | ||
181 | return -EBUSY; | ||
182 | } | ||
183 | |||
184 | nv_wr32(dev, 0x100c80, 0x00000001); | ||
185 | if (!nv_wait(0x100c80, 0x00000001, 0x00000000)) { | ||
186 | NV_ERROR(dev, "timeout: (0x100c80 & 1) == 0 (2)\n"); | ||
187 | NV_ERROR(dev, "0x100c80 = 0x%08x\n", | ||
188 | nv_rd32(dev, 0x100c80)); | ||
189 | return -EBUSY; | ||
190 | } | ||
191 | } | ||
192 | |||
175 | nvbe->bound = false; | 193 | nvbe->bound = false; |
176 | return 0; | 194 | return 0; |
177 | } | 195 | } |
diff --git a/drivers/gpu/drm/nouveau/nouveau_state.c b/drivers/gpu/drm/nouveau/nouveau_state.c index 10656a6be8e6..e1710640a278 100644 --- a/drivers/gpu/drm/nouveau/nouveau_state.c +++ b/drivers/gpu/drm/nouveau/nouveau_state.c | |||
@@ -341,7 +341,7 @@ nouveau_card_init_channel(struct drm_device *dev) | |||
341 | 341 | ||
342 | gpuobj = NULL; | 342 | gpuobj = NULL; |
343 | ret = nouveau_gpuobj_dma_new(dev_priv->channel, NV_CLASS_DMA_IN_MEMORY, | 343 | ret = nouveau_gpuobj_dma_new(dev_priv->channel, NV_CLASS_DMA_IN_MEMORY, |
344 | 0, nouveau_mem_fb_amount(dev), | 344 | 0, dev_priv->vram_size, |
345 | NV_DMA_ACCESS_RW, NV_DMA_TARGET_VIDMEM, | 345 | NV_DMA_ACCESS_RW, NV_DMA_TARGET_VIDMEM, |
346 | &gpuobj); | 346 | &gpuobj); |
347 | if (ret) | 347 | if (ret) |
@@ -427,6 +427,10 @@ nouveau_card_init(struct drm_device *dev) | |||
427 | goto out; | 427 | goto out; |
428 | } | 428 | } |
429 | 429 | ||
430 | ret = nouveau_mem_detect(dev); | ||
431 | if (ret) | ||
432 | goto out_bios; | ||
433 | |||
430 | ret = nouveau_gpuobj_early_init(dev); | 434 | ret = nouveau_gpuobj_early_init(dev); |
431 | if (ret) | 435 | if (ret) |
432 | goto out_bios; | 436 | goto out_bios; |
@@ -502,7 +506,7 @@ nouveau_card_init(struct drm_device *dev) | |||
502 | else | 506 | else |
503 | ret = nv04_display_create(dev); | 507 | ret = nv04_display_create(dev); |
504 | if (ret) | 508 | if (ret) |
505 | goto out_irq; | 509 | goto out_channel; |
506 | } | 510 | } |
507 | 511 | ||
508 | ret = nouveau_backlight_init(dev); | 512 | ret = nouveau_backlight_init(dev); |
@@ -516,6 +520,11 @@ nouveau_card_init(struct drm_device *dev) | |||
516 | 520 | ||
517 | return 0; | 521 | return 0; |
518 | 522 | ||
523 | out_channel: | ||
524 | if (dev_priv->channel) { | ||
525 | nouveau_channel_free(dev_priv->channel); | ||
526 | dev_priv->channel = NULL; | ||
527 | } | ||
519 | out_irq: | 528 | out_irq: |
520 | drm_irq_uninstall(dev); | 529 | drm_irq_uninstall(dev); |
521 | out_fifo: | 530 | out_fifo: |
@@ -533,6 +542,7 @@ out_mc: | |||
533 | out_gpuobj: | 542 | out_gpuobj: |
534 | nouveau_gpuobj_takedown(dev); | 543 | nouveau_gpuobj_takedown(dev); |
535 | out_mem: | 544 | out_mem: |
545 | nouveau_sgdma_takedown(dev); | ||
536 | nouveau_mem_close(dev); | 546 | nouveau_mem_close(dev); |
537 | out_instmem: | 547 | out_instmem: |
538 | engine->instmem.takedown(dev); | 548 | engine->instmem.takedown(dev); |
diff --git a/drivers/gpu/drm/nouveau/nv40_fifo.c b/drivers/gpu/drm/nouveau/nv40_fifo.c index 6b2ef4a9fce1..500ccfd3a0b8 100644 --- a/drivers/gpu/drm/nouveau/nv40_fifo.c +++ b/drivers/gpu/drm/nouveau/nv40_fifo.c | |||
@@ -278,7 +278,7 @@ nv40_fifo_init_ramxx(struct drm_device *dev) | |||
278 | default: | 278 | default: |
279 | nv_wr32(dev, 0x2230, 0); | 279 | nv_wr32(dev, 0x2230, 0); |
280 | nv_wr32(dev, NV40_PFIFO_RAMFC, | 280 | nv_wr32(dev, NV40_PFIFO_RAMFC, |
281 | ((nouveau_mem_fb_amount(dev) - 512 * 1024 + | 281 | ((dev_priv->vram_size - 512 * 1024 + |
282 | dev_priv->ramfc_offset) >> 16) | (3 << 16)); | 282 | dev_priv->ramfc_offset) >> 16) | (3 << 16)); |
283 | break; | 283 | break; |
284 | } | 284 | } |
diff --git a/drivers/gpu/drm/nouveau/nv40_graph.c b/drivers/gpu/drm/nouveau/nv40_graph.c index 53e8afe1dcd1..0616c96e4b67 100644 --- a/drivers/gpu/drm/nouveau/nv40_graph.c +++ b/drivers/gpu/drm/nouveau/nv40_graph.c | |||
@@ -335,6 +335,27 @@ nv40_graph_init(struct drm_device *dev) | |||
335 | nv_wr32(dev, 0x400b38, 0x2ffff800); | 335 | nv_wr32(dev, 0x400b38, 0x2ffff800); |
336 | nv_wr32(dev, 0x400b3c, 0x00006000); | 336 | nv_wr32(dev, 0x400b3c, 0x00006000); |
337 | 337 | ||
338 | /* Tiling related stuff. */ | ||
339 | switch (dev_priv->chipset) { | ||
340 | case 0x44: | ||
341 | case 0x4a: | ||
342 | nv_wr32(dev, 0x400bc4, 0x1003d888); | ||
343 | nv_wr32(dev, 0x400bbc, 0xb7a7b500); | ||
344 | break; | ||
345 | case 0x46: | ||
346 | nv_wr32(dev, 0x400bc4, 0x0000e024); | ||
347 | nv_wr32(dev, 0x400bbc, 0xb7a7b520); | ||
348 | break; | ||
349 | case 0x4c: | ||
350 | case 0x4e: | ||
351 | case 0x67: | ||
352 | nv_wr32(dev, 0x400bc4, 0x1003d888); | ||
353 | nv_wr32(dev, 0x400bbc, 0xb7a7b540); | ||
354 | break; | ||
355 | default: | ||
356 | break; | ||
357 | } | ||
358 | |||
338 | /* Turn all the tiling regions off. */ | 359 | /* Turn all the tiling regions off. */ |
339 | for (i = 0; i < pfb->num_tiles; i++) | 360 | for (i = 0; i < pfb->num_tiles; i++) |
340 | nv40_graph_set_region_tiling(dev, i, 0, 0, 0); | 361 | nv40_graph_set_region_tiling(dev, i, 0, 0, 0); |
diff --git a/drivers/gpu/drm/nouveau/nv50_display.c b/drivers/gpu/drm/nouveau/nv50_display.c index fac6c88a2b1f..649db4c1b690 100644 --- a/drivers/gpu/drm/nouveau/nv50_display.c +++ b/drivers/gpu/drm/nouveau/nv50_display.c | |||
@@ -143,7 +143,7 @@ nv50_evo_channel_new(struct drm_device *dev, struct nouveau_channel **pchan) | |||
143 | } | 143 | } |
144 | 144 | ||
145 | ret = nv50_evo_dmaobj_new(chan, 0x3d, NvEvoVRAM, 0, 0x19, | 145 | ret = nv50_evo_dmaobj_new(chan, 0x3d, NvEvoVRAM, 0, 0x19, |
146 | 0, nouveau_mem_fb_amount(dev)); | 146 | 0, dev_priv->vram_size); |
147 | if (ret) { | 147 | if (ret) { |
148 | nv50_evo_channel_del(pchan); | 148 | nv50_evo_channel_del(pchan); |
149 | return ret; | 149 | return ret; |
@@ -231,7 +231,7 @@ nv50_display_init(struct drm_device *dev) | |||
231 | /* This used to be in crtc unblank, but seems out of place there. */ | 231 | /* This used to be in crtc unblank, but seems out of place there. */ |
232 | nv_wr32(dev, NV50_PDISPLAY_UNK_380, 0); | 232 | nv_wr32(dev, NV50_PDISPLAY_UNK_380, 0); |
233 | /* RAM is clamped to 256 MiB. */ | 233 | /* RAM is clamped to 256 MiB. */ |
234 | ram_amount = nouveau_mem_fb_amount(dev); | 234 | ram_amount = dev_priv->vram_size; |
235 | NV_DEBUG_KMS(dev, "ram_amount %d\n", ram_amount); | 235 | NV_DEBUG_KMS(dev, "ram_amount %d\n", ram_amount); |
236 | if (ram_amount > 256*1024*1024) | 236 | if (ram_amount > 256*1024*1024) |
237 | ram_amount = 256*1024*1024; | 237 | ram_amount = 256*1024*1024; |
@@ -529,8 +529,10 @@ int nv50_display_create(struct drm_device *dev) | |||
529 | } | 529 | } |
530 | 530 | ||
531 | ret = nv50_display_init(dev); | 531 | ret = nv50_display_init(dev); |
532 | if (ret) | 532 | if (ret) { |
533 | nv50_display_destroy(dev); | ||
533 | return ret; | 534 | return ret; |
535 | } | ||
534 | 536 | ||
535 | return 0; | 537 | return 0; |
536 | } | 538 | } |
@@ -885,10 +887,12 @@ nv50_display_error_handler(struct drm_device *dev) | |||
885 | nv_wr32(dev, NV50_PDISPLAY_TRAPPED_ADDR, 0x90000000); | 887 | nv_wr32(dev, NV50_PDISPLAY_TRAPPED_ADDR, 0x90000000); |
886 | } | 888 | } |
887 | 889 | ||
888 | static void | 890 | void |
889 | nv50_display_irq_hotplug(struct drm_device *dev) | 891 | nv50_display_irq_hotplug_bh(struct work_struct *work) |
890 | { | 892 | { |
891 | struct drm_nouveau_private *dev_priv = dev->dev_private; | 893 | struct drm_nouveau_private *dev_priv = |
894 | container_of(work, struct drm_nouveau_private, hpd_work); | ||
895 | struct drm_device *dev = dev_priv->dev; | ||
892 | struct drm_connector *connector; | 896 | struct drm_connector *connector; |
893 | const uint32_t gpio_reg[4] = { 0xe104, 0xe108, 0xe280, 0xe284 }; | 897 | const uint32_t gpio_reg[4] = { 0xe104, 0xe108, 0xe280, 0xe284 }; |
894 | uint32_t unplug_mask, plug_mask, change_mask; | 898 | uint32_t unplug_mask, plug_mask, change_mask; |
@@ -949,8 +953,10 @@ nv50_display_irq_handler(struct drm_device *dev) | |||
949 | struct drm_nouveau_private *dev_priv = dev->dev_private; | 953 | struct drm_nouveau_private *dev_priv = dev->dev_private; |
950 | uint32_t delayed = 0; | 954 | uint32_t delayed = 0; |
951 | 955 | ||
952 | while (nv_rd32(dev, NV50_PMC_INTR_0) & NV50_PMC_INTR_0_HOTPLUG) | 956 | if (nv_rd32(dev, NV50_PMC_INTR_0) & NV50_PMC_INTR_0_HOTPLUG) { |
953 | nv50_display_irq_hotplug(dev); | 957 | if (!work_pending(&dev_priv->hpd_work)) |
958 | queue_work(dev_priv->wq, &dev_priv->hpd_work); | ||
959 | } | ||
954 | 960 | ||
955 | while (nv_rd32(dev, NV50_PMC_INTR_0) & NV50_PMC_INTR_0_DISPLAY) { | 961 | while (nv_rd32(dev, NV50_PMC_INTR_0) & NV50_PMC_INTR_0_DISPLAY) { |
956 | uint32_t intr0 = nv_rd32(dev, NV50_PDISPLAY_INTR_0); | 962 | uint32_t intr0 = nv_rd32(dev, NV50_PDISPLAY_INTR_0); |
diff --git a/drivers/gpu/drm/nouveau/nv50_display.h b/drivers/gpu/drm/nouveau/nv50_display.h index 3ae8d0725f63..581d405ac014 100644 --- a/drivers/gpu/drm/nouveau/nv50_display.h +++ b/drivers/gpu/drm/nouveau/nv50_display.h | |||
@@ -37,6 +37,7 @@ | |||
37 | 37 | ||
38 | void nv50_display_irq_handler(struct drm_device *dev); | 38 | void nv50_display_irq_handler(struct drm_device *dev); |
39 | void nv50_display_irq_handler_bh(struct work_struct *work); | 39 | void nv50_display_irq_handler_bh(struct work_struct *work); |
40 | void nv50_display_irq_hotplug_bh(struct work_struct *work); | ||
40 | int nv50_display_init(struct drm_device *dev); | 41 | int nv50_display_init(struct drm_device *dev); |
41 | int nv50_display_create(struct drm_device *dev); | 42 | int nv50_display_create(struct drm_device *dev); |
42 | int nv50_display_destroy(struct drm_device *dev); | 43 | int nv50_display_destroy(struct drm_device *dev); |
diff --git a/drivers/gpu/drm/nouveau/nv50_fbcon.c b/drivers/gpu/drm/nouveau/nv50_fbcon.c index 25a3cd8794f9..a8c70e7e9184 100644 --- a/drivers/gpu/drm/nouveau/nv50_fbcon.c +++ b/drivers/gpu/drm/nouveau/nv50_fbcon.c | |||
@@ -157,8 +157,11 @@ nv50_fbcon_accel_init(struct fb_info *info) | |||
157 | struct drm_nouveau_private *dev_priv = dev->dev_private; | 157 | struct drm_nouveau_private *dev_priv = dev->dev_private; |
158 | struct nouveau_channel *chan = dev_priv->channel; | 158 | struct nouveau_channel *chan = dev_priv->channel; |
159 | struct nouveau_gpuobj *eng2d = NULL; | 159 | struct nouveau_gpuobj *eng2d = NULL; |
160 | uint64_t fb; | ||
160 | int ret, format; | 161 | int ret, format; |
161 | 162 | ||
163 | fb = info->fix.smem_start - dev_priv->fb_phys + dev_priv->vm_vram_base; | ||
164 | |||
162 | switch (info->var.bits_per_pixel) { | 165 | switch (info->var.bits_per_pixel) { |
163 | case 8: | 166 | case 8: |
164 | format = 0xf3; | 167 | format = 0xf3; |
@@ -248,9 +251,8 @@ nv50_fbcon_accel_init(struct fb_info *info) | |||
248 | OUT_RING(chan, info->fix.line_length); | 251 | OUT_RING(chan, info->fix.line_length); |
249 | OUT_RING(chan, info->var.xres_virtual); | 252 | OUT_RING(chan, info->var.xres_virtual); |
250 | OUT_RING(chan, info->var.yres_virtual); | 253 | OUT_RING(chan, info->var.yres_virtual); |
251 | OUT_RING(chan, 0); | 254 | OUT_RING(chan, upper_32_bits(fb)); |
252 | OUT_RING(chan, info->fix.smem_start - dev_priv->fb_phys + | 255 | OUT_RING(chan, lower_32_bits(fb)); |
253 | dev_priv->vm_vram_base); | ||
254 | BEGIN_RING(chan, NvSub2D, 0x0230, 2); | 256 | BEGIN_RING(chan, NvSub2D, 0x0230, 2); |
255 | OUT_RING(chan, format); | 257 | OUT_RING(chan, format); |
256 | OUT_RING(chan, 1); | 258 | OUT_RING(chan, 1); |
@@ -258,9 +260,8 @@ nv50_fbcon_accel_init(struct fb_info *info) | |||
258 | OUT_RING(chan, info->fix.line_length); | 260 | OUT_RING(chan, info->fix.line_length); |
259 | OUT_RING(chan, info->var.xres_virtual); | 261 | OUT_RING(chan, info->var.xres_virtual); |
260 | OUT_RING(chan, info->var.yres_virtual); | 262 | OUT_RING(chan, info->var.yres_virtual); |
261 | OUT_RING(chan, 0); | 263 | OUT_RING(chan, upper_32_bits(fb)); |
262 | OUT_RING(chan, info->fix.smem_start - dev_priv->fb_phys + | 264 | OUT_RING(chan, lower_32_bits(fb)); |
263 | dev_priv->vm_vram_base); | ||
264 | 265 | ||
265 | return 0; | 266 | return 0; |
266 | } | 267 | } |
diff --git a/drivers/gpu/drm/nouveau/nv50_gpio.c b/drivers/gpu/drm/nouveau/nv50_gpio.c new file mode 100644 index 000000000000..c61782b314e7 --- /dev/null +++ b/drivers/gpu/drm/nouveau/nv50_gpio.c | |||
@@ -0,0 +1,76 @@ | |||
1 | /* | ||
2 | * Copyright 2010 Red Hat Inc. | ||
3 | * | ||
4 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
5 | * copy of this software and associated documentation files (the "Software"), | ||
6 | * to deal in the Software without restriction, including without limitation | ||
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
8 | * and/or sell copies of the Software, and to permit persons to whom the | ||
9 | * Software is furnished to do so, subject to the following conditions: | ||
10 | * | ||
11 | * The above copyright notice and this permission notice shall be included in | ||
12 | * all copies or substantial portions of the Software. | ||
13 | * | ||
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | ||
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | ||
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | ||
20 | * OTHER DEALINGS IN THE SOFTWARE. | ||
21 | * | ||
22 | * Authors: Ben Skeggs | ||
23 | */ | ||
24 | |||
25 | #include "drmP.h" | ||
26 | #include "nouveau_drv.h" | ||
27 | #include "nouveau_hw.h" | ||
28 | |||
29 | static int | ||
30 | nv50_gpio_location(struct dcb_gpio_entry *gpio, uint32_t *reg, uint32_t *shift) | ||
31 | { | ||
32 | const uint32_t nv50_gpio_reg[4] = { 0xe104, 0xe108, 0xe280, 0xe284 }; | ||
33 | |||
34 | if (gpio->line > 32) | ||
35 | return -EINVAL; | ||
36 | |||
37 | *reg = nv50_gpio_reg[gpio->line >> 3]; | ||
38 | *shift = (gpio->line & 7) << 2; | ||
39 | return 0; | ||
40 | } | ||
41 | |||
42 | int | ||
43 | nv50_gpio_get(struct drm_device *dev, enum dcb_gpio_tag tag) | ||
44 | { | ||
45 | struct dcb_gpio_entry *gpio; | ||
46 | uint32_t r, s, v; | ||
47 | |||
48 | gpio = nouveau_bios_gpio_entry(dev, tag); | ||
49 | if (!gpio) | ||
50 | return -ENOENT; | ||
51 | |||
52 | if (nv50_gpio_location(gpio, &r, &s)) | ||
53 | return -EINVAL; | ||
54 | |||
55 | v = nv_rd32(dev, r) >> (s + 2); | ||
56 | return ((v & 1) == (gpio->state[1] & 1)); | ||
57 | } | ||
58 | |||
59 | int | ||
60 | nv50_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state) | ||
61 | { | ||
62 | struct dcb_gpio_entry *gpio; | ||
63 | uint32_t r, s, v; | ||
64 | |||
65 | gpio = nouveau_bios_gpio_entry(dev, tag); | ||
66 | if (!gpio) | ||
67 | return -ENOENT; | ||
68 | |||
69 | if (nv50_gpio_location(gpio, &r, &s)) | ||
70 | return -EINVAL; | ||
71 | |||
72 | v = nv_rd32(dev, r) & ~(0x3 << s); | ||
73 | v |= (gpio->state[state] ^ 2) << s; | ||
74 | nv_wr32(dev, r, v); | ||
75 | return 0; | ||
76 | } | ||
diff --git a/drivers/gpu/drm/nouveau/nv50_graph.c b/drivers/gpu/drm/nouveau/nv50_graph.c index c62b33a02f88..b203d06f601f 100644 --- a/drivers/gpu/drm/nouveau/nv50_graph.c +++ b/drivers/gpu/drm/nouveau/nv50_graph.c | |||
@@ -410,9 +410,10 @@ struct nouveau_pgraph_object_class nv50_graph_grclass[] = { | |||
410 | { 0x5039, false, NULL }, /* m2mf */ | 410 | { 0x5039, false, NULL }, /* m2mf */ |
411 | { 0x502d, false, NULL }, /* 2d */ | 411 | { 0x502d, false, NULL }, /* 2d */ |
412 | { 0x50c0, false, NULL }, /* compute */ | 412 | { 0x50c0, false, NULL }, /* compute */ |
413 | { 0x85c0, false, NULL }, /* compute (nva3, nva5, nva8) */ | ||
413 | { 0x5097, false, NULL }, /* tesla (nv50) */ | 414 | { 0x5097, false, NULL }, /* tesla (nv50) */ |
414 | { 0x8297, false, NULL }, /* tesla (nv80/nv90) */ | 415 | { 0x8297, false, NULL }, /* tesla (nv8x/nv9x) */ |
415 | { 0x8397, false, NULL }, /* tesla (nva0) */ | 416 | { 0x8397, false, NULL }, /* tesla (nva0, nvaa, nvac) */ |
416 | { 0x8597, false, NULL }, /* tesla (nva8) */ | 417 | { 0x8597, false, NULL }, /* tesla (nva3, nva5, nva8) */ |
417 | {} | 418 | {} |
418 | }; | 419 | }; |
diff --git a/drivers/gpu/drm/nouveau/nv50_grctx.c b/drivers/gpu/drm/nouveau/nv50_grctx.c index 546b31949a30..42a8fb20c1e6 100644 --- a/drivers/gpu/drm/nouveau/nv50_grctx.c +++ b/drivers/gpu/drm/nouveau/nv50_grctx.c | |||
@@ -55,12 +55,12 @@ | |||
55 | #define CP_FLAG_AUTO_LOAD ((2 * 32) + 5) | 55 | #define CP_FLAG_AUTO_LOAD ((2 * 32) + 5) |
56 | #define CP_FLAG_AUTO_LOAD_NOT_PENDING 0 | 56 | #define CP_FLAG_AUTO_LOAD_NOT_PENDING 0 |
57 | #define CP_FLAG_AUTO_LOAD_PENDING 1 | 57 | #define CP_FLAG_AUTO_LOAD_PENDING 1 |
58 | #define CP_FLAG_NEWCTX ((2 * 32) + 10) | ||
59 | #define CP_FLAG_NEWCTX_BUSY 0 | ||
60 | #define CP_FLAG_NEWCTX_DONE 1 | ||
58 | #define CP_FLAG_XFER ((2 * 32) + 11) | 61 | #define CP_FLAG_XFER ((2 * 32) + 11) |
59 | #define CP_FLAG_XFER_IDLE 0 | 62 | #define CP_FLAG_XFER_IDLE 0 |
60 | #define CP_FLAG_XFER_BUSY 1 | 63 | #define CP_FLAG_XFER_BUSY 1 |
61 | #define CP_FLAG_NEWCTX ((2 * 32) + 12) | ||
62 | #define CP_FLAG_NEWCTX_BUSY 0 | ||
63 | #define CP_FLAG_NEWCTX_DONE 1 | ||
64 | #define CP_FLAG_ALWAYS ((2 * 32) + 13) | 64 | #define CP_FLAG_ALWAYS ((2 * 32) + 13) |
65 | #define CP_FLAG_ALWAYS_FALSE 0 | 65 | #define CP_FLAG_ALWAYS_FALSE 0 |
66 | #define CP_FLAG_ALWAYS_TRUE 1 | 66 | #define CP_FLAG_ALWAYS_TRUE 1 |
@@ -177,6 +177,7 @@ nv50_grctx_init(struct nouveau_grctx *ctx) | |||
177 | case 0x96: | 177 | case 0x96: |
178 | case 0x98: | 178 | case 0x98: |
179 | case 0xa0: | 179 | case 0xa0: |
180 | case 0xa3: | ||
180 | case 0xa5: | 181 | case 0xa5: |
181 | case 0xa8: | 182 | case 0xa8: |
182 | case 0xaa: | 183 | case 0xaa: |
@@ -364,6 +365,7 @@ nv50_graph_construct_mmio(struct nouveau_grctx *ctx) | |||
364 | case 0xac: | 365 | case 0xac: |
365 | gr_def(ctx, 0x401c00, 0x042500df); | 366 | gr_def(ctx, 0x401c00, 0x042500df); |
366 | break; | 367 | break; |
368 | case 0xa3: | ||
367 | case 0xa5: | 369 | case 0xa5: |
368 | case 0xa8: | 370 | case 0xa8: |
369 | gr_def(ctx, 0x401c00, 0x142500df); | 371 | gr_def(ctx, 0x401c00, 0x142500df); |
@@ -418,6 +420,7 @@ nv50_graph_construct_mmio(struct nouveau_grctx *ctx) | |||
418 | break; | 420 | break; |
419 | case 0x84: | 421 | case 0x84: |
420 | case 0xa0: | 422 | case 0xa0: |
423 | case 0xa3: | ||
421 | case 0xa5: | 424 | case 0xa5: |
422 | case 0xa8: | 425 | case 0xa8: |
423 | case 0xaa: | 426 | case 0xaa: |
@@ -792,6 +795,7 @@ nv50_graph_construct_mmio(struct nouveau_grctx *ctx) | |||
792 | case 0xa5: | 795 | case 0xa5: |
793 | gr_def(ctx, offset + 0x1c, 0x310c0000); | 796 | gr_def(ctx, offset + 0x1c, 0x310c0000); |
794 | break; | 797 | break; |
798 | case 0xa3: | ||
795 | case 0xa8: | 799 | case 0xa8: |
796 | case 0xaa: | 800 | case 0xaa: |
797 | case 0xac: | 801 | case 0xac: |
@@ -859,6 +863,8 @@ nv50_graph_construct_mmio(struct nouveau_grctx *ctx) | |||
859 | else | 863 | else |
860 | gr_def(ctx, offset + 0x8, 0x05010202); | 864 | gr_def(ctx, offset + 0x8, 0x05010202); |
861 | gr_def(ctx, offset + 0xc, 0x00030201); | 865 | gr_def(ctx, offset + 0xc, 0x00030201); |
866 | if (dev_priv->chipset == 0xa3) | ||
867 | cp_ctx(ctx, base + 0x36c, 1); | ||
862 | 868 | ||
863 | cp_ctx(ctx, base + 0x400, 2); | 869 | cp_ctx(ctx, base + 0x400, 2); |
864 | gr_def(ctx, base + 0x404, 0x00000040); | 870 | gr_def(ctx, base + 0x404, 0x00000040); |
@@ -1159,7 +1165,9 @@ nv50_graph_construct_xfer1(struct nouveau_grctx *ctx) | |||
1159 | nv50_graph_construct_gene_unk8(ctx); | 1165 | nv50_graph_construct_gene_unk8(ctx); |
1160 | if (dev_priv->chipset == 0xa0) | 1166 | if (dev_priv->chipset == 0xa0) |
1161 | xf_emit(ctx, 0x189, 0); | 1167 | xf_emit(ctx, 0x189, 0); |
1162 | else if (dev_priv->chipset < 0xa8) | 1168 | else if (dev_priv->chipset == 0xa3) |
1169 | xf_emit(ctx, 0xd5, 0); | ||
1170 | else if (dev_priv->chipset == 0xa5) | ||
1163 | xf_emit(ctx, 0x99, 0); | 1171 | xf_emit(ctx, 0x99, 0); |
1164 | else if (dev_priv->chipset == 0xaa) | 1172 | else if (dev_priv->chipset == 0xaa) |
1165 | xf_emit(ctx, 0x65, 0); | 1173 | xf_emit(ctx, 0x65, 0); |
@@ -1197,6 +1205,8 @@ nv50_graph_construct_xfer1(struct nouveau_grctx *ctx) | |||
1197 | ctx->ctxvals_pos = offset + 4; | 1205 | ctx->ctxvals_pos = offset + 4; |
1198 | if (dev_priv->chipset == 0xa0) | 1206 | if (dev_priv->chipset == 0xa0) |
1199 | xf_emit(ctx, 0xa80, 0); | 1207 | xf_emit(ctx, 0xa80, 0); |
1208 | else if (dev_priv->chipset == 0xa3) | ||
1209 | xf_emit(ctx, 0xa7c, 0); | ||
1200 | else | 1210 | else |
1201 | xf_emit(ctx, 0xa7a, 0); | 1211 | xf_emit(ctx, 0xa7a, 0); |
1202 | xf_emit(ctx, 1, 0x3fffff); | 1212 | xf_emit(ctx, 1, 0x3fffff); |
@@ -1341,6 +1351,7 @@ nv50_graph_construct_gene_unk1(struct nouveau_grctx *ctx) | |||
1341 | xf_emit(ctx, 0x942, 0); | 1351 | xf_emit(ctx, 0x942, 0); |
1342 | break; | 1352 | break; |
1343 | case 0xa0: | 1353 | case 0xa0: |
1354 | case 0xa3: | ||
1344 | xf_emit(ctx, 0x2042, 0); | 1355 | xf_emit(ctx, 0x2042, 0); |
1345 | break; | 1356 | break; |
1346 | case 0xa5: | 1357 | case 0xa5: |
diff --git a/drivers/gpu/drm/nouveau/nv50_instmem.c b/drivers/gpu/drm/nouveau/nv50_instmem.c index de1f5b0062c5..5f21df31f3aa 100644 --- a/drivers/gpu/drm/nouveau/nv50_instmem.c +++ b/drivers/gpu/drm/nouveau/nv50_instmem.c | |||
@@ -63,9 +63,10 @@ nv50_instmem_init(struct drm_device *dev) | |||
63 | struct drm_nouveau_private *dev_priv = dev->dev_private; | 63 | struct drm_nouveau_private *dev_priv = dev->dev_private; |
64 | struct nouveau_channel *chan; | 64 | struct nouveau_channel *chan; |
65 | uint32_t c_offset, c_size, c_ramfc, c_vmpd, c_base, pt_size; | 65 | uint32_t c_offset, c_size, c_ramfc, c_vmpd, c_base, pt_size; |
66 | uint32_t save_nv001700; | ||
67 | uint64_t v; | ||
66 | struct nv50_instmem_priv *priv; | 68 | struct nv50_instmem_priv *priv; |
67 | int ret, i; | 69 | int ret, i; |
68 | uint32_t v, save_nv001700; | ||
69 | 70 | ||
70 | priv = kzalloc(sizeof(*priv), GFP_KERNEL); | 71 | priv = kzalloc(sizeof(*priv), GFP_KERNEL); |
71 | if (!priv) | 72 | if (!priv) |
@@ -76,17 +77,12 @@ nv50_instmem_init(struct drm_device *dev) | |||
76 | for (i = 0x1700; i <= 0x1710; i += 4) | 77 | for (i = 0x1700; i <= 0x1710; i += 4) |
77 | priv->save1700[(i-0x1700)/4] = nv_rd32(dev, i); | 78 | priv->save1700[(i-0x1700)/4] = nv_rd32(dev, i); |
78 | 79 | ||
79 | if (dev_priv->chipset == 0xaa || dev_priv->chipset == 0xac) | ||
80 | dev_priv->vram_sys_base = nv_rd32(dev, 0x100e10) << 12; | ||
81 | else | ||
82 | dev_priv->vram_sys_base = 0; | ||
83 | |||
84 | /* Reserve the last MiB of VRAM, we should probably try to avoid | 80 | /* Reserve the last MiB of VRAM, we should probably try to avoid |
85 | * setting up the below tables over the top of the VBIOS image at | 81 | * setting up the below tables over the top of the VBIOS image at |
86 | * some point. | 82 | * some point. |
87 | */ | 83 | */ |
88 | dev_priv->ramin_rsvd_vram = 1 << 20; | 84 | dev_priv->ramin_rsvd_vram = 1 << 20; |
89 | c_offset = nouveau_mem_fb_amount(dev) - dev_priv->ramin_rsvd_vram; | 85 | c_offset = dev_priv->vram_size - dev_priv->ramin_rsvd_vram; |
90 | c_size = 128 << 10; | 86 | c_size = 128 << 10; |
91 | c_vmpd = ((dev_priv->chipset & 0xf0) == 0x50) ? 0x1400 : 0x200; | 87 | c_vmpd = ((dev_priv->chipset & 0xf0) == 0x50) ? 0x1400 : 0x200; |
92 | c_ramfc = ((dev_priv->chipset & 0xf0) == 0x50) ? 0x0 : 0x20; | 88 | c_ramfc = ((dev_priv->chipset & 0xf0) == 0x50) ? 0x0 : 0x20; |
@@ -106,7 +102,7 @@ nv50_instmem_init(struct drm_device *dev) | |||
106 | dev_priv->vm_gart_size = NV50_VM_BLOCK; | 102 | dev_priv->vm_gart_size = NV50_VM_BLOCK; |
107 | 103 | ||
108 | dev_priv->vm_vram_base = dev_priv->vm_gart_base + dev_priv->vm_gart_size; | 104 | dev_priv->vm_vram_base = dev_priv->vm_gart_base + dev_priv->vm_gart_size; |
109 | dev_priv->vm_vram_size = nouveau_mem_fb_amount(dev); | 105 | dev_priv->vm_vram_size = dev_priv->vram_size; |
110 | if (dev_priv->vm_vram_size > NV50_VM_MAX_VRAM) | 106 | if (dev_priv->vm_vram_size > NV50_VM_MAX_VRAM) |
111 | dev_priv->vm_vram_size = NV50_VM_MAX_VRAM; | 107 | dev_priv->vm_vram_size = NV50_VM_MAX_VRAM; |
112 | dev_priv->vm_vram_size = roundup(dev_priv->vm_vram_size, NV50_VM_BLOCK); | 108 | dev_priv->vm_vram_size = roundup(dev_priv->vm_vram_size, NV50_VM_BLOCK); |
@@ -189,8 +185,8 @@ nv50_instmem_init(struct drm_device *dev) | |||
189 | 185 | ||
190 | i = 0; | 186 | i = 0; |
191 | while (v < dev_priv->vram_sys_base + c_offset + c_size) { | 187 | while (v < dev_priv->vram_sys_base + c_offset + c_size) { |
192 | BAR0_WI32(priv->pramin_pt->gpuobj, i + 0, v); | 188 | BAR0_WI32(priv->pramin_pt->gpuobj, i + 0, lower_32_bits(v)); |
193 | BAR0_WI32(priv->pramin_pt->gpuobj, i + 4, 0x00000000); | 189 | BAR0_WI32(priv->pramin_pt->gpuobj, i + 4, upper_32_bits(v)); |
194 | v += 0x1000; | 190 | v += 0x1000; |
195 | i += 8; | 191 | i += 8; |
196 | } | 192 | } |
diff --git a/drivers/gpu/drm/nouveau/nv50_sor.c b/drivers/gpu/drm/nouveau/nv50_sor.c index c2fff543b06f..0c68698f23df 100644 --- a/drivers/gpu/drm/nouveau/nv50_sor.c +++ b/drivers/gpu/drm/nouveau/nv50_sor.c | |||
@@ -211,7 +211,7 @@ nv50_sor_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode, | |||
211 | mode_ctl = 0x0200; | 211 | mode_ctl = 0x0200; |
212 | break; | 212 | break; |
213 | case OUTPUT_DP: | 213 | case OUTPUT_DP: |
214 | mode_ctl |= 0x00050000; | 214 | mode_ctl |= (nv_encoder->dp.mc_unknown << 16); |
215 | if (nv_encoder->dcb->sorconf.link & 1) | 215 | if (nv_encoder->dcb->sorconf.link & 1) |
216 | mode_ctl |= 0x00000800; | 216 | mode_ctl |= 0x00000800; |
217 | else | 217 | else |
@@ -274,6 +274,7 @@ static const struct drm_encoder_funcs nv50_sor_encoder_funcs = { | |||
274 | int | 274 | int |
275 | nv50_sor_create(struct drm_device *dev, struct dcb_entry *entry) | 275 | nv50_sor_create(struct drm_device *dev, struct dcb_entry *entry) |
276 | { | 276 | { |
277 | struct drm_nouveau_private *dev_priv = dev->dev_private; | ||
277 | struct nouveau_encoder *nv_encoder = NULL; | 278 | struct nouveau_encoder *nv_encoder = NULL; |
278 | struct drm_encoder *encoder; | 279 | struct drm_encoder *encoder; |
279 | bool dum; | 280 | bool dum; |
@@ -319,5 +320,27 @@ nv50_sor_create(struct drm_device *dev, struct dcb_entry *entry) | |||
319 | encoder->possible_crtcs = entry->heads; | 320 | encoder->possible_crtcs = entry->heads; |
320 | encoder->possible_clones = 0; | 321 | encoder->possible_clones = 0; |
321 | 322 | ||
323 | if (nv_encoder->dcb->type == OUTPUT_DP) { | ||
324 | uint32_t mc, or = nv_encoder->or; | ||
325 | |||
326 | if (dev_priv->chipset < 0x90 || | ||
327 | dev_priv->chipset == 0x92 || dev_priv->chipset == 0xa0) | ||
328 | mc = nv_rd32(dev, NV50_PDISPLAY_SOR_MODE_CTRL_C(or)); | ||
329 | else | ||
330 | mc = nv_rd32(dev, NV90_PDISPLAY_SOR_MODE_CTRL_C(or)); | ||
331 | |||
332 | switch ((mc & 0x00000f00) >> 8) { | ||
333 | case 8: | ||
334 | case 9: | ||
335 | nv_encoder->dp.mc_unknown = (mc & 0x000f0000) >> 16; | ||
336 | break; | ||
337 | default: | ||
338 | break; | ||
339 | } | ||
340 | |||
341 | if (!nv_encoder->dp.mc_unknown) | ||
342 | nv_encoder->dp.mc_unknown = 5; | ||
343 | } | ||
344 | |||
322 | return 0; | 345 | return 0; |
323 | } | 346 | } |