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path: root/drivers/gpu/drm/nouveau
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Diffstat (limited to 'drivers/gpu/drm/nouveau')
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_object.c36
-rw-r--r--drivers/gpu/drm/nouveau/nv20_graph.c58
2 files changed, 50 insertions, 44 deletions
diff --git a/drivers/gpu/drm/nouveau/nouveau_object.c b/drivers/gpu/drm/nouveau/nouveau_object.c
index 7d86e05ac883..b6bcb254f4ab 100644
--- a/drivers/gpu/drm/nouveau/nouveau_object.c
+++ b/drivers/gpu/drm/nouveau/nouveau_object.c
@@ -229,25 +229,12 @@ nouveau_gpuobj_new(struct drm_device *dev, struct nouveau_channel *chan,
229 * available. 229 * available.
230 */ 230 */
231 if (chan) { 231 if (chan) {
232 if (chan->ramin_heap.ml_entry.next) { 232 NV_DEBUG(dev, "channel heap\n");
233 NV_DEBUG(dev, "private heap\n"); 233 pramin = &chan->ramin_heap;
234 pramin = &chan->ramin_heap;
235 } else
236 if (dev_priv->card_type < NV_50) {
237 NV_DEBUG(dev, "global heap fallback\n");
238 pramin = &dev_priv->ramin_heap;
239 }
240 } else { 234 } else {
241 NV_DEBUG(dev, "global heap\n"); 235 NV_DEBUG(dev, "global heap\n");
242 pramin = &dev_priv->ramin_heap; 236 pramin = &dev_priv->ramin_heap;
243 }
244
245 if (!pramin) {
246 NV_ERROR(dev, "No PRAMIN heap!\n");
247 return -EINVAL;
248 }
249 237
250 if (!chan) {
251 ret = engine->instmem.populate(dev, gpuobj, &size); 238 ret = engine->instmem.populate(dev, gpuobj, &size);
252 if (ret) { 239 if (ret) {
253 nouveau_gpuobj_del(dev, &gpuobj); 240 nouveau_gpuobj_del(dev, &gpuobj);
@@ -911,6 +898,7 @@ nouveau_gpuobj_channel_init_pramin(struct nouveau_channel *chan)
911 base = 0; 898 base = 0;
912 899
913 /* PGRAPH context */ 900 /* PGRAPH context */
901 size += dev_priv->engine.graph.grctx_size;
914 902
915 if (dev_priv->card_type == NV_50) { 903 if (dev_priv->card_type == NV_50) {
916 /* Various fixed table thingos */ 904 /* Various fixed table thingos */
@@ -921,12 +909,8 @@ nouveau_gpuobj_channel_init_pramin(struct nouveau_channel *chan)
921 size += 0x8000; 909 size += 0x8000;
922 /* RAMFC */ 910 /* RAMFC */
923 size += 0x1000; 911 size += 0x1000;
924 /* PGRAPH context */
925 size += 0x70000;
926 } 912 }
927 913
928 NV_DEBUG(dev, "ch%d PRAMIN size: 0x%08x bytes, base alloc=0x%08x\n",
929 chan->id, size, base);
930 ret = nouveau_gpuobj_new_ref(dev, NULL, NULL, 0, size, 0x1000, 0, 914 ret = nouveau_gpuobj_new_ref(dev, NULL, NULL, 0, size, 0x1000, 0,
931 &chan->ramin); 915 &chan->ramin);
932 if (ret) { 916 if (ret) {
@@ -959,15 +943,11 @@ nouveau_gpuobj_channel_init(struct nouveau_channel *chan,
959 943
960 NV_DEBUG(dev, "ch%d vram=0x%08x tt=0x%08x\n", chan->id, vram_h, tt_h); 944 NV_DEBUG(dev, "ch%d vram=0x%08x tt=0x%08x\n", chan->id, vram_h, tt_h);
961 945
962 /* Reserve a block of PRAMIN for the channel 946 /* Allocate a chunk of memory for per-channel object storage */
963 *XXX: maybe on <NV50 too at some point 947 ret = nouveau_gpuobj_channel_init_pramin(chan);
964 */ 948 if (ret) {
965 if (0 || dev_priv->card_type == NV_50) { 949 NV_ERROR(dev, "init pramin\n");
966 ret = nouveau_gpuobj_channel_init_pramin(chan); 950 return ret;
967 if (ret) {
968 NV_ERROR(dev, "init pramin\n");
969 return ret;
970 }
971 } 951 }
972 952
973 /* NV50 VM 953 /* NV50 VM
diff --git a/drivers/gpu/drm/nouveau/nv20_graph.c b/drivers/gpu/drm/nouveau/nv20_graph.c
index f3e6dd70d22e..0c776ee81e85 100644
--- a/drivers/gpu/drm/nouveau/nv20_graph.c
+++ b/drivers/gpu/drm/nouveau/nv20_graph.c
@@ -370,53 +370,42 @@ nv20_graph_create_context(struct nouveau_channel *chan)
370{ 370{
371 struct drm_device *dev = chan->dev; 371 struct drm_device *dev = chan->dev;
372 struct drm_nouveau_private *dev_priv = dev->dev_private; 372 struct drm_nouveau_private *dev_priv = dev->dev_private;
373 struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph;
373 void (*ctx_init)(struct drm_device *, struct nouveau_gpuobj *); 374 void (*ctx_init)(struct drm_device *, struct nouveau_gpuobj *);
374 unsigned int ctx_size;
375 unsigned int idoffs = 0x28/4; 375 unsigned int idoffs = 0x28/4;
376 int ret; 376 int ret;
377 377
378 switch (dev_priv->chipset) { 378 switch (dev_priv->chipset) {
379 case 0x20: 379 case 0x20:
380 ctx_size = NV20_GRCTX_SIZE;
381 ctx_init = nv20_graph_context_init; 380 ctx_init = nv20_graph_context_init;
382 idoffs = 0; 381 idoffs = 0;
383 break; 382 break;
384 case 0x25: 383 case 0x25:
385 case 0x28: 384 case 0x28:
386 ctx_size = NV25_GRCTX_SIZE;
387 ctx_init = nv25_graph_context_init; 385 ctx_init = nv25_graph_context_init;
388 break; 386 break;
389 case 0x2a: 387 case 0x2a:
390 ctx_size = NV2A_GRCTX_SIZE;
391 ctx_init = nv2a_graph_context_init; 388 ctx_init = nv2a_graph_context_init;
392 idoffs = 0; 389 idoffs = 0;
393 break; 390 break;
394 case 0x30: 391 case 0x30:
395 case 0x31: 392 case 0x31:
396 ctx_size = NV30_31_GRCTX_SIZE;
397 ctx_init = nv30_31_graph_context_init; 393 ctx_init = nv30_31_graph_context_init;
398 break; 394 break;
399 case 0x34: 395 case 0x34:
400 ctx_size = NV34_GRCTX_SIZE;
401 ctx_init = nv34_graph_context_init; 396 ctx_init = nv34_graph_context_init;
402 break; 397 break;
403 case 0x35: 398 case 0x35:
404 case 0x36: 399 case 0x36:
405 ctx_size = NV35_36_GRCTX_SIZE;
406 ctx_init = nv35_36_graph_context_init; 400 ctx_init = nv35_36_graph_context_init;
407 break; 401 break;
408 default: 402 default:
409 ctx_size = 0; 403 BUG_ON(1);
410 ctx_init = nv35_36_graph_context_init;
411 NV_ERROR(dev, "Please contact the devs if you want your NV%x"
412 " card to work\n", dev_priv->chipset);
413 return -ENOSYS;
414 break;
415 } 404 }
416 405
417 ret = nouveau_gpuobj_new_ref(dev, chan, NULL, 0, ctx_size, 16, 406 ret = nouveau_gpuobj_new_ref(dev, chan, NULL, 0, pgraph->grctx_size,
418 NVOBJ_FLAG_ZERO_ALLOC, 407 16, NVOBJ_FLAG_ZERO_ALLOC,
419 &chan->ramin_grctx); 408 &chan->ramin_grctx);
420 if (ret) 409 if (ret)
421 return ret; 410 return ret;
422 411
@@ -535,9 +524,27 @@ nv20_graph_init(struct drm_device *dev)
535{ 524{
536 struct drm_nouveau_private *dev_priv = 525 struct drm_nouveau_private *dev_priv =
537 (struct drm_nouveau_private *)dev->dev_private; 526 (struct drm_nouveau_private *)dev->dev_private;
527 struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph;
538 uint32_t tmp, vramsz; 528 uint32_t tmp, vramsz;
539 int ret, i; 529 int ret, i;
540 530
531 switch (dev_priv->chipset) {
532 case 0x20:
533 pgraph->grctx_size = NV20_GRCTX_SIZE;
534 break;
535 case 0x25:
536 case 0x28:
537 pgraph->grctx_size = NV25_GRCTX_SIZE;
538 break;
539 case 0x2a:
540 pgraph->grctx_size = NV2A_GRCTX_SIZE;
541 break;
542 default:
543 NV_ERROR(dev, "unknown chipset, disabling acceleration\n");
544 pgraph->accel_blocked = true;
545 return 0;
546 }
547
541 nv_wr32(dev, NV03_PMC_ENABLE, 548 nv_wr32(dev, NV03_PMC_ENABLE,
542 nv_rd32(dev, NV03_PMC_ENABLE) & ~NV_PMC_ENABLE_PGRAPH); 549 nv_rd32(dev, NV03_PMC_ENABLE) & ~NV_PMC_ENABLE_PGRAPH);
543 nv_wr32(dev, NV03_PMC_ENABLE, 550 nv_wr32(dev, NV03_PMC_ENABLE,
@@ -647,8 +654,27 @@ int
647nv30_graph_init(struct drm_device *dev) 654nv30_graph_init(struct drm_device *dev)
648{ 655{
649 struct drm_nouveau_private *dev_priv = dev->dev_private; 656 struct drm_nouveau_private *dev_priv = dev->dev_private;
657 struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph;
650 int ret, i; 658 int ret, i;
651 659
660 switch (dev_priv->chipset) {
661 case 0x30:
662 case 0x31:
663 pgraph->grctx_size = NV30_31_GRCTX_SIZE;
664 break;
665 case 0x34:
666 pgraph->grctx_size = NV34_GRCTX_SIZE;
667 break;
668 case 0x35:
669 case 0x36:
670 pgraph->grctx_size = NV35_36_GRCTX_SIZE;
671 break;
672 default:
673 NV_ERROR(dev, "unknown chipset, disabling acceleration\n");
674 pgraph->accel_blocked = true;
675 return 0;
676 }
677
652 nv_wr32(dev, NV03_PMC_ENABLE, 678 nv_wr32(dev, NV03_PMC_ENABLE,
653 nv_rd32(dev, NV03_PMC_ENABLE) & ~NV_PMC_ENABLE_PGRAPH); 679 nv_rd32(dev, NV03_PMC_ENABLE) & ~NV_PMC_ENABLE_PGRAPH);
654 nv_wr32(dev, NV03_PMC_ENABLE, 680 nv_wr32(dev, NV03_PMC_ENABLE,