1 files changed, 51 insertions, 55 deletions

diff --git a/drivers/gpu/drm/nouveau/nv84_fence.c b/drivers/gpu/drm/nouveau/nv84_fence.c
index 5ef87edb878d..b0d147a675c4 100644
--- a/drivers/gpu/drm/nouveau/nv84_fence.c
+++ b/drivers/gpu/drm/nouveau/nv84_fence.c
@@ -22,13 +22,14 @@
  * Authors: Ben Skeggs
  */
 
-#include "drmP.h"
-#include "nouveau_drv.h"
-#include "nouveau_dma.h"
+#include <core/object.h>
+#include <core/class.h>
+
 #include <engine/fifo.h>
-#include <core/ramht.h>
+
+#include "nouveau_drm.h"
+#include "nouveau_dma.h"
 #include "nouveau_fence.h"
-#include "nv50_display.h"
 
 struct nv84_fence_chan {
         struct nouveau_fence_chan base;
@@ -43,13 +44,14 @@ static int
 nv84_fence_emit(struct nouveau_fence *fence)
 {
         struct nouveau_channel *chan = fence->channel;
+        struct nouveau_fifo_chan *fifo = (void *)chan->object;
         int ret = RING_SPACE(chan, 7);
         if (ret == 0) {
                 BEGIN_NV04(chan, 0, NV11_SUBCHAN_DMA_SEMAPHORE, 1);
                 OUT_RING  (chan, NvSema);
                 BEGIN_NV04(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 4);
-                OUT_RING  (chan, upper_32_bits(chan->id * 16));
-                OUT_RING  (chan, lower_32_bits(chan->id * 16));
+                OUT_RING  (chan, upper_32_bits(fifo->chid * 16));
+                OUT_RING  (chan, lower_32_bits(fifo->chid * 16));
                 OUT_RING  (chan, fence->sequence);
                 OUT_RING  (chan, NV84_SUBCHAN_SEMAPHORE_TRIGGER_WRITE_LONG);
                 FIRE_RING (chan);
@@ -62,13 +64,14 @@ static int
 nv84_fence_sync(struct nouveau_fence *fence,
                 struct nouveau_channel *prev, struct nouveau_channel *chan)
 {
+        struct nouveau_fifo_chan *fifo = (void *)prev->object;
         int ret = RING_SPACE(chan, 7);
         if (ret == 0) {
                 BEGIN_NV04(chan, 0, NV11_SUBCHAN_DMA_SEMAPHORE, 1);
                 OUT_RING  (chan, NvSema);
                 BEGIN_NV04(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 4);
-                OUT_RING  (chan, upper_32_bits(prev->id * 16));
-                OUT_RING  (chan, lower_32_bits(prev->id * 16));
+                OUT_RING  (chan, upper_32_bits(fifo->chid * 16));
+                OUT_RING  (chan, lower_32_bits(fifo->chid * 16));
                 OUT_RING  (chan, fence->sequence);
                 OUT_RING  (chan, NV84_SUBCHAN_SEMAPHORE_TRIGGER_ACQUIRE_GEQUAL);
                 FIRE_RING (chan);
@@ -79,9 +82,9 @@ nv84_fence_sync(struct nouveau_fence *fence,
 static u32
 nv84_fence_read(struct nouveau_channel *chan)
 {
-        struct drm_nouveau_private *dev_priv = chan->dev->dev_private;
-        struct nv84_fence_priv *priv = dev_priv->fence.func;
-        return nv_ro32(priv->mem, chan->id * 16);
+        struct nouveau_fifo_chan *fifo = (void *)chan->object;
+        struct nv84_fence_priv *priv = chan->drm->fence;
+        return nv_ro32(priv->mem, fifo->chid * 16);
 }
 
 static void
@@ -96,10 +99,10 @@ nv84_fence_context_del(struct nouveau_channel *chan)
 static int
 nv84_fence_context_new(struct nouveau_channel *chan)
 {
-        struct drm_nouveau_private *dev_priv = chan->dev->dev_private;
-        struct nv84_fence_priv *priv = dev_priv->fence.func;
+        struct nouveau_fifo_chan *fifo = (void *)chan->object;
+        struct nv84_fence_priv *priv = chan->drm->fence;
         struct nv84_fence_chan *fctx;
-        struct nouveau_gpuobj *obj;
+        struct nouveau_object *object;
         int ret, i;
 
         fctx = chan->fence = kzalloc(sizeof(*fctx), GFP_KERNEL);
@@ -108,58 +111,56 @@ nv84_fence_context_new(struct nouveau_channel *chan)
 
         nouveau_fence_context_new(&fctx->base);
 
-        ret = nouveau_gpuobj_dma_new(chan, NV_CLASS_DMA_FROM_MEMORY,
-                                     priv->mem->addr, priv->mem->size,
-                                     NV_MEM_ACCESS_RW,
-                                     NV_MEM_TARGET_VRAM, &obj);
-        if (ret == 0) {
-                ret = nouveau_ramht_insert(chan, NvSema, obj);
-                nouveau_gpuobj_ref(NULL, &obj);
-                nv_wo32(priv->mem, chan->id * 16, 0x00000000);
-        }
+        ret = nouveau_object_new(nv_object(chan->cli), chan->handle,
+                                 NvSema, 0x0002,
+                                 &(struct nv_dma_class) {
+                                        .flags = NV_DMA_TARGET_VRAM |
+                                                 NV_DMA_ACCESS_RDWR,
+                                        .start = priv->mem->addr,
+                                        .limit = priv->mem->addr +
+                                                 priv->mem->size - 1,
+                                 }, sizeof(struct nv_dma_class),
+                                 &object);
 
         /* dma objects for display sync channel semaphore blocks */
-        for (i = 0; i < chan->dev->mode_config.num_crtc; i++) {
-                struct nv50_display *pdisp = nv50_display(chan->dev);
-                struct nv50_display_crtc *dispc = &pdisp->crtc[i];
-                struct nouveau_gpuobj *obj = NULL;
-
-                ret = nouveau_gpuobj_dma_new(chan, NV_CLASS_DMA_IN_MEMORY,
-                                             dispc->sem.bo->bo.offset, 0x1000,
-                                             NV_MEM_ACCESS_RW,
-                                             NV_MEM_TARGET_VRAM, &obj);
-                if (ret)
-                        break;
-
-                ret = nouveau_ramht_insert(chan, NvEvoSema0 + i, obj);
-                nouveau_gpuobj_ref(NULL, &obj);
+        for (i = 0; !ret && i < chan->drm->dev->mode_config.num_crtc; i++) {
+                struct nouveau_bo *bo = nv50sema(chan->drm->dev, i);
+
+                ret = nouveau_object_new(nv_object(chan->cli), chan->handle,
+                                         NvEvoSema0 + i, 0x003d,
+                                         &(struct nv_dma_class) {
+                                                .flags = NV_DMA_TARGET_VRAM |
+                                                         NV_DMA_ACCESS_RDWR,
+                                                .start = bo->bo.offset,
+                                                .limit = bo->bo.offset + 0xfff,
+                                         }, sizeof(struct nv_dma_class),
+                                         &object);
         }
 
         if (ret)
                 nv84_fence_context_del(chan);
+        nv_wo32(priv->mem, fifo->chid * 16, 0x00000000);
         return ret;
 }
 
 static void
-nv84_fence_destroy(struct drm_device *dev)
+nv84_fence_destroy(struct nouveau_drm *drm)
 {
-        struct drm_nouveau_private *dev_priv = dev->dev_private;
-        struct nv84_fence_priv *priv = dev_priv->fence.func;
-
+        struct nv84_fence_priv *priv = drm->fence;
         nouveau_gpuobj_ref(NULL, &priv->mem);
-        dev_priv->fence.func = NULL;
+        drm->fence = NULL;
         kfree(priv);
 }
 
 int
-nv84_fence_create(struct drm_device *dev)
+nv84_fence_create(struct nouveau_drm *drm)
 {
-        struct nouveau_fifo_priv *pfifo = nv_engine(dev, NVOBJ_ENGINE_FIFO);
-        struct drm_nouveau_private *dev_priv = dev->dev_private;
+        struct nouveau_fifo *pfifo = nouveau_fifo(drm->device);
         struct nv84_fence_priv *priv;
+        u32 chan = pfifo->max + 1;
         int ret;
 
-        priv = kzalloc(sizeof(*priv), GFP_KERNEL);
+        priv = drm->fence = kzalloc(sizeof(*priv), GFP_KERNEL);
         if (!priv)
                 return -ENOMEM;
 
@@ -169,15 +170,10 @@ nv84_fence_create(struct drm_device *dev)
         priv->base.emit = nv84_fence_emit;
         priv->base.sync = nv84_fence_sync;
         priv->base.read = nv84_fence_read;
-        dev_priv->fence.func = priv;
-
-        ret = nouveau_gpuobj_new(dev, NULL, 16 * pfifo->channels,
-                                 0x1000, 0, &priv->mem);
-        if (ret)
-                goto out;
 
-out:
+        ret = nouveau_gpuobj_new(drm->device, NULL, chan * 16, 0x1000, 0,
+                                &priv->mem);
         if (ret)
-                nv84_fence_destroy(dev);
+                nv84_fence_destroy(drm);
         return ret;
 }