1 files changed, 94 insertions, 41 deletions

diff --git a/drivers/gpu/drm/nouveau/nv84_crypt.c b/drivers/gpu/drm/nouveau/nv84_crypt.c
index fabc7fd30b1d..75b809a51748 100644
--- a/drivers/gpu/drm/nouveau/nv84_crypt.c
+++ b/drivers/gpu/drm/nouveau/nv84_crypt.c
@@ -26,46 +26,48 @@
 #include "nouveau_drv.h"
 #include "nouveau_util.h"
 #include "nouveau_vm.h"
+#include "nouveau_ramht.h"
 
-static void nv84_crypt_isr(struct drm_device *);
+struct nv84_crypt_engine {
+        struct nouveau_exec_engine base;
+};
 
-int
-nv84_crypt_create_context(struct nouveau_channel *chan)
+static int
+nv84_crypt_context_new(struct nouveau_channel *chan, int engine)
 {
         struct drm_device *dev = chan->dev;
         struct drm_nouveau_private *dev_priv = dev->dev_private;
         struct nouveau_gpuobj *ramin = chan->ramin;
+        struct nouveau_gpuobj *ctx;
         int ret;
 
         NV_DEBUG(dev, "ch%d\n", chan->id);
 
-        ret = nouveau_gpuobj_new(dev, chan, 256, 0,
-                                 NVOBJ_FLAG_ZERO_ALLOC | NVOBJ_FLAG_ZERO_FREE,
-                                 &chan->crypt_ctx);
+        ret = nouveau_gpuobj_new(dev, chan, 256, 0, NVOBJ_FLAG_ZERO_ALLOC |
+                                 NVOBJ_FLAG_ZERO_FREE, &ctx);
         if (ret)
                 return ret;
 
         nv_wo32(ramin, 0xa0, 0x00190000);
-        nv_wo32(ramin, 0xa4, chan->crypt_ctx->vinst + 0xff);
-        nv_wo32(ramin, 0xa8, chan->crypt_ctx->vinst);
+        nv_wo32(ramin, 0xa4, ctx->vinst + ctx->size - 1);
+        nv_wo32(ramin, 0xa8, ctx->vinst);
         nv_wo32(ramin, 0xac, 0);
         nv_wo32(ramin, 0xb0, 0);
         nv_wo32(ramin, 0xb4, 0);
-
         dev_priv->engine.instmem.flush(dev);
-        atomic_inc(&chan->vm->pcrypt_refs);
+
+        atomic_inc(&chan->vm->engref[engine]);
+        chan->engctx[engine] = ctx;
         return 0;
 }
 
-void
-nv84_crypt_destroy_context(struct nouveau_channel *chan)
+static void
+nv84_crypt_context_del(struct nouveau_channel *chan, int engine)
 {
+        struct nouveau_gpuobj *ctx = chan->engctx[engine];
         struct drm_device *dev = chan->dev;
         u32 inst;
 
-        if (!chan->crypt_ctx)
-                return;
-
         inst  = (chan->ramin->vinst >> 12);
         inst |= 0x80000000;
 
@@ -80,43 +82,39 @@ nv84_crypt_destroy_context(struct nouveau_channel *chan)
                 nv_mask(dev, 0x10218c, 0x80000000, 0x00000000);
         nv_wr32(dev, 0x10200c, 0x00000010);
 
-        nouveau_gpuobj_ref(NULL, &chan->crypt_ctx);
-        atomic_dec(&chan->vm->pcrypt_refs);
-}
+        nouveau_gpuobj_ref(NULL, &ctx);
 
-void
-nv84_crypt_tlb_flush(struct drm_device *dev)
-{
-        nv50_vm_flush_engine(dev, 0x0a);
+        atomic_dec(&chan->vm->engref[engine]);
+        chan->engctx[engine] = NULL;
 }
 
-int
-nv84_crypt_init(struct drm_device *dev)
+static int
+nv84_crypt_object_new(struct nouveau_channel *chan, int engine,
+                      u32 handle, u16 class)
 {
+        struct drm_device *dev = chan->dev;
         struct drm_nouveau_private *dev_priv = dev->dev_private;
-        struct nouveau_crypt_engine *pcrypt = &dev_priv->engine.crypt;
-
-        if (!pcrypt->registered) {
-                NVOBJ_CLASS(dev, 0x74c1, CRYPT);
-                pcrypt->registered = true;
-        }
+        struct nouveau_gpuobj *obj = NULL;
+        int ret;
 
-        nv_mask(dev, 0x000200, 0x00004000, 0x00000000);
-        nv_mask(dev, 0x000200, 0x00004000, 0x00004000);
+        ret = nouveau_gpuobj_new(dev, chan, 16, 16, NVOBJ_FLAG_ZERO_FREE, &obj);
+        if (ret)
+                return ret;
+        obj->engine = 5;
+        obj->class  = class;
 
-        nouveau_irq_register(dev, 14, nv84_crypt_isr);
-        nv_wr32(dev, 0x102130, 0xffffffff);
-        nv_wr32(dev, 0x102140, 0xffffffbf);
+        nv_wo32(obj, 0x00, class);
+        dev_priv->engine.instmem.flush(dev);
 
-        nv_wr32(dev, 0x10200c, 0x00000010);
-        return 0;
+        ret = nouveau_ramht_insert(chan, handle, obj);
+        nouveau_gpuobj_ref(NULL, &obj);
+        return ret;
 }
 
-void
-nv84_crypt_fini(struct drm_device *dev)
+static void
+nv84_crypt_tlb_flush(struct drm_device *dev, int engine)
 {
-        nv_wr32(dev, 0x102140, 0x00000000);
-        nouveau_irq_unregister(dev, 14);
+        nv50_vm_flush_engine(dev, 0x0a);
 }
 
 static void
@@ -138,3 +136,58 @@ nv84_crypt_isr(struct drm_device *dev)
 
         nv50_fb_vm_trap(dev, show);
 }
+
+static int
+nv84_crypt_fini(struct drm_device *dev, int engine)
+{
+        nv_wr32(dev, 0x102140, 0x00000000);
+        return 0;
+}
+
+static int
+nv84_crypt_init(struct drm_device *dev, int engine)
+{
+        nv_mask(dev, 0x000200, 0x00004000, 0x00000000);
+        nv_mask(dev, 0x000200, 0x00004000, 0x00004000);
+
+        nv_wr32(dev, 0x102130, 0xffffffff);
+        nv_wr32(dev, 0x102140, 0xffffffbf);
+
+        nv_wr32(dev, 0x10200c, 0x00000010);
+        return 0;
+}
+
+static void
+nv84_crypt_destroy(struct drm_device *dev, int engine)
+{
+        struct nv84_crypt_engine *pcrypt = nv_engine(dev, engine);
+
+        NVOBJ_ENGINE_DEL(dev, CRYPT);
+
+        nouveau_irq_unregister(dev, 14);
+        kfree(pcrypt);
+}
+
+int
+nv84_crypt_create(struct drm_device *dev)
+{
+        struct nv84_crypt_engine *pcrypt;
+
+        pcrypt = kzalloc(sizeof(*pcrypt), GFP_KERNEL);
+        if (!pcrypt)
+                return -ENOMEM;
+
+        pcrypt->base.destroy = nv84_crypt_destroy;
+        pcrypt->base.init = nv84_crypt_init;
+        pcrypt->base.fini = nv84_crypt_fini;
+        pcrypt->base.context_new = nv84_crypt_context_new;
+        pcrypt->base.context_del = nv84_crypt_context_del;
+        pcrypt->base.object_new = nv84_crypt_object_new;
+        pcrypt->base.tlb_flush = nv84_crypt_tlb_flush;
+
+        nouveau_irq_register(dev, 14, nv84_crypt_isr);
+
+        NVOBJ_ENGINE_ADD(dev, CRYPT, &pcrypt->base);
+        NVOBJ_CLASS (dev, 0x74c1, CRYPT);
+        return 0;
+}