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path: root/drivers/gpu/drm/nouveau/nv50_vm.c
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Diffstat (limited to 'drivers/gpu/drm/nouveau/nv50_vm.c')
-rw-r--r--drivers/gpu/drm/nouveau/nv50_vm.c180
1 files changed, 180 insertions, 0 deletions
diff --git a/drivers/gpu/drm/nouveau/nv50_vm.c b/drivers/gpu/drm/nouveau/nv50_vm.c
new file mode 100644
index 000000000000..38e523e10995
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/nv50_vm.c
@@ -0,0 +1,180 @@
1/*
2 * Copyright 2010 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs
23 */
24
25#include "drmP.h"
26
27#include "nouveau_drv.h"
28#include "nouveau_vm.h"
29
30void
31nv50_vm_map_pgt(struct nouveau_gpuobj *pgd, u32 pde,
32 struct nouveau_gpuobj *pgt[2])
33{
34 struct drm_nouveau_private *dev_priv = pgd->dev->dev_private;
35 u64 phys = 0xdeadcafe00000000ULL;
36 u32 coverage = 0;
37
38 if (pgt[0]) {
39 phys = 0x00000003 | pgt[0]->vinst; /* present, 4KiB pages */
40 coverage = (pgt[0]->size >> 3) << 12;
41 } else
42 if (pgt[1]) {
43 phys = 0x00000001 | pgt[1]->vinst; /* present */
44 coverage = (pgt[1]->size >> 3) << 16;
45 }
46
47 if (phys & 1) {
48 if (dev_priv->vram_sys_base) {
49 phys += dev_priv->vram_sys_base;
50 phys |= 0x30;
51 }
52
53 if (coverage <= 32 * 1024 * 1024)
54 phys |= 0x60;
55 else if (coverage <= 64 * 1024 * 1024)
56 phys |= 0x40;
57 else if (coverage < 128 * 1024 * 1024)
58 phys |= 0x20;
59 }
60
61 nv_wo32(pgd, (pde * 8) + 0, lower_32_bits(phys));
62 nv_wo32(pgd, (pde * 8) + 4, upper_32_bits(phys));
63}
64
65static inline u64
66nv50_vm_addr(struct nouveau_vma *vma, struct nouveau_gpuobj *pgt,
67 u64 phys, u32 memtype, u32 target)
68{
69 struct drm_nouveau_private *dev_priv = pgt->dev->dev_private;
70
71 phys |= 1; /* present */
72 phys |= (u64)memtype << 40;
73
74 /* IGPs don't have real VRAM, re-target to stolen system memory */
75 if (target == 0 && dev_priv->vram_sys_base) {
76 phys += dev_priv->vram_sys_base;
77 target = 3;
78 }
79
80 phys |= target << 4;
81
82 if (vma->access & NV_MEM_ACCESS_SYS)
83 phys |= (1 << 6);
84
85 if (!(vma->access & NV_MEM_ACCESS_WO))
86 phys |= (1 << 3);
87
88 return phys;
89}
90
91void
92nv50_vm_map(struct nouveau_vma *vma, struct nouveau_gpuobj *pgt,
93 struct nouveau_vram *mem, u32 pte, u32 cnt, u64 phys)
94{
95 u32 block;
96 int i;
97
98 phys = nv50_vm_addr(vma, pgt, phys, mem->memtype, 0);
99 pte <<= 3;
100 cnt <<= 3;
101
102 while (cnt) {
103 u32 offset_h = upper_32_bits(phys);
104 u32 offset_l = lower_32_bits(phys);
105
106 for (i = 7; i >= 0; i--) {
107 block = 1 << (i + 3);
108 if (cnt >= block && !(pte & (block - 1)))
109 break;
110 }
111 offset_l |= (i << 7);
112
113 phys += block << (vma->node->type - 3);
114 cnt -= block;
115
116 while (block) {
117 nv_wo32(pgt, pte + 0, offset_l);
118 nv_wo32(pgt, pte + 4, offset_h);
119 pte += 8;
120 block -= 8;
121 }
122 }
123}
124
125void
126nv50_vm_map_sg(struct nouveau_vma *vma, struct nouveau_gpuobj *pgt,
127 u32 pte, dma_addr_t *list, u32 cnt)
128{
129 pte <<= 3;
130 while (cnt--) {
131 u64 phys = nv50_vm_addr(vma, pgt, (u64)*list++, 0, 2);
132 nv_wo32(pgt, pte + 0, lower_32_bits(phys));
133 nv_wo32(pgt, pte + 4, upper_32_bits(phys));
134 pte += 8;
135 }
136}
137
138void
139nv50_vm_unmap(struct nouveau_gpuobj *pgt, u32 pte, u32 cnt)
140{
141 pte <<= 3;
142 while (cnt--) {
143 nv_wo32(pgt, pte + 0, 0x00000000);
144 nv_wo32(pgt, pte + 4, 0x00000000);
145 pte += 8;
146 }
147}
148
149void
150nv50_vm_flush(struct nouveau_vm *vm)
151{
152 struct drm_nouveau_private *dev_priv = vm->dev->dev_private;
153 struct nouveau_instmem_engine *pinstmem = &dev_priv->engine.instmem;
154 struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo;
155 struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph;
156 struct nouveau_crypt_engine *pcrypt = &dev_priv->engine.crypt;
157
158 pinstmem->flush(vm->dev);
159
160 /* BAR */
161 if (vm != dev_priv->chan_vm) {
162 nv50_vm_flush_engine(vm->dev, 6);
163 return;
164 }
165
166 pfifo->tlb_flush(vm->dev);
167
168 if (atomic_read(&vm->pgraph_refs))
169 pgraph->tlb_flush(vm->dev);
170 if (atomic_read(&vm->pcrypt_refs))
171 pcrypt->tlb_flush(vm->dev);
172}
173
174void
175nv50_vm_flush_engine(struct drm_device *dev, int engine)
176{
177 nv_wr32(dev, 0x100c80, (engine << 16) | 1);
178 if (!nv_wait(dev, 0x100c80, 0x00000001, 0x00000000))
179 NV_ERROR(dev, "vm flush timeout: engine %d\n", engine);
180}
generated by cgit v1.2.2 (git 2.25.0) at 2025-10-10 19:41:59 -0400