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path: root/drivers/gpu/drm/nouveau/nv50_fbcon.c
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Diffstat (limited to 'drivers/gpu/drm/nouveau/nv50_fbcon.c')
-rw-r--r--drivers/gpu/drm/nouveau/nv50_fbcon.c273
1 files changed, 273 insertions, 0 deletions
diff --git a/drivers/gpu/drm/nouveau/nv50_fbcon.c b/drivers/gpu/drm/nouveau/nv50_fbcon.c
new file mode 100644
index 000000000000..6bcc6d39e9b0
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/nv50_fbcon.c
@@ -0,0 +1,273 @@
1#include "drmP.h"
2#include "nouveau_drv.h"
3#include "nouveau_dma.h"
4#include "nouveau_fbcon.h"
5
6static void
7nv50_fbcon_fillrect(struct fb_info *info, const struct fb_fillrect *rect)
8{
9 struct nouveau_fbcon_par *par = info->par;
10 struct drm_device *dev = par->dev;
11 struct drm_nouveau_private *dev_priv = dev->dev_private;
12 struct nouveau_channel *chan = dev_priv->channel;
13
14 if (info->state != FBINFO_STATE_RUNNING)
15 return;
16
17 if (!(info->flags & FBINFO_HWACCEL_DISABLED) &&
18 RING_SPACE(chan, rect->rop == ROP_COPY ? 7 : 11)) {
19 NV_ERROR(dev, "GPU lockup - switching to software fbcon\n");
20
21 info->flags |= FBINFO_HWACCEL_DISABLED;
22 }
23
24 if (info->flags & FBINFO_HWACCEL_DISABLED) {
25 cfb_fillrect(info, rect);
26 return;
27 }
28
29 if (rect->rop != ROP_COPY) {
30 BEGIN_RING(chan, NvSub2D, 0x02ac, 1);
31 OUT_RING(chan, 1);
32 }
33 BEGIN_RING(chan, NvSub2D, 0x0588, 1);
34 OUT_RING(chan, rect->color);
35 BEGIN_RING(chan, NvSub2D, 0x0600, 4);
36 OUT_RING(chan, rect->dx);
37 OUT_RING(chan, rect->dy);
38 OUT_RING(chan, rect->dx + rect->width);
39 OUT_RING(chan, rect->dy + rect->height);
40 if (rect->rop != ROP_COPY) {
41 BEGIN_RING(chan, NvSub2D, 0x02ac, 1);
42 OUT_RING(chan, 3);
43 }
44 FIRE_RING(chan);
45}
46
47static void
48nv50_fbcon_copyarea(struct fb_info *info, const struct fb_copyarea *region)
49{
50 struct nouveau_fbcon_par *par = info->par;
51 struct drm_device *dev = par->dev;
52 struct drm_nouveau_private *dev_priv = dev->dev_private;
53 struct nouveau_channel *chan = dev_priv->channel;
54
55 if (info->state != FBINFO_STATE_RUNNING)
56 return;
57
58 if (!(info->flags & FBINFO_HWACCEL_DISABLED) && RING_SPACE(chan, 12)) {
59 NV_ERROR(dev, "GPU lockup - switching to software fbcon\n");
60
61 info->flags |= FBINFO_HWACCEL_DISABLED;
62 }
63
64 if (info->flags & FBINFO_HWACCEL_DISABLED) {
65 cfb_copyarea(info, region);
66 return;
67 }
68
69 BEGIN_RING(chan, NvSub2D, 0x0110, 1);
70 OUT_RING(chan, 0);
71 BEGIN_RING(chan, NvSub2D, 0x08b0, 4);
72 OUT_RING(chan, region->dx);
73 OUT_RING(chan, region->dy);
74 OUT_RING(chan, region->width);
75 OUT_RING(chan, region->height);
76 BEGIN_RING(chan, NvSub2D, 0x08d0, 4);
77 OUT_RING(chan, 0);
78 OUT_RING(chan, region->sx);
79 OUT_RING(chan, 0);
80 OUT_RING(chan, region->sy);
81 FIRE_RING(chan);
82}
83
84static void
85nv50_fbcon_imageblit(struct fb_info *info, const struct fb_image *image)
86{
87 struct nouveau_fbcon_par *par = info->par;
88 struct drm_device *dev = par->dev;
89 struct drm_nouveau_private *dev_priv = dev->dev_private;
90 struct nouveau_channel *chan = dev_priv->channel;
91 uint32_t width, dwords, *data = (uint32_t *)image->data;
92 uint32_t mask = ~(~0 >> (32 - info->var.bits_per_pixel));
93 uint32_t *palette = info->pseudo_palette;
94
95 if (info->state != FBINFO_STATE_RUNNING)
96 return;
97
98 if (image->depth != 1) {
99 cfb_imageblit(info, image);
100 return;
101 }
102
103 if (!(info->flags & FBINFO_HWACCEL_DISABLED) && RING_SPACE(chan, 11)) {
104 NV_ERROR(dev, "GPU lockup - switching to software fbcon\n");
105 info->flags |= FBINFO_HWACCEL_DISABLED;
106 }
107
108 if (info->flags & FBINFO_HWACCEL_DISABLED) {
109 cfb_imageblit(info, image);
110 return;
111 }
112
113 width = (image->width + 31) & ~31;
114 dwords = (width * image->height) >> 5;
115
116 BEGIN_RING(chan, NvSub2D, 0x0814, 2);
117 if (info->fix.visual == FB_VISUAL_TRUECOLOR ||
118 info->fix.visual == FB_VISUAL_DIRECTCOLOR) {
119 OUT_RING(chan, palette[image->bg_color] | mask);
120 OUT_RING(chan, palette[image->fg_color] | mask);
121 } else {
122 OUT_RING(chan, image->bg_color);
123 OUT_RING(chan, image->fg_color);
124 }
125 BEGIN_RING(chan, NvSub2D, 0x0838, 2);
126 OUT_RING(chan, image->width);
127 OUT_RING(chan, image->height);
128 BEGIN_RING(chan, NvSub2D, 0x0850, 4);
129 OUT_RING(chan, 0);
130 OUT_RING(chan, image->dx);
131 OUT_RING(chan, 0);
132 OUT_RING(chan, image->dy);
133
134 while (dwords) {
135 int push = dwords > 2047 ? 2047 : dwords;
136
137 if (RING_SPACE(chan, push + 1)) {
138 NV_ERROR(dev,
139 "GPU lockup - switching to software fbcon\n");
140 info->flags |= FBINFO_HWACCEL_DISABLED;
141 cfb_imageblit(info, image);
142 return;
143 }
144
145 dwords -= push;
146
147 BEGIN_RING(chan, NvSub2D, 0x40000860, push);
148 OUT_RINGp(chan, data, push);
149 data += push;
150 }
151
152 FIRE_RING(chan);
153}
154
155int
156nv50_fbcon_accel_init(struct fb_info *info)
157{
158 struct nouveau_fbcon_par *par = info->par;
159 struct drm_device *dev = par->dev;
160 struct drm_nouveau_private *dev_priv = dev->dev_private;
161 struct nouveau_channel *chan = dev_priv->channel;
162 struct nouveau_gpuobj *eng2d = NULL;
163 int ret, format;
164
165 switch (info->var.bits_per_pixel) {
166 case 8:
167 format = 0xf3;
168 break;
169 case 15:
170 format = 0xf8;
171 break;
172 case 16:
173 format = 0xe8;
174 break;
175 case 32:
176 switch (info->var.transp.length) {
177 case 0: /* depth 24 */
178 case 8: /* depth 32, just use 24.. */
179 format = 0xe6;
180 break;
181 case 2: /* depth 30 */
182 format = 0xd1;
183 break;
184 default:
185 return -EINVAL;
186 }
187 break;
188 default:
189 return -EINVAL;
190 }
191
192 ret = nouveau_gpuobj_gr_new(dev_priv->channel, 0x502d, &eng2d);
193 if (ret)
194 return ret;
195
196 ret = nouveau_gpuobj_ref_add(dev, dev_priv->channel, Nv2D, eng2d, NULL);
197 if (ret)
198 return ret;
199
200 ret = RING_SPACE(chan, 59);
201 if (ret) {
202 NV_ERROR(dev, "GPU lockup - switching to software fbcon\n");
203 return ret;
204 }
205
206 BEGIN_RING(chan, NvSub2D, 0x0000, 1);
207 OUT_RING(chan, Nv2D);
208 BEGIN_RING(chan, NvSub2D, 0x0180, 4);
209 OUT_RING(chan, NvNotify0);
210 OUT_RING(chan, chan->vram_handle);
211 OUT_RING(chan, chan->vram_handle);
212 OUT_RING(chan, chan->vram_handle);
213 BEGIN_RING(chan, NvSub2D, 0x0290, 1);
214 OUT_RING(chan, 0);
215 BEGIN_RING(chan, NvSub2D, 0x0888, 1);
216 OUT_RING(chan, 1);
217 BEGIN_RING(chan, NvSub2D, 0x02ac, 1);
218 OUT_RING(chan, 3);
219 BEGIN_RING(chan, NvSub2D, 0x02a0, 1);
220 OUT_RING(chan, 0x55);
221 BEGIN_RING(chan, NvSub2D, 0x08c0, 4);
222 OUT_RING(chan, 0);
223 OUT_RING(chan, 1);
224 OUT_RING(chan, 0);
225 OUT_RING(chan, 1);
226 BEGIN_RING(chan, NvSub2D, 0x0580, 2);
227 OUT_RING(chan, 4);
228 OUT_RING(chan, format);
229 BEGIN_RING(chan, NvSub2D, 0x02e8, 2);
230 OUT_RING(chan, 2);
231 OUT_RING(chan, 1);
232 BEGIN_RING(chan, NvSub2D, 0x0804, 1);
233 OUT_RING(chan, format);
234 BEGIN_RING(chan, NvSub2D, 0x0800, 1);
235 OUT_RING(chan, 1);
236 BEGIN_RING(chan, NvSub2D, 0x0808, 3);
237 OUT_RING(chan, 0);
238 OUT_RING(chan, 0);
239 OUT_RING(chan, 0);
240 BEGIN_RING(chan, NvSub2D, 0x081c, 1);
241 OUT_RING(chan, 1);
242 BEGIN_RING(chan, NvSub2D, 0x0840, 4);
243 OUT_RING(chan, 0);
244 OUT_RING(chan, 1);
245 OUT_RING(chan, 0);
246 OUT_RING(chan, 1);
247 BEGIN_RING(chan, NvSub2D, 0x0200, 2);
248 OUT_RING(chan, format);
249 OUT_RING(chan, 1);
250 BEGIN_RING(chan, NvSub2D, 0x0214, 5);
251 OUT_RING(chan, info->fix.line_length);
252 OUT_RING(chan, info->var.xres_virtual);
253 OUT_RING(chan, info->var.yres_virtual);
254 OUT_RING(chan, 0);
255 OUT_RING(chan, info->fix.smem_start - dev_priv->fb_phys +
256 dev_priv->vm_vram_base);
257 BEGIN_RING(chan, NvSub2D, 0x0230, 2);
258 OUT_RING(chan, format);
259 OUT_RING(chan, 1);
260 BEGIN_RING(chan, NvSub2D, 0x0244, 5);
261 OUT_RING(chan, info->fix.line_length);
262 OUT_RING(chan, info->var.xres_virtual);
263 OUT_RING(chan, info->var.yres_virtual);
264 OUT_RING(chan, 0);
265 OUT_RING(chan, info->fix.smem_start - dev_priv->fb_phys +
266 dev_priv->vm_vram_base);
267
268 info->fbops->fb_fillrect = nv50_fbcon_fillrect;
269 info->fbops->fb_copyarea = nv50_fbcon_copyarea;
270 info->fbops->fb_imageblit = nv50_fbcon_imageblit;
271 return 0;
272}
273
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-01 01:36:30 -0400