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path: root/drivers/gpu/drm/nouveau/nv50_display.c
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Diffstat (limited to 'drivers/gpu/drm/nouveau/nv50_display.c')
-rw-r--r--drivers/gpu/drm/nouveau/nv50_display.c22
1 files changed, 14 insertions, 8 deletions
diff --git a/drivers/gpu/drm/nouveau/nv50_display.c b/drivers/gpu/drm/nouveau/nv50_display.c
index fac6c88a2b1f..649db4c1b690 100644
--- a/drivers/gpu/drm/nouveau/nv50_display.c
+++ b/drivers/gpu/drm/nouveau/nv50_display.c
@@ -143,7 +143,7 @@ nv50_evo_channel_new(struct drm_device *dev, struct nouveau_channel **pchan)
143 } 143 }
144 144
145 ret = nv50_evo_dmaobj_new(chan, 0x3d, NvEvoVRAM, 0, 0x19, 145 ret = nv50_evo_dmaobj_new(chan, 0x3d, NvEvoVRAM, 0, 0x19,
146 0, nouveau_mem_fb_amount(dev)); 146 0, dev_priv->vram_size);
147 if (ret) { 147 if (ret) {
148 nv50_evo_channel_del(pchan); 148 nv50_evo_channel_del(pchan);
149 return ret; 149 return ret;
@@ -231,7 +231,7 @@ nv50_display_init(struct drm_device *dev)
231 /* This used to be in crtc unblank, but seems out of place there. */ 231 /* This used to be in crtc unblank, but seems out of place there. */
232 nv_wr32(dev, NV50_PDISPLAY_UNK_380, 0); 232 nv_wr32(dev, NV50_PDISPLAY_UNK_380, 0);
233 /* RAM is clamped to 256 MiB. */ 233 /* RAM is clamped to 256 MiB. */
234 ram_amount = nouveau_mem_fb_amount(dev); 234 ram_amount = dev_priv->vram_size;
235 NV_DEBUG_KMS(dev, "ram_amount %d\n", ram_amount); 235 NV_DEBUG_KMS(dev, "ram_amount %d\n", ram_amount);
236 if (ram_amount > 256*1024*1024) 236 if (ram_amount > 256*1024*1024)
237 ram_amount = 256*1024*1024; 237 ram_amount = 256*1024*1024;
@@ -529,8 +529,10 @@ int nv50_display_create(struct drm_device *dev)
529 } 529 }
530 530
531 ret = nv50_display_init(dev); 531 ret = nv50_display_init(dev);
532 if (ret) 532 if (ret) {
533 nv50_display_destroy(dev);
533 return ret; 534 return ret;
535 }
534 536
535 return 0; 537 return 0;
536} 538}
@@ -885,10 +887,12 @@ nv50_display_error_handler(struct drm_device *dev)
885 nv_wr32(dev, NV50_PDISPLAY_TRAPPED_ADDR, 0x90000000); 887 nv_wr32(dev, NV50_PDISPLAY_TRAPPED_ADDR, 0x90000000);
886} 888}
887 889
888static void 890void
889nv50_display_irq_hotplug(struct drm_device *dev) 891nv50_display_irq_hotplug_bh(struct work_struct *work)
890{ 892{
891 struct drm_nouveau_private *dev_priv = dev->dev_private; 893 struct drm_nouveau_private *dev_priv =
894 container_of(work, struct drm_nouveau_private, hpd_work);
895 struct drm_device *dev = dev_priv->dev;
892 struct drm_connector *connector; 896 struct drm_connector *connector;
893 const uint32_t gpio_reg[4] = { 0xe104, 0xe108, 0xe280, 0xe284 }; 897 const uint32_t gpio_reg[4] = { 0xe104, 0xe108, 0xe280, 0xe284 };
894 uint32_t unplug_mask, plug_mask, change_mask; 898 uint32_t unplug_mask, plug_mask, change_mask;
@@ -949,8 +953,10 @@ nv50_display_irq_handler(struct drm_device *dev)
949 struct drm_nouveau_private *dev_priv = dev->dev_private; 953 struct drm_nouveau_private *dev_priv = dev->dev_private;
950 uint32_t delayed = 0; 954 uint32_t delayed = 0;
951 955
952 while (nv_rd32(dev, NV50_PMC_INTR_0) & NV50_PMC_INTR_0_HOTPLUG) 956 if (nv_rd32(dev, NV50_PMC_INTR_0) & NV50_PMC_INTR_0_HOTPLUG) {
953 nv50_display_irq_hotplug(dev); 957 if (!work_pending(&dev_priv->hpd_work))
958 queue_work(dev_priv->wq, &dev_priv->hpd_work);
959 }
954 960
955 while (nv_rd32(dev, NV50_PMC_INTR_0) & NV50_PMC_INTR_0_DISPLAY) { 961 while (nv_rd32(dev, NV50_PMC_INTR_0) & NV50_PMC_INTR_0_DISPLAY) {
956 uint32_t intr0 = nv_rd32(dev, NV50_PDISPLAY_INTR_0); 962 uint32_t intr0 = nv_rd32(dev, NV50_PDISPLAY_INTR_0);