aboutsummaryrefslogtreecommitdiffstats
path: root/drivers/gpu/drm/nouveau/nv50_display.c
diff options
context:
space:
mode:
Diffstat (limited to 'drivers/gpu/drm/nouveau/nv50_display.c')
-rw-r--r--drivers/gpu/drm/nouveau/nv50_display.c32
1 files changed, 19 insertions, 13 deletions
diff --git a/drivers/gpu/drm/nouveau/nv50_display.c b/drivers/gpu/drm/nouveau/nv50_display.c
index 6f89674ebb96..b65d2ddd415d 100644
--- a/drivers/gpu/drm/nouveau/nv50_display.c
+++ b/drivers/gpu/drm/nouveau/nv50_display.c
@@ -30,6 +30,7 @@
30#include "nouveau_connector.h" 30#include "nouveau_connector.h"
31#include "nouveau_fb.h" 31#include "nouveau_fb.h"
32#include "nouveau_fbcon.h" 32#include "nouveau_fbcon.h"
33#include "nouveau_ramht.h"
33#include "drm_crtc_helper.h" 34#include "drm_crtc_helper.h"
34 35
35static void 36static void
@@ -66,12 +67,6 @@ nv50_evo_dmaobj_new(struct nouveau_channel *evo, uint32_t class, uint32_t name,
66 return ret; 67 return ret;
67 obj->engine = NVOBJ_ENGINE_DISPLAY; 68 obj->engine = NVOBJ_ENGINE_DISPLAY;
68 69
69 ret = nouveau_gpuobj_ref_add(dev, evo, name, obj, NULL);
70 if (ret) {
71 nouveau_gpuobj_del(dev, &obj);
72 return ret;
73 }
74
75 nv_wo32(obj, 0, (tile_flags << 22) | (magic_flags << 16) | class); 70 nv_wo32(obj, 0, (tile_flags << 22) | (magic_flags << 16) | class);
76 nv_wo32(obj, 4, limit); 71 nv_wo32(obj, 4, limit);
77 nv_wo32(obj, 8, offset); 72 nv_wo32(obj, 8, offset);
@@ -83,6 +78,12 @@ nv50_evo_dmaobj_new(struct nouveau_channel *evo, uint32_t class, uint32_t name,
83 nv_wo32(obj, 20, 0x00020000); 78 nv_wo32(obj, 20, 0x00020000);
84 dev_priv->engine.instmem.flush(dev); 79 dev_priv->engine.instmem.flush(dev);
85 80
81 ret = nouveau_ramht_insert(evo, name, obj);
82 nouveau_gpuobj_ref(NULL, &obj);
83 if (ret) {
84 return ret;
85 }
86
86 return 0; 87 return 0;
87} 88}
88 89
@@ -90,6 +91,7 @@ static int
90nv50_evo_channel_new(struct drm_device *dev, struct nouveau_channel **pchan) 91nv50_evo_channel_new(struct drm_device *dev, struct nouveau_channel **pchan)
91{ 92{
92 struct drm_nouveau_private *dev_priv = dev->dev_private; 93 struct drm_nouveau_private *dev_priv = dev->dev_private;
94 struct nouveau_gpuobj *ramht = NULL;
93 struct nouveau_channel *chan; 95 struct nouveau_channel *chan;
94 int ret; 96 int ret;
95 97
@@ -103,10 +105,8 @@ nv50_evo_channel_new(struct drm_device *dev, struct nouveau_channel **pchan)
103 chan->user_get = 4; 105 chan->user_get = 4;
104 chan->user_put = 0; 106 chan->user_put = 0;
105 107
106 INIT_LIST_HEAD(&chan->ramht_refs); 108 ret = nouveau_gpuobj_new(dev, NULL, 32768, 0x1000,
107 109 NVOBJ_FLAG_ZERO_ALLOC, &chan->ramin);
108 ret = nouveau_gpuobj_new_ref(dev, NULL, NULL, 0, 32768, 0x1000,
109 NVOBJ_FLAG_ZERO_ALLOC, &chan->ramin);
110 if (ret) { 110 if (ret) {
111 NV_ERROR(dev, "Error allocating EVO channel memory: %d\n", ret); 111 NV_ERROR(dev, "Error allocating EVO channel memory: %d\n", ret);
112 nv50_evo_channel_del(pchan); 112 nv50_evo_channel_del(pchan);
@@ -120,14 +120,20 @@ nv50_evo_channel_new(struct drm_device *dev, struct nouveau_channel **pchan)
120 return ret; 120 return ret;
121 } 121 }
122 122
123 ret = nouveau_gpuobj_new_ref(dev, chan, chan, 0, 4096, 16, 123 ret = nouveau_gpuobj_new(dev, chan, 4096, 16, 0, &ramht);
124 0, &chan->ramht);
125 if (ret) { 124 if (ret) {
126 NV_ERROR(dev, "Unable to allocate EVO RAMHT: %d\n", ret); 125 NV_ERROR(dev, "Unable to allocate EVO RAMHT: %d\n", ret);
127 nv50_evo_channel_del(pchan); 126 nv50_evo_channel_del(pchan);
128 return ret; 127 return ret;
129 } 128 }
130 129
130 ret = nouveau_ramht_new(dev, ramht, &chan->ramht);
131 nouveau_gpuobj_ref(NULL, &ramht);
132 if (ret) {
133 nv50_evo_channel_del(pchan);
134 return ret;
135 }
136
131 if (dev_priv->chipset != 0x50) { 137 if (dev_priv->chipset != 0x50) {
132 ret = nv50_evo_dmaobj_new(chan, 0x3d, NvEvoFB16, 0x70, 0x19, 138 ret = nv50_evo_dmaobj_new(chan, 0x3d, NvEvoFB16, 0x70, 0x19,
133 0, 0xffffffff); 139 0, 0xffffffff);
@@ -321,7 +327,7 @@ nv50_display_init(struct drm_device *dev)
321 } 327 }
322 } 328 }
323 329
324 nv_wr32(dev, NV50_PDISPLAY_OBJECTS, (evo->ramin->instance >> 8) | 9); 330 nv_wr32(dev, NV50_PDISPLAY_OBJECTS, (evo->ramin->vinst >> 8) | 9);
325 331
326 /* initialise fifo */ 332 /* initialise fifo */
327 nv_wr32(dev, NV50_PDISPLAY_CHANNEL_DMA_CB(0), 333 nv_wr32(dev, NV50_PDISPLAY_CHANNEL_DMA_CB(0),