diff options
Diffstat (limited to 'drivers/gpu/drm/nouveau/nv50_display.c')
-rw-r--r-- | drivers/gpu/drm/nouveau/nv50_display.c | 50 |
1 files changed, 25 insertions, 25 deletions
diff --git a/drivers/gpu/drm/nouveau/nv50_display.c b/drivers/gpu/drm/nouveau/nv50_display.c index 8b78b9cfa383..211e5e9565ce 100644 --- a/drivers/gpu/drm/nouveau/nv50_display.c +++ b/drivers/gpu/drm/nouveau/nv50_display.c | |||
@@ -140,11 +140,11 @@ nv50_display_sync(struct drm_device *dev) | |||
140 | 140 | ||
141 | ret = RING_SPACE(evo, 6); | 141 | ret = RING_SPACE(evo, 6); |
142 | if (ret == 0) { | 142 | if (ret == 0) { |
143 | BEGIN_RING(evo, 0, 0x0084, 1); | 143 | BEGIN_NV04(evo, 0, 0x0084, 1); |
144 | OUT_RING (evo, 0x80000000); | 144 | OUT_RING (evo, 0x80000000); |
145 | BEGIN_RING(evo, 0, 0x0080, 1); | 145 | BEGIN_NV04(evo, 0, 0x0080, 1); |
146 | OUT_RING (evo, 0); | 146 | OUT_RING (evo, 0); |
147 | BEGIN_RING(evo, 0, 0x0084, 1); | 147 | BEGIN_NV04(evo, 0, 0x0084, 1); |
148 | OUT_RING (evo, 0x00000000); | 148 | OUT_RING (evo, 0x00000000); |
149 | 149 | ||
150 | nv_wo32(disp->ntfy, 0x000, 0x00000000); | 150 | nv_wo32(disp->ntfy, 0x000, 0x00000000); |
@@ -267,7 +267,7 @@ nv50_display_init(struct drm_device *dev) | |||
267 | ret = RING_SPACE(evo, 3); | 267 | ret = RING_SPACE(evo, 3); |
268 | if (ret) | 268 | if (ret) |
269 | return ret; | 269 | return ret; |
270 | BEGIN_RING(evo, 0, NV50_EVO_UNK84, 2); | 270 | BEGIN_NV04(evo, 0, NV50_EVO_UNK84, 2); |
271 | OUT_RING (evo, NV50_EVO_UNK84_NOTIFY_DISABLED); | 271 | OUT_RING (evo, NV50_EVO_UNK84_NOTIFY_DISABLED); |
272 | OUT_RING (evo, NvEvoSync); | 272 | OUT_RING (evo, NvEvoSync); |
273 | 273 | ||
@@ -292,7 +292,7 @@ nv50_display_fini(struct drm_device *dev) | |||
292 | 292 | ||
293 | ret = RING_SPACE(evo, 2); | 293 | ret = RING_SPACE(evo, 2); |
294 | if (ret == 0) { | 294 | if (ret == 0) { |
295 | BEGIN_RING(evo, 0, NV50_EVO_UPDATE, 1); | 295 | BEGIN_NV04(evo, 0, NV50_EVO_UPDATE, 1); |
296 | OUT_RING(evo, 0); | 296 | OUT_RING(evo, 0); |
297 | } | 297 | } |
298 | FIRE_RING(evo); | 298 | FIRE_RING(evo); |
@@ -438,13 +438,13 @@ nv50_display_flip_stop(struct drm_crtc *crtc) | |||
438 | return; | 438 | return; |
439 | } | 439 | } |
440 | 440 | ||
441 | BEGIN_RING(evo, 0, 0x0084, 1); | 441 | BEGIN_NV04(evo, 0, 0x0084, 1); |
442 | OUT_RING (evo, 0x00000000); | 442 | OUT_RING (evo, 0x00000000); |
443 | BEGIN_RING(evo, 0, 0x0094, 1); | 443 | BEGIN_NV04(evo, 0, 0x0094, 1); |
444 | OUT_RING (evo, 0x00000000); | 444 | OUT_RING (evo, 0x00000000); |
445 | BEGIN_RING(evo, 0, 0x00c0, 1); | 445 | BEGIN_NV04(evo, 0, 0x00c0, 1); |
446 | OUT_RING (evo, 0x00000000); | 446 | OUT_RING (evo, 0x00000000); |
447 | BEGIN_RING(evo, 0, 0x0080, 1); | 447 | BEGIN_NV04(evo, 0, 0x0080, 1); |
448 | OUT_RING (evo, 0x00000000); | 448 | OUT_RING (evo, 0x00000000); |
449 | FIRE_RING (evo); | 449 | FIRE_RING (evo); |
450 | } | 450 | } |
@@ -474,15 +474,15 @@ nv50_display_flip_next(struct drm_crtc *crtc, struct drm_framebuffer *fb, | |||
474 | } | 474 | } |
475 | 475 | ||
476 | if (dev_priv->chipset < 0xc0) { | 476 | if (dev_priv->chipset < 0xc0) { |
477 | BEGIN_RING(chan, 0, 0x0060, 2); | 477 | BEGIN_NV04(chan, 0, 0x0060, 2); |
478 | OUT_RING (chan, NvEvoSema0 + nv_crtc->index); | 478 | OUT_RING (chan, NvEvoSema0 + nv_crtc->index); |
479 | OUT_RING (chan, dispc->sem.offset); | 479 | OUT_RING (chan, dispc->sem.offset); |
480 | BEGIN_RING(chan, 0, 0x006c, 1); | 480 | BEGIN_NV04(chan, 0, 0x006c, 1); |
481 | OUT_RING (chan, 0xf00d0000 | dispc->sem.value); | 481 | OUT_RING (chan, 0xf00d0000 | dispc->sem.value); |
482 | BEGIN_RING(chan, 0, 0x0064, 2); | 482 | BEGIN_NV04(chan, 0, 0x0064, 2); |
483 | OUT_RING (chan, dispc->sem.offset ^ 0x10); | 483 | OUT_RING (chan, dispc->sem.offset ^ 0x10); |
484 | OUT_RING (chan, 0x74b1e000); | 484 | OUT_RING (chan, 0x74b1e000); |
485 | BEGIN_RING(chan, 0, 0x0060, 1); | 485 | BEGIN_NV04(chan, 0, 0x0060, 1); |
486 | if (dev_priv->chipset < 0x84) | 486 | if (dev_priv->chipset < 0x84) |
487 | OUT_RING (chan, NvSema); | 487 | OUT_RING (chan, NvSema); |
488 | else | 488 | else |
@@ -490,12 +490,12 @@ nv50_display_flip_next(struct drm_crtc *crtc, struct drm_framebuffer *fb, | |||
490 | } else { | 490 | } else { |
491 | u64 offset = chan->dispc_vma[nv_crtc->index].offset; | 491 | u64 offset = chan->dispc_vma[nv_crtc->index].offset; |
492 | offset += dispc->sem.offset; | 492 | offset += dispc->sem.offset; |
493 | BEGIN_NVC0(chan, 2, 0, 0x0010, 4); | 493 | BEGIN_NVC0(chan, 0, 0x0010, 4); |
494 | OUT_RING (chan, upper_32_bits(offset)); | 494 | OUT_RING (chan, upper_32_bits(offset)); |
495 | OUT_RING (chan, lower_32_bits(offset)); | 495 | OUT_RING (chan, lower_32_bits(offset)); |
496 | OUT_RING (chan, 0xf00d0000 | dispc->sem.value); | 496 | OUT_RING (chan, 0xf00d0000 | dispc->sem.value); |
497 | OUT_RING (chan, 0x1002); | 497 | OUT_RING (chan, 0x1002); |
498 | BEGIN_NVC0(chan, 2, 0, 0x0010, 4); | 498 | BEGIN_NVC0(chan, 0, 0x0010, 4); |
499 | OUT_RING (chan, upper_32_bits(offset)); | 499 | OUT_RING (chan, upper_32_bits(offset)); |
500 | OUT_RING (chan, lower_32_bits(offset ^ 0x10)); | 500 | OUT_RING (chan, lower_32_bits(offset ^ 0x10)); |
501 | OUT_RING (chan, 0x74b1e000); | 501 | OUT_RING (chan, 0x74b1e000); |
@@ -508,40 +508,40 @@ nv50_display_flip_next(struct drm_crtc *crtc, struct drm_framebuffer *fb, | |||
508 | } | 508 | } |
509 | 509 | ||
510 | /* queue the flip on the crtc's "display sync" channel */ | 510 | /* queue the flip on the crtc's "display sync" channel */ |
511 | BEGIN_RING(evo, 0, 0x0100, 1); | 511 | BEGIN_NV04(evo, 0, 0x0100, 1); |
512 | OUT_RING (evo, 0xfffe0000); | 512 | OUT_RING (evo, 0xfffe0000); |
513 | if (chan) { | 513 | if (chan) { |
514 | BEGIN_RING(evo, 0, 0x0084, 1); | 514 | BEGIN_NV04(evo, 0, 0x0084, 1); |
515 | OUT_RING (evo, 0x00000100); | 515 | OUT_RING (evo, 0x00000100); |
516 | } else { | 516 | } else { |
517 | BEGIN_RING(evo, 0, 0x0084, 1); | 517 | BEGIN_NV04(evo, 0, 0x0084, 1); |
518 | OUT_RING (evo, 0x00000010); | 518 | OUT_RING (evo, 0x00000010); |
519 | /* allows gamma somehow, PDISP will bitch at you if | 519 | /* allows gamma somehow, PDISP will bitch at you if |
520 | * you don't wait for vblank before changing this.. | 520 | * you don't wait for vblank before changing this.. |
521 | */ | 521 | */ |
522 | BEGIN_RING(evo, 0, 0x00e0, 1); | 522 | BEGIN_NV04(evo, 0, 0x00e0, 1); |
523 | OUT_RING (evo, 0x40000000); | 523 | OUT_RING (evo, 0x40000000); |
524 | } | 524 | } |
525 | BEGIN_RING(evo, 0, 0x0088, 4); | 525 | BEGIN_NV04(evo, 0, 0x0088, 4); |
526 | OUT_RING (evo, dispc->sem.offset); | 526 | OUT_RING (evo, dispc->sem.offset); |
527 | OUT_RING (evo, 0xf00d0000 | dispc->sem.value); | 527 | OUT_RING (evo, 0xf00d0000 | dispc->sem.value); |
528 | OUT_RING (evo, 0x74b1e000); | 528 | OUT_RING (evo, 0x74b1e000); |
529 | OUT_RING (evo, NvEvoSync); | 529 | OUT_RING (evo, NvEvoSync); |
530 | BEGIN_RING(evo, 0, 0x00a0, 2); | 530 | BEGIN_NV04(evo, 0, 0x00a0, 2); |
531 | OUT_RING (evo, 0x00000000); | 531 | OUT_RING (evo, 0x00000000); |
532 | OUT_RING (evo, 0x00000000); | 532 | OUT_RING (evo, 0x00000000); |
533 | BEGIN_RING(evo, 0, 0x00c0, 1); | 533 | BEGIN_NV04(evo, 0, 0x00c0, 1); |
534 | OUT_RING (evo, nv_fb->r_dma); | 534 | OUT_RING (evo, nv_fb->r_dma); |
535 | BEGIN_RING(evo, 0, 0x0110, 2); | 535 | BEGIN_NV04(evo, 0, 0x0110, 2); |
536 | OUT_RING (evo, 0x00000000); | 536 | OUT_RING (evo, 0x00000000); |
537 | OUT_RING (evo, 0x00000000); | 537 | OUT_RING (evo, 0x00000000); |
538 | BEGIN_RING(evo, 0, 0x0800, 5); | 538 | BEGIN_NV04(evo, 0, 0x0800, 5); |
539 | OUT_RING (evo, nv_fb->nvbo->bo.offset >> 8); | 539 | OUT_RING (evo, nv_fb->nvbo->bo.offset >> 8); |
540 | OUT_RING (evo, 0); | 540 | OUT_RING (evo, 0); |
541 | OUT_RING (evo, (fb->height << 16) | fb->width); | 541 | OUT_RING (evo, (fb->height << 16) | fb->width); |
542 | OUT_RING (evo, nv_fb->r_pitch); | 542 | OUT_RING (evo, nv_fb->r_pitch); |
543 | OUT_RING (evo, nv_fb->r_format); | 543 | OUT_RING (evo, nv_fb->r_format); |
544 | BEGIN_RING(evo, 0, 0x0080, 1); | 544 | BEGIN_NV04(evo, 0, 0x0080, 1); |
545 | OUT_RING (evo, 0x00000000); | 545 | OUT_RING (evo, 0x00000000); |
546 | FIRE_RING (evo); | 546 | FIRE_RING (evo); |
547 | 547 | ||