diff options
Diffstat (limited to 'drivers/gpu/drm/nouveau/nv40_fifo.c')
-rw-r--r-- | drivers/gpu/drm/nouveau/nv40_fifo.c | 20 |
1 files changed, 7 insertions, 13 deletions
diff --git a/drivers/gpu/drm/nouveau/nv40_fifo.c b/drivers/gpu/drm/nouveau/nv40_fifo.c index d337b8b28cdd..49b9a35a9cd6 100644 --- a/drivers/gpu/drm/nouveau/nv40_fifo.c +++ b/drivers/gpu/drm/nouveau/nv40_fifo.c | |||
@@ -47,6 +47,11 @@ nv40_fifo_create_context(struct nouveau_channel *chan) | |||
47 | if (ret) | 47 | if (ret) |
48 | return ret; | 48 | return ret; |
49 | 49 | ||
50 | chan->user = ioremap(pci_resource_start(dev->pdev, 0) + | ||
51 | NV40_USER(chan->id), PAGE_SIZE); | ||
52 | if (!chan->user) | ||
53 | return -ENOMEM; | ||
54 | |||
50 | spin_lock_irqsave(&dev_priv->context_switch_lock, flags); | 55 | spin_lock_irqsave(&dev_priv->context_switch_lock, flags); |
51 | 56 | ||
52 | nv_wi32(dev, fc + 0, chan->pushbuf_base); | 57 | nv_wi32(dev, fc + 0, chan->pushbuf_base); |
@@ -59,7 +64,6 @@ nv40_fifo_create_context(struct nouveau_channel *chan) | |||
59 | NV_PFIFO_CACHE1_BIG_ENDIAN | | 64 | NV_PFIFO_CACHE1_BIG_ENDIAN | |
60 | #endif | 65 | #endif |
61 | 0x30000000 /* no idea.. */); | 66 | 0x30000000 /* no idea.. */); |
62 | nv_wi32(dev, fc + 56, chan->ramin_grctx->pinst >> 4); | ||
63 | nv_wi32(dev, fc + 60, 0x0001FFFF); | 67 | nv_wi32(dev, fc + 60, 0x0001FFFF); |
64 | 68 | ||
65 | /* enable the fifo dma operation */ | 69 | /* enable the fifo dma operation */ |
@@ -70,17 +74,6 @@ nv40_fifo_create_context(struct nouveau_channel *chan) | |||
70 | return 0; | 74 | return 0; |
71 | } | 75 | } |
72 | 76 | ||
73 | void | ||
74 | nv40_fifo_destroy_context(struct nouveau_channel *chan) | ||
75 | { | ||
76 | struct drm_device *dev = chan->dev; | ||
77 | |||
78 | nv_wr32(dev, NV04_PFIFO_MODE, | ||
79 | nv_rd32(dev, NV04_PFIFO_MODE) & ~(1 << chan->id)); | ||
80 | |||
81 | nouveau_gpuobj_ref(NULL, &chan->ramfc); | ||
82 | } | ||
83 | |||
84 | static void | 77 | static void |
85 | nv40_fifo_do_load_context(struct drm_device *dev, int chid) | 78 | nv40_fifo_do_load_context(struct drm_device *dev, int chid) |
86 | { | 79 | { |
@@ -279,6 +272,7 @@ nv40_fifo_init_ramxx(struct drm_device *dev) | |||
279 | static void | 272 | static void |
280 | nv40_fifo_init_intr(struct drm_device *dev) | 273 | nv40_fifo_init_intr(struct drm_device *dev) |
281 | { | 274 | { |
275 | nouveau_irq_register(dev, 8, nv04_fifo_isr); | ||
282 | nv_wr32(dev, 0x002100, 0xffffffff); | 276 | nv_wr32(dev, 0x002100, 0xffffffff); |
283 | nv_wr32(dev, 0x002140, 0xffffffff); | 277 | nv_wr32(dev, 0x002140, 0xffffffff); |
284 | } | 278 | } |
@@ -301,7 +295,7 @@ nv40_fifo_init(struct drm_device *dev) | |||
301 | pfifo->reassign(dev, true); | 295 | pfifo->reassign(dev, true); |
302 | 296 | ||
303 | for (i = 0; i < dev_priv->engine.fifo.channels; i++) { | 297 | for (i = 0; i < dev_priv->engine.fifo.channels; i++) { |
304 | if (dev_priv->fifos[i]) { | 298 | if (dev_priv->channels.ptr[i]) { |
305 | uint32_t mode = nv_rd32(dev, NV04_PFIFO_MODE); | 299 | uint32_t mode = nv_rd32(dev, NV04_PFIFO_MODE); |
306 | nv_wr32(dev, NV04_PFIFO_MODE, mode | (1 << i)); | 300 | nv_wr32(dev, NV04_PFIFO_MODE, mode | (1 << i)); |
307 | } | 301 | } |