1 files changed, 10 insertions, 10 deletions

diff --git a/drivers/gpu/drm/nouveau/nv40_fifo.c b/drivers/gpu/drm/nouveau/nv40_fifo.c
index 2b67f1835c39..d337b8b28cdd 100644
--- a/drivers/gpu/drm/nouveau/nv40_fifo.c
+++ b/drivers/gpu/drm/nouveau/nv40_fifo.c
@@ -27,8 +27,9 @@
 #include "drmP.h"
 #include "nouveau_drv.h"
 #include "nouveau_drm.h"
+#include "nouveau_ramht.h"
 
-#define NV40_RAMFC(c) (dev_priv->ramfc_offset + ((c) * NV40_RAMFC__SIZE))
+#define NV40_RAMFC(c) (dev_priv->ramfc->pinst + ((c) * NV40_RAMFC__SIZE))
 #define NV40_RAMFC__SIZE 128
 
 int
@@ -42,7 +43,7 @@ nv40_fifo_create_context(struct nouveau_channel *chan)
 
         ret = nouveau_gpuobj_new_fake(dev, NV40_RAMFC(chan->id), ~0,
                                       NV40_RAMFC__SIZE, NVOBJ_FLAG_ZERO_ALLOC |
-                                      NVOBJ_FLAG_ZERO_FREE, NULL, &chan->ramfc);
+                                      NVOBJ_FLAG_ZERO_FREE, &chan->ramfc);
         if (ret)
                 return ret;
 
@@ -50,7 +51,7 @@ nv40_fifo_create_context(struct nouveau_channel *chan)
 
         nv_wi32(dev, fc +  0, chan->pushbuf_base);
         nv_wi32(dev, fc +  4, chan->pushbuf_base);
-        nv_wi32(dev, fc + 12, chan->pushbuf->instance >> 4);
+        nv_wi32(dev, fc + 12, chan->pushbuf->pinst >> 4);
         nv_wi32(dev, fc + 24, NV_PFIFO_CACHE1_DMA_FETCH_TRIG_128_BYTES |
                               NV_PFIFO_CACHE1_DMA_FETCH_SIZE_128_BYTES |
                               NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_8 |
@@ -58,7 +59,7 @@ nv40_fifo_create_context(struct nouveau_channel *chan)
                               NV_PFIFO_CACHE1_BIG_ENDIAN |
 #endif
                               0x30000000 /* no idea.. */);
-        nv_wi32(dev, fc + 56, chan->ramin_grctx->instance >> 4);
+        nv_wi32(dev, fc + 56, chan->ramin_grctx->pinst >> 4);
         nv_wi32(dev, fc + 60, 0x0001FFFF);
 
         /* enable the fifo dma operation */
@@ -77,8 +78,7 @@ nv40_fifo_destroy_context(struct nouveau_channel *chan)
         nv_wr32(dev, NV04_PFIFO_MODE,
                 nv_rd32(dev, NV04_PFIFO_MODE) & ~(1 << chan->id));
 
-        if (chan->ramfc)
-                nouveau_gpuobj_ref_del(dev, &chan->ramfc);
+        nouveau_gpuobj_ref(NULL, &chan->ramfc);
 }
 
 static void
@@ -241,9 +241,9 @@ nv40_fifo_init_ramxx(struct drm_device *dev)
         struct drm_nouveau_private *dev_priv = dev->dev_private;
 
         nv_wr32(dev, NV03_PFIFO_RAMHT, (0x03 << 24) /* search 128 */ |
-                                       ((dev_priv->ramht_bits - 9) << 16) |
-                                       (dev_priv->ramht_offset >> 8));
-        nv_wr32(dev, NV03_PFIFO_RAMRO, dev_priv->ramro_offset>>8);
+                                       ((dev_priv->ramht->bits - 9) << 16) |
+                                       (dev_priv->ramht->gpuobj->pinst >> 8));
+        nv_wr32(dev, NV03_PFIFO_RAMRO, dev_priv->ramro->pinst >> 8);
 
         switch (dev_priv->chipset) {
         case 0x47:
@@ -271,7 +271,7 @@ nv40_fifo_init_ramxx(struct drm_device *dev)
                 nv_wr32(dev, 0x2230, 0);
                 nv_wr32(dev, NV40_PFIFO_RAMFC,
                         ((dev_priv->vram_size - 512 * 1024 +
-                          dev_priv->ramfc_offset) >> 16) | (3 << 16));
+                          dev_priv->ramfc->pinst) >> 16) | (3 << 16));
                 break;
         }
 }