diff options
Diffstat (limited to 'drivers/gpu/drm/nouveau/nv17_tv.c')
-rw-r--r-- | drivers/gpu/drm/nouveau/nv17_tv.c | 115 |
1 files changed, 105 insertions, 10 deletions
diff --git a/drivers/gpu/drm/nouveau/nv17_tv.c b/drivers/gpu/drm/nouveau/nv17_tv.c index 81c01353a9f9..58b917c3341b 100644 --- a/drivers/gpu/drm/nouveau/nv17_tv.c +++ b/drivers/gpu/drm/nouveau/nv17_tv.c | |||
@@ -33,13 +33,103 @@ | |||
33 | #include "nouveau_hw.h" | 33 | #include "nouveau_hw.h" |
34 | #include "nv17_tv.h" | 34 | #include "nv17_tv.h" |
35 | 35 | ||
36 | enum drm_connector_status nv17_tv_detect(struct drm_encoder *encoder, | 36 | static uint32_t nv42_tv_sample_load(struct drm_encoder *encoder) |
37 | struct drm_connector *connector, | ||
38 | uint32_t pin_mask) | ||
39 | { | 37 | { |
38 | struct drm_device *dev = encoder->dev; | ||
39 | struct drm_nouveau_private *dev_priv = dev->dev_private; | ||
40 | uint32_t testval, regoffset = nv04_dac_output_offset(encoder); | ||
41 | uint32_t gpio0, gpio1, fp_htotal, fp_hsync_start, fp_hsync_end, | ||
42 | fp_control, test_ctrl, dacclk, ctv_14, ctv_1c, ctv_6c; | ||
43 | uint32_t sample = 0; | ||
44 | int head; | ||
45 | |||
46 | #define RGB_TEST_DATA(r, g, b) (r << 0 | g << 10 | b << 20) | ||
47 | testval = RGB_TEST_DATA(0x82, 0xeb, 0x82); | ||
48 | if (dev_priv->vbios->tvdactestval) | ||
49 | testval = dev_priv->vbios->tvdactestval; | ||
50 | |||
51 | dacclk = NVReadRAMDAC(dev, 0, NV_PRAMDAC_DACCLK + regoffset); | ||
52 | head = (dacclk & 0x100) >> 8; | ||
53 | |||
54 | /* Save the previous state. */ | ||
55 | gpio1 = nv17_gpio_get(dev, DCB_GPIO_TVDAC1); | ||
56 | gpio0 = nv17_gpio_get(dev, DCB_GPIO_TVDAC0); | ||
57 | fp_htotal = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_HTOTAL); | ||
58 | fp_hsync_start = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_HSYNC_START); | ||
59 | fp_hsync_end = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_HSYNC_END); | ||
60 | fp_control = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_TG_CONTROL); | ||
61 | test_ctrl = NVReadRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + regoffset); | ||
62 | ctv_1c = NVReadRAMDAC(dev, head, 0x680c1c); | ||
63 | ctv_14 = NVReadRAMDAC(dev, head, 0x680c14); | ||
64 | ctv_6c = NVReadRAMDAC(dev, head, 0x680c6c); | ||
65 | |||
66 | /* Prepare the DAC for load detection. */ | ||
67 | nv17_gpio_set(dev, DCB_GPIO_TVDAC1, true); | ||
68 | nv17_gpio_set(dev, DCB_GPIO_TVDAC0, true); | ||
69 | |||
70 | NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_HTOTAL, 1343); | ||
71 | NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_HSYNC_START, 1047); | ||
72 | NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_HSYNC_END, 1183); | ||
73 | NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_TG_CONTROL, | ||
74 | NV_PRAMDAC_FP_TG_CONTROL_DISPEN_POS | | ||
75 | NV_PRAMDAC_FP_TG_CONTROL_WIDTH_12 | | ||
76 | NV_PRAMDAC_FP_TG_CONTROL_READ_PROG | | ||
77 | NV_PRAMDAC_FP_TG_CONTROL_HSYNC_POS | | ||
78 | NV_PRAMDAC_FP_TG_CONTROL_VSYNC_POS); | ||
79 | |||
80 | NVWriteRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + regoffset, 0); | ||
81 | |||
82 | NVWriteRAMDAC(dev, 0, NV_PRAMDAC_DACCLK + regoffset, | ||
83 | (dacclk & ~0xff) | 0x22); | ||
84 | msleep(1); | ||
85 | NVWriteRAMDAC(dev, 0, NV_PRAMDAC_DACCLK + regoffset, | ||
86 | (dacclk & ~0xff) | 0x21); | ||
87 | |||
88 | NVWriteRAMDAC(dev, head, 0x680c1c, 1 << 20); | ||
89 | NVWriteRAMDAC(dev, head, 0x680c14, 4 << 16); | ||
90 | |||
91 | /* Sample pin 0x4 (usually S-video luma). */ | ||
92 | NVWriteRAMDAC(dev, head, 0x680c6c, testval >> 10 & 0x3ff); | ||
93 | msleep(20); | ||
94 | sample |= NVReadRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + regoffset) | ||
95 | & 0x4 << 28; | ||
96 | |||
97 | /* Sample the remaining pins. */ | ||
98 | NVWriteRAMDAC(dev, head, 0x680c6c, testval & 0x3ff); | ||
99 | msleep(20); | ||
100 | sample |= NVReadRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + regoffset) | ||
101 | & 0xa << 28; | ||
102 | |||
103 | /* Restore the previous state. */ | ||
104 | NVWriteRAMDAC(dev, head, 0x680c1c, ctv_1c); | ||
105 | NVWriteRAMDAC(dev, head, 0x680c14, ctv_14); | ||
106 | NVWriteRAMDAC(dev, head, 0x680c6c, ctv_6c); | ||
107 | NVWriteRAMDAC(dev, 0, NV_PRAMDAC_DACCLK + regoffset, dacclk); | ||
108 | NVWriteRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + regoffset, test_ctrl); | ||
109 | NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_TG_CONTROL, fp_control); | ||
110 | NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_HSYNC_END, fp_hsync_end); | ||
111 | NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_HSYNC_START, fp_hsync_start); | ||
112 | NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_HTOTAL, fp_htotal); | ||
113 | nv17_gpio_set(dev, DCB_GPIO_TVDAC1, gpio1); | ||
114 | nv17_gpio_set(dev, DCB_GPIO_TVDAC0, gpio0); | ||
115 | |||
116 | return sample; | ||
117 | } | ||
118 | |||
119 | static enum drm_connector_status | ||
120 | nv17_tv_detect(struct drm_encoder *encoder, struct drm_connector *connector) | ||
121 | { | ||
122 | struct drm_device *dev = encoder->dev; | ||
123 | struct drm_nouveau_private *dev_priv = dev->dev_private; | ||
124 | struct drm_mode_config *conf = &dev->mode_config; | ||
40 | struct nv17_tv_encoder *tv_enc = to_tv_enc(encoder); | 125 | struct nv17_tv_encoder *tv_enc = to_tv_enc(encoder); |
126 | struct dcb_entry *dcb = tv_enc->base.dcb; | ||
41 | 127 | ||
42 | tv_enc->pin_mask = pin_mask >> 28 & 0xe; | 128 | if (dev_priv->chipset == 0x42 || |
129 | dev_priv->chipset == 0x43) | ||
130 | tv_enc->pin_mask = nv42_tv_sample_load(encoder) >> 28 & 0xe; | ||
131 | else | ||
132 | tv_enc->pin_mask = nv17_dac_sample_load(encoder) >> 28 & 0xe; | ||
43 | 133 | ||
44 | switch (tv_enc->pin_mask) { | 134 | switch (tv_enc->pin_mask) { |
45 | case 0x2: | 135 | case 0x2: |
@@ -50,7 +140,7 @@ enum drm_connector_status nv17_tv_detect(struct drm_encoder *encoder, | |||
50 | tv_enc->subconnector = DRM_MODE_SUBCONNECTOR_SVIDEO; | 140 | tv_enc->subconnector = DRM_MODE_SUBCONNECTOR_SVIDEO; |
51 | break; | 141 | break; |
52 | case 0xe: | 142 | case 0xe: |
53 | if (nouveau_encoder(encoder)->dcb->tvconf.has_component_output) | 143 | if (dcb->tvconf.has_component_output) |
54 | tv_enc->subconnector = DRM_MODE_SUBCONNECTOR_Component; | 144 | tv_enc->subconnector = DRM_MODE_SUBCONNECTOR_Component; |
55 | else | 145 | else |
56 | tv_enc->subconnector = DRM_MODE_SUBCONNECTOR_SCART; | 146 | tv_enc->subconnector = DRM_MODE_SUBCONNECTOR_SCART; |
@@ -61,11 +151,16 @@ enum drm_connector_status nv17_tv_detect(struct drm_encoder *encoder, | |||
61 | } | 151 | } |
62 | 152 | ||
63 | drm_connector_property_set_value(connector, | 153 | drm_connector_property_set_value(connector, |
64 | encoder->dev->mode_config.tv_subconnector_property, | 154 | conf->tv_subconnector_property, |
65 | tv_enc->subconnector); | 155 | tv_enc->subconnector); |
66 | 156 | ||
67 | return tv_enc->subconnector ? connector_status_connected : | 157 | if (tv_enc->subconnector) { |
68 | connector_status_disconnected; | 158 | NV_INFO(dev, "Load detected on output %c\n", |
159 | '@' + ffs(dcb->or)); | ||
160 | return connector_status_connected; | ||
161 | } else { | ||
162 | return connector_status_disconnected; | ||
163 | } | ||
69 | } | 164 | } |
70 | 165 | ||
71 | static const struct { | 166 | static const struct { |
@@ -633,7 +728,7 @@ static struct drm_encoder_helper_funcs nv17_tv_helper_funcs = { | |||
633 | .prepare = nv17_tv_prepare, | 728 | .prepare = nv17_tv_prepare, |
634 | .commit = nv17_tv_commit, | 729 | .commit = nv17_tv_commit, |
635 | .mode_set = nv17_tv_mode_set, | 730 | .mode_set = nv17_tv_mode_set, |
636 | .detect = nv17_dac_detect, | 731 | .detect = nv17_tv_detect, |
637 | }; | 732 | }; |
638 | 733 | ||
639 | static struct drm_encoder_slave_funcs nv17_tv_slave_funcs = { | 734 | static struct drm_encoder_slave_funcs nv17_tv_slave_funcs = { |