diff options
Diffstat (limited to 'drivers/gpu/drm/nouveau/nv04_display.c')
-rw-r--r-- | drivers/gpu/drm/nouveau/nv04_display.c | 36 |
1 files changed, 12 insertions, 24 deletions
diff --git a/drivers/gpu/drm/nouveau/nv04_display.c b/drivers/gpu/drm/nouveau/nv04_display.c index 93200da8f2d3..c6df391ebb2e 100644 --- a/drivers/gpu/drm/nouveau/nv04_display.c +++ b/drivers/gpu/drm/nouveau/nv04_display.c | |||
@@ -32,8 +32,6 @@ | |||
32 | #include "nouveau_encoder.h" | 32 | #include "nouveau_encoder.h" |
33 | #include "nouveau_connector.h" | 33 | #include "nouveau_connector.h" |
34 | 34 | ||
35 | #define MULTIPLE_ENCODERS(e) (e & (e - 1)) | ||
36 | |||
37 | static void | 35 | static void |
38 | nv04_display_store_initial_head_owner(struct drm_device *dev) | 36 | nv04_display_store_initial_head_owner(struct drm_device *dev) |
39 | { | 37 | { |
@@ -41,7 +39,7 @@ nv04_display_store_initial_head_owner(struct drm_device *dev) | |||
41 | 39 | ||
42 | if (dev_priv->chipset != 0x11) { | 40 | if (dev_priv->chipset != 0x11) { |
43 | dev_priv->crtc_owner = NVReadVgaCrtc(dev, 0, NV_CIO_CRE_44); | 41 | dev_priv->crtc_owner = NVReadVgaCrtc(dev, 0, NV_CIO_CRE_44); |
44 | goto ownerknown; | 42 | return; |
45 | } | 43 | } |
46 | 44 | ||
47 | /* reading CR44 is broken on nv11, so we attempt to infer it */ | 45 | /* reading CR44 is broken on nv11, so we attempt to infer it */ |
@@ -52,8 +50,6 @@ nv04_display_store_initial_head_owner(struct drm_device *dev) | |||
52 | bool tvA = false; | 50 | bool tvA = false; |
53 | bool tvB = false; | 51 | bool tvB = false; |
54 | 52 | ||
55 | NVLockVgaCrtcs(dev, false); | ||
56 | |||
57 | slaved_on_B = NVReadVgaCrtc(dev, 1, NV_CIO_CRE_PIXEL_INDEX) & | 53 | slaved_on_B = NVReadVgaCrtc(dev, 1, NV_CIO_CRE_PIXEL_INDEX) & |
58 | 0x80; | 54 | 0x80; |
59 | if (slaved_on_B) | 55 | if (slaved_on_B) |
@@ -66,8 +62,6 @@ nv04_display_store_initial_head_owner(struct drm_device *dev) | |||
66 | tvA = !(NVReadVgaCrtc(dev, 0, NV_CIO_CRE_LCD__INDEX) & | 62 | tvA = !(NVReadVgaCrtc(dev, 0, NV_CIO_CRE_LCD__INDEX) & |
67 | MASK(NV_CIO_CRE_LCD_LCD_SELECT)); | 63 | MASK(NV_CIO_CRE_LCD_LCD_SELECT)); |
68 | 64 | ||
69 | NVLockVgaCrtcs(dev, true); | ||
70 | |||
71 | if (slaved_on_A && !tvA) | 65 | if (slaved_on_A && !tvA) |
72 | dev_priv->crtc_owner = 0x0; | 66 | dev_priv->crtc_owner = 0x0; |
73 | else if (slaved_on_B && !tvB) | 67 | else if (slaved_on_B && !tvB) |
@@ -79,12 +73,6 @@ nv04_display_store_initial_head_owner(struct drm_device *dev) | |||
79 | else | 73 | else |
80 | dev_priv->crtc_owner = 0x0; | 74 | dev_priv->crtc_owner = 0x0; |
81 | } | 75 | } |
82 | |||
83 | ownerknown: | ||
84 | /* we need to ensure the heads are not tied henceforth, or reading any | ||
85 | * 8 bit reg on head B will fail | ||
86 | * setting a single arbitrary head solves that */ | ||
87 | NVSetOwner(dev, 0); | ||
88 | } | 76 | } |
89 | 77 | ||
90 | int | 78 | int |
@@ -99,8 +87,13 @@ nv04_display_create(struct drm_device *dev) | |||
99 | 87 | ||
100 | NV_DEBUG_KMS(dev, "\n"); | 88 | NV_DEBUG_KMS(dev, "\n"); |
101 | 89 | ||
102 | if (nv_two_heads(dev)) | 90 | NVLockVgaCrtcs(dev, false); |
91 | |||
92 | if (nv_two_heads(dev)) { | ||
103 | nv04_display_store_initial_head_owner(dev); | 93 | nv04_display_store_initial_head_owner(dev); |
94 | NVSetOwner(dev, 0); | ||
95 | } | ||
96 | |||
104 | nouveau_hw_save_vga_fonts(dev, 1); | 97 | nouveau_hw_save_vga_fonts(dev, 1); |
105 | 98 | ||
106 | drm_mode_config_init(dev); | 99 | drm_mode_config_init(dev); |
@@ -168,8 +161,6 @@ nv04_display_create(struct drm_device *dev) | |||
168 | } | 161 | } |
169 | 162 | ||
170 | /* Save previous state */ | 163 | /* Save previous state */ |
171 | NVLockVgaCrtcs(dev, false); | ||
172 | |||
173 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) | 164 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) |
174 | crtc->funcs->save(crtc); | 165 | crtc->funcs->save(crtc); |
175 | 166 | ||
@@ -185,6 +176,7 @@ nv04_display_create(struct drm_device *dev) | |||
185 | void | 176 | void |
186 | nv04_display_destroy(struct drm_device *dev) | 177 | nv04_display_destroy(struct drm_device *dev) |
187 | { | 178 | { |
179 | struct drm_nouveau_private *dev_priv = dev->dev_private; | ||
188 | struct drm_encoder *encoder; | 180 | struct drm_encoder *encoder; |
189 | struct drm_crtc *crtc; | 181 | struct drm_crtc *crtc; |
190 | 182 | ||
@@ -200,8 +192,6 @@ nv04_display_destroy(struct drm_device *dev) | |||
200 | } | 192 | } |
201 | 193 | ||
202 | /* Restore state */ | 194 | /* Restore state */ |
203 | NVLockVgaCrtcs(dev, false); | ||
204 | |||
205 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { | 195 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { |
206 | struct drm_encoder_helper_funcs *func = encoder->helper_private; | 196 | struct drm_encoder_helper_funcs *func = encoder->helper_private; |
207 | 197 | ||
@@ -214,12 +204,15 @@ nv04_display_destroy(struct drm_device *dev) | |||
214 | drm_mode_config_cleanup(dev); | 204 | drm_mode_config_cleanup(dev); |
215 | 205 | ||
216 | nouveau_hw_save_vga_fonts(dev, 0); | 206 | nouveau_hw_save_vga_fonts(dev, 0); |
207 | |||
208 | if (nv_two_heads(dev)) | ||
209 | NVSetOwner(dev, dev_priv->crtc_owner); | ||
210 | NVLockVgaCrtcs(dev, true); | ||
217 | } | 211 | } |
218 | 212 | ||
219 | void | 213 | void |
220 | nv04_display_restore(struct drm_device *dev) | 214 | nv04_display_restore(struct drm_device *dev) |
221 | { | 215 | { |
222 | struct drm_nouveau_private *dev_priv = dev->dev_private; | ||
223 | struct drm_encoder *encoder; | 216 | struct drm_encoder *encoder; |
224 | struct drm_crtc *crtc; | 217 | struct drm_crtc *crtc; |
225 | 218 | ||
@@ -241,10 +234,5 @@ nv04_display_restore(struct drm_device *dev) | |||
241 | 234 | ||
242 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) | 235 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) |
243 | crtc->funcs->restore(crtc); | 236 | crtc->funcs->restore(crtc); |
244 | |||
245 | if (nv_two_heads(dev)) | ||
246 | NVSetOwner(dev, dev_priv->crtc_owner); | ||
247 | |||
248 | NVLockVgaCrtcs(dev, true); | ||
249 | } | 237 | } |
250 | 238 | ||