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path: root/drivers/gpu/drm/nouveau/nouveau_state.c
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Diffstat (limited to 'drivers/gpu/drm/nouveau/nouveau_state.c')
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_state.c51
1 files changed, 51 insertions, 0 deletions
diff --git a/drivers/gpu/drm/nouveau/nouveau_state.c b/drivers/gpu/drm/nouveau/nouveau_state.c
index cf16bfb99c71..989322be3728 100644
--- a/drivers/gpu/drm/nouveau/nouveau_state.c
+++ b/drivers/gpu/drm/nouveau/nouveau_state.c
@@ -359,6 +359,54 @@ static int nouveau_init_engine_ptrs(struct drm_device *dev)
359 engine->gpio.set = nv50_gpio_set; 359 engine->gpio.set = nv50_gpio_set;
360 engine->gpio.irq_enable = nv50_gpio_irq_enable; 360 engine->gpio.irq_enable = nv50_gpio_irq_enable;
361 break; 361 break;
362 case 0xC0:
363 engine->instmem.init = nvc0_instmem_init;
364 engine->instmem.takedown = nvc0_instmem_takedown;
365 engine->instmem.suspend = nvc0_instmem_suspend;
366 engine->instmem.resume = nvc0_instmem_resume;
367 engine->instmem.populate = nvc0_instmem_populate;
368 engine->instmem.clear = nvc0_instmem_clear;
369 engine->instmem.bind = nvc0_instmem_bind;
370 engine->instmem.unbind = nvc0_instmem_unbind;
371 engine->instmem.flush = nvc0_instmem_flush;
372 engine->mc.init = nv50_mc_init;
373 engine->mc.takedown = nv50_mc_takedown;
374 engine->timer.init = nv04_timer_init;
375 engine->timer.read = nv04_timer_read;
376 engine->timer.takedown = nv04_timer_takedown;
377 engine->fb.init = nvc0_fb_init;
378 engine->fb.takedown = nvc0_fb_takedown;
379 engine->graph.grclass = NULL; //nvc0_graph_grclass;
380 engine->graph.init = nvc0_graph_init;
381 engine->graph.takedown = nvc0_graph_takedown;
382 engine->graph.fifo_access = nvc0_graph_fifo_access;
383 engine->graph.channel = nvc0_graph_channel;
384 engine->graph.create_context = nvc0_graph_create_context;
385 engine->graph.destroy_context = nvc0_graph_destroy_context;
386 engine->graph.load_context = nvc0_graph_load_context;
387 engine->graph.unload_context = nvc0_graph_unload_context;
388 engine->fifo.channels = 128;
389 engine->fifo.init = nvc0_fifo_init;
390 engine->fifo.takedown = nvc0_fifo_takedown;
391 engine->fifo.disable = nvc0_fifo_disable;
392 engine->fifo.enable = nvc0_fifo_enable;
393 engine->fifo.reassign = nvc0_fifo_reassign;
394 engine->fifo.channel_id = nvc0_fifo_channel_id;
395 engine->fifo.create_context = nvc0_fifo_create_context;
396 engine->fifo.destroy_context = nvc0_fifo_destroy_context;
397 engine->fifo.load_context = nvc0_fifo_load_context;
398 engine->fifo.unload_context = nvc0_fifo_unload_context;
399 engine->display.early_init = nv50_display_early_init;
400 engine->display.late_takedown = nv50_display_late_takedown;
401 engine->display.create = nv50_display_create;
402 engine->display.init = nv50_display_init;
403 engine->display.destroy = nv50_display_destroy;
404 engine->gpio.init = nv50_gpio_init;
405 engine->gpio.takedown = nouveau_stub_takedown;
406 engine->gpio.get = nv50_gpio_get;
407 engine->gpio.set = nv50_gpio_set;
408 engine->gpio.irq_enable = nv50_gpio_irq_enable;
409 break;
362 default: 410 default:
363 NV_ERROR(dev, "NV%02x unsupported\n", dev_priv->chipset); 411 NV_ERROR(dev, "NV%02x unsupported\n", dev_priv->chipset);
364 return 1; 412 return 1;
@@ -815,6 +863,9 @@ int nouveau_load(struct drm_device *dev, unsigned long flags)
815 case 0xa0: 863 case 0xa0:
816 dev_priv->card_type = NV_50; 864 dev_priv->card_type = NV_50;
817 break; 865 break;
866 case 0xc0:
867 dev_priv->card_type = NV_C0;
868 break;
818 default: 869 default:
819 NV_INFO(dev, "Unsupported chipset 0x%08x\n", reg0); 870 NV_INFO(dev, "Unsupported chipset 0x%08x\n", reg0);
820 ret = -EINVAL; 871 ret = -EINVAL;