diff options
Diffstat (limited to 'drivers/gpu/drm/nouveau/nouveau_reg.h')
| -rw-r--r-- | drivers/gpu/drm/nouveau/nouveau_reg.h | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/drivers/gpu/drm/nouveau/nouveau_reg.h b/drivers/gpu/drm/nouveau/nouveau_reg.h index 04e8fb795269..f18cdfc3400f 100644 --- a/drivers/gpu/drm/nouveau/nouveau_reg.h +++ b/drivers/gpu/drm/nouveau/nouveau_reg.h | |||
| @@ -639,9 +639,9 @@ | |||
| 639 | # define NV50_PCONNECTOR_I2C_PORT_4 0x0000e240 | 639 | # define NV50_PCONNECTOR_I2C_PORT_4 0x0000e240 |
| 640 | # define NV50_PCONNECTOR_I2C_PORT_5 0x0000e258 | 640 | # define NV50_PCONNECTOR_I2C_PORT_5 0x0000e258 |
| 641 | 641 | ||
| 642 | #define NV50_AUXCH_DATA_OUT(i,n) ((n) * 4 + (i) * 0x50 + 0x0000e4c0) | 642 | #define NV50_AUXCH_DATA_OUT(i, n) ((n) * 4 + (i) * 0x50 + 0x0000e4c0) |
| 643 | #define NV50_AUXCH_DATA_OUT__SIZE 4 | 643 | #define NV50_AUXCH_DATA_OUT__SIZE 4 |
| 644 | #define NV50_AUXCH_DATA_IN(i,n) ((n) * 4 + (i) * 0x50 + 0x0000e4d0) | 644 | #define NV50_AUXCH_DATA_IN(i, n) ((n) * 4 + (i) * 0x50 + 0x0000e4d0) |
| 645 | #define NV50_AUXCH_DATA_IN__SIZE 4 | 645 | #define NV50_AUXCH_DATA_IN__SIZE 4 |
| 646 | #define NV50_AUXCH_ADDR(i) ((i) * 0x50 + 0x0000e4e0) | 646 | #define NV50_AUXCH_ADDR(i) ((i) * 0x50 + 0x0000e4e0) |
| 647 | #define NV50_AUXCH_CTRL(i) ((i) * 0x50 + 0x0000e4e4) | 647 | #define NV50_AUXCH_CTRL(i) ((i) * 0x50 + 0x0000e4e4) |
| @@ -829,7 +829,7 @@ | |||
| 829 | #define NV50_PDISPLAY_SOR_BACKLIGHT 0x0061c084 | 829 | #define NV50_PDISPLAY_SOR_BACKLIGHT 0x0061c084 |
| 830 | #define NV50_PDISPLAY_SOR_BACKLIGHT_ENABLE 0x80000000 | 830 | #define NV50_PDISPLAY_SOR_BACKLIGHT_ENABLE 0x80000000 |
| 831 | #define NV50_PDISPLAY_SOR_BACKLIGHT_LEVEL 0x00000fff | 831 | #define NV50_PDISPLAY_SOR_BACKLIGHT_LEVEL 0x00000fff |
| 832 | #define NV50_SOR_DP_CTRL(i,l) (0x0061c10c + (i) * 0x800 + (l) * 0x80) | 832 | #define NV50_SOR_DP_CTRL(i, l) (0x0061c10c + (i) * 0x800 + (l) * 0x80) |
| 833 | #define NV50_SOR_DP_CTRL_ENABLED 0x00000001 | 833 | #define NV50_SOR_DP_CTRL_ENABLED 0x00000001 |
| 834 | #define NV50_SOR_DP_CTRL_ENHANCED_FRAME_ENABLED 0x00004000 | 834 | #define NV50_SOR_DP_CTRL_ENHANCED_FRAME_ENABLED 0x00004000 |
| 835 | #define NV50_SOR_DP_CTRL_LANE_MASK 0x001f0000 | 835 | #define NV50_SOR_DP_CTRL_LANE_MASK 0x001f0000 |
| @@ -841,10 +841,10 @@ | |||
| 841 | #define NV50_SOR_DP_CTRL_TRAINING_PATTERN_DISABLED 0x00000000 | 841 | #define NV50_SOR_DP_CTRL_TRAINING_PATTERN_DISABLED 0x00000000 |
| 842 | #define NV50_SOR_DP_CTRL_TRAINING_PATTERN_1 0x01000000 | 842 | #define NV50_SOR_DP_CTRL_TRAINING_PATTERN_1 0x01000000 |
| 843 | #define NV50_SOR_DP_CTRL_TRAINING_PATTERN_2 0x02000000 | 843 | #define NV50_SOR_DP_CTRL_TRAINING_PATTERN_2 0x02000000 |
| 844 | #define NV50_SOR_DP_UNK118(i,l) (0x0061c118 + (i) * 0x800 + (l) * 0x80) | 844 | #define NV50_SOR_DP_UNK118(i, l) (0x0061c118 + (i) * 0x800 + (l) * 0x80) |
| 845 | #define NV50_SOR_DP_UNK120(i,l) (0x0061c120 + (i) * 0x800 + (l) * 0x80) | 845 | #define NV50_SOR_DP_UNK120(i, l) (0x0061c120 + (i) * 0x800 + (l) * 0x80) |
| 846 | #define NV50_SOR_DP_UNK128(i,l) (0x0061c128 + (i) * 0x800 + (l) * 0x80) | 846 | #define NV50_SOR_DP_UNK128(i, l) (0x0061c128 + (i) * 0x800 + (l) * 0x80) |
| 847 | #define NV50_SOR_DP_UNK130(i,l) (0x0061c130 + (i) * 0x800 + (l) * 0x80) | 847 | #define NV50_SOR_DP_UNK130(i, l) (0x0061c130 + (i) * 0x800 + (l) * 0x80) |
| 848 | 848 | ||
| 849 | #define NV50_PDISPLAY_USER(i) ((i) * 0x1000 + 0x00640000) | 849 | #define NV50_PDISPLAY_USER(i) ((i) * 0x1000 + 0x00640000) |
| 850 | #define NV50_PDISPLAY_USER_PUT(i) ((i) * 0x1000 + 0x00640000) | 850 | #define NV50_PDISPLAY_USER_PUT(i) ((i) * 0x1000 + 0x00640000) |