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path: root/drivers/gpu/drm/nouveau/nouveau_irq.c
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Diffstat (limited to 'drivers/gpu/drm/nouveau/nouveau_irq.c')
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_irq.c42
1 files changed, 23 insertions, 19 deletions
diff --git a/drivers/gpu/drm/nouveau/nouveau_irq.c b/drivers/gpu/drm/nouveau/nouveau_irq.c
index 6fd51a51c608..7bfd9e6c9d67 100644
--- a/drivers/gpu/drm/nouveau/nouveau_irq.c
+++ b/drivers/gpu/drm/nouveau/nouveau_irq.c
@@ -42,6 +42,13 @@
42#include "nouveau_connector.h" 42#include "nouveau_connector.h"
43#include "nv50_display.h" 43#include "nv50_display.h"
44 44
45static DEFINE_RATELIMIT_STATE(nouveau_ratelimit_state, 3 * HZ, 20);
46
47static int nouveau_ratelimit(void)
48{
49 return __ratelimit(&nouveau_ratelimit_state);
50}
51
45void 52void
46nouveau_irq_preinstall(struct drm_device *dev) 53nouveau_irq_preinstall(struct drm_device *dev)
47{ 54{
@@ -53,6 +60,7 @@ nouveau_irq_preinstall(struct drm_device *dev)
53 if (dev_priv->card_type >= NV_50) { 60 if (dev_priv->card_type >= NV_50) {
54 INIT_WORK(&dev_priv->irq_work, nv50_display_irq_handler_bh); 61 INIT_WORK(&dev_priv->irq_work, nv50_display_irq_handler_bh);
55 INIT_WORK(&dev_priv->hpd_work, nv50_display_irq_hotplug_bh); 62 INIT_WORK(&dev_priv->hpd_work, nv50_display_irq_hotplug_bh);
63 spin_lock_init(&dev_priv->hpd_state.lock);
56 INIT_LIST_HEAD(&dev_priv->vbl_waiting); 64 INIT_LIST_HEAD(&dev_priv->vbl_waiting);
57 } 65 }
58} 66}
@@ -202,8 +210,8 @@ nouveau_fifo_irq_handler(struct drm_device *dev)
202 } 210 }
203 211
204 if (status & NV_PFIFO_INTR_DMA_PUSHER) { 212 if (status & NV_PFIFO_INTR_DMA_PUSHER) {
205 u32 get = nv_rd32(dev, 0x003244); 213 u32 dma_get = nv_rd32(dev, 0x003244);
206 u32 put = nv_rd32(dev, 0x003240); 214 u32 dma_put = nv_rd32(dev, 0x003240);
207 u32 push = nv_rd32(dev, 0x003220); 215 u32 push = nv_rd32(dev, 0x003220);
208 u32 state = nv_rd32(dev, 0x003228); 216 u32 state = nv_rd32(dev, 0x003228);
209 217
@@ -213,16 +221,18 @@ nouveau_fifo_irq_handler(struct drm_device *dev)
213 u32 ib_get = nv_rd32(dev, 0x003334); 221 u32 ib_get = nv_rd32(dev, 0x003334);
214 u32 ib_put = nv_rd32(dev, 0x003330); 222 u32 ib_put = nv_rd32(dev, 0x003330);
215 223
216 NV_INFO(dev, "PFIFO_DMA_PUSHER - Ch %d Get 0x%02x%08x " 224 if (nouveau_ratelimit())
225 NV_INFO(dev, "PFIFO_DMA_PUSHER - Ch %d Get 0x%02x%08x "
217 "Put 0x%02x%08x IbGet 0x%08x IbPut 0x%08x " 226 "Put 0x%02x%08x IbGet 0x%08x IbPut 0x%08x "
218 "State 0x%08x Push 0x%08x\n", 227 "State 0x%08x Push 0x%08x\n",
219 chid, ho_get, get, ho_put, put, ib_get, ib_put, 228 chid, ho_get, dma_get, ho_put,
220 state, push); 229 dma_put, ib_get, ib_put, state,
230 push);
221 231
222 /* METHOD_COUNT, in DMA_STATE on earlier chipsets */ 232 /* METHOD_COUNT, in DMA_STATE on earlier chipsets */
223 nv_wr32(dev, 0x003364, 0x00000000); 233 nv_wr32(dev, 0x003364, 0x00000000);
224 if (get != put || ho_get != ho_put) { 234 if (dma_get != dma_put || ho_get != ho_put) {
225 nv_wr32(dev, 0x003244, put); 235 nv_wr32(dev, 0x003244, dma_put);
226 nv_wr32(dev, 0x003328, ho_put); 236 nv_wr32(dev, 0x003328, ho_put);
227 } else 237 } else
228 if (ib_get != ib_put) { 238 if (ib_get != ib_put) {
@@ -231,10 +241,10 @@ nouveau_fifo_irq_handler(struct drm_device *dev)
231 } else { 241 } else {
232 NV_INFO(dev, "PFIFO_DMA_PUSHER - Ch %d Get 0x%08x " 242 NV_INFO(dev, "PFIFO_DMA_PUSHER - Ch %d Get 0x%08x "
233 "Put 0x%08x State 0x%08x Push 0x%08x\n", 243 "Put 0x%08x State 0x%08x Push 0x%08x\n",
234 chid, get, put, state, push); 244 chid, dma_get, dma_put, state, push);
235 245
236 if (get != put) 246 if (dma_get != dma_put)
237 nv_wr32(dev, 0x003244, put); 247 nv_wr32(dev, 0x003244, dma_put);
238 } 248 }
239 249
240 nv_wr32(dev, 0x003228, 0x00000000); 250 nv_wr32(dev, 0x003228, 0x00000000);
@@ -266,8 +276,9 @@ nouveau_fifo_irq_handler(struct drm_device *dev)
266 } 276 }
267 277
268 if (status) { 278 if (status) {
269 NV_INFO(dev, "PFIFO_INTR 0x%08x - Ch %d\n", 279 if (nouveau_ratelimit())
270 status, chid); 280 NV_INFO(dev, "PFIFO_INTR 0x%08x - Ch %d\n",
281 status, chid);
271 nv_wr32(dev, NV03_PFIFO_INTR_0, status); 282 nv_wr32(dev, NV03_PFIFO_INTR_0, status);
272 status = 0; 283 status = 0;
273 } 284 }
@@ -544,13 +555,6 @@ nouveau_pgraph_intr_notify(struct drm_device *dev, uint32_t nsource)
544 nouveau_graph_dump_trap_info(dev, "PGRAPH_NOTIFY", &trap); 555 nouveau_graph_dump_trap_info(dev, "PGRAPH_NOTIFY", &trap);
545} 556}
546 557
547static DEFINE_RATELIMIT_STATE(nouveau_ratelimit_state, 3 * HZ, 20);
548
549static int nouveau_ratelimit(void)
550{
551 return __ratelimit(&nouveau_ratelimit_state);
552}
553
554 558
555static inline void 559static inline void
556nouveau_pgraph_intr_error(struct drm_device *dev, uint32_t nsource) 560nouveau_pgraph_intr_error(struct drm_device *dev, uint32_t nsource)