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Diffstat (limited to 'drivers/gpu/drm/nouveau/nouveau_drv.h')
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_drv.h1286
1 files changed, 1286 insertions, 0 deletions
diff --git a/drivers/gpu/drm/nouveau/nouveau_drv.h b/drivers/gpu/drm/nouveau/nouveau_drv.h
new file mode 100644
index 000000000000..88b4c7b77e7f
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/nouveau_drv.h
@@ -0,0 +1,1286 @@
1/*
2 * Copyright 2005 Stephane Marchesin.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25#ifndef __NOUVEAU_DRV_H__
26#define __NOUVEAU_DRV_H__
27
28#define DRIVER_AUTHOR "Stephane Marchesin"
29#define DRIVER_EMAIL "dri-devel@lists.sourceforge.net"
30
31#define DRIVER_NAME "nouveau"
32#define DRIVER_DESC "nVidia Riva/TNT/GeForce"
33#define DRIVER_DATE "20090420"
34
35#define DRIVER_MAJOR 0
36#define DRIVER_MINOR 0
37#define DRIVER_PATCHLEVEL 15
38
39#define NOUVEAU_FAMILY 0x0000FFFF
40#define NOUVEAU_FLAGS 0xFFFF0000
41
42#include "ttm/ttm_bo_api.h"
43#include "ttm/ttm_bo_driver.h"
44#include "ttm/ttm_placement.h"
45#include "ttm/ttm_memory.h"
46#include "ttm/ttm_module.h"
47
48struct nouveau_fpriv {
49 struct ttm_object_file *tfile;
50};
51
52#define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT)
53
54#include "nouveau_drm.h"
55#include "nouveau_reg.h"
56#include "nouveau_bios.h"
57
58#define MAX_NUM_DCB_ENTRIES 16
59
60#define NOUVEAU_MAX_CHANNEL_NR 128
61
62#define NV50_VM_MAX_VRAM (2*1024*1024*1024ULL)
63#define NV50_VM_BLOCK (512*1024*1024ULL)
64#define NV50_VM_VRAM_NR (NV50_VM_MAX_VRAM / NV50_VM_BLOCK)
65
66struct nouveau_bo {
67 struct ttm_buffer_object bo;
68 struct ttm_placement placement;
69 u32 placements[3];
70 struct ttm_bo_kmap_obj kmap;
71 struct list_head head;
72
73 /* protected by ttm_bo_reserve() */
74 struct drm_file *reserved_by;
75 struct list_head entry;
76 int pbbo_index;
77
78 struct nouveau_channel *channel;
79
80 bool mappable;
81 bool no_vm;
82
83 uint32_t tile_mode;
84 uint32_t tile_flags;
85
86 struct drm_gem_object *gem;
87 struct drm_file *cpu_filp;
88 int pin_refcnt;
89};
90
91static inline struct nouveau_bo *
92nouveau_bo(struct ttm_buffer_object *bo)
93{
94 return container_of(bo, struct nouveau_bo, bo);
95}
96
97static inline struct nouveau_bo *
98nouveau_gem_object(struct drm_gem_object *gem)
99{
100 return gem ? gem->driver_private : NULL;
101}
102
103/* TODO: submit equivalent to TTM generic API upstream? */
104static inline void __iomem *
105nvbo_kmap_obj_iovirtual(struct nouveau_bo *nvbo)
106{
107 bool is_iomem;
108 void __iomem *ioptr = (void __force __iomem *)ttm_kmap_obj_virtual(
109 &nvbo->kmap, &is_iomem);
110 WARN_ON_ONCE(ioptr && !is_iomem);
111 return ioptr;
112}
113
114struct mem_block {
115 struct mem_block *next;
116 struct mem_block *prev;
117 uint64_t start;
118 uint64_t size;
119 struct drm_file *file_priv; /* NULL: free, -1: heap, other: real files */
120};
121
122enum nouveau_flags {
123 NV_NFORCE = 0x10000000,
124 NV_NFORCE2 = 0x20000000
125};
126
127#define NVOBJ_ENGINE_SW 0
128#define NVOBJ_ENGINE_GR 1
129#define NVOBJ_ENGINE_DISPLAY 2
130#define NVOBJ_ENGINE_INT 0xdeadbeef
131
132#define NVOBJ_FLAG_ALLOW_NO_REFS (1 << 0)
133#define NVOBJ_FLAG_ZERO_ALLOC (1 << 1)
134#define NVOBJ_FLAG_ZERO_FREE (1 << 2)
135#define NVOBJ_FLAG_FAKE (1 << 3)
136struct nouveau_gpuobj {
137 struct list_head list;
138
139 struct nouveau_channel *im_channel;
140 struct mem_block *im_pramin;
141 struct nouveau_bo *im_backing;
142 uint32_t im_backing_start;
143 uint32_t *im_backing_suspend;
144 int im_bound;
145
146 uint32_t flags;
147 int refcount;
148
149 uint32_t engine;
150 uint32_t class;
151
152 void (*dtor)(struct drm_device *, struct nouveau_gpuobj *);
153 void *priv;
154};
155
156struct nouveau_gpuobj_ref {
157 struct list_head list;
158
159 struct nouveau_gpuobj *gpuobj;
160 uint32_t instance;
161
162 struct nouveau_channel *channel;
163 int handle;
164};
165
166struct nouveau_channel {
167 struct drm_device *dev;
168 int id;
169
170 /* owner of this fifo */
171 struct drm_file *file_priv;
172 /* mapping of the fifo itself */
173 struct drm_local_map *map;
174
175 /* mapping of the regs controling the fifo */
176 void __iomem *user;
177 uint32_t user_get;
178 uint32_t user_put;
179
180 /* Fencing */
181 struct {
182 /* lock protects the pending list only */
183 spinlock_t lock;
184 struct list_head pending;
185 uint32_t sequence;
186 uint32_t sequence_ack;
187 uint32_t last_sequence_irq;
188 } fence;
189
190 /* DMA push buffer */
191 struct nouveau_gpuobj_ref *pushbuf;
192 struct nouveau_bo *pushbuf_bo;
193 uint32_t pushbuf_base;
194
195 /* Notifier memory */
196 struct nouveau_bo *notifier_bo;
197 struct mem_block *notifier_heap;
198
199 /* PFIFO context */
200 struct nouveau_gpuobj_ref *ramfc;
201 struct nouveau_gpuobj_ref *cache;
202
203 /* PGRAPH context */
204 /* XXX may be merge 2 pointers as private data ??? */
205 struct nouveau_gpuobj_ref *ramin_grctx;
206 void *pgraph_ctx;
207
208 /* NV50 VM */
209 struct nouveau_gpuobj *vm_pd;
210 struct nouveau_gpuobj_ref *vm_gart_pt;
211 struct nouveau_gpuobj_ref *vm_vram_pt[NV50_VM_VRAM_NR];
212
213 /* Objects */
214 struct nouveau_gpuobj_ref *ramin; /* Private instmem */
215 struct mem_block *ramin_heap; /* Private PRAMIN heap */
216 struct nouveau_gpuobj_ref *ramht; /* Hash table */
217 struct list_head ramht_refs; /* Objects referenced by RAMHT */
218
219 /* GPU object info for stuff used in-kernel (mm_enabled) */
220 uint32_t m2mf_ntfy;
221 uint32_t vram_handle;
222 uint32_t gart_handle;
223 bool accel_done;
224
225 /* Push buffer state (only for drm's channel on !mm_enabled) */
226 struct {
227 int max;
228 int free;
229 int cur;
230 int put;
231 /* access via pushbuf_bo */
232 } dma;
233
234 uint32_t sw_subchannel[8];
235
236 struct {
237 struct nouveau_gpuobj *vblsem;
238 uint32_t vblsem_offset;
239 uint32_t vblsem_rval;
240 struct list_head vbl_wait;
241 } nvsw;
242
243 struct {
244 bool active;
245 char name[32];
246 struct drm_info_list info;
247 } debugfs;
248};
249
250struct nouveau_instmem_engine {
251 void *priv;
252
253 int (*init)(struct drm_device *dev);
254 void (*takedown)(struct drm_device *dev);
255 int (*suspend)(struct drm_device *dev);
256 void (*resume)(struct drm_device *dev);
257
258 int (*populate)(struct drm_device *, struct nouveau_gpuobj *,
259 uint32_t *size);
260 void (*clear)(struct drm_device *, struct nouveau_gpuobj *);
261 int (*bind)(struct drm_device *, struct nouveau_gpuobj *);
262 int (*unbind)(struct drm_device *, struct nouveau_gpuobj *);
263 void (*prepare_access)(struct drm_device *, bool write);
264 void (*finish_access)(struct drm_device *);
265};
266
267struct nouveau_mc_engine {
268 int (*init)(struct drm_device *dev);
269 void (*takedown)(struct drm_device *dev);
270};
271
272struct nouveau_timer_engine {
273 int (*init)(struct drm_device *dev);
274 void (*takedown)(struct drm_device *dev);
275 uint64_t (*read)(struct drm_device *dev);
276};
277
278struct nouveau_fb_engine {
279 int (*init)(struct drm_device *dev);
280 void (*takedown)(struct drm_device *dev);
281};
282
283struct nouveau_fifo_engine {
284 void *priv;
285
286 int channels;
287
288 int (*init)(struct drm_device *);
289 void (*takedown)(struct drm_device *);
290
291 void (*disable)(struct drm_device *);
292 void (*enable)(struct drm_device *);
293 bool (*reassign)(struct drm_device *, bool enable);
294
295 int (*channel_id)(struct drm_device *);
296
297 int (*create_context)(struct nouveau_channel *);
298 void (*destroy_context)(struct nouveau_channel *);
299 int (*load_context)(struct nouveau_channel *);
300 int (*unload_context)(struct drm_device *);
301};
302
303struct nouveau_pgraph_object_method {
304 int id;
305 int (*exec)(struct nouveau_channel *chan, int grclass, int mthd,
306 uint32_t data);
307};
308
309struct nouveau_pgraph_object_class {
310 int id;
311 bool software;
312 struct nouveau_pgraph_object_method *methods;
313};
314
315struct nouveau_pgraph_engine {
316 struct nouveau_pgraph_object_class *grclass;
317 bool accel_blocked;
318 void *ctxprog;
319 void *ctxvals;
320
321 int (*init)(struct drm_device *);
322 void (*takedown)(struct drm_device *);
323
324 void (*fifo_access)(struct drm_device *, bool);
325
326 struct nouveau_channel *(*channel)(struct drm_device *);
327 int (*create_context)(struct nouveau_channel *);
328 void (*destroy_context)(struct nouveau_channel *);
329 int (*load_context)(struct nouveau_channel *);
330 int (*unload_context)(struct drm_device *);
331};
332
333struct nouveau_engine {
334 struct nouveau_instmem_engine instmem;
335 struct nouveau_mc_engine mc;
336 struct nouveau_timer_engine timer;
337 struct nouveau_fb_engine fb;
338 struct nouveau_pgraph_engine graph;
339 struct nouveau_fifo_engine fifo;
340};
341
342struct nouveau_pll_vals {
343 union {
344 struct {
345#ifdef __BIG_ENDIAN
346 uint8_t N1, M1, N2, M2;
347#else
348 uint8_t M1, N1, M2, N2;
349#endif
350 };
351 struct {
352 uint16_t NM1, NM2;
353 } __attribute__((packed));
354 };
355 int log2P;
356
357 int refclk;
358};
359
360enum nv04_fp_display_regs {
361 FP_DISPLAY_END,
362 FP_TOTAL,
363 FP_CRTC,
364 FP_SYNC_START,
365 FP_SYNC_END,
366 FP_VALID_START,
367 FP_VALID_END
368};
369
370struct nv04_crtc_reg {
371 unsigned char MiscOutReg; /* */
372 uint8_t CRTC[0x9f];
373 uint8_t CR58[0x10];
374 uint8_t Sequencer[5];
375 uint8_t Graphics[9];
376 uint8_t Attribute[21];
377 unsigned char DAC[768]; /* Internal Colorlookuptable */
378
379 /* PCRTC regs */
380 uint32_t fb_start;
381 uint32_t crtc_cfg;
382 uint32_t cursor_cfg;
383 uint32_t gpio_ext;
384 uint32_t crtc_830;
385 uint32_t crtc_834;
386 uint32_t crtc_850;
387 uint32_t crtc_eng_ctrl;
388
389 /* PRAMDAC regs */
390 uint32_t nv10_cursync;
391 struct nouveau_pll_vals pllvals;
392 uint32_t ramdac_gen_ctrl;
393 uint32_t ramdac_630;
394 uint32_t ramdac_634;
395 uint32_t tv_setup;
396 uint32_t tv_vtotal;
397 uint32_t tv_vskew;
398 uint32_t tv_vsync_delay;
399 uint32_t tv_htotal;
400 uint32_t tv_hskew;
401 uint32_t tv_hsync_delay;
402 uint32_t tv_hsync_delay2;
403 uint32_t fp_horiz_regs[7];
404 uint32_t fp_vert_regs[7];
405 uint32_t dither;
406 uint32_t fp_control;
407 uint32_t dither_regs[6];
408 uint32_t fp_debug_0;
409 uint32_t fp_debug_1;
410 uint32_t fp_debug_2;
411 uint32_t fp_margin_color;
412 uint32_t ramdac_8c0;
413 uint32_t ramdac_a20;
414 uint32_t ramdac_a24;
415 uint32_t ramdac_a34;
416 uint32_t ctv_regs[38];
417};
418
419struct nv04_output_reg {
420 uint32_t output;
421 int head;
422};
423
424struct nv04_mode_state {
425 uint32_t bpp;
426 uint32_t width;
427 uint32_t height;
428 uint32_t interlace;
429 uint32_t repaint0;
430 uint32_t repaint1;
431 uint32_t screen;
432 uint32_t scale;
433 uint32_t dither;
434 uint32_t extra;
435 uint32_t fifo;
436 uint32_t pixel;
437 uint32_t horiz;
438 int arbitration0;
439 int arbitration1;
440 uint32_t pll;
441 uint32_t pllB;
442 uint32_t vpll;
443 uint32_t vpll2;
444 uint32_t vpllB;
445 uint32_t vpll2B;
446 uint32_t pllsel;
447 uint32_t sel_clk;
448 uint32_t general;
449 uint32_t crtcOwner;
450 uint32_t head;
451 uint32_t head2;
452 uint32_t cursorConfig;
453 uint32_t cursor0;
454 uint32_t cursor1;
455 uint32_t cursor2;
456 uint32_t timingH;
457 uint32_t timingV;
458 uint32_t displayV;
459 uint32_t crtcSync;
460
461 struct nv04_crtc_reg crtc_reg[2];
462};
463
464enum nouveau_card_type {
465 NV_04 = 0x00,
466 NV_10 = 0x10,
467 NV_20 = 0x20,
468 NV_30 = 0x30,
469 NV_40 = 0x40,
470 NV_50 = 0x50,
471};
472
473struct drm_nouveau_private {
474 struct drm_device *dev;
475 enum {
476 NOUVEAU_CARD_INIT_DOWN,
477 NOUVEAU_CARD_INIT_DONE,
478 NOUVEAU_CARD_INIT_FAILED
479 } init_state;
480
481 /* the card type, takes NV_* as values */
482 enum nouveau_card_type card_type;
483 /* exact chipset, derived from NV_PMC_BOOT_0 */
484 int chipset;
485 int flags;
486
487 void __iomem *mmio;
488 void __iomem *ramin;
489 uint32_t ramin_size;
490
491 struct workqueue_struct *wq;
492 struct work_struct irq_work;
493
494 struct list_head vbl_waiting;
495
496 struct {
497 struct ttm_global_reference mem_global_ref;
498 struct ttm_bo_global_ref bo_global_ref;
499 struct ttm_bo_device bdev;
500 spinlock_t bo_list_lock;
501 struct list_head bo_list;
502 atomic_t validate_sequence;
503 } ttm;
504
505 struct fb_info *fbdev_info;
506
507 int fifo_alloc_count;
508 struct nouveau_channel *fifos[NOUVEAU_MAX_CHANNEL_NR];
509
510 struct nouveau_engine engine;
511 struct nouveau_channel *channel;
512
513 /* RAMIN configuration, RAMFC, RAMHT and RAMRO offsets */
514 struct nouveau_gpuobj *ramht;
515 uint32_t ramin_rsvd_vram;
516 uint32_t ramht_offset;
517 uint32_t ramht_size;
518 uint32_t ramht_bits;
519 uint32_t ramfc_offset;
520 uint32_t ramfc_size;
521 uint32_t ramro_offset;
522 uint32_t ramro_size;
523
524 /* base physical adresses */
525 uint64_t fb_phys;
526 uint64_t fb_available_size;
527 uint64_t fb_mappable_pages;
528 uint64_t fb_aper_free;
529
530 struct {
531 enum {
532 NOUVEAU_GART_NONE = 0,
533 NOUVEAU_GART_AGP,
534 NOUVEAU_GART_SGDMA
535 } type;
536 uint64_t aper_base;
537 uint64_t aper_size;
538 uint64_t aper_free;
539
540 struct nouveau_gpuobj *sg_ctxdma;
541 struct page *sg_dummy_page;
542 dma_addr_t sg_dummy_bus;
543
544 /* nottm hack */
545 struct drm_ttm_backend *sg_be;
546 unsigned long sg_handle;
547 } gart_info;
548
549 /* G8x/G9x virtual address space */
550 uint64_t vm_gart_base;
551 uint64_t vm_gart_size;
552 uint64_t vm_vram_base;
553 uint64_t vm_vram_size;
554 uint64_t vm_end;
555 struct nouveau_gpuobj *vm_vram_pt[NV50_VM_VRAM_NR];
556 int vm_vram_pt_nr;
557
558 /* the mtrr covering the FB */
559 int fb_mtrr;
560
561 struct mem_block *ramin_heap;
562
563 /* context table pointed to be NV_PGRAPH_CHANNEL_CTX_TABLE (0x400780) */
564 uint32_t ctx_table_size;
565 struct nouveau_gpuobj_ref *ctx_table;
566
567 struct list_head gpuobj_list;
568
569 struct nvbios VBIOS;
570 struct nouveau_bios_info *vbios;
571
572 struct nv04_mode_state mode_reg;
573 struct nv04_mode_state saved_reg;
574 uint32_t saved_vga_font[4][16384];
575 uint32_t crtc_owner;
576 uint32_t dac_users[4];
577
578 struct nouveau_suspend_resume {
579 uint32_t fifo_mode;
580 uint32_t graph_ctx_control;
581 uint32_t graph_state;
582 uint32_t *ramin_copy;
583 uint64_t ramin_size;
584 } susres;
585
586 struct backlight_device *backlight;
587 bool acpi_dsm;
588
589 struct nouveau_channel *evo;
590
591 struct {
592 struct dentry *channel_root;
593 } debugfs;
594};
595
596static inline struct drm_nouveau_private *
597nouveau_bdev(struct ttm_bo_device *bd)
598{
599 return container_of(bd, struct drm_nouveau_private, ttm.bdev);
600}
601
602static inline int
603nouveau_bo_ref(struct nouveau_bo *ref, struct nouveau_bo **pnvbo)
604{
605 struct nouveau_bo *prev;
606
607 if (!pnvbo)
608 return -EINVAL;
609 prev = *pnvbo;
610
611 *pnvbo = ref ? nouveau_bo(ttm_bo_reference(&ref->bo)) : NULL;
612 if (prev) {
613 struct ttm_buffer_object *bo = &prev->bo;
614
615 ttm_bo_unref(&bo);
616 }
617
618 return 0;
619}
620
621#define NOUVEAU_CHECK_INITIALISED_WITH_RETURN do { \
622 struct drm_nouveau_private *nv = dev->dev_private; \
623 if (nv->init_state != NOUVEAU_CARD_INIT_DONE) { \
624 NV_ERROR(dev, "called without init\n"); \
625 return -EINVAL; \
626 } \
627} while (0)
628
629#define NOUVEAU_GET_USER_CHANNEL_WITH_RETURN(id, cl, ch) do { \
630 struct drm_nouveau_private *nv = dev->dev_private; \
631 if (!nouveau_channel_owner(dev, (cl), (id))) { \
632 NV_ERROR(dev, "pid %d doesn't own channel %d\n", \
633 DRM_CURRENTPID, (id)); \
634 return -EPERM; \
635 } \
636 (ch) = nv->fifos[(id)]; \
637} while (0)
638
639/* nouveau_drv.c */
640extern int nouveau_noagp;
641extern int nouveau_duallink;
642extern int nouveau_uscript_lvds;
643extern int nouveau_uscript_tmds;
644extern int nouveau_vram_pushbuf;
645extern int nouveau_vram_notify;
646extern int nouveau_fbpercrtc;
647extern char *nouveau_tv_norm;
648extern int nouveau_reg_debug;
649extern char *nouveau_vbios;
650
651/* nouveau_state.c */
652extern void nouveau_preclose(struct drm_device *dev, struct drm_file *);
653extern int nouveau_load(struct drm_device *, unsigned long flags);
654extern int nouveau_firstopen(struct drm_device *);
655extern void nouveau_lastclose(struct drm_device *);
656extern int nouveau_unload(struct drm_device *);
657extern int nouveau_ioctl_getparam(struct drm_device *, void *data,
658 struct drm_file *);
659extern int nouveau_ioctl_setparam(struct drm_device *, void *data,
660 struct drm_file *);
661extern bool nouveau_wait_until(struct drm_device *, uint64_t timeout,
662 uint32_t reg, uint32_t mask, uint32_t val);
663extern bool nouveau_wait_for_idle(struct drm_device *);
664extern int nouveau_card_init(struct drm_device *);
665extern int nouveau_ioctl_card_init(struct drm_device *, void *data,
666 struct drm_file *);
667extern int nouveau_ioctl_suspend(struct drm_device *, void *data,
668 struct drm_file *);
669extern int nouveau_ioctl_resume(struct drm_device *, void *data,
670 struct drm_file *);
671
672/* nouveau_mem.c */
673extern int nouveau_mem_init_heap(struct mem_block **, uint64_t start,
674 uint64_t size);
675extern struct mem_block *nouveau_mem_alloc_block(struct mem_block *,
676 uint64_t size, int align2,
677 struct drm_file *, int tail);
678extern void nouveau_mem_takedown(struct mem_block **heap);
679extern void nouveau_mem_free_block(struct mem_block *);
680extern uint64_t nouveau_mem_fb_amount(struct drm_device *);
681extern void nouveau_mem_release(struct drm_file *, struct mem_block *heap);
682extern int nouveau_mem_init(struct drm_device *);
683extern int nouveau_mem_init_agp(struct drm_device *);
684extern void nouveau_mem_close(struct drm_device *);
685extern int nv50_mem_vm_bind_linear(struct drm_device *, uint64_t virt,
686 uint32_t size, uint32_t flags,
687 uint64_t phys);
688extern void nv50_mem_vm_unbind(struct drm_device *, uint64_t virt,
689 uint32_t size);
690
691/* nouveau_notifier.c */
692extern int nouveau_notifier_init_channel(struct nouveau_channel *);
693extern void nouveau_notifier_takedown_channel(struct nouveau_channel *);
694extern int nouveau_notifier_alloc(struct nouveau_channel *, uint32_t handle,
695 int cout, uint32_t *offset);
696extern int nouveau_notifier_offset(struct nouveau_gpuobj *, uint32_t *);
697extern int nouveau_ioctl_notifier_alloc(struct drm_device *, void *data,
698 struct drm_file *);
699extern int nouveau_ioctl_notifier_free(struct drm_device *, void *data,
700 struct drm_file *);
701
702/* nouveau_channel.c */
703extern struct drm_ioctl_desc nouveau_ioctls[];
704extern int nouveau_max_ioctl;
705extern void nouveau_channel_cleanup(struct drm_device *, struct drm_file *);
706extern int nouveau_channel_owner(struct drm_device *, struct drm_file *,
707 int channel);
708extern int nouveau_channel_alloc(struct drm_device *dev,
709 struct nouveau_channel **chan,
710 struct drm_file *file_priv,
711 uint32_t fb_ctxdma, uint32_t tt_ctxdma);
712extern void nouveau_channel_free(struct nouveau_channel *);
713extern int nouveau_channel_idle(struct nouveau_channel *chan);
714
715/* nouveau_object.c */
716extern int nouveau_gpuobj_early_init(struct drm_device *);
717extern int nouveau_gpuobj_init(struct drm_device *);
718extern void nouveau_gpuobj_takedown(struct drm_device *);
719extern void nouveau_gpuobj_late_takedown(struct drm_device *);
720extern int nouveau_gpuobj_suspend(struct drm_device *dev);
721extern void nouveau_gpuobj_suspend_cleanup(struct drm_device *dev);
722extern void nouveau_gpuobj_resume(struct drm_device *dev);
723extern int nouveau_gpuobj_channel_init(struct nouveau_channel *,
724 uint32_t vram_h, uint32_t tt_h);
725extern void nouveau_gpuobj_channel_takedown(struct nouveau_channel *);
726extern int nouveau_gpuobj_new(struct drm_device *, struct nouveau_channel *,
727 uint32_t size, int align, uint32_t flags,
728 struct nouveau_gpuobj **);
729extern int nouveau_gpuobj_del(struct drm_device *, struct nouveau_gpuobj **);
730extern int nouveau_gpuobj_ref_add(struct drm_device *, struct nouveau_channel *,
731 uint32_t handle, struct nouveau_gpuobj *,
732 struct nouveau_gpuobj_ref **);
733extern int nouveau_gpuobj_ref_del(struct drm_device *,
734 struct nouveau_gpuobj_ref **);
735extern int nouveau_gpuobj_ref_find(struct nouveau_channel *, uint32_t handle,
736 struct nouveau_gpuobj_ref **ref_ret);
737extern int nouveau_gpuobj_new_ref(struct drm_device *,
738 struct nouveau_channel *alloc_chan,
739 struct nouveau_channel *ref_chan,
740 uint32_t handle, uint32_t size, int align,
741 uint32_t flags, struct nouveau_gpuobj_ref **);
742extern int nouveau_gpuobj_new_fake(struct drm_device *,
743 uint32_t p_offset, uint32_t b_offset,
744 uint32_t size, uint32_t flags,
745 struct nouveau_gpuobj **,
746 struct nouveau_gpuobj_ref**);
747extern int nouveau_gpuobj_dma_new(struct nouveau_channel *, int class,
748 uint64_t offset, uint64_t size, int access,
749 int target, struct nouveau_gpuobj **);
750extern int nouveau_gpuobj_gart_dma_new(struct nouveau_channel *,
751 uint64_t offset, uint64_t size,
752 int access, struct nouveau_gpuobj **,
753 uint32_t *o_ret);
754extern int nouveau_gpuobj_gr_new(struct nouveau_channel *, int class,
755 struct nouveau_gpuobj **);
756extern int nouveau_ioctl_grobj_alloc(struct drm_device *, void *data,
757 struct drm_file *);
758extern int nouveau_ioctl_gpuobj_free(struct drm_device *, void *data,
759 struct drm_file *);
760
761/* nouveau_irq.c */
762extern irqreturn_t nouveau_irq_handler(DRM_IRQ_ARGS);
763extern void nouveau_irq_preinstall(struct drm_device *);
764extern int nouveau_irq_postinstall(struct drm_device *);
765extern void nouveau_irq_uninstall(struct drm_device *);
766
767/* nouveau_sgdma.c */
768extern int nouveau_sgdma_init(struct drm_device *);
769extern void nouveau_sgdma_takedown(struct drm_device *);
770extern int nouveau_sgdma_get_page(struct drm_device *, uint32_t offset,
771 uint32_t *page);
772extern struct ttm_backend *nouveau_sgdma_init_ttm(struct drm_device *);
773
774/* nouveau_debugfs.c */
775#if defined(CONFIG_DRM_NOUVEAU_DEBUG)
776extern int nouveau_debugfs_init(struct drm_minor *);
777extern void nouveau_debugfs_takedown(struct drm_minor *);
778extern int nouveau_debugfs_channel_init(struct nouveau_channel *);
779extern void nouveau_debugfs_channel_fini(struct nouveau_channel *);
780#else
781static inline int
782nouveau_debugfs_init(struct drm_minor *minor)
783{
784 return 0;
785}
786
787static inline void nouveau_debugfs_takedown(struct drm_minor *minor)
788{
789}
790
791static inline int
792nouveau_debugfs_channel_init(struct nouveau_channel *chan)
793{
794 return 0;
795}
796
797static inline void
798nouveau_debugfs_channel_fini(struct nouveau_channel *chan)
799{
800}
801#endif
802
803/* nouveau_dma.c */
804extern int nouveau_dma_init(struct nouveau_channel *);
805extern int nouveau_dma_wait(struct nouveau_channel *, int size);
806
807/* nouveau_acpi.c */
808#ifdef CONFIG_ACPI
809extern int nouveau_hybrid_setup(struct drm_device *dev);
810extern bool nouveau_dsm_probe(struct drm_device *dev);
811#else
812static inline int nouveau_hybrid_setup(struct drm_device *dev)
813{
814 return 0;
815}
816static inline bool nouveau_dsm_probe(struct drm_device *dev)
817{
818 return false;
819}
820#endif
821
822/* nouveau_backlight.c */
823#ifdef CONFIG_DRM_NOUVEAU_BACKLIGHT
824extern int nouveau_backlight_init(struct drm_device *);
825extern void nouveau_backlight_exit(struct drm_device *);
826#else
827static inline int nouveau_backlight_init(struct drm_device *dev)
828{
829 return 0;
830}
831
832static inline void nouveau_backlight_exit(struct drm_device *dev) { }
833#endif
834
835/* nouveau_bios.c */
836extern int nouveau_bios_init(struct drm_device *);
837extern void nouveau_bios_takedown(struct drm_device *dev);
838extern int nouveau_run_vbios_init(struct drm_device *);
839extern void nouveau_bios_run_init_table(struct drm_device *, uint16_t table,
840 struct dcb_entry *);
841extern struct dcb_gpio_entry *nouveau_bios_gpio_entry(struct drm_device *,
842 enum dcb_gpio_tag);
843extern struct dcb_connector_table_entry *
844nouveau_bios_connector_entry(struct drm_device *, int index);
845extern int get_pll_limits(struct drm_device *, uint32_t limit_match,
846 struct pll_lims *);
847extern int nouveau_bios_run_display_table(struct drm_device *,
848 struct dcb_entry *,
849 uint32_t script, int pxclk);
850extern void *nouveau_bios_dp_table(struct drm_device *, struct dcb_entry *,
851 int *length);
852extern bool nouveau_bios_fp_mode(struct drm_device *, struct drm_display_mode *);
853extern uint8_t *nouveau_bios_embedded_edid(struct drm_device *);
854extern int nouveau_bios_parse_lvds_table(struct drm_device *, int pxclk,
855 bool *dl, bool *if_is_24bit);
856extern int run_tmds_table(struct drm_device *, struct dcb_entry *,
857 int head, int pxclk);
858extern int call_lvds_script(struct drm_device *, struct dcb_entry *, int head,
859 enum LVDS_script, int pxclk);
860
861/* nouveau_ttm.c */
862int nouveau_ttm_global_init(struct drm_nouveau_private *);
863void nouveau_ttm_global_release(struct drm_nouveau_private *);
864int nouveau_ttm_mmap(struct file *, struct vm_area_struct *);
865
866/* nouveau_dp.c */
867int nouveau_dp_auxch(struct nouveau_i2c_chan *auxch, int cmd, int addr,
868 uint8_t *data, int data_nr);
869bool nouveau_dp_detect(struct drm_encoder *);
870bool nouveau_dp_link_train(struct drm_encoder *);
871
872/* nv04_fb.c */
873extern int nv04_fb_init(struct drm_device *);
874extern void nv04_fb_takedown(struct drm_device *);
875
876/* nv10_fb.c */
877extern int nv10_fb_init(struct drm_device *);
878extern void nv10_fb_takedown(struct drm_device *);
879
880/* nv40_fb.c */
881extern int nv40_fb_init(struct drm_device *);
882extern void nv40_fb_takedown(struct drm_device *);
883
884/* nv04_fifo.c */
885extern int nv04_fifo_init(struct drm_device *);
886extern void nv04_fifo_disable(struct drm_device *);
887extern void nv04_fifo_enable(struct drm_device *);
888extern bool nv04_fifo_reassign(struct drm_device *, bool);
889extern int nv04_fifo_channel_id(struct drm_device *);
890extern int nv04_fifo_create_context(struct nouveau_channel *);
891extern void nv04_fifo_destroy_context(struct nouveau_channel *);
892extern int nv04_fifo_load_context(struct nouveau_channel *);
893extern int nv04_fifo_unload_context(struct drm_device *);
894
895/* nv10_fifo.c */
896extern int nv10_fifo_init(struct drm_device *);
897extern int nv10_fifo_channel_id(struct drm_device *);
898extern int nv10_fifo_create_context(struct nouveau_channel *);
899extern void nv10_fifo_destroy_context(struct nouveau_channel *);
900extern int nv10_fifo_load_context(struct nouveau_channel *);
901extern int nv10_fifo_unload_context(struct drm_device *);
902
903/* nv40_fifo.c */
904extern int nv40_fifo_init(struct drm_device *);
905extern int nv40_fifo_create_context(struct nouveau_channel *);
906extern void nv40_fifo_destroy_context(struct nouveau_channel *);
907extern int nv40_fifo_load_context(struct nouveau_channel *);
908extern int nv40_fifo_unload_context(struct drm_device *);
909
910/* nv50_fifo.c */
911extern int nv50_fifo_init(struct drm_device *);
912extern void nv50_fifo_takedown(struct drm_device *);
913extern int nv50_fifo_channel_id(struct drm_device *);
914extern int nv50_fifo_create_context(struct nouveau_channel *);
915extern void nv50_fifo_destroy_context(struct nouveau_channel *);
916extern int nv50_fifo_load_context(struct nouveau_channel *);
917extern int nv50_fifo_unload_context(struct drm_device *);
918
919/* nv04_graph.c */
920extern struct nouveau_pgraph_object_class nv04_graph_grclass[];
921extern int nv04_graph_init(struct drm_device *);
922extern void nv04_graph_takedown(struct drm_device *);
923extern void nv04_graph_fifo_access(struct drm_device *, bool);
924extern struct nouveau_channel *nv04_graph_channel(struct drm_device *);
925extern int nv04_graph_create_context(struct nouveau_channel *);
926extern void nv04_graph_destroy_context(struct nouveau_channel *);
927extern int nv04_graph_load_context(struct nouveau_channel *);
928extern int nv04_graph_unload_context(struct drm_device *);
929extern void nv04_graph_context_switch(struct drm_device *);
930
931/* nv10_graph.c */
932extern struct nouveau_pgraph_object_class nv10_graph_grclass[];
933extern int nv10_graph_init(struct drm_device *);
934extern void nv10_graph_takedown(struct drm_device *);
935extern struct nouveau_channel *nv10_graph_channel(struct drm_device *);
936extern int nv10_graph_create_context(struct nouveau_channel *);
937extern void nv10_graph_destroy_context(struct nouveau_channel *);
938extern int nv10_graph_load_context(struct nouveau_channel *);
939extern int nv10_graph_unload_context(struct drm_device *);
940extern void nv10_graph_context_switch(struct drm_device *);
941
942/* nv20_graph.c */
943extern struct nouveau_pgraph_object_class nv20_graph_grclass[];
944extern struct nouveau_pgraph_object_class nv30_graph_grclass[];
945extern int nv20_graph_create_context(struct nouveau_channel *);
946extern void nv20_graph_destroy_context(struct nouveau_channel *);
947extern int nv20_graph_load_context(struct nouveau_channel *);
948extern int nv20_graph_unload_context(struct drm_device *);
949extern int nv20_graph_init(struct drm_device *);
950extern void nv20_graph_takedown(struct drm_device *);
951extern int nv30_graph_init(struct drm_device *);
952
953/* nv40_graph.c */
954extern struct nouveau_pgraph_object_class nv40_graph_grclass[];
955extern int nv40_graph_init(struct drm_device *);
956extern void nv40_graph_takedown(struct drm_device *);
957extern struct nouveau_channel *nv40_graph_channel(struct drm_device *);
958extern int nv40_graph_create_context(struct nouveau_channel *);
959extern void nv40_graph_destroy_context(struct nouveau_channel *);
960extern int nv40_graph_load_context(struct nouveau_channel *);
961extern int nv40_graph_unload_context(struct drm_device *);
962extern int nv40_grctx_init(struct drm_device *);
963extern void nv40_grctx_fini(struct drm_device *);
964extern void nv40_grctx_vals_load(struct drm_device *, struct nouveau_gpuobj *);
965
966/* nv50_graph.c */
967extern struct nouveau_pgraph_object_class nv50_graph_grclass[];
968extern int nv50_graph_init(struct drm_device *);
969extern void nv50_graph_takedown(struct drm_device *);
970extern void nv50_graph_fifo_access(struct drm_device *, bool);
971extern struct nouveau_channel *nv50_graph_channel(struct drm_device *);
972extern int nv50_graph_create_context(struct nouveau_channel *);
973extern void nv50_graph_destroy_context(struct nouveau_channel *);
974extern int nv50_graph_load_context(struct nouveau_channel *);
975extern int nv50_graph_unload_context(struct drm_device *);
976extern void nv50_graph_context_switch(struct drm_device *);
977
978/* nv04_instmem.c */
979extern int nv04_instmem_init(struct drm_device *);
980extern void nv04_instmem_takedown(struct drm_device *);
981extern int nv04_instmem_suspend(struct drm_device *);
982extern void nv04_instmem_resume(struct drm_device *);
983extern int nv04_instmem_populate(struct drm_device *, struct nouveau_gpuobj *,
984 uint32_t *size);
985extern void nv04_instmem_clear(struct drm_device *, struct nouveau_gpuobj *);
986extern int nv04_instmem_bind(struct drm_device *, struct nouveau_gpuobj *);
987extern int nv04_instmem_unbind(struct drm_device *, struct nouveau_gpuobj *);
988extern void nv04_instmem_prepare_access(struct drm_device *, bool write);
989extern void nv04_instmem_finish_access(struct drm_device *);
990
991/* nv50_instmem.c */
992extern int nv50_instmem_init(struct drm_device *);
993extern void nv50_instmem_takedown(struct drm_device *);
994extern int nv50_instmem_suspend(struct drm_device *);
995extern void nv50_instmem_resume(struct drm_device *);
996extern int nv50_instmem_populate(struct drm_device *, struct nouveau_gpuobj *,
997 uint32_t *size);
998extern void nv50_instmem_clear(struct drm_device *, struct nouveau_gpuobj *);
999extern int nv50_instmem_bind(struct drm_device *, struct nouveau_gpuobj *);
1000extern int nv50_instmem_unbind(struct drm_device *, struct nouveau_gpuobj *);
1001extern void nv50_instmem_prepare_access(struct drm_device *, bool write);
1002extern void nv50_instmem_finish_access(struct drm_device *);
1003
1004/* nv04_mc.c */
1005extern int nv04_mc_init(struct drm_device *);
1006extern void nv04_mc_takedown(struct drm_device *);
1007
1008/* nv40_mc.c */
1009extern int nv40_mc_init(struct drm_device *);
1010extern void nv40_mc_takedown(struct drm_device *);
1011
1012/* nv50_mc.c */
1013extern int nv50_mc_init(struct drm_device *);
1014extern void nv50_mc_takedown(struct drm_device *);
1015
1016/* nv04_timer.c */
1017extern int nv04_timer_init(struct drm_device *);
1018extern uint64_t nv04_timer_read(struct drm_device *);
1019extern void nv04_timer_takedown(struct drm_device *);
1020
1021extern long nouveau_compat_ioctl(struct file *file, unsigned int cmd,
1022 unsigned long arg);
1023
1024/* nv04_dac.c */
1025extern int nv04_dac_create(struct drm_device *dev, struct dcb_entry *entry);
1026extern enum drm_connector_status nv17_dac_detect(struct drm_encoder *encoder,
1027 struct drm_connector *connector);
1028extern int nv04_dac_output_offset(struct drm_encoder *encoder);
1029extern void nv04_dac_update_dacclk(struct drm_encoder *encoder, bool enable);
1030
1031/* nv04_dfp.c */
1032extern int nv04_dfp_create(struct drm_device *dev, struct dcb_entry *entry);
1033extern int nv04_dfp_get_bound_head(struct drm_device *dev, struct dcb_entry *dcbent);
1034extern void nv04_dfp_bind_head(struct drm_device *dev, struct dcb_entry *dcbent,
1035 int head, bool dl);
1036extern void nv04_dfp_disable(struct drm_device *dev, int head);
1037extern void nv04_dfp_update_fp_control(struct drm_encoder *encoder, int mode);
1038
1039/* nv04_tv.c */
1040extern int nv04_tv_identify(struct drm_device *dev, int i2c_index);
1041extern int nv04_tv_create(struct drm_device *dev, struct dcb_entry *entry);
1042
1043/* nv17_tv.c */
1044extern int nv17_tv_create(struct drm_device *dev, struct dcb_entry *entry);
1045extern enum drm_connector_status nv17_tv_detect(struct drm_encoder *encoder,
1046 struct drm_connector *connector,
1047 uint32_t pin_mask);
1048
1049/* nv04_display.c */
1050extern int nv04_display_create(struct drm_device *);
1051extern void nv04_display_destroy(struct drm_device *);
1052extern void nv04_display_restore(struct drm_device *);
1053
1054/* nv04_crtc.c */
1055extern int nv04_crtc_create(struct drm_device *, int index);
1056
1057/* nouveau_bo.c */
1058extern struct ttm_bo_driver nouveau_bo_driver;
1059extern int nouveau_bo_new(struct drm_device *, struct nouveau_channel *,
1060 int size, int align, uint32_t flags,
1061 uint32_t tile_mode, uint32_t tile_flags,
1062 bool no_vm, bool mappable, struct nouveau_bo **);
1063extern int nouveau_bo_pin(struct nouveau_bo *, uint32_t flags);
1064extern int nouveau_bo_unpin(struct nouveau_bo *);
1065extern int nouveau_bo_map(struct nouveau_bo *);
1066extern void nouveau_bo_unmap(struct nouveau_bo *);
1067extern void nouveau_bo_placement_set(struct nouveau_bo *, uint32_t memtype);
1068extern u16 nouveau_bo_rd16(struct nouveau_bo *nvbo, unsigned index);
1069extern void nouveau_bo_wr16(struct nouveau_bo *nvbo, unsigned index, u16 val);
1070extern u32 nouveau_bo_rd32(struct nouveau_bo *nvbo, unsigned index);
1071extern void nouveau_bo_wr32(struct nouveau_bo *nvbo, unsigned index, u32 val);
1072
1073/* nouveau_fence.c */
1074struct nouveau_fence;
1075extern int nouveau_fence_init(struct nouveau_channel *);
1076extern void nouveau_fence_fini(struct nouveau_channel *);
1077extern void nouveau_fence_update(struct nouveau_channel *);
1078extern int nouveau_fence_new(struct nouveau_channel *, struct nouveau_fence **,
1079 bool emit);
1080extern int nouveau_fence_emit(struct nouveau_fence *);
1081struct nouveau_channel *nouveau_fence_channel(struct nouveau_fence *);
1082extern bool nouveau_fence_signalled(void *obj, void *arg);
1083extern int nouveau_fence_wait(void *obj, void *arg, bool lazy, bool intr);
1084extern int nouveau_fence_flush(void *obj, void *arg);
1085extern void nouveau_fence_unref(void **obj);
1086extern void *nouveau_fence_ref(void *obj);
1087extern void nouveau_fence_handler(struct drm_device *dev, int channel);
1088
1089/* nouveau_gem.c */
1090extern int nouveau_gem_new(struct drm_device *, struct nouveau_channel *,
1091 int size, int align, uint32_t flags,
1092 uint32_t tile_mode, uint32_t tile_flags,
1093 bool no_vm, bool mappable, struct nouveau_bo **);
1094extern int nouveau_gem_object_new(struct drm_gem_object *);
1095extern void nouveau_gem_object_del(struct drm_gem_object *);
1096extern int nouveau_gem_ioctl_new(struct drm_device *, void *,
1097 struct drm_file *);
1098extern int nouveau_gem_ioctl_pushbuf(struct drm_device *, void *,
1099 struct drm_file *);
1100extern int nouveau_gem_ioctl_pushbuf_call(struct drm_device *, void *,
1101 struct drm_file *);
1102extern int nouveau_gem_ioctl_pushbuf_call2(struct drm_device *, void *,
1103 struct drm_file *);
1104extern int nouveau_gem_ioctl_pin(struct drm_device *, void *,
1105 struct drm_file *);
1106extern int nouveau_gem_ioctl_unpin(struct drm_device *, void *,
1107 struct drm_file *);
1108extern int nouveau_gem_ioctl_tile(struct drm_device *, void *,
1109 struct drm_file *);
1110extern int nouveau_gem_ioctl_cpu_prep(struct drm_device *, void *,
1111 struct drm_file *);
1112extern int nouveau_gem_ioctl_cpu_fini(struct drm_device *, void *,
1113 struct drm_file *);
1114extern int nouveau_gem_ioctl_info(struct drm_device *, void *,
1115 struct drm_file *);
1116
1117/* nv17_gpio.c */
1118int nv17_gpio_get(struct drm_device *dev, enum dcb_gpio_tag tag);
1119int nv17_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state);
1120
1121#ifndef ioread32_native
1122#ifdef __BIG_ENDIAN
1123#define ioread16_native ioread16be
1124#define iowrite16_native iowrite16be
1125#define ioread32_native ioread32be
1126#define iowrite32_native iowrite32be
1127#else /* def __BIG_ENDIAN */
1128#define ioread16_native ioread16
1129#define iowrite16_native iowrite16
1130#define ioread32_native ioread32
1131#define iowrite32_native iowrite32
1132#endif /* def __BIG_ENDIAN else */
1133#endif /* !ioread32_native */
1134
1135/* channel control reg access */
1136static inline u32 nvchan_rd32(struct nouveau_channel *chan, unsigned reg)
1137{
1138 return ioread32_native(chan->user + reg);
1139}
1140
1141static inline void nvchan_wr32(struct nouveau_channel *chan,
1142 unsigned reg, u32 val)
1143{
1144 iowrite32_native(val, chan->user + reg);
1145}
1146
1147/* register access */
1148static inline u32 nv_rd32(struct drm_device *dev, unsigned reg)
1149{
1150 struct drm_nouveau_private *dev_priv = dev->dev_private;
1151 return ioread32_native(dev_priv->mmio + reg);
1152}
1153
1154static inline void nv_wr32(struct drm_device *dev, unsigned reg, u32 val)
1155{
1156 struct drm_nouveau_private *dev_priv = dev->dev_private;
1157 iowrite32_native(val, dev_priv->mmio + reg);
1158}
1159
1160static inline u8 nv_rd08(struct drm_device *dev, unsigned reg)
1161{
1162 struct drm_nouveau_private *dev_priv = dev->dev_private;
1163 return ioread8(dev_priv->mmio + reg);
1164}
1165
1166static inline void nv_wr08(struct drm_device *dev, unsigned reg, u8 val)
1167{
1168 struct drm_nouveau_private *dev_priv = dev->dev_private;
1169 iowrite8(val, dev_priv->mmio + reg);
1170}
1171
1172#define nv_wait(reg, mask, val) \
1173 nouveau_wait_until(dev, 2000000000ULL, (reg), (mask), (val))
1174
1175/* PRAMIN access */
1176static inline u32 nv_ri32(struct drm_device *dev, unsigned offset)
1177{
1178 struct drm_nouveau_private *dev_priv = dev->dev_private;
1179 return ioread32_native(dev_priv->ramin + offset);
1180}
1181
1182static inline void nv_wi32(struct drm_device *dev, unsigned offset, u32 val)
1183{
1184 struct drm_nouveau_private *dev_priv = dev->dev_private;
1185 iowrite32_native(val, dev_priv->ramin + offset);
1186}
1187
1188/* object access */
1189static inline u32 nv_ro32(struct drm_device *dev, struct nouveau_gpuobj *obj,
1190 unsigned index)
1191{
1192 return nv_ri32(dev, obj->im_pramin->start + index * 4);
1193}
1194
1195static inline void nv_wo32(struct drm_device *dev, struct nouveau_gpuobj *obj,
1196 unsigned index, u32 val)
1197{
1198 nv_wi32(dev, obj->im_pramin->start + index * 4, val);
1199}
1200
1201/*
1202 * Logging
1203 * Argument d is (struct drm_device *).
1204 */
1205#define NV_PRINTK(level, d, fmt, arg...) \
1206 printk(level "[" DRM_NAME "] " DRIVER_NAME " %s: " fmt, \
1207 pci_name(d->pdev), ##arg)
1208#ifndef NV_DEBUG_NOTRACE
1209#define NV_DEBUG(d, fmt, arg...) do { \
1210 if (drm_debug) { \
1211 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \
1212 __LINE__, ##arg); \
1213 } \
1214} while (0)
1215#else
1216#define NV_DEBUG(d, fmt, arg...) do { \
1217 if (drm_debug) \
1218 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \
1219} while (0)
1220#endif
1221#define NV_ERROR(d, fmt, arg...) NV_PRINTK(KERN_ERR, d, fmt, ##arg)
1222#define NV_INFO(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg)
1223#define NV_TRACEWARN(d, fmt, arg...) NV_PRINTK(KERN_NOTICE, d, fmt, ##arg)
1224#define NV_TRACE(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg)
1225#define NV_WARN(d, fmt, arg...) NV_PRINTK(KERN_WARNING, d, fmt, ##arg)
1226
1227/* nouveau_reg_debug bitmask */
1228enum {
1229 NOUVEAU_REG_DEBUG_MC = 0x1,
1230 NOUVEAU_REG_DEBUG_VIDEO = 0x2,
1231 NOUVEAU_REG_DEBUG_FB = 0x4,
1232 NOUVEAU_REG_DEBUG_EXTDEV = 0x8,
1233 NOUVEAU_REG_DEBUG_CRTC = 0x10,
1234 NOUVEAU_REG_DEBUG_RAMDAC = 0x20,
1235 NOUVEAU_REG_DEBUG_VGACRTC = 0x40,
1236 NOUVEAU_REG_DEBUG_RMVIO = 0x80,
1237 NOUVEAU_REG_DEBUG_VGAATTR = 0x100,
1238 NOUVEAU_REG_DEBUG_EVO = 0x200,
1239};
1240
1241#define NV_REG_DEBUG(type, dev, fmt, arg...) do { \
1242 if (nouveau_reg_debug & NOUVEAU_REG_DEBUG_##type) \
1243 NV_PRINTK(KERN_DEBUG, dev, "%s: " fmt, __func__, ##arg); \
1244} while (0)
1245
1246static inline bool
1247nv_two_heads(struct drm_device *dev)
1248{
1249 struct drm_nouveau_private *dev_priv = dev->dev_private;
1250 const int impl = dev->pci_device & 0x0ff0;
1251
1252 if (dev_priv->card_type >= NV_10 && impl != 0x0100 &&
1253 impl != 0x0150 && impl != 0x01a0 && impl != 0x0200)
1254 return true;
1255
1256 return false;
1257}
1258
1259static inline bool
1260nv_gf4_disp_arch(struct drm_device *dev)
1261{
1262 return nv_two_heads(dev) && (dev->pci_device & 0x0ff0) != 0x0110;
1263}
1264
1265static inline bool
1266nv_two_reg_pll(struct drm_device *dev)
1267{
1268 struct drm_nouveau_private *dev_priv = dev->dev_private;
1269 const int impl = dev->pci_device & 0x0ff0;
1270
1271 if (impl == 0x0310 || impl == 0x0340 || dev_priv->card_type >= NV_40)
1272 return true;
1273 return false;
1274}
1275
1276#define NV50_NVSW 0x0000506e
1277#define NV50_NVSW_DMA_SEMAPHORE 0x00000060
1278#define NV50_NVSW_SEMAPHORE_OFFSET 0x00000064
1279#define NV50_NVSW_SEMAPHORE_ACQUIRE 0x00000068
1280#define NV50_NVSW_SEMAPHORE_RELEASE 0x0000006c
1281#define NV50_NVSW_DMA_VBLSEM 0x0000018c
1282#define NV50_NVSW_VBLSEM_OFFSET 0x00000400
1283#define NV50_NVSW_VBLSEM_RELEASE_VALUE 0x00000404
1284#define NV50_NVSW_VBLSEM_RELEASE 0x00000408
1285
1286#endif /* __NOUVEAU_DRV_H__ */
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-11 19:41:43 -0500