diff options
Diffstat (limited to 'drivers/gpu/drm/msm/adreno/a3xx.xml.h')
-rw-r--r-- | drivers/gpu/drm/msm/adreno/a3xx.xml.h | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/drivers/gpu/drm/msm/adreno/a3xx.xml.h b/drivers/gpu/drm/msm/adreno/a3xx.xml.h index 303e8a9e91a5..82d015279b47 100644 --- a/drivers/gpu/drm/msm/adreno/a3xx.xml.h +++ b/drivers/gpu/drm/msm/adreno/a3xx.xml.h | |||
@@ -12,9 +12,9 @@ The rules-ng-ng source files this header was generated from are: | |||
12 | - /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2013-03-31 16:51:27) | 12 | - /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2013-03-31 16:51:27) |
13 | - /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml ( 32901 bytes, from 2014-06-02 15:21:30) | 13 | - /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml ( 32901 bytes, from 2014-06-02 15:21:30) |
14 | - /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 9859 bytes, from 2014-06-02 15:21:30) | 14 | - /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 9859 bytes, from 2014-06-02 15:21:30) |
15 | - /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 14477 bytes, from 2014-05-16 11:51:57) | 15 | - /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 14960 bytes, from 2014-07-27 17:22:13) |
16 | - /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 58020 bytes, from 2014-06-25 12:57:16) | 16 | - /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 58020 bytes, from 2014-08-01 12:22:48) |
17 | - /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 26602 bytes, from 2014-06-25 12:57:16) | 17 | - /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 41068 bytes, from 2014-08-01 12:22:48) |
18 | 18 | ||
19 | Copyright (C) 2013-2014 by the following authors: | 19 | Copyright (C) 2013-2014 by the following authors: |
20 | - Rob Clark <robdclark@gmail.com> (robclark) | 20 | - Rob Clark <robdclark@gmail.com> (robclark) |
@@ -654,7 +654,7 @@ static inline uint32_t A3XX_GRAS_SU_POINT_SIZE(float val) | |||
654 | #define A3XX_GRAS_SU_POLY_OFFSET_SCALE_VAL__SHIFT 0 | 654 | #define A3XX_GRAS_SU_POLY_OFFSET_SCALE_VAL__SHIFT 0 |
655 | static inline uint32_t A3XX_GRAS_SU_POLY_OFFSET_SCALE_VAL(float val) | 655 | static inline uint32_t A3XX_GRAS_SU_POLY_OFFSET_SCALE_VAL(float val) |
656 | { | 656 | { |
657 | return ((((uint32_t)(val * 40.0))) << A3XX_GRAS_SU_POLY_OFFSET_SCALE_VAL__SHIFT) & A3XX_GRAS_SU_POLY_OFFSET_SCALE_VAL__MASK; | 657 | return ((((uint32_t)(val * 28.0))) << A3XX_GRAS_SU_POLY_OFFSET_SCALE_VAL__SHIFT) & A3XX_GRAS_SU_POLY_OFFSET_SCALE_VAL__MASK; |
658 | } | 658 | } |
659 | 659 | ||
660 | #define REG_A3XX_GRAS_SU_POLY_OFFSET_OFFSET 0x0000206d | 660 | #define REG_A3XX_GRAS_SU_POLY_OFFSET_OFFSET 0x0000206d |
@@ -662,7 +662,7 @@ static inline uint32_t A3XX_GRAS_SU_POLY_OFFSET_SCALE_VAL(float val) | |||
662 | #define A3XX_GRAS_SU_POLY_OFFSET_OFFSET__SHIFT 0 | 662 | #define A3XX_GRAS_SU_POLY_OFFSET_OFFSET__SHIFT 0 |
663 | static inline uint32_t A3XX_GRAS_SU_POLY_OFFSET_OFFSET(float val) | 663 | static inline uint32_t A3XX_GRAS_SU_POLY_OFFSET_OFFSET(float val) |
664 | { | 664 | { |
665 | return ((((uint32_t)(val * 44.0))) << A3XX_GRAS_SU_POLY_OFFSET_OFFSET__SHIFT) & A3XX_GRAS_SU_POLY_OFFSET_OFFSET__MASK; | 665 | return ((((uint32_t)(val * 28.0))) << A3XX_GRAS_SU_POLY_OFFSET_OFFSET__SHIFT) & A3XX_GRAS_SU_POLY_OFFSET_OFFSET__MASK; |
666 | } | 666 | } |
667 | 667 | ||
668 | #define REG_A3XX_GRAS_SU_MODE_CONTROL 0x00002070 | 668 | #define REG_A3XX_GRAS_SU_MODE_CONTROL 0x00002070 |
@@ -1696,7 +1696,7 @@ static inline uint32_t A3XX_SP_VS_CTRL_REG1_CONSTFOOTPRINT(uint32_t val) | |||
1696 | { | 1696 | { |
1697 | return ((val) << A3XX_SP_VS_CTRL_REG1_CONSTFOOTPRINT__SHIFT) & A3XX_SP_VS_CTRL_REG1_CONSTFOOTPRINT__MASK; | 1697 | return ((val) << A3XX_SP_VS_CTRL_REG1_CONSTFOOTPRINT__SHIFT) & A3XX_SP_VS_CTRL_REG1_CONSTFOOTPRINT__MASK; |
1698 | } | 1698 | } |
1699 | #define A3XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING__MASK 0x3f000000 | 1699 | #define A3XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING__MASK 0x7f000000 |
1700 | #define A3XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING__SHIFT 24 | 1700 | #define A3XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING__SHIFT 24 |
1701 | static inline uint32_t A3XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING(uint32_t val) | 1701 | static inline uint32_t A3XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING(uint32_t val) |
1702 | { | 1702 | { |