3 files changed, 87 insertions, 30 deletions

diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index e5daad5f75fb..27ea6bdebce7 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -2737,24 +2737,11 @@ i915_gem_retire_requests_ring(struct intel_engine_cs *ring)
 
         WARN_ON(i915_verify_lists(ring->dev));
 
-        /* Move any buffers on the active list that are no longer referenced
-         * by the ringbuffer to the flushing/inactive lists as appropriate,
-         * before we free the context associated with the requests.
+        /* Retire requests first as we use it above for the early return.
+         * If we retire requests last, we may use a later seqno and so clear
+         * the requests lists without clearing the active list, leading to
+         * confusion.
          */
-        while (!list_empty(&ring->active_list)) {
-                struct drm_i915_gem_object *obj;
-
-                obj = list_first_entry(&ring->active_list,
-                                      struct drm_i915_gem_object,
-                                      ring_list);
-
-                if (!i915_gem_request_completed(obj->last_read_req, true))
-                        break;
-
-                i915_gem_object_move_to_inactive(obj);
-        }
-
-
         while (!list_empty(&ring->request_list)) {
                 struct drm_i915_gem_request *request;
                 struct intel_ringbuffer *ringbuf;
@@ -2789,6 +2776,23 @@ i915_gem_retire_requests_ring(struct intel_engine_cs *ring)
                 i915_gem_free_request(request);
         }
 
+        /* Move any buffers on the active list that are no longer referenced
+         * by the ringbuffer to the flushing/inactive lists as appropriate,
+         * before we free the context associated with the requests.
+         */
+        while (!list_empty(&ring->active_list)) {
+                struct drm_i915_gem_object *obj;
+
+                obj = list_first_entry(&ring->active_list,
+                                      struct drm_i915_gem_object,
+                                      ring_list);
+
+                if (!i915_gem_request_completed(obj->last_read_req, true))
+                        break;
+
+                i915_gem_object_move_to_inactive(obj);
+        }
+
         if (unlikely(ring->trace_irq_req &&
                      i915_gem_request_completed(ring->trace_irq_req, true))) {
                 ring->irq_put(ring);
@@ -2936,9 +2940,9 @@ i915_gem_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *file)
         req = obj->last_read_req;
 
         /* Do this after OLR check to make sure we make forward progress polling
-         * on this IOCTL with a timeout <=0 (like busy ioctl)
+         * on this IOCTL with a timeout == 0 (like busy ioctl)
          */
-        if (args->timeout_ns <= 0) {
+        if (args->timeout_ns == 0) {
                 ret = -ETIME;
                 goto out;
         }
@@ -2948,7 +2952,8 @@ i915_gem_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *file)
         i915_gem_request_reference(req);
         mutex_unlock(&dev->struct_mutex);
 
-        ret = __i915_wait_request(req, reset_counter, true, &args->timeout_ns,
+        ret = __i915_wait_request(req, reset_counter, true,
+                                  args->timeout_ns > 0 ? &args->timeout_ns : NULL,
                                   file->driver_priv);
         mutex_lock(&dev->struct_mutex);
         i915_gem_request_unreference(req);
@@ -4792,6 +4797,9 @@ i915_gem_init_hw(struct drm_device *dev)
         if (INTEL_INFO(dev)->gen < 6 && !intel_enable_gtt())
                 return -EIO;
 
+        /* Double layer security blanket, see i915_gem_init() */
+        intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
+
         if (dev_priv->ellc_size)
                 I915_WRITE(HSW_IDICR, I915_READ(HSW_IDICR) | IDIHASHMSK(0xf));
 
@@ -4824,7 +4832,7 @@ i915_gem_init_hw(struct drm_device *dev)
         for_each_ring(ring, dev_priv, i) {
                 ret = ring->init_hw(ring);
                 if (ret)
-                        return ret;
+                        goto out;
         }
 
         for (i = 0; i < NUM_L3_SLICES(dev); i++)
@@ -4841,9 +4849,11 @@ i915_gem_init_hw(struct drm_device *dev)
                 DRM_ERROR("Context enable failed %d\n", ret);
                 i915_gem_cleanup_ringbuffer(dev);
 
-                return ret;
+                goto out;
         }
 
+out:
+        intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
         return ret;
 }
 
@@ -4877,6 +4887,14 @@ int i915_gem_init(struct drm_device *dev)
                 dev_priv->gt.stop_ring = intel_logical_ring_stop;
         }
 
+        /* This is just a security blanket to placate dragons.
+         * On some systems, we very sporadically observe that the first TLBs
+         * used by the CS may be stale, despite us poking the TLB reset. If
+         * we hold the forcewake during initialisation these problems
+         * just magically go away.
+         */
+        intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
+
         ret = i915_gem_init_userptr(dev);
         if (ret)
                 goto out_unlock;
@@ -4903,6 +4921,7 @@ int i915_gem_init(struct drm_device *dev)
         }
 
 out_unlock:
+        intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
         mutex_unlock(&dev->struct_mutex);
 
         return ret;
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index e730789b53b7..f75173c20f47 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -37,6 +37,7 @@
 #include <drm/i915_drm.h>
 #include "i915_drv.h"
 #include "i915_trace.h"
+#include <drm/drm_atomic.h>
 #include <drm/drm_atomic_helper.h>
 #include <drm/drm_dp_helper.h>
 #include <drm/drm_crtc_helper.h>
@@ -2416,6 +2417,14 @@ out_unref_obj:
         return false;
 }
 
+/* Update plane->state->fb to match plane->fb after driver-internal updates */
+static void
+update_state_fb(struct drm_plane *plane)
+{
+        if (plane->fb != plane->state->fb)
+                drm_atomic_set_fb_for_plane(plane->state, plane->fb);
+}
+
 static void
 intel_find_plane_obj(struct intel_crtc *intel_crtc,
                      struct intel_initial_plane_config *plane_config)
@@ -2429,8 +2438,15 @@ intel_find_plane_obj(struct intel_crtc *intel_crtc,
         if (!intel_crtc->base.primary->fb)
                 return;
 
-        if (intel_alloc_plane_obj(intel_crtc, plane_config))
+        if (intel_alloc_plane_obj(intel_crtc, plane_config)) {
+                struct drm_plane *primary = intel_crtc->base.primary;
+
+                primary->state->crtc = &intel_crtc->base;
+                primary->crtc = &intel_crtc->base;
+                update_state_fb(primary);
+
                 return;
+        }
 
         kfree(intel_crtc->base.primary->fb);
         intel_crtc->base.primary->fb = NULL;
@@ -2453,15 +2469,21 @@ intel_find_plane_obj(struct intel_crtc *intel_crtc,
                         continue;
 
                 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
+                        struct drm_plane *primary = intel_crtc->base.primary;
+
                         if (obj->tiling_mode != I915_TILING_NONE)
                                 dev_priv->preserve_bios_swizzle = true;
 
                         drm_framebuffer_reference(c->primary->fb);
-                        intel_crtc->base.primary->fb = c->primary->fb;
+                        primary->fb = c->primary->fb;
+                        primary->state->crtc = &intel_crtc->base;
+                        primary->crtc = &intel_crtc->base;
                         obj->frontbuffer_bits |= INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
                         break;
                 }
         }
+
+        update_state_fb(intel_crtc->base.primary);
 }
 
 static void i9xx_update_primary_plane(struct drm_crtc *crtc,
@@ -6602,6 +6624,10 @@ i9xx_get_initial_plane_config(struct intel_crtc *crtc,
         struct drm_framebuffer *fb;
         struct intel_framebuffer *intel_fb;
 
+        val = I915_READ(DSPCNTR(plane));
+        if (!(val & DISPLAY_PLANE_ENABLE))
+                return;
+
         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
         if (!intel_fb) {
                 DRM_DEBUG_KMS("failed to alloc fb\n");
@@ -6610,8 +6636,6 @@ i9xx_get_initial_plane_config(struct intel_crtc *crtc,
 
         fb = &intel_fb->base;
 
-        val = I915_READ(DSPCNTR(plane));
-
         if (INTEL_INFO(dev)->gen >= 4)
                 if (val & DISPPLANE_TILED)
                         plane_config->tiling = I915_TILING_X;
@@ -7643,6 +7667,9 @@ skylake_get_initial_plane_config(struct intel_crtc *crtc,
         fb = &intel_fb->base;
 
         val = I915_READ(PLANE_CTL(pipe, 0));
+        if (!(val & PLANE_CTL_ENABLE))
+                goto error;
+
         if (val & PLANE_CTL_TILED_MASK)
                 plane_config->tiling = I915_TILING_X;
 
@@ -7730,6 +7757,10 @@ ironlake_get_initial_plane_config(struct intel_crtc *crtc,
         struct drm_framebuffer *fb;
         struct intel_framebuffer *intel_fb;
 
+        val = I915_READ(DSPCNTR(pipe));
+        if (!(val & DISPLAY_PLANE_ENABLE))
+                return;
+
         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
         if (!intel_fb) {
                 DRM_DEBUG_KMS("failed to alloc fb\n");
@@ -7738,8 +7769,6 @@ ironlake_get_initial_plane_config(struct intel_crtc *crtc,
 
         fb = &intel_fb->base;
 
-        val = I915_READ(DSPCNTR(pipe));
-
         if (INTEL_INFO(dev)->gen >= 4)
                 if (val & DISPPLANE_TILED)
                         plane_config->tiling = I915_TILING_X;
@@ -9716,7 +9745,7 @@ void intel_check_page_flip(struct drm_device *dev, int pipe)
         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 
-        WARN_ON(!in_irq());
+        WARN_ON(!in_interrupt());
 
         if (crtc == NULL)
                 return;
@@ -9816,6 +9845,7 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc,
         drm_gem_object_reference(&obj->base);
 
         crtc->primary->fb = fb;
+        update_state_fb(crtc->primary);
 
         work->pending_flip_obj = obj;
 
@@ -9884,6 +9914,7 @@ cleanup_unpin:
 cleanup_pending:
         atomic_dec(&intel_crtc->unpin_work_count);
         crtc->primary->fb = old_fb;
+        update_state_fb(crtc->primary);
         drm_gem_object_unreference(&work->old_fb_obj->base);
         drm_gem_object_unreference(&obj->base);
         mutex_unlock(&dev->struct_mutex);
@@ -13718,6 +13749,7 @@ void intel_modeset_gem_init(struct drm_device *dev)
                                   to_intel_crtc(c)->pipe);
                         drm_framebuffer_unreference(c->primary->fb);
                         c->primary->fb = NULL;
+                        update_state_fb(c->primary);
                 }
         }
         mutex_unlock(&dev->struct_mutex);
diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
index c47a3baa53d5..4e8fb891d4ea 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -1048,8 +1048,14 @@ static void intel_uncore_fw_domains_init(struct drm_device *dev)
 
                 /* We need to init first for ECOBUS access and then
                  * determine later if we want to reinit, in case of MT access is
-                 * not working
+                 * not working. In this stage we don't know which flavour this
+                 * ivb is, so it is better to reset also the gen6 fw registers
+                 * before the ecobus check.
                  */
+
+                __raw_i915_write32(dev_priv, FORCEWAKE, 0);
+                __raw_posting_read(dev_priv, ECOBUS);
+
                 fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER,
                                FORCEWAKE_MT, FORCEWAKE_MT_ACK);