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-rw-r--r--drivers/gpu/drm/i915/Makefile2
-rw-r--r--drivers/gpu/drm/i915/dvo.h7
-rw-r--r--drivers/gpu/drm/i915/i915_debugfs.c53
-rw-r--r--drivers/gpu/drm/i915/i915_dma.c123
-rw-r--r--drivers/gpu/drm/i915/i915_drv.c66
-rw-r--r--drivers/gpu/drm/i915/i915_drv.h72
-rw-r--r--drivers/gpu/drm/i915/i915_gem.c365
-rw-r--r--drivers/gpu/drm/i915/i915_gem_evict.c271
-rw-r--r--drivers/gpu/drm/i915/i915_irq.c135
-rw-r--r--drivers/gpu/drm/i915/i915_opregion.c10
-rw-r--r--drivers/gpu/drm/i915/i915_reg.h15
-rw-r--r--drivers/gpu/drm/i915/i915_suspend.c97
-rw-r--r--drivers/gpu/drm/i915/intel_crt.c53
-rw-r--r--drivers/gpu/drm/i915/intel_display.c725
-rw-r--r--drivers/gpu/drm/i915/intel_dp.c654
-rw-r--r--drivers/gpu/drm/i915/intel_drv.h39
-rw-r--r--drivers/gpu/drm/i915/intel_dvo.c136
-rw-r--r--drivers/gpu/drm/i915/intel_hdmi.c77
-rw-r--r--drivers/gpu/drm/i915/intel_lvds.c106
-rw-r--r--drivers/gpu/drm/i915/intel_overlay.c101
-rw-r--r--drivers/gpu/drm/i915/intel_panel.c111
-rw-r--r--drivers/gpu/drm/i915/intel_ringbuffer.c111
-rw-r--r--drivers/gpu/drm/i915/intel_ringbuffer.h13
-rw-r--r--drivers/gpu/drm/i915/intel_sdvo.c2148
-rw-r--r--drivers/gpu/drm/i915/intel_sdvo_regs.h50
-rw-r--r--drivers/gpu/drm/i915/intel_tv.c162
26 files changed, 3031 insertions, 2671 deletions
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index da78f2c0d909..5c8e53458edb 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -8,6 +8,7 @@ i915-y := i915_drv.o i915_dma.o i915_irq.o i915_mem.o \
8 i915_suspend.o \ 8 i915_suspend.o \
9 i915_gem.o \ 9 i915_gem.o \
10 i915_gem_debug.o \ 10 i915_gem_debug.o \
11 i915_gem_evict.o \
11 i915_gem_tiling.o \ 12 i915_gem_tiling.o \
12 i915_trace_points.o \ 13 i915_trace_points.o \
13 intel_display.o \ 14 intel_display.o \
@@ -18,6 +19,7 @@ i915-y := i915_drv.o i915_dma.o i915_irq.o i915_mem.o \
18 intel_hdmi.o \ 19 intel_hdmi.o \
19 intel_sdvo.o \ 20 intel_sdvo.o \
20 intel_modes.o \ 21 intel_modes.o \
22 intel_panel.o \
21 intel_i2c.o \ 23 intel_i2c.o \
22 intel_fb.o \ 24 intel_fb.o \
23 intel_tv.o \ 25 intel_tv.o \
diff --git a/drivers/gpu/drm/i915/dvo.h b/drivers/gpu/drm/i915/dvo.h
index 0d6ff640e1c6..8c2ad014c47f 100644
--- a/drivers/gpu/drm/i915/dvo.h
+++ b/drivers/gpu/drm/i915/dvo.h
@@ -30,20 +30,17 @@
30#include "intel_drv.h" 30#include "intel_drv.h"
31 31
32struct intel_dvo_device { 32struct intel_dvo_device {
33 char *name; 33 const char *name;
34 int type; 34 int type;
35 /* DVOA/B/C output register */ 35 /* DVOA/B/C output register */
36 u32 dvo_reg; 36 u32 dvo_reg;
37 /* GPIO register used for i2c bus to control this device */ 37 /* GPIO register used for i2c bus to control this device */
38 u32 gpio; 38 u32 gpio;
39 int slave_addr; 39 int slave_addr;
40 struct i2c_adapter *i2c_bus;
41 40
42 const struct intel_dvo_dev_ops *dev_ops; 41 const struct intel_dvo_dev_ops *dev_ops;
43 void *dev_priv; 42 void *dev_priv;
44 43 struct i2c_adapter *i2c_bus;
45 struct drm_display_mode *panel_fixed_mode;
46 bool panel_wants_dither;
47}; 44};
48 45
49struct intel_dvo_dev_ops { 46struct intel_dvo_dev_ops {
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 9214119c0154..5e43d7076789 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -31,6 +31,7 @@
31#include <linux/slab.h> 31#include <linux/slab.h>
32#include "drmP.h" 32#include "drmP.h"
33#include "drm.h" 33#include "drm.h"
34#include "intel_drv.h"
34#include "i915_drm.h" 35#include "i915_drm.h"
35#include "i915_drv.h" 36#include "i915_drv.h"
36 37
@@ -121,6 +122,54 @@ static int i915_gem_object_list_info(struct seq_file *m, void *data)
121 return 0; 122 return 0;
122} 123}
123 124
125static int i915_gem_pageflip_info(struct seq_file *m, void *data)
126{
127 struct drm_info_node *node = (struct drm_info_node *) m->private;
128 struct drm_device *dev = node->minor->dev;
129 unsigned long flags;
130 struct intel_crtc *crtc;
131
132 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
133 const char *pipe = crtc->pipe ? "B" : "A";
134 const char *plane = crtc->plane ? "B" : "A";
135 struct intel_unpin_work *work;
136
137 spin_lock_irqsave(&dev->event_lock, flags);
138 work = crtc->unpin_work;
139 if (work == NULL) {
140 seq_printf(m, "No flip due on pipe %s (plane %s)\n",
141 pipe, plane);
142 } else {
143 if (!work->pending) {
144 seq_printf(m, "Flip queued on pipe %s (plane %s)\n",
145 pipe, plane);
146 } else {
147 seq_printf(m, "Flip pending (waiting for vsync) on pipe %s (plane %s)\n",
148 pipe, plane);
149 }
150 if (work->enable_stall_check)
151 seq_printf(m, "Stall check enabled, ");
152 else
153 seq_printf(m, "Stall check waiting for page flip ioctl, ");
154 seq_printf(m, "%d prepares\n", work->pending);
155
156 if (work->old_fb_obj) {
157 struct drm_i915_gem_object *obj_priv = to_intel_bo(work->old_fb_obj);
158 if(obj_priv)
159 seq_printf(m, "Old framebuffer gtt_offset 0x%08x\n", obj_priv->gtt_offset );
160 }
161 if (work->pending_flip_obj) {
162 struct drm_i915_gem_object *obj_priv = to_intel_bo(work->pending_flip_obj);
163 if(obj_priv)
164 seq_printf(m, "New framebuffer gtt_offset 0x%08x\n", obj_priv->gtt_offset );
165 }
166 }
167 spin_unlock_irqrestore(&dev->event_lock, flags);
168 }
169
170 return 0;
171}
172
124static int i915_gem_request_info(struct seq_file *m, void *data) 173static int i915_gem_request_info(struct seq_file *m, void *data)
125{ 174{
126 struct drm_info_node *node = (struct drm_info_node *) m->private; 175 struct drm_info_node *node = (struct drm_info_node *) m->private;
@@ -467,6 +516,9 @@ static int i915_error_state(struct seq_file *m, void *unused)
467 } 516 }
468 } 517 }
469 518
519 if (error->overlay)
520 intel_overlay_print_error_state(m, error->overlay);
521
470out: 522out:
471 spin_unlock_irqrestore(&dev_priv->error_lock, flags); 523 spin_unlock_irqrestore(&dev_priv->error_lock, flags);
472 524
@@ -774,6 +826,7 @@ static struct drm_info_list i915_debugfs_list[] = {
774 {"i915_gem_active", i915_gem_object_list_info, 0, (void *) ACTIVE_LIST}, 826 {"i915_gem_active", i915_gem_object_list_info, 0, (void *) ACTIVE_LIST},
775 {"i915_gem_flushing", i915_gem_object_list_info, 0, (void *) FLUSHING_LIST}, 827 {"i915_gem_flushing", i915_gem_object_list_info, 0, (void *) FLUSHING_LIST},
776 {"i915_gem_inactive", i915_gem_object_list_info, 0, (void *) INACTIVE_LIST}, 828 {"i915_gem_inactive", i915_gem_object_list_info, 0, (void *) INACTIVE_LIST},
829 {"i915_gem_pageflip", i915_gem_pageflip_info, 0},
777 {"i915_gem_request", i915_gem_request_info, 0}, 830 {"i915_gem_request", i915_gem_request_info, 0},
778 {"i915_gem_seqno", i915_gem_seqno_info, 0}, 831 {"i915_gem_seqno", i915_gem_seqno_info, 0},
779 {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0}, 832 {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0},
diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index f19ffe87af3c..9d67b4853030 100644
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@ -499,6 +499,13 @@ static int i915_dispatch_batchbuffer(struct drm_device * dev,
499 } 499 }
500 } 500 }
501 501
502
503 if (IS_G4X(dev) || IS_IRONLAKE(dev)) {
504 BEGIN_LP_RING(2);
505 OUT_RING(MI_FLUSH | MI_NO_WRITE_FLUSH | MI_INVALIDATE_ISP);
506 OUT_RING(MI_NOOP);
507 ADVANCE_LP_RING();
508 }
502 i915_emit_breadcrumb(dev); 509 i915_emit_breadcrumb(dev);
503 510
504 return 0; 511 return 0;
@@ -613,8 +620,10 @@ static int i915_batchbuffer(struct drm_device *dev, void *data,
613 ret = copy_from_user(cliprects, batch->cliprects, 620 ret = copy_from_user(cliprects, batch->cliprects,
614 batch->num_cliprects * 621 batch->num_cliprects *
615 sizeof(struct drm_clip_rect)); 622 sizeof(struct drm_clip_rect));
616 if (ret != 0) 623 if (ret != 0) {
624 ret = -EFAULT;
617 goto fail_free; 625 goto fail_free;
626 }
618 } 627 }
619 628
620 mutex_lock(&dev->struct_mutex); 629 mutex_lock(&dev->struct_mutex);
@@ -655,8 +664,10 @@ static int i915_cmdbuffer(struct drm_device *dev, void *data,
655 return -ENOMEM; 664 return -ENOMEM;
656 665
657 ret = copy_from_user(batch_data, cmdbuf->buf, cmdbuf->sz); 666 ret = copy_from_user(batch_data, cmdbuf->buf, cmdbuf->sz);
658 if (ret != 0) 667 if (ret != 0) {
668 ret = -EFAULT;
659 goto fail_batch_free; 669 goto fail_batch_free;
670 }
660 671
661 if (cmdbuf->num_cliprects) { 672 if (cmdbuf->num_cliprects) {
662 cliprects = kcalloc(cmdbuf->num_cliprects, 673 cliprects = kcalloc(cmdbuf->num_cliprects,
@@ -669,8 +680,10 @@ static int i915_cmdbuffer(struct drm_device *dev, void *data,
669 ret = copy_from_user(cliprects, cmdbuf->cliprects, 680 ret = copy_from_user(cliprects, cmdbuf->cliprects,
670 cmdbuf->num_cliprects * 681 cmdbuf->num_cliprects *
671 sizeof(struct drm_clip_rect)); 682 sizeof(struct drm_clip_rect));
672 if (ret != 0) 683 if (ret != 0) {
684 ret = -EFAULT;
673 goto fail_clip_free; 685 goto fail_clip_free;
686 }
674 } 687 }
675 688
676 mutex_lock(&dev->struct_mutex); 689 mutex_lock(&dev->struct_mutex);
@@ -878,7 +891,7 @@ intel_alloc_mchbar_resource(struct drm_device *dev)
878 int reg = IS_I965G(dev) ? MCHBAR_I965 : MCHBAR_I915; 891 int reg = IS_I965G(dev) ? MCHBAR_I965 : MCHBAR_I915;
879 u32 temp_lo, temp_hi = 0; 892 u32 temp_lo, temp_hi = 0;
880 u64 mchbar_addr; 893 u64 mchbar_addr;
881 int ret = 0; 894 int ret;
882 895
883 if (IS_I965G(dev)) 896 if (IS_I965G(dev))
884 pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi); 897 pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi);
@@ -888,22 +901,23 @@ intel_alloc_mchbar_resource(struct drm_device *dev)
888 /* If ACPI doesn't have it, assume we need to allocate it ourselves */ 901 /* If ACPI doesn't have it, assume we need to allocate it ourselves */
889#ifdef CONFIG_PNP 902#ifdef CONFIG_PNP
890 if (mchbar_addr && 903 if (mchbar_addr &&
891 pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE)) { 904 pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE))
892 ret = 0; 905 return 0;
893 goto out;
894 }
895#endif 906#endif
896 907
897 /* Get some space for it */ 908 /* Get some space for it */
898 ret = pci_bus_alloc_resource(dev_priv->bridge_dev->bus, &dev_priv->mch_res, 909 dev_priv->mch_res.name = "i915 MCHBAR";
910 dev_priv->mch_res.flags = IORESOURCE_MEM;
911 ret = pci_bus_alloc_resource(dev_priv->bridge_dev->bus,
912 &dev_priv->mch_res,
899 MCHBAR_SIZE, MCHBAR_SIZE, 913 MCHBAR_SIZE, MCHBAR_SIZE,
900 PCIBIOS_MIN_MEM, 914 PCIBIOS_MIN_MEM,
901 0, pcibios_align_resource, 915 0, pcibios_align_resource,
902 dev_priv->bridge_dev); 916 dev_priv->bridge_dev);
903 if (ret) { 917 if (ret) {
904 DRM_DEBUG_DRIVER("failed bus alloc: %d\n", ret); 918 DRM_DEBUG_DRIVER("failed bus alloc: %d\n", ret);
905 dev_priv->mch_res.start = 0; 919 dev_priv->mch_res.start = 0;
906 goto out; 920 return ret;
907 } 921 }
908 922
909 if (IS_I965G(dev)) 923 if (IS_I965G(dev))
@@ -912,8 +926,7 @@ intel_alloc_mchbar_resource(struct drm_device *dev)
912 926
913 pci_write_config_dword(dev_priv->bridge_dev, reg, 927 pci_write_config_dword(dev_priv->bridge_dev, reg,
914 lower_32_bits(dev_priv->mch_res.start)); 928 lower_32_bits(dev_priv->mch_res.start));
915out: 929 return 0;
916 return ret;
917} 930}
918 931
919/* Setup MCHBAR if possible, return true if we should disable it again */ 932/* Setup MCHBAR if possible, return true if we should disable it again */
@@ -2075,6 +2088,10 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
2075 goto free_priv; 2088 goto free_priv;
2076 } 2089 }
2077 2090
2091 /* overlay on gen2 is broken and can't address above 1G */
2092 if (IS_GEN2(dev))
2093 dma_set_coherent_mask(&dev->pdev->dev, DMA_BIT_MASK(30));
2094
2078 dev_priv->regs = ioremap(base, size); 2095 dev_priv->regs = ioremap(base, size);
2079 if (!dev_priv->regs) { 2096 if (!dev_priv->regs) {
2080 DRM_ERROR("failed to map registers\n"); 2097 DRM_ERROR("failed to map registers\n");
@@ -2360,46 +2377,46 @@ void i915_driver_postclose(struct drm_device *dev, struct drm_file *file_priv)
2360} 2377}
2361 2378
2362struct drm_ioctl_desc i915_ioctls[] = { 2379struct drm_ioctl_desc i915_ioctls[] = {
2363 DRM_IOCTL_DEF(DRM_I915_INIT, i915_dma_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 2380 DRM_IOCTL_DEF_DRV(I915_INIT, i915_dma_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2364 DRM_IOCTL_DEF(DRM_I915_FLUSH, i915_flush_ioctl, DRM_AUTH), 2381 DRM_IOCTL_DEF_DRV(I915_FLUSH, i915_flush_ioctl, DRM_AUTH),
2365 DRM_IOCTL_DEF(DRM_I915_FLIP, i915_flip_bufs, DRM_AUTH), 2382 DRM_IOCTL_DEF_DRV(I915_FLIP, i915_flip_bufs, DRM_AUTH),
2366 DRM_IOCTL_DEF(DRM_I915_BATCHBUFFER, i915_batchbuffer, DRM_AUTH), 2383 DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER, i915_batchbuffer, DRM_AUTH),
2367 DRM_IOCTL_DEF(DRM_I915_IRQ_EMIT, i915_irq_emit, DRM_AUTH), 2384 DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT, i915_irq_emit, DRM_AUTH),
2368 DRM_IOCTL_DEF(DRM_I915_IRQ_WAIT, i915_irq_wait, DRM_AUTH), 2385 DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT, i915_irq_wait, DRM_AUTH),
2369 DRM_IOCTL_DEF(DRM_I915_GETPARAM, i915_getparam, DRM_AUTH), 2386 DRM_IOCTL_DEF_DRV(I915_GETPARAM, i915_getparam, DRM_AUTH),
2370 DRM_IOCTL_DEF(DRM_I915_SETPARAM, i915_setparam, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 2387 DRM_IOCTL_DEF_DRV(I915_SETPARAM, i915_setparam, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2371 DRM_IOCTL_DEF(DRM_I915_ALLOC, i915_mem_alloc, DRM_AUTH), 2388 DRM_IOCTL_DEF_DRV(I915_ALLOC, i915_mem_alloc, DRM_AUTH),
2372 DRM_IOCTL_DEF(DRM_I915_FREE, i915_mem_free, DRM_AUTH), 2389 DRM_IOCTL_DEF_DRV(I915_FREE, i915_mem_free, DRM_AUTH),
2373 DRM_IOCTL_DEF(DRM_I915_INIT_HEAP, i915_mem_init_heap, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 2390 DRM_IOCTL_DEF_DRV(I915_INIT_HEAP, i915_mem_init_heap, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2374 DRM_IOCTL_DEF(DRM_I915_CMDBUFFER, i915_cmdbuffer, DRM_AUTH), 2391 DRM_IOCTL_DEF_DRV(I915_CMDBUFFER, i915_cmdbuffer, DRM_AUTH),
2375 DRM_IOCTL_DEF(DRM_I915_DESTROY_HEAP, i915_mem_destroy_heap, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY ), 2392 DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP, i915_mem_destroy_heap, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2376 DRM_IOCTL_DEF(DRM_I915_SET_VBLANK_PIPE, i915_vblank_pipe_set, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY ), 2393 DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE, i915_vblank_pipe_set, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2377 DRM_IOCTL_DEF(DRM_I915_GET_VBLANK_PIPE, i915_vblank_pipe_get, DRM_AUTH ), 2394 DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE, i915_vblank_pipe_get, DRM_AUTH),
2378 DRM_IOCTL_DEF(DRM_I915_VBLANK_SWAP, i915_vblank_swap, DRM_AUTH), 2395 DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP, i915_vblank_swap, DRM_AUTH),
2379 DRM_IOCTL_DEF(DRM_I915_HWS_ADDR, i915_set_status_page, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 2396 DRM_IOCTL_DEF_DRV(I915_HWS_ADDR, i915_set_status_page, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2380 DRM_IOCTL_DEF(DRM_I915_GEM_INIT, i915_gem_init_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED), 2397 DRM_IOCTL_DEF_DRV(I915_GEM_INIT, i915_gem_init_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
2381 DRM_IOCTL_DEF(DRM_I915_GEM_EXECBUFFER, i915_gem_execbuffer, DRM_AUTH|DRM_UNLOCKED), 2398 DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER, i915_gem_execbuffer, DRM_AUTH|DRM_UNLOCKED),
2382 DRM_IOCTL_DEF(DRM_I915_GEM_EXECBUFFER2, i915_gem_execbuffer2, DRM_AUTH|DRM_UNLOCKED), 2399 DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2, i915_gem_execbuffer2, DRM_AUTH|DRM_UNLOCKED),
2383 DRM_IOCTL_DEF(DRM_I915_GEM_PIN, i915_gem_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY|DRM_UNLOCKED), 2400 DRM_IOCTL_DEF_DRV(I915_GEM_PIN, i915_gem_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY|DRM_UNLOCKED),
2384 DRM_IOCTL_DEF(DRM_I915_GEM_UNPIN, i915_gem_unpin_ioctl, DRM_AUTH|DRM_ROOT_ONLY|DRM_UNLOCKED), 2401 DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN, i915_gem_unpin_ioctl, DRM_AUTH|DRM_ROOT_ONLY|DRM_UNLOCKED),
2385 DRM_IOCTL_DEF(DRM_I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_AUTH|DRM_UNLOCKED), 2402 DRM_IOCTL_DEF_DRV(I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_AUTH|DRM_UNLOCKED),
2386 DRM_IOCTL_DEF(DRM_I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_AUTH|DRM_UNLOCKED), 2403 DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_AUTH|DRM_UNLOCKED),
2387 DRM_IOCTL_DEF(DRM_I915_GEM_ENTERVT, i915_gem_entervt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED), 2404 DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, i915_gem_entervt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
2388 DRM_IOCTL_DEF(DRM_I915_GEM_LEAVEVT, i915_gem_leavevt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED), 2405 DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, i915_gem_leavevt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
2389 DRM_IOCTL_DEF(DRM_I915_GEM_CREATE, i915_gem_create_ioctl, DRM_UNLOCKED), 2406 DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_UNLOCKED),
2390 DRM_IOCTL_DEF(DRM_I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_UNLOCKED), 2407 DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_UNLOCKED),
2391 DRM_IOCTL_DEF(DRM_I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_UNLOCKED), 2408 DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_UNLOCKED),
2392 DRM_IOCTL_DEF(DRM_I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_UNLOCKED), 2409 DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_UNLOCKED),
2393 DRM_IOCTL_DEF(DRM_I915_GEM_MMAP_GTT, i915_gem_mmap_gtt_ioctl, DRM_UNLOCKED), 2410 DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_GTT, i915_gem_mmap_gtt_ioctl, DRM_UNLOCKED),
2394 DRM_IOCTL_DEF(DRM_I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_UNLOCKED), 2411 DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_UNLOCKED),
2395 DRM_IOCTL_DEF(DRM_I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_UNLOCKED), 2412 DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_UNLOCKED),
2396 DRM_IOCTL_DEF(DRM_I915_GEM_SET_TILING, i915_gem_set_tiling, DRM_UNLOCKED), 2413 DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING, i915_gem_set_tiling, DRM_UNLOCKED),
2397 DRM_IOCTL_DEF(DRM_I915_GEM_GET_TILING, i915_gem_get_tiling, DRM_UNLOCKED), 2414 DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING, i915_gem_get_tiling, DRM_UNLOCKED),
2398 DRM_IOCTL_DEF(DRM_I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_UNLOCKED), 2415 DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_UNLOCKED),
2399 DRM_IOCTL_DEF(DRM_I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id, DRM_UNLOCKED), 2416 DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id, DRM_UNLOCKED),
2400 DRM_IOCTL_DEF(DRM_I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_UNLOCKED), 2417 DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_UNLOCKED),
2401 DRM_IOCTL_DEF(DRM_I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED), 2418 DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
2402 DRM_IOCTL_DEF(DRM_I915_OVERLAY_ATTRS, intel_overlay_attrs, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED), 2419 DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS, intel_overlay_attrs, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
2403}; 2420};
2404 2421
2405int i915_max_ioctl = DRM_ARRAY_SIZE(i915_ioctls); 2422int i915_max_ioctl = DRM_ARRAY_SIZE(i915_ioctls);
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 5044f653e8ea..216deb579785 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -61,91 +61,86 @@ extern int intel_agp_enabled;
61 .driver_data = (unsigned long) info } 61 .driver_data = (unsigned long) info }
62 62
63static const struct intel_device_info intel_i830_info = { 63static const struct intel_device_info intel_i830_info = {
64 .is_i8xx = 1, .is_mobile = 1, .cursor_needs_physical = 1, 64 .gen = 2, .is_i8xx = 1, .is_mobile = 1, .cursor_needs_physical = 1,
65}; 65};
66 66
67static const struct intel_device_info intel_845g_info = { 67static const struct intel_device_info intel_845g_info = {
68 .is_i8xx = 1, 68 .gen = 2, .is_i8xx = 1,
69}; 69};
70 70
71static const struct intel_device_info intel_i85x_info = { 71static const struct intel_device_info intel_i85x_info = {
72 .is_i8xx = 1, .is_i85x = 1, .is_mobile = 1, 72 .gen = 2, .is_i8xx = 1, .is_i85x = 1, .is_mobile = 1,
73 .cursor_needs_physical = 1, 73 .cursor_needs_physical = 1,
74}; 74};
75 75
76static const struct intel_device_info intel_i865g_info = { 76static const struct intel_device_info intel_i865g_info = {
77 .is_i8xx = 1, 77 .gen = 2, .is_i8xx = 1,
78}; 78};
79 79
80static const struct intel_device_info intel_i915g_info = { 80static const struct intel_device_info intel_i915g_info = {
81 .is_i915g = 1, .is_i9xx = 1, .cursor_needs_physical = 1, 81 .gen = 3, .is_i915g = 1, .is_i9xx = 1, .cursor_needs_physical = 1,
82}; 82};
83static const struct intel_device_info intel_i915gm_info = { 83static const struct intel_device_info intel_i915gm_info = {
84 .is_i9xx = 1, .is_mobile = 1, 84 .gen = 3, .is_i9xx = 1, .is_mobile = 1,
85 .cursor_needs_physical = 1, 85 .cursor_needs_physical = 1,
86}; 86};
87static const struct intel_device_info intel_i945g_info = { 87static const struct intel_device_info intel_i945g_info = {
88 .is_i9xx = 1, .has_hotplug = 1, .cursor_needs_physical = 1, 88 .gen = 3, .is_i9xx = 1, .has_hotplug = 1, .cursor_needs_physical = 1,
89}; 89};
90static const struct intel_device_info intel_i945gm_info = { 90static const struct intel_device_info intel_i945gm_info = {
91 .is_i945gm = 1, .is_i9xx = 1, .is_mobile = 1, 91 .gen = 3, .is_i945gm = 1, .is_i9xx = 1, .is_mobile = 1,
92 .has_hotplug = 1, .cursor_needs_physical = 1, 92 .has_hotplug = 1, .cursor_needs_physical = 1,
93}; 93};
94 94
95static const struct intel_device_info intel_i965g_info = { 95static const struct intel_device_info intel_i965g_info = {
96 .is_broadwater = 1, .is_i965g = 1, .is_i9xx = 1, .has_hotplug = 1, 96 .gen = 4, .is_broadwater = 1, .is_i965g = 1, .is_i9xx = 1,
97 .has_hotplug = 1,
97}; 98};
98 99
99static const struct intel_device_info intel_i965gm_info = { 100static const struct intel_device_info intel_i965gm_info = {
100 .is_crestline = 1, .is_i965g = 1, .is_i965gm = 1, .is_i9xx = 1, 101 .gen = 4, .is_crestline = 1, .is_i965g = 1, .is_i965gm = 1, .is_i9xx = 1,
101 .is_mobile = 1, .has_fbc = 1, .has_rc6 = 1, 102 .is_mobile = 1, .has_fbc = 1, .has_rc6 = 1, .has_hotplug = 1,
102 .has_hotplug = 1,
103}; 103};
104 104
105static const struct intel_device_info intel_g33_info = { 105static const struct intel_device_info intel_g33_info = {
106 .is_g33 = 1, .is_i9xx = 1, .need_gfx_hws = 1, 106 .gen = 3, .is_g33 = 1, .is_i9xx = 1,
107 .has_hotplug = 1, 107 .need_gfx_hws = 1, .has_hotplug = 1,
108}; 108};
109 109
110static const struct intel_device_info intel_g45_info = { 110static const struct intel_device_info intel_g45_info = {
111 .is_i965g = 1, .is_g4x = 1, .is_i9xx = 1, .need_gfx_hws = 1, 111 .gen = 4, .is_i965g = 1, .is_g4x = 1, .is_i9xx = 1, .need_gfx_hws = 1,
112 .has_pipe_cxsr = 1, 112 .has_pipe_cxsr = 1, .has_hotplug = 1,
113 .has_hotplug = 1,
114}; 113};
115 114
116static const struct intel_device_info intel_gm45_info = { 115static const struct intel_device_info intel_gm45_info = {
117 .is_i965g = 1, .is_g4x = 1, .is_i9xx = 1, 116 .gen = 4, .is_i965g = 1, .is_g4x = 1, .is_i9xx = 1,
118 .is_mobile = 1, .need_gfx_hws = 1, .has_fbc = 1, .has_rc6 = 1, 117 .is_mobile = 1, .need_gfx_hws = 1, .has_fbc = 1, .has_rc6 = 1,
119 .has_pipe_cxsr = 1, 118 .has_pipe_cxsr = 1, .has_hotplug = 1,
120 .has_hotplug = 1,
121}; 119};
122 120
123static const struct intel_device_info intel_pineview_info = { 121static const struct intel_device_info intel_pineview_info = {
124 .is_g33 = 1, .is_pineview = 1, .is_mobile = 1, .is_i9xx = 1, 122 .gen = 3, .is_g33 = 1, .is_pineview = 1, .is_mobile = 1, .is_i9xx = 1,
125 .need_gfx_hws = 1, 123 .need_gfx_hws = 1, .has_hotplug = 1,
126 .has_hotplug = 1,
127}; 124};
128 125
129static const struct intel_device_info intel_ironlake_d_info = { 126static const struct intel_device_info intel_ironlake_d_info = {
130 .is_ironlake = 1, .is_i965g = 1, .is_i9xx = 1, .need_gfx_hws = 1, 127 .gen = 5, .is_ironlake = 1, .is_i965g = 1, .is_i9xx = 1,
131 .has_pipe_cxsr = 1, 128 .need_gfx_hws = 1, .has_pipe_cxsr = 1, .has_hotplug = 1,
132 .has_hotplug = 1,
133}; 129};
134 130
135static const struct intel_device_info intel_ironlake_m_info = { 131static const struct intel_device_info intel_ironlake_m_info = {
136 .is_ironlake = 1, .is_mobile = 1, .is_i965g = 1, .is_i9xx = 1, 132 .gen = 5, .is_ironlake = 1, .is_mobile = 1, .is_i965g = 1, .is_i9xx = 1,
137 .need_gfx_hws = 1, .has_fbc = 1, .has_rc6 = 1, 133 .need_gfx_hws = 1, .has_fbc = 1, .has_rc6 = 1, .has_hotplug = 1,
138 .has_hotplug = 1,
139}; 134};
140 135
141static const struct intel_device_info intel_sandybridge_d_info = { 136static const struct intel_device_info intel_sandybridge_d_info = {
142 .is_i965g = 1, .is_i9xx = 1, .need_gfx_hws = 1, 137 .gen = 6, .is_i965g = 1, .is_i9xx = 1,
143 .has_hotplug = 1, .is_gen6 = 1, 138 .need_gfx_hws = 1, .has_hotplug = 1,
144}; 139};
145 140
146static const struct intel_device_info intel_sandybridge_m_info = { 141static const struct intel_device_info intel_sandybridge_m_info = {
147 .is_i965g = 1, .is_mobile = 1, .is_i9xx = 1, .need_gfx_hws = 1, 142 .gen = 6, .is_i965g = 1, .is_mobile = 1, .is_i9xx = 1,
148 .has_hotplug = 1, .is_gen6 = 1, 143 .need_gfx_hws = 1, .has_hotplug = 1,
149}; 144};
150 145
151static const struct pci_device_id pciidlist[] = { /* aka */ 146static const struct pci_device_id pciidlist[] = { /* aka */
@@ -180,7 +175,12 @@ static const struct pci_device_id pciidlist[] = { /* aka */
180 INTEL_VGA_DEVICE(0x0042, &intel_ironlake_d_info), 175 INTEL_VGA_DEVICE(0x0042, &intel_ironlake_d_info),
181 INTEL_VGA_DEVICE(0x0046, &intel_ironlake_m_info), 176 INTEL_VGA_DEVICE(0x0046, &intel_ironlake_m_info),
182 INTEL_VGA_DEVICE(0x0102, &intel_sandybridge_d_info), 177 INTEL_VGA_DEVICE(0x0102, &intel_sandybridge_d_info),
178 INTEL_VGA_DEVICE(0x0112, &intel_sandybridge_d_info),
179 INTEL_VGA_DEVICE(0x0122, &intel_sandybridge_d_info),
183 INTEL_VGA_DEVICE(0x0106, &intel_sandybridge_m_info), 180 INTEL_VGA_DEVICE(0x0106, &intel_sandybridge_m_info),
181 INTEL_VGA_DEVICE(0x0116, &intel_sandybridge_m_info),
182 INTEL_VGA_DEVICE(0x0126, &intel_sandybridge_m_info),
183 INTEL_VGA_DEVICE(0x010A, &intel_sandybridge_d_info),
184 {0, 0, 0} 184 {0, 0, 0}
185}; 185};
186 186
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 906663b9929e..af4a263cf257 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -113,6 +113,9 @@ struct intel_opregion {
113 int enabled; 113 int enabled;
114}; 114};
115 115
116struct intel_overlay;
117struct intel_overlay_error_state;
118
116struct drm_i915_master_private { 119struct drm_i915_master_private {
117 drm_local_map_t *sarea; 120 drm_local_map_t *sarea;
118 struct _drm_i915_sarea *sarea_priv; 121 struct _drm_i915_sarea *sarea_priv;
@@ -166,6 +169,7 @@ struct drm_i915_error_state {
166 u32 purgeable:1; 169 u32 purgeable:1;
167 } *active_bo; 170 } *active_bo;
168 u32 active_bo_count; 171 u32 active_bo_count;
172 struct intel_overlay_error_state *overlay;
169}; 173};
170 174
171struct drm_i915_display_funcs { 175struct drm_i915_display_funcs {
@@ -186,9 +190,8 @@ struct drm_i915_display_funcs {
186 /* clock gating init */ 190 /* clock gating init */
187}; 191};
188 192
189struct intel_overlay;
190
191struct intel_device_info { 193struct intel_device_info {
194 u8 gen;
192 u8 is_mobile : 1; 195 u8 is_mobile : 1;
193 u8 is_i8xx : 1; 196 u8 is_i8xx : 1;
194 u8 is_i85x : 1; 197 u8 is_i85x : 1;
@@ -204,7 +207,6 @@ struct intel_device_info {
204 u8 is_broadwater : 1; 207 u8 is_broadwater : 1;
205 u8 is_crestline : 1; 208 u8 is_crestline : 1;
206 u8 is_ironlake : 1; 209 u8 is_ironlake : 1;
207 u8 is_gen6 : 1;
208 u8 has_fbc : 1; 210 u8 has_fbc : 1;
209 u8 has_rc6 : 1; 211 u8 has_rc6 : 1;
210 u8 has_pipe_cxsr : 1; 212 u8 has_pipe_cxsr : 1;
@@ -242,6 +244,7 @@ typedef struct drm_i915_private {
242 struct pci_dev *bridge_dev; 244 struct pci_dev *bridge_dev;
243 struct intel_ring_buffer render_ring; 245 struct intel_ring_buffer render_ring;
244 struct intel_ring_buffer bsd_ring; 246 struct intel_ring_buffer bsd_ring;
247 uint32_t next_seqno;
245 248
246 drm_dma_handle_t *status_page_dmah; 249 drm_dma_handle_t *status_page_dmah;
247 void *seqno_page; 250 void *seqno_page;
@@ -251,6 +254,7 @@ typedef struct drm_i915_private {
251 drm_local_map_t hws_map; 254 drm_local_map_t hws_map;
252 struct drm_gem_object *seqno_obj; 255 struct drm_gem_object *seqno_obj;
253 struct drm_gem_object *pwrctx; 256 struct drm_gem_object *pwrctx;
257 struct drm_gem_object *renderctx;
254 258
255 struct resource mch_res; 259 struct resource mch_res;
256 260
@@ -285,6 +289,9 @@ typedef struct drm_i915_private {
285 unsigned int sr01, adpa, ppcr, dvob, dvoc, lvds; 289 unsigned int sr01, adpa, ppcr, dvob, dvoc, lvds;
286 int vblank_pipe; 290 int vblank_pipe;
287 int num_pipe; 291 int num_pipe;
292 u32 flush_rings;
293#define FLUSH_RENDER_RING 0x1
294#define FLUSH_BSD_RING 0x2
288 295
289 /* For hangcheck timer */ 296 /* For hangcheck timer */
290#define DRM_I915_HANGCHECK_PERIOD 75 /* in jiffies */ 297#define DRM_I915_HANGCHECK_PERIOD 75 /* in jiffies */
@@ -568,8 +575,6 @@ typedef struct drm_i915_private {
568 */ 575 */
569 struct delayed_work retire_work; 576 struct delayed_work retire_work;
570 577
571 uint32_t next_gem_seqno;
572
573 /** 578 /**
574 * Waiting sequence number, if any 579 * Waiting sequence number, if any
575 */ 580 */
@@ -610,6 +615,8 @@ typedef struct drm_i915_private {
610 struct sdvo_device_mapping sdvo_mappings[2]; 615 struct sdvo_device_mapping sdvo_mappings[2];
611 /* indicate whether the LVDS_BORDER should be enabled or not */ 616 /* indicate whether the LVDS_BORDER should be enabled or not */
612 unsigned int lvds_border_bits; 617 unsigned int lvds_border_bits;
618 /* Panel fitter placement and size for Ironlake+ */
619 u32 pch_pf_pos, pch_pf_size;
613 620
614 struct drm_crtc *plane_to_crtc_mapping[2]; 621 struct drm_crtc *plane_to_crtc_mapping[2];
615 struct drm_crtc *pipe_to_crtc_mapping[2]; 622 struct drm_crtc *pipe_to_crtc_mapping[2];
@@ -669,6 +676,8 @@ struct drm_i915_gem_object {
669 struct list_head list; 676 struct list_head list;
670 /** This object's place on GPU write list */ 677 /** This object's place on GPU write list */
671 struct list_head gpu_write_list; 678 struct list_head gpu_write_list;
679 /** This object's place on eviction list */
680 struct list_head evict_list;
672 681
673 /** 682 /**
674 * This is set if the object is on the active or flushing lists 683 * This is set if the object is on the active or flushing lists
@@ -978,6 +987,7 @@ int i915_gem_init_ringbuffer(struct drm_device *dev);
978void i915_gem_cleanup_ringbuffer(struct drm_device *dev); 987void i915_gem_cleanup_ringbuffer(struct drm_device *dev);
979int i915_gem_do_init(struct drm_device *dev, unsigned long start, 988int i915_gem_do_init(struct drm_device *dev, unsigned long start,
980 unsigned long end); 989 unsigned long end);
990int i915_gpu_idle(struct drm_device *dev);
981int i915_gem_idle(struct drm_device *dev); 991int i915_gem_idle(struct drm_device *dev);
982uint32_t i915_add_request(struct drm_device *dev, 992uint32_t i915_add_request(struct drm_device *dev,
983 struct drm_file *file_priv, 993 struct drm_file *file_priv,
@@ -991,7 +1001,9 @@ int i915_gem_object_set_to_gtt_domain(struct drm_gem_object *obj,
991 int write); 1001 int write);
992int i915_gem_object_set_to_display_plane(struct drm_gem_object *obj); 1002int i915_gem_object_set_to_display_plane(struct drm_gem_object *obj);
993int i915_gem_attach_phys_object(struct drm_device *dev, 1003int i915_gem_attach_phys_object(struct drm_device *dev,
994 struct drm_gem_object *obj, int id); 1004 struct drm_gem_object *obj,
1005 int id,
1006 int align);
995void i915_gem_detach_phys_object(struct drm_device *dev, 1007void i915_gem_detach_phys_object(struct drm_device *dev,
996 struct drm_gem_object *obj); 1008 struct drm_gem_object *obj);
997void i915_gem_free_all_phys_object(struct drm_device *dev); 1009void i915_gem_free_all_phys_object(struct drm_device *dev);
@@ -1003,6 +1015,11 @@ int i915_gem_object_flush_write_domain(struct drm_gem_object *obj);
1003void i915_gem_shrinker_init(void); 1015void i915_gem_shrinker_init(void);
1004void i915_gem_shrinker_exit(void); 1016void i915_gem_shrinker_exit(void);
1005 1017
1018/* i915_gem_evict.c */
1019int i915_gem_evict_something(struct drm_device *dev, int min_size, unsigned alignment);
1020int i915_gem_evict_everything(struct drm_device *dev);
1021int i915_gem_evict_inactive(struct drm_device *dev);
1022
1006/* i915_gem_tiling.c */ 1023/* i915_gem_tiling.c */
1007void i915_gem_detect_bit_6_swizzle(struct drm_device *dev); 1024void i915_gem_detect_bit_6_swizzle(struct drm_device *dev);
1008void i915_gem_object_do_bit_17_swizzle(struct drm_gem_object *obj); 1025void i915_gem_object_do_bit_17_swizzle(struct drm_gem_object *obj);
@@ -1066,6 +1083,10 @@ extern bool ironlake_set_drps(struct drm_device *dev, u8 val);
1066extern void intel_detect_pch (struct drm_device *dev); 1083extern void intel_detect_pch (struct drm_device *dev);
1067extern int intel_trans_dp_port_sel (struct drm_crtc *crtc); 1084extern int intel_trans_dp_port_sel (struct drm_crtc *crtc);
1068 1085
1086/* overlay */
1087extern struct intel_overlay_error_state *intel_overlay_capture_error_state(struct drm_device *dev);
1088extern void intel_overlay_print_error_state(struct seq_file *m, struct intel_overlay_error_state *error);
1089
1069/** 1090/**
1070 * Lock test for when it's just for synchronization of ring access. 1091 * Lock test for when it's just for synchronization of ring access.
1071 * 1092 *
@@ -1092,26 +1113,26 @@ extern int intel_trans_dp_port_sel (struct drm_crtc *crtc);
1092#define I915_VERBOSE 0 1113#define I915_VERBOSE 0
1093 1114
1094#define BEGIN_LP_RING(n) do { \ 1115#define BEGIN_LP_RING(n) do { \
1095 drm_i915_private_t *dev_priv = dev->dev_private; \ 1116 drm_i915_private_t *dev_priv__ = dev->dev_private; \
1096 if (I915_VERBOSE) \ 1117 if (I915_VERBOSE) \
1097 DRM_DEBUG(" BEGIN_LP_RING %x\n", (int)(n)); \ 1118 DRM_DEBUG(" BEGIN_LP_RING %x\n", (int)(n)); \
1098 intel_ring_begin(dev, &dev_priv->render_ring, (n)); \ 1119 intel_ring_begin(dev, &dev_priv__->render_ring, (n)); \
1099} while (0) 1120} while (0)
1100 1121
1101 1122
1102#define OUT_RING(x) do { \ 1123#define OUT_RING(x) do { \
1103 drm_i915_private_t *dev_priv = dev->dev_private; \ 1124 drm_i915_private_t *dev_priv__ = dev->dev_private; \
1104 if (I915_VERBOSE) \ 1125 if (I915_VERBOSE) \
1105 DRM_DEBUG(" OUT_RING %x\n", (int)(x)); \ 1126 DRM_DEBUG(" OUT_RING %x\n", (int)(x)); \
1106 intel_ring_emit(dev, &dev_priv->render_ring, x); \ 1127 intel_ring_emit(dev, &dev_priv__->render_ring, x); \
1107} while (0) 1128} while (0)
1108 1129
1109#define ADVANCE_LP_RING() do { \ 1130#define ADVANCE_LP_RING() do { \
1110 drm_i915_private_t *dev_priv = dev->dev_private; \ 1131 drm_i915_private_t *dev_priv__ = dev->dev_private; \
1111 if (I915_VERBOSE) \ 1132 if (I915_VERBOSE) \
1112 DRM_DEBUG("ADVANCE_LP_RING %x\n", \ 1133 DRM_DEBUG("ADVANCE_LP_RING %x\n", \
1113 dev_priv->render_ring.tail); \ 1134 dev_priv__->render_ring.tail); \
1114 intel_ring_advance(dev, &dev_priv->render_ring); \ 1135 intel_ring_advance(dev, &dev_priv__->render_ring); \
1115} while(0) 1136} while(0)
1116 1137
1117/** 1138/**
@@ -1141,7 +1162,6 @@ extern int intel_trans_dp_port_sel (struct drm_crtc *crtc);
1141#define IS_845G(dev) ((dev)->pci_device == 0x2562) 1162#define IS_845G(dev) ((dev)->pci_device == 0x2562)
1142#define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x) 1163#define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x)
1143#define IS_I865G(dev) ((dev)->pci_device == 0x2572) 1164#define IS_I865G(dev) ((dev)->pci_device == 0x2572)
1144#define IS_GEN2(dev) (INTEL_INFO(dev)->is_i8xx)
1145#define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g) 1165#define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g)
1146#define IS_I915GM(dev) ((dev)->pci_device == 0x2592) 1166#define IS_I915GM(dev) ((dev)->pci_device == 0x2592)
1147#define IS_I945G(dev) ((dev)->pci_device == 0x2772) 1167#define IS_I945G(dev) ((dev)->pci_device == 0x2772)
@@ -1160,27 +1180,13 @@ extern int intel_trans_dp_port_sel (struct drm_crtc *crtc);
1160#define IS_IRONLAKE_M(dev) ((dev)->pci_device == 0x0046) 1180#define IS_IRONLAKE_M(dev) ((dev)->pci_device == 0x0046)
1161#define IS_IRONLAKE(dev) (INTEL_INFO(dev)->is_ironlake) 1181#define IS_IRONLAKE(dev) (INTEL_INFO(dev)->is_ironlake)
1162#define IS_I9XX(dev) (INTEL_INFO(dev)->is_i9xx) 1182#define IS_I9XX(dev) (INTEL_INFO(dev)->is_i9xx)
1163#define IS_GEN6(dev) (INTEL_INFO(dev)->is_gen6)
1164#define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile) 1183#define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile)
1165 1184
1166#define IS_GEN3(dev) (IS_I915G(dev) || \ 1185#define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2)
1167 IS_I915GM(dev) || \ 1186#define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3)
1168 IS_I945G(dev) || \ 1187#define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4)
1169 IS_I945GM(dev) || \ 1188#define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5)
1170 IS_G33(dev) || \ 1189#define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6)
1171 IS_PINEVIEW(dev))
1172#define IS_GEN4(dev) ((dev)->pci_device == 0x2972 || \
1173 (dev)->pci_device == 0x2982 || \
1174 (dev)->pci_device == 0x2992 || \
1175 (dev)->pci_device == 0x29A2 || \
1176 (dev)->pci_device == 0x2A02 || \
1177 (dev)->pci_device == 0x2A12 || \
1178 (dev)->pci_device == 0x2E02 || \
1179 (dev)->pci_device == 0x2E12 || \
1180 (dev)->pci_device == 0x2E22 || \
1181 (dev)->pci_device == 0x2E32 || \
1182 (dev)->pci_device == 0x2A42 || \
1183 (dev)->pci_device == 0x2E42)
1184 1190
1185#define HAS_BSD(dev) (IS_IRONLAKE(dev) || IS_G4X(dev)) 1191#define HAS_BSD(dev) (IS_IRONLAKE(dev) || IS_G4X(dev))
1186#define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws) 1192#define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws)
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 0758c7802e6b..16fca1d1799a 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -34,7 +34,9 @@
34#include <linux/slab.h> 34#include <linux/slab.h>
35#include <linux/swap.h> 35#include <linux/swap.h>
36#include <linux/pci.h> 36#include <linux/pci.h>
37#include <linux/intel-gtt.h>
37 38
39static uint32_t i915_gem_get_gtt_alignment(struct drm_gem_object *obj);
38static int i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj); 40static int i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj);
39static void i915_gem_object_flush_gtt_write_domain(struct drm_gem_object *obj); 41static void i915_gem_object_flush_gtt_write_domain(struct drm_gem_object *obj);
40static void i915_gem_object_flush_cpu_write_domain(struct drm_gem_object *obj); 42static void i915_gem_object_flush_cpu_write_domain(struct drm_gem_object *obj);
@@ -48,8 +50,6 @@ static int i915_gem_object_wait_rendering(struct drm_gem_object *obj);
48static int i915_gem_object_bind_to_gtt(struct drm_gem_object *obj, 50static int i915_gem_object_bind_to_gtt(struct drm_gem_object *obj,
49 unsigned alignment); 51 unsigned alignment);
50static void i915_gem_clear_fence_reg(struct drm_gem_object *obj); 52static void i915_gem_clear_fence_reg(struct drm_gem_object *obj);
51static int i915_gem_evict_something(struct drm_device *dev, int min_size);
52static int i915_gem_evict_from_inactive_list(struct drm_device *dev);
53static int i915_gem_phys_pwrite(struct drm_device *dev, struct drm_gem_object *obj, 53static int i915_gem_phys_pwrite(struct drm_device *dev, struct drm_gem_object *obj,
54 struct drm_i915_gem_pwrite *args, 54 struct drm_i915_gem_pwrite *args,
55 struct drm_file *file_priv); 55 struct drm_file *file_priv);
@@ -58,6 +58,14 @@ static void i915_gem_free_object_tail(struct drm_gem_object *obj);
58static LIST_HEAD(shrink_list); 58static LIST_HEAD(shrink_list);
59static DEFINE_SPINLOCK(shrink_list_lock); 59static DEFINE_SPINLOCK(shrink_list_lock);
60 60
61static inline bool
62i915_gem_object_is_inactive(struct drm_i915_gem_object *obj_priv)
63{
64 return obj_priv->gtt_space &&
65 !obj_priv->active &&
66 obj_priv->pin_count == 0;
67}
68
61int i915_gem_do_init(struct drm_device *dev, unsigned long start, 69int i915_gem_do_init(struct drm_device *dev, unsigned long start,
62 unsigned long end) 70 unsigned long end)
63{ 71{
@@ -128,12 +136,15 @@ i915_gem_create_ioctl(struct drm_device *dev, void *data,
128 return -ENOMEM; 136 return -ENOMEM;
129 137
130 ret = drm_gem_handle_create(file_priv, obj, &handle); 138 ret = drm_gem_handle_create(file_priv, obj, &handle);
131 drm_gem_object_unreference_unlocked(obj); 139 if (ret) {
132 if (ret) 140 drm_gem_object_unreference_unlocked(obj);
133 return ret; 141 return ret;
142 }
134 143
135 args->handle = handle; 144 /* Sink the floating reference from kref_init(handlecount) */
145 drm_gem_object_handle_unreference_unlocked(obj);
136 146
147 args->handle = handle;
137 return 0; 148 return 0;
138} 149}
139 150
@@ -313,7 +324,8 @@ i915_gem_object_get_pages_or_evict(struct drm_gem_object *obj)
313 if (ret == -ENOMEM) { 324 if (ret == -ENOMEM) {
314 struct drm_device *dev = obj->dev; 325 struct drm_device *dev = obj->dev;
315 326
316 ret = i915_gem_evict_something(dev, obj->size); 327 ret = i915_gem_evict_something(dev, obj->size,
328 i915_gem_get_gtt_alignment(obj));
317 if (ret) 329 if (ret)
318 return ret; 330 return ret;
319 331
@@ -1036,6 +1048,11 @@ i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1036 ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0); 1048 ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0);
1037 } 1049 }
1038 1050
1051
1052 /* Maintain LRU order of "inactive" objects */
1053 if (ret == 0 && i915_gem_object_is_inactive(obj_priv))
1054 list_move_tail(&obj_priv->list, &dev_priv->mm.inactive_list);
1055
1039 drm_gem_object_unreference(obj); 1056 drm_gem_object_unreference(obj);
1040 mutex_unlock(&dev->struct_mutex); 1057 mutex_unlock(&dev->struct_mutex);
1041 return ret; 1058 return ret;
@@ -1137,7 +1154,7 @@ int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
1137{ 1154{
1138 struct drm_gem_object *obj = vma->vm_private_data; 1155 struct drm_gem_object *obj = vma->vm_private_data;
1139 struct drm_device *dev = obj->dev; 1156 struct drm_device *dev = obj->dev;
1140 struct drm_i915_private *dev_priv = dev->dev_private; 1157 drm_i915_private_t *dev_priv = dev->dev_private;
1141 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); 1158 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1142 pgoff_t page_offset; 1159 pgoff_t page_offset;
1143 unsigned long pfn; 1160 unsigned long pfn;
@@ -1155,8 +1172,6 @@ int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
1155 if (ret) 1172 if (ret)
1156 goto unlock; 1173 goto unlock;
1157 1174
1158 list_add_tail(&obj_priv->list, &dev_priv->mm.inactive_list);
1159
1160 ret = i915_gem_object_set_to_gtt_domain(obj, write); 1175 ret = i915_gem_object_set_to_gtt_domain(obj, write);
1161 if (ret) 1176 if (ret)
1162 goto unlock; 1177 goto unlock;
@@ -1169,6 +1184,9 @@ int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
1169 goto unlock; 1184 goto unlock;
1170 } 1185 }
1171 1186
1187 if (i915_gem_object_is_inactive(obj_priv))
1188 list_move_tail(&obj_priv->list, &dev_priv->mm.inactive_list);
1189
1172 pfn = ((dev->agp->base + obj_priv->gtt_offset) >> PAGE_SHIFT) + 1190 pfn = ((dev->agp->base + obj_priv->gtt_offset) >> PAGE_SHIFT) +
1173 page_offset; 1191 page_offset;
1174 1192
@@ -1363,7 +1381,6 @@ i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
1363 struct drm_file *file_priv) 1381 struct drm_file *file_priv)
1364{ 1382{
1365 struct drm_i915_gem_mmap_gtt *args = data; 1383 struct drm_i915_gem_mmap_gtt *args = data;
1366 struct drm_i915_private *dev_priv = dev->dev_private;
1367 struct drm_gem_object *obj; 1384 struct drm_gem_object *obj;
1368 struct drm_i915_gem_object *obj_priv; 1385 struct drm_i915_gem_object *obj_priv;
1369 int ret; 1386 int ret;
@@ -1409,7 +1426,6 @@ i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
1409 mutex_unlock(&dev->struct_mutex); 1426 mutex_unlock(&dev->struct_mutex);
1410 return ret; 1427 return ret;
1411 } 1428 }
1412 list_add_tail(&obj_priv->list, &dev_priv->mm.inactive_list);
1413 } 1429 }
1414 1430
1415 drm_gem_object_unreference(obj); 1431 drm_gem_object_unreference(obj);
@@ -1493,9 +1509,16 @@ i915_gem_object_truncate(struct drm_gem_object *obj)
1493 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); 1509 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1494 struct inode *inode; 1510 struct inode *inode;
1495 1511
1512 /* Our goal here is to return as much of the memory as
1513 * is possible back to the system as we are called from OOM.
1514 * To do this we must instruct the shmfs to drop all of its
1515 * backing pages, *now*. Here we mirror the actions taken
1516 * when by shmem_delete_inode() to release the backing store.
1517 */
1496 inode = obj->filp->f_path.dentry->d_inode; 1518 inode = obj->filp->f_path.dentry->d_inode;
1497 if (inode->i_op->truncate) 1519 truncate_inode_pages(inode->i_mapping, 0);
1498 inode->i_op->truncate (inode); 1520 if (inode->i_op->truncate_range)
1521 inode->i_op->truncate_range(inode, 0, (loff_t)-1);
1499 1522
1500 obj_priv->madv = __I915_MADV_PURGED; 1523 obj_priv->madv = __I915_MADV_PURGED;
1501} 1524}
@@ -1887,19 +1910,6 @@ i915_gem_flush(struct drm_device *dev,
1887 flush_domains); 1910 flush_domains);
1888} 1911}
1889 1912
1890static void
1891i915_gem_flush_ring(struct drm_device *dev,
1892 uint32_t invalidate_domains,
1893 uint32_t flush_domains,
1894 struct intel_ring_buffer *ring)
1895{
1896 if (flush_domains & I915_GEM_DOMAIN_CPU)
1897 drm_agp_chipset_flush(dev);
1898 ring->flush(dev, ring,
1899 invalidate_domains,
1900 flush_domains);
1901}
1902
1903/** 1913/**
1904 * Ensures that all rendering to the object has completed and the object is 1914 * Ensures that all rendering to the object has completed and the object is
1905 * safe to unbind from the GTT or access from the CPU. 1915 * safe to unbind from the GTT or access from the CPU.
@@ -1973,8 +1983,6 @@ i915_gem_object_unbind(struct drm_gem_object *obj)
1973 * cause memory corruption through use-after-free. 1983 * cause memory corruption through use-after-free.
1974 */ 1984 */
1975 1985
1976 BUG_ON(obj_priv->active);
1977
1978 /* release the fence reg _after_ flushing */ 1986 /* release the fence reg _after_ flushing */
1979 if (obj_priv->fence_reg != I915_FENCE_REG_NONE) 1987 if (obj_priv->fence_reg != I915_FENCE_REG_NONE)
1980 i915_gem_clear_fence_reg(obj); 1988 i915_gem_clear_fence_reg(obj);
@@ -2010,34 +2018,7 @@ i915_gem_object_unbind(struct drm_gem_object *obj)
2010 return ret; 2018 return ret;
2011} 2019}
2012 2020
2013static struct drm_gem_object * 2021int
2014i915_gem_find_inactive_object(struct drm_device *dev, int min_size)
2015{
2016 drm_i915_private_t *dev_priv = dev->dev_private;
2017 struct drm_i915_gem_object *obj_priv;
2018 struct drm_gem_object *best = NULL;
2019 struct drm_gem_object *first = NULL;
2020
2021 /* Try to find the smallest clean object */
2022 list_for_each_entry(obj_priv, &dev_priv->mm.inactive_list, list) {
2023 struct drm_gem_object *obj = &obj_priv->base;
2024 if (obj->size >= min_size) {
2025 if ((!obj_priv->dirty ||
2026 i915_gem_object_is_purgeable(obj_priv)) &&
2027 (!best || obj->size < best->size)) {
2028 best = obj;
2029 if (best->size == min_size)
2030 return best;
2031 }
2032 if (!first)
2033 first = obj;
2034 }
2035 }
2036
2037 return best ? best : first;
2038}
2039
2040static int
2041i915_gpu_idle(struct drm_device *dev) 2022i915_gpu_idle(struct drm_device *dev)
2042{ 2023{
2043 drm_i915_private_t *dev_priv = dev->dev_private; 2024 drm_i915_private_t *dev_priv = dev->dev_private;
@@ -2078,155 +2059,6 @@ i915_gpu_idle(struct drm_device *dev)
2078 return ret; 2059 return ret;
2079} 2060}
2080 2061
2081static int
2082i915_gem_evict_everything(struct drm_device *dev)
2083{
2084 drm_i915_private_t *dev_priv = dev->dev_private;
2085 int ret;
2086 bool lists_empty;
2087
2088 spin_lock(&dev_priv->mm.active_list_lock);
2089 lists_empty = (list_empty(&dev_priv->mm.inactive_list) &&
2090 list_empty(&dev_priv->mm.flushing_list) &&
2091 list_empty(&dev_priv->render_ring.active_list) &&
2092 (!HAS_BSD(dev)
2093 || list_empty(&dev_priv->bsd_ring.active_list)));
2094 spin_unlock(&dev_priv->mm.active_list_lock);
2095
2096 if (lists_empty)
2097 return -ENOSPC;
2098
2099 /* Flush everything (on to the inactive lists) and evict */
2100 ret = i915_gpu_idle(dev);
2101 if (ret)
2102 return ret;
2103
2104 BUG_ON(!list_empty(&dev_priv->mm.flushing_list));
2105
2106 ret = i915_gem_evict_from_inactive_list(dev);
2107 if (ret)
2108 return ret;
2109
2110 spin_lock(&dev_priv->mm.active_list_lock);
2111 lists_empty = (list_empty(&dev_priv->mm.inactive_list) &&
2112 list_empty(&dev_priv->mm.flushing_list) &&
2113 list_empty(&dev_priv->render_ring.active_list) &&
2114 (!HAS_BSD(dev)
2115 || list_empty(&dev_priv->bsd_ring.active_list)));
2116 spin_unlock(&dev_priv->mm.active_list_lock);
2117 BUG_ON(!lists_empty);
2118
2119 return 0;
2120}
2121
2122static int
2123i915_gem_evict_something(struct drm_device *dev, int min_size)
2124{
2125 drm_i915_private_t *dev_priv = dev->dev_private;
2126 struct drm_gem_object *obj;
2127 int ret;
2128
2129 struct intel_ring_buffer *render_ring = &dev_priv->render_ring;
2130 struct intel_ring_buffer *bsd_ring = &dev_priv->bsd_ring;
2131 for (;;) {
2132 i915_gem_retire_requests(dev);
2133
2134 /* If there's an inactive buffer available now, grab it
2135 * and be done.
2136 */
2137 obj = i915_gem_find_inactive_object(dev, min_size);
2138 if (obj) {
2139 struct drm_i915_gem_object *obj_priv;
2140
2141#if WATCH_LRU
2142 DRM_INFO("%s: evicting %p\n", __func__, obj);
2143#endif
2144 obj_priv = to_intel_bo(obj);
2145 BUG_ON(obj_priv->pin_count != 0);
2146 BUG_ON(obj_priv->active);
2147
2148 /* Wait on the rendering and unbind the buffer. */
2149 return i915_gem_object_unbind(obj);
2150 }
2151
2152 /* If we didn't get anything, but the ring is still processing
2153 * things, wait for the next to finish and hopefully leave us
2154 * a buffer to evict.
2155 */
2156 if (!list_empty(&render_ring->request_list)) {
2157 struct drm_i915_gem_request *request;
2158
2159 request = list_first_entry(&render_ring->request_list,
2160 struct drm_i915_gem_request,
2161 list);
2162
2163 ret = i915_wait_request(dev,
2164 request->seqno, request->ring);
2165 if (ret)
2166 return ret;
2167
2168 continue;
2169 }
2170
2171 if (HAS_BSD(dev) && !list_empty(&bsd_ring->request_list)) {
2172 struct drm_i915_gem_request *request;
2173
2174 request = list_first_entry(&bsd_ring->request_list,
2175 struct drm_i915_gem_request,
2176 list);
2177
2178 ret = i915_wait_request(dev,
2179 request->seqno, request->ring);
2180 if (ret)
2181 return ret;
2182
2183 continue;
2184 }
2185
2186 /* If we didn't have anything on the request list but there
2187 * are buffers awaiting a flush, emit one and try again.
2188 * When we wait on it, those buffers waiting for that flush
2189 * will get moved to inactive.
2190 */
2191 if (!list_empty(&dev_priv->mm.flushing_list)) {
2192 struct drm_i915_gem_object *obj_priv;
2193
2194 /* Find an object that we can immediately reuse */
2195 list_for_each_entry(obj_priv, &dev_priv->mm.flushing_list, list) {
2196 obj = &obj_priv->base;
2197 if (obj->size >= min_size)
2198 break;
2199
2200 obj = NULL;
2201 }
2202
2203 if (obj != NULL) {
2204 uint32_t seqno;
2205
2206 i915_gem_flush_ring(dev,
2207 obj->write_domain,
2208 obj->write_domain,
2209 obj_priv->ring);
2210 seqno = i915_add_request(dev, NULL,
2211 obj->write_domain,
2212 obj_priv->ring);
2213 if (seqno == 0)
2214 return -ENOMEM;
2215 continue;
2216 }
2217 }
2218
2219 /* If we didn't do any of the above, there's no single buffer
2220 * large enough to swap out for the new one, so just evict
2221 * everything and start again. (This should be rare.)
2222 */
2223 if (!list_empty (&dev_priv->mm.inactive_list))
2224 return i915_gem_evict_from_inactive_list(dev);
2225 else
2226 return i915_gem_evict_everything(dev);
2227 }
2228}
2229
2230int 2062int
2231i915_gem_object_get_pages(struct drm_gem_object *obj, 2063i915_gem_object_get_pages(struct drm_gem_object *obj,
2232 gfp_t gfpmask) 2064 gfp_t gfpmask)
@@ -2666,7 +2498,7 @@ i915_gem_object_bind_to_gtt(struct drm_gem_object *obj, unsigned alignment)
2666#if WATCH_LRU 2498#if WATCH_LRU
2667 DRM_INFO("%s: GTT full, evicting something\n", __func__); 2499 DRM_INFO("%s: GTT full, evicting something\n", __func__);
2668#endif 2500#endif
2669 ret = i915_gem_evict_something(dev, obj->size); 2501 ret = i915_gem_evict_something(dev, obj->size, alignment);
2670 if (ret) 2502 if (ret)
2671 return ret; 2503 return ret;
2672 2504
@@ -2684,7 +2516,8 @@ i915_gem_object_bind_to_gtt(struct drm_gem_object *obj, unsigned alignment)
2684 2516
2685 if (ret == -ENOMEM) { 2517 if (ret == -ENOMEM) {
2686 /* first try to clear up some space from the GTT */ 2518 /* first try to clear up some space from the GTT */
2687 ret = i915_gem_evict_something(dev, obj->size); 2519 ret = i915_gem_evict_something(dev, obj->size,
2520 alignment);
2688 if (ret) { 2521 if (ret) {
2689 /* now try to shrink everyone else */ 2522 /* now try to shrink everyone else */
2690 if (gfpmask) { 2523 if (gfpmask) {
@@ -2714,7 +2547,7 @@ i915_gem_object_bind_to_gtt(struct drm_gem_object *obj, unsigned alignment)
2714 drm_mm_put_block(obj_priv->gtt_space); 2547 drm_mm_put_block(obj_priv->gtt_space);
2715 obj_priv->gtt_space = NULL; 2548 obj_priv->gtt_space = NULL;
2716 2549
2717 ret = i915_gem_evict_something(dev, obj->size); 2550 ret = i915_gem_evict_something(dev, obj->size, alignment);
2718 if (ret) 2551 if (ret)
2719 return ret; 2552 return ret;
2720 2553
@@ -2723,6 +2556,9 @@ i915_gem_object_bind_to_gtt(struct drm_gem_object *obj, unsigned alignment)
2723 atomic_inc(&dev->gtt_count); 2556 atomic_inc(&dev->gtt_count);
2724 atomic_add(obj->size, &dev->gtt_memory); 2557 atomic_add(obj->size, &dev->gtt_memory);
2725 2558
2559 /* keep track of bounds object by adding it to the inactive list */
2560 list_add_tail(&obj_priv->list, &dev_priv->mm.inactive_list);
2561
2726 /* Assert that the object is not currently in any GPU domain. As it 2562 /* Assert that the object is not currently in any GPU domain. As it
2727 * wasn't in the GTT, there shouldn't be any way it could have been in 2563 * wasn't in the GTT, there shouldn't be any way it could have been in
2728 * a GPU cache 2564 * a GPU cache
@@ -3117,6 +2953,7 @@ static void
3117i915_gem_object_set_to_gpu_domain(struct drm_gem_object *obj) 2953i915_gem_object_set_to_gpu_domain(struct drm_gem_object *obj)
3118{ 2954{
3119 struct drm_device *dev = obj->dev; 2955 struct drm_device *dev = obj->dev;
2956 drm_i915_private_t *dev_priv = dev->dev_private;
3120 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); 2957 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
3121 uint32_t invalidate_domains = 0; 2958 uint32_t invalidate_domains = 0;
3122 uint32_t flush_domains = 0; 2959 uint32_t flush_domains = 0;
@@ -3179,6 +3016,13 @@ i915_gem_object_set_to_gpu_domain(struct drm_gem_object *obj)
3179 obj->pending_write_domain = obj->write_domain; 3016 obj->pending_write_domain = obj->write_domain;
3180 obj->read_domains = obj->pending_read_domains; 3017 obj->read_domains = obj->pending_read_domains;
3181 3018
3019 if (flush_domains & I915_GEM_GPU_DOMAINS) {
3020 if (obj_priv->ring == &dev_priv->render_ring)
3021 dev_priv->flush_rings |= FLUSH_RENDER_RING;
3022 else if (obj_priv->ring == &dev_priv->bsd_ring)
3023 dev_priv->flush_rings |= FLUSH_BSD_RING;
3024 }
3025
3182 dev->invalidate_domains |= invalidate_domains; 3026 dev->invalidate_domains |= invalidate_domains;
3183 dev->flush_domains |= flush_domains; 3027 dev->flush_domains |= flush_domains;
3184#if WATCH_BUF 3028#if WATCH_BUF
@@ -3718,7 +3562,6 @@ i915_gem_do_execbuffer(struct drm_device *dev, void *data,
3718 ring = &dev_priv->render_ring; 3562 ring = &dev_priv->render_ring;
3719 } 3563 }
3720 3564
3721
3722 if (args->buffer_count < 1) { 3565 if (args->buffer_count < 1) {
3723 DRM_ERROR("execbuf with %d buffers\n", args->buffer_count); 3566 DRM_ERROR("execbuf with %d buffers\n", args->buffer_count);
3724 return -EINVAL; 3567 return -EINVAL;
@@ -3746,6 +3589,7 @@ i915_gem_do_execbuffer(struct drm_device *dev, void *data,
3746 if (ret != 0) { 3589 if (ret != 0) {
3747 DRM_ERROR("copy %d cliprects failed: %d\n", 3590 DRM_ERROR("copy %d cliprects failed: %d\n",
3748 args->num_cliprects, ret); 3591 args->num_cliprects, ret);
3592 ret = -EFAULT;
3749 goto pre_mutex_err; 3593 goto pre_mutex_err;
3750 } 3594 }
3751 } 3595 }
@@ -3892,6 +3736,7 @@ i915_gem_do_execbuffer(struct drm_device *dev, void *data,
3892 */ 3736 */
3893 dev->invalidate_domains = 0; 3737 dev->invalidate_domains = 0;
3894 dev->flush_domains = 0; 3738 dev->flush_domains = 0;
3739 dev_priv->flush_rings = 0;
3895 3740
3896 for (i = 0; i < args->buffer_count; i++) { 3741 for (i = 0; i < args->buffer_count; i++) {
3897 struct drm_gem_object *obj = object_list[i]; 3742 struct drm_gem_object *obj = object_list[i];
@@ -3912,16 +3757,14 @@ i915_gem_do_execbuffer(struct drm_device *dev, void *data,
3912 i915_gem_flush(dev, 3757 i915_gem_flush(dev,
3913 dev->invalidate_domains, 3758 dev->invalidate_domains,
3914 dev->flush_domains); 3759 dev->flush_domains);
3915 if (dev->flush_domains & I915_GEM_GPU_DOMAINS) { 3760 if (dev_priv->flush_rings & FLUSH_RENDER_RING)
3916 (void)i915_add_request(dev, file_priv, 3761 (void)i915_add_request(dev, file_priv,
3917 dev->flush_domains, 3762 dev->flush_domains,
3918 &dev_priv->render_ring); 3763 &dev_priv->render_ring);
3919 3764 if (dev_priv->flush_rings & FLUSH_BSD_RING)
3920 if (HAS_BSD(dev)) 3765 (void)i915_add_request(dev, file_priv,
3921 (void)i915_add_request(dev, file_priv, 3766 dev->flush_domains,
3922 dev->flush_domains, 3767 &dev_priv->bsd_ring);
3923 &dev_priv->bsd_ring);
3924 }
3925 } 3768 }
3926 3769
3927 for (i = 0; i < args->buffer_count; i++) { 3770 for (i = 0; i < args->buffer_count; i++) {
@@ -4192,6 +4035,10 @@ i915_gem_object_pin(struct drm_gem_object *obj, uint32_t alignment)
4192 if (alignment == 0) 4035 if (alignment == 0)
4193 alignment = i915_gem_get_gtt_alignment(obj); 4036 alignment = i915_gem_get_gtt_alignment(obj);
4194 if (obj_priv->gtt_offset & (alignment - 1)) { 4037 if (obj_priv->gtt_offset & (alignment - 1)) {
4038 WARN(obj_priv->pin_count,
4039 "bo is already pinned with incorrect alignment:"
4040 " offset=%x, req.alignment=%x\n",
4041 obj_priv->gtt_offset, alignment);
4195 ret = i915_gem_object_unbind(obj); 4042 ret = i915_gem_object_unbind(obj);
4196 if (ret) 4043 if (ret)
4197 return ret; 4044 return ret;
@@ -4213,8 +4060,7 @@ i915_gem_object_pin(struct drm_gem_object *obj, uint32_t alignment)
4213 atomic_inc(&dev->pin_count); 4060 atomic_inc(&dev->pin_count);
4214 atomic_add(obj->size, &dev->pin_memory); 4061 atomic_add(obj->size, &dev->pin_memory);
4215 if (!obj_priv->active && 4062 if (!obj_priv->active &&
4216 (obj->write_domain & I915_GEM_GPU_DOMAINS) == 0 && 4063 (obj->write_domain & I915_GEM_GPU_DOMAINS) == 0)
4217 !list_empty(&obj_priv->list))
4218 list_del_init(&obj_priv->list); 4064 list_del_init(&obj_priv->list);
4219 } 4065 }
4220 i915_verify_inactive(dev, __FILE__, __LINE__); 4066 i915_verify_inactive(dev, __FILE__, __LINE__);
@@ -4359,22 +4205,34 @@ i915_gem_busy_ioctl(struct drm_device *dev, void *data,
4359 } 4205 }
4360 4206
4361 mutex_lock(&dev->struct_mutex); 4207 mutex_lock(&dev->struct_mutex);
4362 /* Update the active list for the hardware's current position.
4363 * Otherwise this only updates on a delayed timer or when irqs are
4364 * actually unmasked, and our working set ends up being larger than
4365 * required.
4366 */
4367 i915_gem_retire_requests(dev);
4368 4208
4369 obj_priv = to_intel_bo(obj); 4209 /* Count all active objects as busy, even if they are currently not used
4370 /* Don't count being on the flushing list against the object being 4210 * by the gpu. Users of this interface expect objects to eventually
4371 * done. Otherwise, a buffer left on the flushing list but not getting 4211 * become non-busy without any further actions, therefore emit any
4372 * flushed (because nobody's flushing that domain) won't ever return 4212 * necessary flushes here.
4373 * unbusy and get reused by libdrm's bo cache. The other expected
4374 * consumer of this interface, OpenGL's occlusion queries, also specs
4375 * that the objects get unbusy "eventually" without any interference.
4376 */ 4213 */
4377 args->busy = obj_priv->active && obj_priv->last_rendering_seqno != 0; 4214 obj_priv = to_intel_bo(obj);
4215 args->busy = obj_priv->active;
4216 if (args->busy) {
4217 /* Unconditionally flush objects, even when the gpu still uses this
4218 * object. Userspace calling this function indicates that it wants to
4219 * use this buffer rather sooner than later, so issuing the required
4220 * flush earlier is beneficial.
4221 */
4222 if (obj->write_domain) {
4223 i915_gem_flush(dev, 0, obj->write_domain);
4224 (void)i915_add_request(dev, file_priv, obj->write_domain, obj_priv->ring);
4225 }
4226
4227 /* Update the active list for the hardware's current position.
4228 * Otherwise this only updates on a delayed timer or when irqs
4229 * are actually unmasked, and our working set ends up being
4230 * larger than required.
4231 */
4232 i915_gem_retire_requests_ring(dev, obj_priv->ring);
4233
4234 args->busy = obj_priv->active;
4235 }
4378 4236
4379 drm_gem_object_unreference(obj); 4237 drm_gem_object_unreference(obj);
4380 mutex_unlock(&dev->struct_mutex); 4238 mutex_unlock(&dev->struct_mutex);
@@ -4514,30 +4372,6 @@ void i915_gem_free_object(struct drm_gem_object *obj)
4514 i915_gem_free_object_tail(obj); 4372 i915_gem_free_object_tail(obj);
4515} 4373}
4516 4374
4517/** Unbinds all inactive objects. */
4518static int
4519i915_gem_evict_from_inactive_list(struct drm_device *dev)
4520{
4521 drm_i915_private_t *dev_priv = dev->dev_private;
4522
4523 while (!list_empty(&dev_priv->mm.inactive_list)) {
4524 struct drm_gem_object *obj;
4525 int ret;
4526
4527 obj = &list_first_entry(&dev_priv->mm.inactive_list,
4528 struct drm_i915_gem_object,
4529 list)->base;
4530
4531 ret = i915_gem_object_unbind(obj);
4532 if (ret != 0) {
4533 DRM_ERROR("Error unbinding object: %d\n", ret);
4534 return ret;
4535 }
4536 }
4537
4538 return 0;
4539}
4540
4541int 4375int
4542i915_gem_idle(struct drm_device *dev) 4376i915_gem_idle(struct drm_device *dev)
4543{ 4377{
@@ -4562,7 +4396,7 @@ i915_gem_idle(struct drm_device *dev)
4562 4396
4563 /* Under UMS, be paranoid and evict. */ 4397 /* Under UMS, be paranoid and evict. */
4564 if (!drm_core_check_feature(dev, DRIVER_MODESET)) { 4398 if (!drm_core_check_feature(dev, DRIVER_MODESET)) {
4565 ret = i915_gem_evict_from_inactive_list(dev); 4399 ret = i915_gem_evict_inactive(dev);
4566 if (ret) { 4400 if (ret) {
4567 mutex_unlock(&dev->struct_mutex); 4401 mutex_unlock(&dev->struct_mutex);
4568 return ret; 4402 return ret;
@@ -4680,6 +4514,8 @@ i915_gem_init_ringbuffer(struct drm_device *dev)
4680 goto cleanup_render_ring; 4514 goto cleanup_render_ring;
4681 } 4515 }
4682 4516
4517 dev_priv->next_seqno = 1;
4518
4683 return 0; 4519 return 0;
4684 4520
4685cleanup_render_ring: 4521cleanup_render_ring:
@@ -4841,7 +4677,7 @@ i915_gem_load(struct drm_device *dev)
4841 * e.g. for cursor + overlay regs 4677 * e.g. for cursor + overlay regs
4842 */ 4678 */
4843int i915_gem_init_phys_object(struct drm_device *dev, 4679int i915_gem_init_phys_object(struct drm_device *dev,
4844 int id, int size) 4680 int id, int size, int align)
4845{ 4681{
4846 drm_i915_private_t *dev_priv = dev->dev_private; 4682 drm_i915_private_t *dev_priv = dev->dev_private;
4847 struct drm_i915_gem_phys_object *phys_obj; 4683 struct drm_i915_gem_phys_object *phys_obj;
@@ -4856,7 +4692,7 @@ int i915_gem_init_phys_object(struct drm_device *dev,
4856 4692
4857 phys_obj->id = id; 4693 phys_obj->id = id;
4858 4694
4859 phys_obj->handle = drm_pci_alloc(dev, size, 0); 4695 phys_obj->handle = drm_pci_alloc(dev, size, align);
4860 if (!phys_obj->handle) { 4696 if (!phys_obj->handle) {
4861 ret = -ENOMEM; 4697 ret = -ENOMEM;
4862 goto kfree_obj; 4698 goto kfree_obj;
@@ -4938,7 +4774,9 @@ out:
4938 4774
4939int 4775int
4940i915_gem_attach_phys_object(struct drm_device *dev, 4776i915_gem_attach_phys_object(struct drm_device *dev,
4941 struct drm_gem_object *obj, int id) 4777 struct drm_gem_object *obj,
4778 int id,
4779 int align)
4942{ 4780{
4943 drm_i915_private_t *dev_priv = dev->dev_private; 4781 drm_i915_private_t *dev_priv = dev->dev_private;
4944 struct drm_i915_gem_object *obj_priv; 4782 struct drm_i915_gem_object *obj_priv;
@@ -4957,11 +4795,10 @@ i915_gem_attach_phys_object(struct drm_device *dev,
4957 i915_gem_detach_phys_object(dev, obj); 4795 i915_gem_detach_phys_object(dev, obj);
4958 } 4796 }
4959 4797
4960
4961 /* create a new object */ 4798 /* create a new object */
4962 if (!dev_priv->mm.phys_objs[id - 1]) { 4799 if (!dev_priv->mm.phys_objs[id - 1]) {
4963 ret = i915_gem_init_phys_object(dev, id, 4800 ret = i915_gem_init_phys_object(dev, id,
4964 obj->size); 4801 obj->size, align);
4965 if (ret) { 4802 if (ret) {
4966 DRM_ERROR("failed to init phys object %d size: %zu\n", id, obj->size); 4803 DRM_ERROR("failed to init phys object %d size: %zu\n", id, obj->size);
4967 goto out; 4804 goto out;
diff --git a/drivers/gpu/drm/i915/i915_gem_evict.c b/drivers/gpu/drm/i915/i915_gem_evict.c
new file mode 100644
index 000000000000..72cae3cccad8
--- /dev/null
+++ b/drivers/gpu/drm/i915/i915_gem_evict.c
@@ -0,0 +1,271 @@
1/*
2 * Copyright © 2008-2010 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 * Chris Wilson <chris@chris-wilson.co.uuk>
26 *
27 */
28
29#include "drmP.h"
30#include "drm.h"
31#include "i915_drv.h"
32#include "i915_drm.h"
33
34static struct drm_i915_gem_object *
35i915_gem_next_active_object(struct drm_device *dev,
36 struct list_head **render_iter,
37 struct list_head **bsd_iter)
38{
39 drm_i915_private_t *dev_priv = dev->dev_private;
40 struct drm_i915_gem_object *render_obj = NULL, *bsd_obj = NULL;
41
42 if (*render_iter != &dev_priv->render_ring.active_list)
43 render_obj = list_entry(*render_iter,
44 struct drm_i915_gem_object,
45 list);
46
47 if (HAS_BSD(dev)) {
48 if (*bsd_iter != &dev_priv->bsd_ring.active_list)
49 bsd_obj = list_entry(*bsd_iter,
50 struct drm_i915_gem_object,
51 list);
52
53 if (render_obj == NULL) {
54 *bsd_iter = (*bsd_iter)->next;
55 return bsd_obj;
56 }
57
58 if (bsd_obj == NULL) {
59 *render_iter = (*render_iter)->next;
60 return render_obj;
61 }
62
63 /* XXX can we handle seqno wrapping? */
64 if (render_obj->last_rendering_seqno < bsd_obj->last_rendering_seqno) {
65 *render_iter = (*render_iter)->next;
66 return render_obj;
67 } else {
68 *bsd_iter = (*bsd_iter)->next;
69 return bsd_obj;
70 }
71 } else {
72 *render_iter = (*render_iter)->next;
73 return render_obj;
74 }
75}
76
77static bool
78mark_free(struct drm_i915_gem_object *obj_priv,
79 struct list_head *unwind)
80{
81 list_add(&obj_priv->evict_list, unwind);
82 return drm_mm_scan_add_block(obj_priv->gtt_space);
83}
84
85#define i915_for_each_active_object(OBJ, R, B) \
86 *(R) = dev_priv->render_ring.active_list.next; \
87 *(B) = dev_priv->bsd_ring.active_list.next; \
88 while (((OBJ) = i915_gem_next_active_object(dev, (R), (B))) != NULL)
89
90int
91i915_gem_evict_something(struct drm_device *dev, int min_size, unsigned alignment)
92{
93 drm_i915_private_t *dev_priv = dev->dev_private;
94 struct list_head eviction_list, unwind_list;
95 struct drm_i915_gem_object *obj_priv, *tmp_obj_priv;
96 struct list_head *render_iter, *bsd_iter;
97 int ret = 0;
98
99 i915_gem_retire_requests(dev);
100
101 /* Re-check for free space after retiring requests */
102 if (drm_mm_search_free(&dev_priv->mm.gtt_space,
103 min_size, alignment, 0))
104 return 0;
105
106 /*
107 * The goal is to evict objects and amalgamate space in LRU order.
108 * The oldest idle objects reside on the inactive list, which is in
109 * retirement order. The next objects to retire are those on the (per
110 * ring) active list that do not have an outstanding flush. Once the
111 * hardware reports completion (the seqno is updated after the
112 * batchbuffer has been finished) the clean buffer objects would
113 * be retired to the inactive list. Any dirty objects would be added
114 * to the tail of the flushing list. So after processing the clean
115 * active objects we need to emit a MI_FLUSH to retire the flushing
116 * list, hence the retirement order of the flushing list is in
117 * advance of the dirty objects on the active lists.
118 *
119 * The retirement sequence is thus:
120 * 1. Inactive objects (already retired)
121 * 2. Clean active objects
122 * 3. Flushing list
123 * 4. Dirty active objects.
124 *
125 * On each list, the oldest objects lie at the HEAD with the freshest
126 * object on the TAIL.
127 */
128
129 INIT_LIST_HEAD(&unwind_list);
130 drm_mm_init_scan(&dev_priv->mm.gtt_space, min_size, alignment);
131
132 /* First see if there is a large enough contiguous idle region... */
133 list_for_each_entry(obj_priv, &dev_priv->mm.inactive_list, list) {
134 if (mark_free(obj_priv, &unwind_list))
135 goto found;
136 }
137
138 /* Now merge in the soon-to-be-expired objects... */
139 i915_for_each_active_object(obj_priv, &render_iter, &bsd_iter) {
140 /* Does the object require an outstanding flush? */
141 if (obj_priv->base.write_domain || obj_priv->pin_count)
142 continue;
143
144 if (mark_free(obj_priv, &unwind_list))
145 goto found;
146 }
147
148 /* Finally add anything with a pending flush (in order of retirement) */
149 list_for_each_entry(obj_priv, &dev_priv->mm.flushing_list, list) {
150 if (obj_priv->pin_count)
151 continue;
152
153 if (mark_free(obj_priv, &unwind_list))
154 goto found;
155 }
156 i915_for_each_active_object(obj_priv, &render_iter, &bsd_iter) {
157 if (! obj_priv->base.write_domain || obj_priv->pin_count)
158 continue;
159
160 if (mark_free(obj_priv, &unwind_list))
161 goto found;
162 }
163
164 /* Nothing found, clean up and bail out! */
165 list_for_each_entry(obj_priv, &unwind_list, evict_list) {
166 ret = drm_mm_scan_remove_block(obj_priv->gtt_space);
167 BUG_ON(ret);
168 }
169
170 /* We expect the caller to unpin, evict all and try again, or give up.
171 * So calling i915_gem_evict_everything() is unnecessary.
172 */
173 return -ENOSPC;
174
175found:
176 INIT_LIST_HEAD(&eviction_list);
177 list_for_each_entry_safe(obj_priv, tmp_obj_priv,
178 &unwind_list, evict_list) {
179 if (drm_mm_scan_remove_block(obj_priv->gtt_space)) {
180 /* drm_mm doesn't allow any other other operations while
181 * scanning, therefore store to be evicted objects on a
182 * temporary list. */
183 list_move(&obj_priv->evict_list, &eviction_list);
184 }
185 }
186
187 /* Unbinding will emit any required flushes */
188 list_for_each_entry_safe(obj_priv, tmp_obj_priv,
189 &eviction_list, evict_list) {
190#if WATCH_LRU
191 DRM_INFO("%s: evicting %p\n", __func__, obj);
192#endif
193 ret = i915_gem_object_unbind(&obj_priv->base);
194 if (ret)
195 return ret;
196 }
197
198 /* The just created free hole should be on the top of the free stack
199 * maintained by drm_mm, so this BUG_ON actually executes in O(1).
200 * Furthermore all accessed data has just recently been used, so it
201 * should be really fast, too. */
202 BUG_ON(!drm_mm_search_free(&dev_priv->mm.gtt_space, min_size,
203 alignment, 0));
204
205 return 0;
206}
207
208int
209i915_gem_evict_everything(struct drm_device *dev)
210{
211 drm_i915_private_t *dev_priv = dev->dev_private;
212 int ret;
213 bool lists_empty;
214
215 spin_lock(&dev_priv->mm.active_list_lock);
216 lists_empty = (list_empty(&dev_priv->mm.inactive_list) &&
217 list_empty(&dev_priv->mm.flushing_list) &&
218 list_empty(&dev_priv->render_ring.active_list) &&
219 (!HAS_BSD(dev)
220 || list_empty(&dev_priv->bsd_ring.active_list)));
221 spin_unlock(&dev_priv->mm.active_list_lock);
222
223 if (lists_empty)
224 return -ENOSPC;
225
226 /* Flush everything (on to the inactive lists) and evict */
227 ret = i915_gpu_idle(dev);
228 if (ret)
229 return ret;
230
231 BUG_ON(!list_empty(&dev_priv->mm.flushing_list));
232
233 ret = i915_gem_evict_inactive(dev);
234 if (ret)
235 return ret;
236
237 spin_lock(&dev_priv->mm.active_list_lock);
238 lists_empty = (list_empty(&dev_priv->mm.inactive_list) &&
239 list_empty(&dev_priv->mm.flushing_list) &&
240 list_empty(&dev_priv->render_ring.active_list) &&
241 (!HAS_BSD(dev)
242 || list_empty(&dev_priv->bsd_ring.active_list)));
243 spin_unlock(&dev_priv->mm.active_list_lock);
244 BUG_ON(!lists_empty);
245
246 return 0;
247}
248
249/** Unbinds all inactive objects. */
250int
251i915_gem_evict_inactive(struct drm_device *dev)
252{
253 drm_i915_private_t *dev_priv = dev->dev_private;
254
255 while (!list_empty(&dev_priv->mm.inactive_list)) {
256 struct drm_gem_object *obj;
257 int ret;
258
259 obj = &list_first_entry(&dev_priv->mm.inactive_list,
260 struct drm_i915_gem_object,
261 list)->base;
262
263 ret = i915_gem_object_unbind(obj);
264 if (ret != 0) {
265 DRM_ERROR("Error unbinding object: %d\n", ret);
266 return ret;
267 }
268 }
269
270 return 0;
271}
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 85785a8844ed..59457e83b011 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -425,9 +425,11 @@ static struct drm_i915_error_object *
425i915_error_object_create(struct drm_device *dev, 425i915_error_object_create(struct drm_device *dev,
426 struct drm_gem_object *src) 426 struct drm_gem_object *src)
427{ 427{
428 drm_i915_private_t *dev_priv = dev->dev_private;
428 struct drm_i915_error_object *dst; 429 struct drm_i915_error_object *dst;
429 struct drm_i915_gem_object *src_priv; 430 struct drm_i915_gem_object *src_priv;
430 int page, page_count; 431 int page, page_count;
432 u32 reloc_offset;
431 433
432 if (src == NULL) 434 if (src == NULL)
433 return NULL; 435 return NULL;
@@ -442,18 +444,27 @@ i915_error_object_create(struct drm_device *dev,
442 if (dst == NULL) 444 if (dst == NULL)
443 return NULL; 445 return NULL;
444 446
447 reloc_offset = src_priv->gtt_offset;
445 for (page = 0; page < page_count; page++) { 448 for (page = 0; page < page_count; page++) {
446 void *s, *d = kmalloc(PAGE_SIZE, GFP_ATOMIC);
447 unsigned long flags; 449 unsigned long flags;
450 void __iomem *s;
451 void *d;
448 452
453 d = kmalloc(PAGE_SIZE, GFP_ATOMIC);
449 if (d == NULL) 454 if (d == NULL)
450 goto unwind; 455 goto unwind;
456
451 local_irq_save(flags); 457 local_irq_save(flags);
452 s = kmap_atomic(src_priv->pages[page], KM_IRQ0); 458 s = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping,
453 memcpy(d, s, PAGE_SIZE); 459 reloc_offset,
454 kunmap_atomic(s, KM_IRQ0); 460 KM_IRQ0);
461 memcpy_fromio(d, s, PAGE_SIZE);
462 io_mapping_unmap_atomic(s, KM_IRQ0);
455 local_irq_restore(flags); 463 local_irq_restore(flags);
464
456 dst->pages[page] = d; 465 dst->pages[page] = d;
466
467 reloc_offset += PAGE_SIZE;
457 } 468 }
458 dst->page_count = page_count; 469 dst->page_count = page_count;
459 dst->gtt_offset = src_priv->gtt_offset; 470 dst->gtt_offset = src_priv->gtt_offset;
@@ -489,6 +500,7 @@ i915_error_state_free(struct drm_device *dev,
489 i915_error_object_free(error->batchbuffer[1]); 500 i915_error_object_free(error->batchbuffer[1]);
490 i915_error_object_free(error->ringbuffer); 501 i915_error_object_free(error->ringbuffer);
491 kfree(error->active_bo); 502 kfree(error->active_bo);
503 kfree(error->overlay);
492 kfree(error); 504 kfree(error);
493} 505}
494 506
@@ -612,18 +624,57 @@ static void i915_capture_error_state(struct drm_device *dev)
612 624
613 if (batchbuffer[1] == NULL && 625 if (batchbuffer[1] == NULL &&
614 error->acthd >= obj_priv->gtt_offset && 626 error->acthd >= obj_priv->gtt_offset &&
615 error->acthd < obj_priv->gtt_offset + obj->size && 627 error->acthd < obj_priv->gtt_offset + obj->size)
616 batchbuffer[0] != obj)
617 batchbuffer[1] = obj; 628 batchbuffer[1] = obj;
618 629
619 count++; 630 count++;
620 } 631 }
632 /* Scan the other lists for completeness for those bizarre errors. */
633 if (batchbuffer[0] == NULL || batchbuffer[1] == NULL) {
634 list_for_each_entry(obj_priv, &dev_priv->mm.flushing_list, list) {
635 struct drm_gem_object *obj = &obj_priv->base;
636
637 if (batchbuffer[0] == NULL &&
638 bbaddr >= obj_priv->gtt_offset &&
639 bbaddr < obj_priv->gtt_offset + obj->size)
640 batchbuffer[0] = obj;
641
642 if (batchbuffer[1] == NULL &&
643 error->acthd >= obj_priv->gtt_offset &&
644 error->acthd < obj_priv->gtt_offset + obj->size)
645 batchbuffer[1] = obj;
646
647 if (batchbuffer[0] && batchbuffer[1])
648 break;
649 }
650 }
651 if (batchbuffer[0] == NULL || batchbuffer[1] == NULL) {
652 list_for_each_entry(obj_priv, &dev_priv->mm.inactive_list, list) {
653 struct drm_gem_object *obj = &obj_priv->base;
654
655 if (batchbuffer[0] == NULL &&
656 bbaddr >= obj_priv->gtt_offset &&
657 bbaddr < obj_priv->gtt_offset + obj->size)
658 batchbuffer[0] = obj;
659
660 if (batchbuffer[1] == NULL &&
661 error->acthd >= obj_priv->gtt_offset &&
662 error->acthd < obj_priv->gtt_offset + obj->size)
663 batchbuffer[1] = obj;
664
665 if (batchbuffer[0] && batchbuffer[1])
666 break;
667 }
668 }
621 669
622 /* We need to copy these to an anonymous buffer as the simplest 670 /* We need to copy these to an anonymous buffer as the simplest
623 * method to avoid being overwritten by userpace. 671 * method to avoid being overwritten by userpace.
624 */ 672 */
625 error->batchbuffer[0] = i915_error_object_create(dev, batchbuffer[0]); 673 error->batchbuffer[0] = i915_error_object_create(dev, batchbuffer[0]);
626 error->batchbuffer[1] = i915_error_object_create(dev, batchbuffer[1]); 674 if (batchbuffer[1] != batchbuffer[0])
675 error->batchbuffer[1] = i915_error_object_create(dev, batchbuffer[1]);
676 else
677 error->batchbuffer[1] = NULL;
627 678
628 /* Record the ringbuffer */ 679 /* Record the ringbuffer */
629 error->ringbuffer = i915_error_object_create(dev, 680 error->ringbuffer = i915_error_object_create(dev,
@@ -667,6 +718,8 @@ static void i915_capture_error_state(struct drm_device *dev)
667 718
668 do_gettimeofday(&error->time); 719 do_gettimeofday(&error->time);
669 720
721 error->overlay = intel_overlay_capture_error_state(dev);
722
670 spin_lock_irqsave(&dev_priv->error_lock, flags); 723 spin_lock_irqsave(&dev_priv->error_lock, flags);
671 if (dev_priv->first_error == NULL) { 724 if (dev_priv->first_error == NULL) {
672 dev_priv->first_error = error; 725 dev_priv->first_error = error;
@@ -834,6 +887,49 @@ static void i915_handle_error(struct drm_device *dev, bool wedged)
834 queue_work(dev_priv->wq, &dev_priv->error_work); 887 queue_work(dev_priv->wq, &dev_priv->error_work);
835} 888}
836 889
890static void i915_pageflip_stall_check(struct drm_device *dev, int pipe)
891{
892 drm_i915_private_t *dev_priv = dev->dev_private;
893 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
894 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
895 struct drm_i915_gem_object *obj_priv;
896 struct intel_unpin_work *work;
897 unsigned long flags;
898 bool stall_detected;
899
900 /* Ignore early vblank irqs */
901 if (intel_crtc == NULL)
902 return;
903
904 spin_lock_irqsave(&dev->event_lock, flags);
905 work = intel_crtc->unpin_work;
906
907 if (work == NULL || work->pending || !work->enable_stall_check) {
908 /* Either the pending flip IRQ arrived, or we're too early. Don't check */
909 spin_unlock_irqrestore(&dev->event_lock, flags);
910 return;
911 }
912
913 /* Potential stall - if we see that the flip has happened, assume a missed interrupt */
914 obj_priv = to_intel_bo(work->pending_flip_obj);
915 if(IS_I965G(dev)) {
916 int dspsurf = intel_crtc->plane == 0 ? DSPASURF : DSPBSURF;
917 stall_detected = I915_READ(dspsurf) == obj_priv->gtt_offset;
918 } else {
919 int dspaddr = intel_crtc->plane == 0 ? DSPAADDR : DSPBADDR;
920 stall_detected = I915_READ(dspaddr) == (obj_priv->gtt_offset +
921 crtc->y * crtc->fb->pitch +
922 crtc->x * crtc->fb->bits_per_pixel/8);
923 }
924
925 spin_unlock_irqrestore(&dev->event_lock, flags);
926
927 if (stall_detected) {
928 DRM_DEBUG_DRIVER("Pageflip stall detected\n");
929 intel_prepare_page_flip(dev, intel_crtc->plane);
930 }
931}
932
837irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS) 933irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS)
838{ 934{
839 struct drm_device *dev = (struct drm_device *) arg; 935 struct drm_device *dev = (struct drm_device *) arg;
@@ -951,15 +1047,19 @@ irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS)
951 if (pipea_stats & vblank_status) { 1047 if (pipea_stats & vblank_status) {
952 vblank++; 1048 vblank++;
953 drm_handle_vblank(dev, 0); 1049 drm_handle_vblank(dev, 0);
954 if (!dev_priv->flip_pending_is_done) 1050 if (!dev_priv->flip_pending_is_done) {
1051 i915_pageflip_stall_check(dev, 0);
955 intel_finish_page_flip(dev, 0); 1052 intel_finish_page_flip(dev, 0);
1053 }
956 } 1054 }
957 1055
958 if (pipeb_stats & vblank_status) { 1056 if (pipeb_stats & vblank_status) {
959 vblank++; 1057 vblank++;
960 drm_handle_vblank(dev, 1); 1058 drm_handle_vblank(dev, 1);
961 if (!dev_priv->flip_pending_is_done) 1059 if (!dev_priv->flip_pending_is_done) {
1060 i915_pageflip_stall_check(dev, 1);
962 intel_finish_page_flip(dev, 1); 1061 intel_finish_page_flip(dev, 1);
1062 }
963 } 1063 }
964 1064
965 if ((pipea_stats & PIPE_LEGACY_BLC_EVENT_STATUS) || 1065 if ((pipea_stats & PIPE_LEGACY_BLC_EVENT_STATUS) ||
@@ -1251,6 +1351,16 @@ void i915_hangcheck_elapsed(unsigned long data)
1251 &dev_priv->render_ring), 1351 &dev_priv->render_ring),
1252 i915_get_tail_request(dev)->seqno)) { 1352 i915_get_tail_request(dev)->seqno)) {
1253 dev_priv->hangcheck_count = 0; 1353 dev_priv->hangcheck_count = 0;
1354
1355 /* Issue a wake-up to catch stuck h/w. */
1356 if (dev_priv->render_ring.waiting_gem_seqno |
1357 dev_priv->bsd_ring.waiting_gem_seqno) {
1358 DRM_ERROR("Hangcheck timer elapsed... GPU idle, missed IRQ.\n");
1359 if (dev_priv->render_ring.waiting_gem_seqno)
1360 DRM_WAKEUP(&dev_priv->render_ring.irq_queue);
1361 if (dev_priv->bsd_ring.waiting_gem_seqno)
1362 DRM_WAKEUP(&dev_priv->bsd_ring.irq_queue);
1363 }
1254 return; 1364 return;
1255 } 1365 }
1256 1366
@@ -1318,12 +1428,17 @@ static int ironlake_irq_postinstall(struct drm_device *dev)
1318 I915_WRITE(DEIER, dev_priv->de_irq_enable_reg); 1428 I915_WRITE(DEIER, dev_priv->de_irq_enable_reg);
1319 (void) I915_READ(DEIER); 1429 (void) I915_READ(DEIER);
1320 1430
1321 /* user interrupt should be enabled, but masked initial */ 1431 /* Gen6 only needs render pipe_control now */
1432 if (IS_GEN6(dev))
1433 render_mask = GT_PIPE_NOTIFY;
1434
1322 dev_priv->gt_irq_mask_reg = ~render_mask; 1435 dev_priv->gt_irq_mask_reg = ~render_mask;
1323 dev_priv->gt_irq_enable_reg = render_mask; 1436 dev_priv->gt_irq_enable_reg = render_mask;
1324 1437
1325 I915_WRITE(GTIIR, I915_READ(GTIIR)); 1438 I915_WRITE(GTIIR, I915_READ(GTIIR));
1326 I915_WRITE(GTIMR, dev_priv->gt_irq_mask_reg); 1439 I915_WRITE(GTIMR, dev_priv->gt_irq_mask_reg);
1440 if (IS_GEN6(dev))
1441 I915_WRITE(GEN6_RENDER_IMR, ~GEN6_RENDER_PIPE_CONTROL_NOTIFY_INTERRUPT);
1327 I915_WRITE(GTIER, dev_priv->gt_irq_enable_reg); 1442 I915_WRITE(GTIER, dev_priv->gt_irq_enable_reg);
1328 (void) I915_READ(GTIER); 1443 (void) I915_READ(GTIER);
1329 1444
diff --git a/drivers/gpu/drm/i915/i915_opregion.c b/drivers/gpu/drm/i915/i915_opregion.c
index d1bf92b99788..ea5d3fea4b61 100644
--- a/drivers/gpu/drm/i915/i915_opregion.c
+++ b/drivers/gpu/drm/i915/i915_opregion.c
@@ -114,10 +114,6 @@ struct opregion_asle {
114#define ASLE_REQ_MSK 0xf 114#define ASLE_REQ_MSK 0xf
115 115
116/* response bits of ASLE irq request */ 116/* response bits of ASLE irq request */
117#define ASLE_ALS_ILLUM_FAIL (2<<10)
118#define ASLE_BACKLIGHT_FAIL (2<<12)
119#define ASLE_PFIT_FAIL (2<<14)
120#define ASLE_PWM_FREQ_FAIL (2<<16)
121#define ASLE_ALS_ILLUM_FAILED (1<<10) 117#define ASLE_ALS_ILLUM_FAILED (1<<10)
122#define ASLE_BACKLIGHT_FAILED (1<<12) 118#define ASLE_BACKLIGHT_FAILED (1<<12)
123#define ASLE_PFIT_FAILED (1<<14) 119#define ASLE_PFIT_FAILED (1<<14)
@@ -155,11 +151,11 @@ static u32 asle_set_backlight(struct drm_device *dev, u32 bclp)
155 u32 max_backlight, level, shift; 151 u32 max_backlight, level, shift;
156 152
157 if (!(bclp & ASLE_BCLP_VALID)) 153 if (!(bclp & ASLE_BCLP_VALID))
158 return ASLE_BACKLIGHT_FAIL; 154 return ASLE_BACKLIGHT_FAILED;
159 155
160 bclp &= ASLE_BCLP_MSK; 156 bclp &= ASLE_BCLP_MSK;
161 if (bclp < 0 || bclp > 255) 157 if (bclp < 0 || bclp > 255)
162 return ASLE_BACKLIGHT_FAIL; 158 return ASLE_BACKLIGHT_FAILED;
163 159
164 blc_pwm_ctl = I915_READ(BLC_PWM_CTL); 160 blc_pwm_ctl = I915_READ(BLC_PWM_CTL);
165 blc_pwm_ctl2 = I915_READ(BLC_PWM_CTL2); 161 blc_pwm_ctl2 = I915_READ(BLC_PWM_CTL2);
@@ -211,7 +207,7 @@ static u32 asle_set_pfit(struct drm_device *dev, u32 pfit)
211 /* Panel fitting is currently controlled by the X code, so this is a 207 /* Panel fitting is currently controlled by the X code, so this is a
212 noop until modesetting support works fully */ 208 noop until modesetting support works fully */
213 if (!(pfit & ASLE_PFIT_VALID)) 209 if (!(pfit & ASLE_PFIT_VALID))
214 return ASLE_PFIT_FAIL; 210 return ASLE_PFIT_FAILED;
215 return 0; 211 return 0;
216} 212}
217 213
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 281db6e5403a..d094e9129223 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -170,6 +170,7 @@
170#define MI_NO_WRITE_FLUSH (1 << 2) 170#define MI_NO_WRITE_FLUSH (1 << 2)
171#define MI_SCENE_COUNT (1 << 3) /* just increment scene count */ 171#define MI_SCENE_COUNT (1 << 3) /* just increment scene count */
172#define MI_END_SCENE (1 << 4) /* flush binner and incr scene count */ 172#define MI_END_SCENE (1 << 4) /* flush binner and incr scene count */
173#define MI_INVALIDATE_ISP (1 << 5) /* invalidate indirect state pointers */
173#define MI_BATCH_BUFFER_END MI_INSTR(0x0a, 0) 174#define MI_BATCH_BUFFER_END MI_INSTR(0x0a, 0)
174#define MI_REPORT_HEAD MI_INSTR(0x07, 0) 175#define MI_REPORT_HEAD MI_INSTR(0x07, 0)
175#define MI_OVERLAY_FLIP MI_INSTR(0x11,0) 176#define MI_OVERLAY_FLIP MI_INSTR(0x11,0)
@@ -180,6 +181,12 @@
180#define MI_DISPLAY_FLIP MI_INSTR(0x14, 2) 181#define MI_DISPLAY_FLIP MI_INSTR(0x14, 2)
181#define MI_DISPLAY_FLIP_I915 MI_INSTR(0x14, 1) 182#define MI_DISPLAY_FLIP_I915 MI_INSTR(0x14, 1)
182#define MI_DISPLAY_FLIP_PLANE(n) ((n) << 20) 183#define MI_DISPLAY_FLIP_PLANE(n) ((n) << 20)
184#define MI_SET_CONTEXT MI_INSTR(0x18, 0)
185#define MI_MM_SPACE_GTT (1<<8)
186#define MI_MM_SPACE_PHYSICAL (0<<8)
187#define MI_SAVE_EXT_STATE_EN (1<<3)
188#define MI_RESTORE_EXT_STATE_EN (1<<2)
189#define MI_RESTORE_INHIBIT (1<<0)
183#define MI_STORE_DWORD_IMM MI_INSTR(0x20, 1) 190#define MI_STORE_DWORD_IMM MI_INSTR(0x20, 1)
184#define MI_MEM_VIRTUAL (1 << 22) /* 965+ only */ 191#define MI_MEM_VIRTUAL (1 << 22) /* 965+ only */
185#define MI_STORE_DWORD_INDEX MI_INSTR(0x21, 1) 192#define MI_STORE_DWORD_INDEX MI_INSTR(0x21, 1)
@@ -312,6 +319,7 @@
312 319
313#define MI_MODE 0x0209c 320#define MI_MODE 0x0209c
314# define VS_TIMER_DISPATCH (1 << 6) 321# define VS_TIMER_DISPATCH (1 << 6)
322# define MI_FLUSH_ENABLE (1 << 11)
315 323
316#define SCPD0 0x0209c /* 915+ only */ 324#define SCPD0 0x0209c /* 915+ only */
317#define IER 0x020a0 325#define IER 0x020a0
@@ -1100,6 +1108,11 @@
1100#define PEG_BAND_GAP_DATA 0x14d68 1108#define PEG_BAND_GAP_DATA 0x14d68
1101 1109
1102/* 1110/*
1111 * Logical Context regs
1112 */
1113#define CCID 0x2180
1114#define CCID_EN (1<<0)
1115/*
1103 * Overlay regs 1116 * Overlay regs
1104 */ 1117 */
1105 1118
@@ -2069,6 +2082,7 @@
2069#define PIPE_DITHER_TYPE_ST01 (1 << 2) 2082#define PIPE_DITHER_TYPE_ST01 (1 << 2)
2070/* Pipe A */ 2083/* Pipe A */
2071#define PIPEADSL 0x70000 2084#define PIPEADSL 0x70000
2085#define DSL_LINEMASK 0x00000fff
2072#define PIPEACONF 0x70008 2086#define PIPEACONF 0x70008
2073#define PIPEACONF_ENABLE (1<<31) 2087#define PIPEACONF_ENABLE (1<<31)
2074#define PIPEACONF_DISABLE 0 2088#define PIPEACONF_DISABLE 0
@@ -2928,6 +2942,7 @@
2928#define TRANS_DP_VSYNC_ACTIVE_LOW 0 2942#define TRANS_DP_VSYNC_ACTIVE_LOW 0
2929#define TRANS_DP_HSYNC_ACTIVE_HIGH (1<<3) 2943#define TRANS_DP_HSYNC_ACTIVE_HIGH (1<<3)
2930#define TRANS_DP_HSYNC_ACTIVE_LOW 0 2944#define TRANS_DP_HSYNC_ACTIVE_LOW 0
2945#define TRANS_DP_SYNC_MASK (3<<3)
2931 2946
2932/* SNB eDP training params */ 2947/* SNB eDP training params */
2933/* SNB A-stepping */ 2948/* SNB A-stepping */
diff --git a/drivers/gpu/drm/i915/i915_suspend.c b/drivers/gpu/drm/i915/i915_suspend.c
index 6e2025274db5..2c6b98f2440e 100644
--- a/drivers/gpu/drm/i915/i915_suspend.c
+++ b/drivers/gpu/drm/i915/i915_suspend.c
@@ -34,7 +34,7 @@ static bool i915_pipe_enabled(struct drm_device *dev, enum pipe pipe)
34 struct drm_i915_private *dev_priv = dev->dev_private; 34 struct drm_i915_private *dev_priv = dev->dev_private;
35 u32 dpll_reg; 35 u32 dpll_reg;
36 36
37 if (IS_IRONLAKE(dev)) { 37 if (HAS_PCH_SPLIT(dev)) {
38 dpll_reg = (pipe == PIPE_A) ? PCH_DPLL_A: PCH_DPLL_B; 38 dpll_reg = (pipe == PIPE_A) ? PCH_DPLL_A: PCH_DPLL_B;
39 } else { 39 } else {
40 dpll_reg = (pipe == PIPE_A) ? DPLL_A: DPLL_B; 40 dpll_reg = (pipe == PIPE_A) ? DPLL_A: DPLL_B;
@@ -53,7 +53,7 @@ static void i915_save_palette(struct drm_device *dev, enum pipe pipe)
53 if (!i915_pipe_enabled(dev, pipe)) 53 if (!i915_pipe_enabled(dev, pipe))
54 return; 54 return;
55 55
56 if (IS_IRONLAKE(dev)) 56 if (HAS_PCH_SPLIT(dev))
57 reg = (pipe == PIPE_A) ? LGC_PALETTE_A : LGC_PALETTE_B; 57 reg = (pipe == PIPE_A) ? LGC_PALETTE_A : LGC_PALETTE_B;
58 58
59 if (pipe == PIPE_A) 59 if (pipe == PIPE_A)
@@ -75,7 +75,7 @@ static void i915_restore_palette(struct drm_device *dev, enum pipe pipe)
75 if (!i915_pipe_enabled(dev, pipe)) 75 if (!i915_pipe_enabled(dev, pipe))
76 return; 76 return;
77 77
78 if (IS_IRONLAKE(dev)) 78 if (HAS_PCH_SPLIT(dev))
79 reg = (pipe == PIPE_A) ? LGC_PALETTE_A : LGC_PALETTE_B; 79 reg = (pipe == PIPE_A) ? LGC_PALETTE_A : LGC_PALETTE_B;
80 80
81 if (pipe == PIPE_A) 81 if (pipe == PIPE_A)
@@ -239,7 +239,7 @@ static void i915_save_modeset_reg(struct drm_device *dev)
239 if (drm_core_check_feature(dev, DRIVER_MODESET)) 239 if (drm_core_check_feature(dev, DRIVER_MODESET))
240 return; 240 return;
241 241
242 if (IS_IRONLAKE(dev)) { 242 if (HAS_PCH_SPLIT(dev)) {
243 dev_priv->savePCH_DREF_CONTROL = I915_READ(PCH_DREF_CONTROL); 243 dev_priv->savePCH_DREF_CONTROL = I915_READ(PCH_DREF_CONTROL);
244 dev_priv->saveDISP_ARB_CTL = I915_READ(DISP_ARB_CTL); 244 dev_priv->saveDISP_ARB_CTL = I915_READ(DISP_ARB_CTL);
245 } 245 }
@@ -247,7 +247,7 @@ static void i915_save_modeset_reg(struct drm_device *dev)
247 /* Pipe & plane A info */ 247 /* Pipe & plane A info */
248 dev_priv->savePIPEACONF = I915_READ(PIPEACONF); 248 dev_priv->savePIPEACONF = I915_READ(PIPEACONF);
249 dev_priv->savePIPEASRC = I915_READ(PIPEASRC); 249 dev_priv->savePIPEASRC = I915_READ(PIPEASRC);
250 if (IS_IRONLAKE(dev)) { 250 if (HAS_PCH_SPLIT(dev)) {
251 dev_priv->saveFPA0 = I915_READ(PCH_FPA0); 251 dev_priv->saveFPA0 = I915_READ(PCH_FPA0);
252 dev_priv->saveFPA1 = I915_READ(PCH_FPA1); 252 dev_priv->saveFPA1 = I915_READ(PCH_FPA1);
253 dev_priv->saveDPLL_A = I915_READ(PCH_DPLL_A); 253 dev_priv->saveDPLL_A = I915_READ(PCH_DPLL_A);
@@ -256,7 +256,7 @@ static void i915_save_modeset_reg(struct drm_device *dev)
256 dev_priv->saveFPA1 = I915_READ(FPA1); 256 dev_priv->saveFPA1 = I915_READ(FPA1);
257 dev_priv->saveDPLL_A = I915_READ(DPLL_A); 257 dev_priv->saveDPLL_A = I915_READ(DPLL_A);
258 } 258 }
259 if (IS_I965G(dev) && !IS_IRONLAKE(dev)) 259 if (IS_I965G(dev) && !HAS_PCH_SPLIT(dev))
260 dev_priv->saveDPLL_A_MD = I915_READ(DPLL_A_MD); 260 dev_priv->saveDPLL_A_MD = I915_READ(DPLL_A_MD);
261 dev_priv->saveHTOTAL_A = I915_READ(HTOTAL_A); 261 dev_priv->saveHTOTAL_A = I915_READ(HTOTAL_A);
262 dev_priv->saveHBLANK_A = I915_READ(HBLANK_A); 262 dev_priv->saveHBLANK_A = I915_READ(HBLANK_A);
@@ -264,10 +264,10 @@ static void i915_save_modeset_reg(struct drm_device *dev)
264 dev_priv->saveVTOTAL_A = I915_READ(VTOTAL_A); 264 dev_priv->saveVTOTAL_A = I915_READ(VTOTAL_A);
265 dev_priv->saveVBLANK_A = I915_READ(VBLANK_A); 265 dev_priv->saveVBLANK_A = I915_READ(VBLANK_A);
266 dev_priv->saveVSYNC_A = I915_READ(VSYNC_A); 266 dev_priv->saveVSYNC_A = I915_READ(VSYNC_A);
267 if (!IS_IRONLAKE(dev)) 267 if (!HAS_PCH_SPLIT(dev))
268 dev_priv->saveBCLRPAT_A = I915_READ(BCLRPAT_A); 268 dev_priv->saveBCLRPAT_A = I915_READ(BCLRPAT_A);
269 269
270 if (IS_IRONLAKE(dev)) { 270 if (HAS_PCH_SPLIT(dev)) {
271 dev_priv->savePIPEA_DATA_M1 = I915_READ(PIPEA_DATA_M1); 271 dev_priv->savePIPEA_DATA_M1 = I915_READ(PIPEA_DATA_M1);
272 dev_priv->savePIPEA_DATA_N1 = I915_READ(PIPEA_DATA_N1); 272 dev_priv->savePIPEA_DATA_N1 = I915_READ(PIPEA_DATA_N1);
273 dev_priv->savePIPEA_LINK_M1 = I915_READ(PIPEA_LINK_M1); 273 dev_priv->savePIPEA_LINK_M1 = I915_READ(PIPEA_LINK_M1);
@@ -304,7 +304,7 @@ static void i915_save_modeset_reg(struct drm_device *dev)
304 /* Pipe & plane B info */ 304 /* Pipe & plane B info */
305 dev_priv->savePIPEBCONF = I915_READ(PIPEBCONF); 305 dev_priv->savePIPEBCONF = I915_READ(PIPEBCONF);
306 dev_priv->savePIPEBSRC = I915_READ(PIPEBSRC); 306 dev_priv->savePIPEBSRC = I915_READ(PIPEBSRC);
307 if (IS_IRONLAKE(dev)) { 307 if (HAS_PCH_SPLIT(dev)) {
308 dev_priv->saveFPB0 = I915_READ(PCH_FPB0); 308 dev_priv->saveFPB0 = I915_READ(PCH_FPB0);
309 dev_priv->saveFPB1 = I915_READ(PCH_FPB1); 309 dev_priv->saveFPB1 = I915_READ(PCH_FPB1);
310 dev_priv->saveDPLL_B = I915_READ(PCH_DPLL_B); 310 dev_priv->saveDPLL_B = I915_READ(PCH_DPLL_B);
@@ -313,7 +313,7 @@ static void i915_save_modeset_reg(struct drm_device *dev)
313 dev_priv->saveFPB1 = I915_READ(FPB1); 313 dev_priv->saveFPB1 = I915_READ(FPB1);
314 dev_priv->saveDPLL_B = I915_READ(DPLL_B); 314 dev_priv->saveDPLL_B = I915_READ(DPLL_B);
315 } 315 }
316 if (IS_I965G(dev) && !IS_IRONLAKE(dev)) 316 if (IS_I965G(dev) && !HAS_PCH_SPLIT(dev))
317 dev_priv->saveDPLL_B_MD = I915_READ(DPLL_B_MD); 317 dev_priv->saveDPLL_B_MD = I915_READ(DPLL_B_MD);
318 dev_priv->saveHTOTAL_B = I915_READ(HTOTAL_B); 318 dev_priv->saveHTOTAL_B = I915_READ(HTOTAL_B);
319 dev_priv->saveHBLANK_B = I915_READ(HBLANK_B); 319 dev_priv->saveHBLANK_B = I915_READ(HBLANK_B);
@@ -321,10 +321,10 @@ static void i915_save_modeset_reg(struct drm_device *dev)
321 dev_priv->saveVTOTAL_B = I915_READ(VTOTAL_B); 321 dev_priv->saveVTOTAL_B = I915_READ(VTOTAL_B);
322 dev_priv->saveVBLANK_B = I915_READ(VBLANK_B); 322 dev_priv->saveVBLANK_B = I915_READ(VBLANK_B);
323 dev_priv->saveVSYNC_B = I915_READ(VSYNC_B); 323 dev_priv->saveVSYNC_B = I915_READ(VSYNC_B);
324 if (!IS_IRONLAKE(dev)) 324 if (!HAS_PCH_SPLIT(dev))
325 dev_priv->saveBCLRPAT_B = I915_READ(BCLRPAT_B); 325 dev_priv->saveBCLRPAT_B = I915_READ(BCLRPAT_B);
326 326
327 if (IS_IRONLAKE(dev)) { 327 if (HAS_PCH_SPLIT(dev)) {
328 dev_priv->savePIPEB_DATA_M1 = I915_READ(PIPEB_DATA_M1); 328 dev_priv->savePIPEB_DATA_M1 = I915_READ(PIPEB_DATA_M1);
329 dev_priv->savePIPEB_DATA_N1 = I915_READ(PIPEB_DATA_N1); 329 dev_priv->savePIPEB_DATA_N1 = I915_READ(PIPEB_DATA_N1);
330 dev_priv->savePIPEB_LINK_M1 = I915_READ(PIPEB_LINK_M1); 330 dev_priv->savePIPEB_LINK_M1 = I915_READ(PIPEB_LINK_M1);
@@ -369,7 +369,7 @@ static void i915_restore_modeset_reg(struct drm_device *dev)
369 if (drm_core_check_feature(dev, DRIVER_MODESET)) 369 if (drm_core_check_feature(dev, DRIVER_MODESET))
370 return; 370 return;
371 371
372 if (IS_IRONLAKE(dev)) { 372 if (HAS_PCH_SPLIT(dev)) {
373 dpll_a_reg = PCH_DPLL_A; 373 dpll_a_reg = PCH_DPLL_A;
374 dpll_b_reg = PCH_DPLL_B; 374 dpll_b_reg = PCH_DPLL_B;
375 fpa0_reg = PCH_FPA0; 375 fpa0_reg = PCH_FPA0;
@@ -385,7 +385,7 @@ static void i915_restore_modeset_reg(struct drm_device *dev)
385 fpb1_reg = FPB1; 385 fpb1_reg = FPB1;
386 } 386 }
387 387
388 if (IS_IRONLAKE(dev)) { 388 if (HAS_PCH_SPLIT(dev)) {
389 I915_WRITE(PCH_DREF_CONTROL, dev_priv->savePCH_DREF_CONTROL); 389 I915_WRITE(PCH_DREF_CONTROL, dev_priv->savePCH_DREF_CONTROL);
390 I915_WRITE(DISP_ARB_CTL, dev_priv->saveDISP_ARB_CTL); 390 I915_WRITE(DISP_ARB_CTL, dev_priv->saveDISP_ARB_CTL);
391 } 391 }
@@ -395,16 +395,20 @@ static void i915_restore_modeset_reg(struct drm_device *dev)
395 if (dev_priv->saveDPLL_A & DPLL_VCO_ENABLE) { 395 if (dev_priv->saveDPLL_A & DPLL_VCO_ENABLE) {
396 I915_WRITE(dpll_a_reg, dev_priv->saveDPLL_A & 396 I915_WRITE(dpll_a_reg, dev_priv->saveDPLL_A &
397 ~DPLL_VCO_ENABLE); 397 ~DPLL_VCO_ENABLE);
398 DRM_UDELAY(150); 398 POSTING_READ(dpll_a_reg);
399 udelay(150);
399 } 400 }
400 I915_WRITE(fpa0_reg, dev_priv->saveFPA0); 401 I915_WRITE(fpa0_reg, dev_priv->saveFPA0);
401 I915_WRITE(fpa1_reg, dev_priv->saveFPA1); 402 I915_WRITE(fpa1_reg, dev_priv->saveFPA1);
402 /* Actually enable it */ 403 /* Actually enable it */
403 I915_WRITE(dpll_a_reg, dev_priv->saveDPLL_A); 404 I915_WRITE(dpll_a_reg, dev_priv->saveDPLL_A);
404 DRM_UDELAY(150); 405 POSTING_READ(dpll_a_reg);
405 if (IS_I965G(dev) && !IS_IRONLAKE(dev)) 406 udelay(150);
407 if (IS_I965G(dev) && !HAS_PCH_SPLIT(dev)) {
406 I915_WRITE(DPLL_A_MD, dev_priv->saveDPLL_A_MD); 408 I915_WRITE(DPLL_A_MD, dev_priv->saveDPLL_A_MD);
407 DRM_UDELAY(150); 409 POSTING_READ(DPLL_A_MD);
410 }
411 udelay(150);
408 412
409 /* Restore mode */ 413 /* Restore mode */
410 I915_WRITE(HTOTAL_A, dev_priv->saveHTOTAL_A); 414 I915_WRITE(HTOTAL_A, dev_priv->saveHTOTAL_A);
@@ -413,10 +417,10 @@ static void i915_restore_modeset_reg(struct drm_device *dev)
413 I915_WRITE(VTOTAL_A, dev_priv->saveVTOTAL_A); 417 I915_WRITE(VTOTAL_A, dev_priv->saveVTOTAL_A);
414 I915_WRITE(VBLANK_A, dev_priv->saveVBLANK_A); 418 I915_WRITE(VBLANK_A, dev_priv->saveVBLANK_A);
415 I915_WRITE(VSYNC_A, dev_priv->saveVSYNC_A); 419 I915_WRITE(VSYNC_A, dev_priv->saveVSYNC_A);
416 if (!IS_IRONLAKE(dev)) 420 if (!HAS_PCH_SPLIT(dev))
417 I915_WRITE(BCLRPAT_A, dev_priv->saveBCLRPAT_A); 421 I915_WRITE(BCLRPAT_A, dev_priv->saveBCLRPAT_A);
418 422
419 if (IS_IRONLAKE(dev)) { 423 if (HAS_PCH_SPLIT(dev)) {
420 I915_WRITE(PIPEA_DATA_M1, dev_priv->savePIPEA_DATA_M1); 424 I915_WRITE(PIPEA_DATA_M1, dev_priv->savePIPEA_DATA_M1);
421 I915_WRITE(PIPEA_DATA_N1, dev_priv->savePIPEA_DATA_N1); 425 I915_WRITE(PIPEA_DATA_N1, dev_priv->savePIPEA_DATA_N1);
422 I915_WRITE(PIPEA_LINK_M1, dev_priv->savePIPEA_LINK_M1); 426 I915_WRITE(PIPEA_LINK_M1, dev_priv->savePIPEA_LINK_M1);
@@ -460,16 +464,20 @@ static void i915_restore_modeset_reg(struct drm_device *dev)
460 if (dev_priv->saveDPLL_B & DPLL_VCO_ENABLE) { 464 if (dev_priv->saveDPLL_B & DPLL_VCO_ENABLE) {
461 I915_WRITE(dpll_b_reg, dev_priv->saveDPLL_B & 465 I915_WRITE(dpll_b_reg, dev_priv->saveDPLL_B &
462 ~DPLL_VCO_ENABLE); 466 ~DPLL_VCO_ENABLE);
463 DRM_UDELAY(150); 467 POSTING_READ(dpll_b_reg);
468 udelay(150);
464 } 469 }
465 I915_WRITE(fpb0_reg, dev_priv->saveFPB0); 470 I915_WRITE(fpb0_reg, dev_priv->saveFPB0);
466 I915_WRITE(fpb1_reg, dev_priv->saveFPB1); 471 I915_WRITE(fpb1_reg, dev_priv->saveFPB1);
467 /* Actually enable it */ 472 /* Actually enable it */
468 I915_WRITE(dpll_b_reg, dev_priv->saveDPLL_B); 473 I915_WRITE(dpll_b_reg, dev_priv->saveDPLL_B);
469 DRM_UDELAY(150); 474 POSTING_READ(dpll_b_reg);
470 if (IS_I965G(dev) && !IS_IRONLAKE(dev)) 475 udelay(150);
476 if (IS_I965G(dev) && !HAS_PCH_SPLIT(dev)) {
471 I915_WRITE(DPLL_B_MD, dev_priv->saveDPLL_B_MD); 477 I915_WRITE(DPLL_B_MD, dev_priv->saveDPLL_B_MD);
472 DRM_UDELAY(150); 478 POSTING_READ(DPLL_B_MD);
479 }
480 udelay(150);
473 481
474 /* Restore mode */ 482 /* Restore mode */
475 I915_WRITE(HTOTAL_B, dev_priv->saveHTOTAL_B); 483 I915_WRITE(HTOTAL_B, dev_priv->saveHTOTAL_B);
@@ -478,10 +486,10 @@ static void i915_restore_modeset_reg(struct drm_device *dev)
478 I915_WRITE(VTOTAL_B, dev_priv->saveVTOTAL_B); 486 I915_WRITE(VTOTAL_B, dev_priv->saveVTOTAL_B);
479 I915_WRITE(VBLANK_B, dev_priv->saveVBLANK_B); 487 I915_WRITE(VBLANK_B, dev_priv->saveVBLANK_B);
480 I915_WRITE(VSYNC_B, dev_priv->saveVSYNC_B); 488 I915_WRITE(VSYNC_B, dev_priv->saveVSYNC_B);
481 if (!IS_IRONLAKE(dev)) 489 if (!HAS_PCH_SPLIT(dev))
482 I915_WRITE(BCLRPAT_B, dev_priv->saveBCLRPAT_B); 490 I915_WRITE(BCLRPAT_B, dev_priv->saveBCLRPAT_B);
483 491
484 if (IS_IRONLAKE(dev)) { 492 if (HAS_PCH_SPLIT(dev)) {
485 I915_WRITE(PIPEB_DATA_M1, dev_priv->savePIPEB_DATA_M1); 493 I915_WRITE(PIPEB_DATA_M1, dev_priv->savePIPEB_DATA_M1);
486 I915_WRITE(PIPEB_DATA_N1, dev_priv->savePIPEB_DATA_N1); 494 I915_WRITE(PIPEB_DATA_N1, dev_priv->savePIPEB_DATA_N1);
487 I915_WRITE(PIPEB_LINK_M1, dev_priv->savePIPEB_LINK_M1); 495 I915_WRITE(PIPEB_LINK_M1, dev_priv->savePIPEB_LINK_M1);
@@ -546,14 +554,14 @@ void i915_save_display(struct drm_device *dev)
546 dev_priv->saveCURSIZE = I915_READ(CURSIZE); 554 dev_priv->saveCURSIZE = I915_READ(CURSIZE);
547 555
548 /* CRT state */ 556 /* CRT state */
549 if (IS_IRONLAKE(dev)) { 557 if (HAS_PCH_SPLIT(dev)) {
550 dev_priv->saveADPA = I915_READ(PCH_ADPA); 558 dev_priv->saveADPA = I915_READ(PCH_ADPA);
551 } else { 559 } else {
552 dev_priv->saveADPA = I915_READ(ADPA); 560 dev_priv->saveADPA = I915_READ(ADPA);
553 } 561 }
554 562
555 /* LVDS state */ 563 /* LVDS state */
556 if (IS_IRONLAKE(dev)) { 564 if (HAS_PCH_SPLIT(dev)) {
557 dev_priv->savePP_CONTROL = I915_READ(PCH_PP_CONTROL); 565 dev_priv->savePP_CONTROL = I915_READ(PCH_PP_CONTROL);
558 dev_priv->saveBLC_PWM_CTL = I915_READ(BLC_PWM_PCH_CTL1); 566 dev_priv->saveBLC_PWM_CTL = I915_READ(BLC_PWM_PCH_CTL1);
559 dev_priv->saveBLC_PWM_CTL2 = I915_READ(BLC_PWM_PCH_CTL2); 567 dev_priv->saveBLC_PWM_CTL2 = I915_READ(BLC_PWM_PCH_CTL2);
@@ -571,10 +579,10 @@ void i915_save_display(struct drm_device *dev)
571 dev_priv->saveLVDS = I915_READ(LVDS); 579 dev_priv->saveLVDS = I915_READ(LVDS);
572 } 580 }
573 581
574 if (!IS_I830(dev) && !IS_845G(dev) && !IS_IRONLAKE(dev)) 582 if (!IS_I830(dev) && !IS_845G(dev) && !HAS_PCH_SPLIT(dev))
575 dev_priv->savePFIT_CONTROL = I915_READ(PFIT_CONTROL); 583 dev_priv->savePFIT_CONTROL = I915_READ(PFIT_CONTROL);
576 584
577 if (IS_IRONLAKE(dev)) { 585 if (HAS_PCH_SPLIT(dev)) {
578 dev_priv->savePP_ON_DELAYS = I915_READ(PCH_PP_ON_DELAYS); 586 dev_priv->savePP_ON_DELAYS = I915_READ(PCH_PP_ON_DELAYS);
579 dev_priv->savePP_OFF_DELAYS = I915_READ(PCH_PP_OFF_DELAYS); 587 dev_priv->savePP_OFF_DELAYS = I915_READ(PCH_PP_OFF_DELAYS);
580 dev_priv->savePP_DIVISOR = I915_READ(PCH_PP_DIVISOR); 588 dev_priv->savePP_DIVISOR = I915_READ(PCH_PP_DIVISOR);
@@ -602,7 +610,7 @@ void i915_save_display(struct drm_device *dev)
602 610
603 /* Only save FBC state on the platform that supports FBC */ 611 /* Only save FBC state on the platform that supports FBC */
604 if (I915_HAS_FBC(dev)) { 612 if (I915_HAS_FBC(dev)) {
605 if (IS_IRONLAKE_M(dev)) { 613 if (HAS_PCH_SPLIT(dev)) {
606 dev_priv->saveDPFC_CB_BASE = I915_READ(ILK_DPFC_CB_BASE); 614 dev_priv->saveDPFC_CB_BASE = I915_READ(ILK_DPFC_CB_BASE);
607 } else if (IS_GM45(dev)) { 615 } else if (IS_GM45(dev)) {
608 dev_priv->saveDPFC_CB_BASE = I915_READ(DPFC_CB_BASE); 616 dev_priv->saveDPFC_CB_BASE = I915_READ(DPFC_CB_BASE);
@@ -618,7 +626,7 @@ void i915_save_display(struct drm_device *dev)
618 dev_priv->saveVGA0 = I915_READ(VGA0); 626 dev_priv->saveVGA0 = I915_READ(VGA0);
619 dev_priv->saveVGA1 = I915_READ(VGA1); 627 dev_priv->saveVGA1 = I915_READ(VGA1);
620 dev_priv->saveVGA_PD = I915_READ(VGA_PD); 628 dev_priv->saveVGA_PD = I915_READ(VGA_PD);
621 if (IS_IRONLAKE(dev)) 629 if (HAS_PCH_SPLIT(dev))
622 dev_priv->saveVGACNTRL = I915_READ(CPU_VGACNTRL); 630 dev_priv->saveVGACNTRL = I915_READ(CPU_VGACNTRL);
623 else 631 else
624 dev_priv->saveVGACNTRL = I915_READ(VGACNTRL); 632 dev_priv->saveVGACNTRL = I915_READ(VGACNTRL);
@@ -660,24 +668,24 @@ void i915_restore_display(struct drm_device *dev)
660 I915_WRITE(CURSIZE, dev_priv->saveCURSIZE); 668 I915_WRITE(CURSIZE, dev_priv->saveCURSIZE);
661 669
662 /* CRT state */ 670 /* CRT state */
663 if (IS_IRONLAKE(dev)) 671 if (HAS_PCH_SPLIT(dev))
664 I915_WRITE(PCH_ADPA, dev_priv->saveADPA); 672 I915_WRITE(PCH_ADPA, dev_priv->saveADPA);
665 else 673 else
666 I915_WRITE(ADPA, dev_priv->saveADPA); 674 I915_WRITE(ADPA, dev_priv->saveADPA);
667 675
668 /* LVDS state */ 676 /* LVDS state */
669 if (IS_I965G(dev) && !IS_IRONLAKE(dev)) 677 if (IS_I965G(dev) && !HAS_PCH_SPLIT(dev))
670 I915_WRITE(BLC_PWM_CTL2, dev_priv->saveBLC_PWM_CTL2); 678 I915_WRITE(BLC_PWM_CTL2, dev_priv->saveBLC_PWM_CTL2);
671 679
672 if (IS_IRONLAKE(dev)) { 680 if (HAS_PCH_SPLIT(dev)) {
673 I915_WRITE(PCH_LVDS, dev_priv->saveLVDS); 681 I915_WRITE(PCH_LVDS, dev_priv->saveLVDS);
674 } else if (IS_MOBILE(dev) && !IS_I830(dev)) 682 } else if (IS_MOBILE(dev) && !IS_I830(dev))
675 I915_WRITE(LVDS, dev_priv->saveLVDS); 683 I915_WRITE(LVDS, dev_priv->saveLVDS);
676 684
677 if (!IS_I830(dev) && !IS_845G(dev) && !IS_IRONLAKE(dev)) 685 if (!IS_I830(dev) && !IS_845G(dev) && !HAS_PCH_SPLIT(dev))
678 I915_WRITE(PFIT_CONTROL, dev_priv->savePFIT_CONTROL); 686 I915_WRITE(PFIT_CONTROL, dev_priv->savePFIT_CONTROL);
679 687
680 if (IS_IRONLAKE(dev)) { 688 if (HAS_PCH_SPLIT(dev)) {
681 I915_WRITE(BLC_PWM_PCH_CTL1, dev_priv->saveBLC_PWM_CTL); 689 I915_WRITE(BLC_PWM_PCH_CTL1, dev_priv->saveBLC_PWM_CTL);
682 I915_WRITE(BLC_PWM_PCH_CTL2, dev_priv->saveBLC_PWM_CTL2); 690 I915_WRITE(BLC_PWM_PCH_CTL2, dev_priv->saveBLC_PWM_CTL2);
683 I915_WRITE(BLC_PWM_CPU_CTL, dev_priv->saveBLC_CPU_PWM_CTL); 691 I915_WRITE(BLC_PWM_CPU_CTL, dev_priv->saveBLC_CPU_PWM_CTL);
@@ -708,7 +716,7 @@ void i915_restore_display(struct drm_device *dev)
708 716
709 /* only restore FBC info on the platform that supports FBC*/ 717 /* only restore FBC info on the platform that supports FBC*/
710 if (I915_HAS_FBC(dev)) { 718 if (I915_HAS_FBC(dev)) {
711 if (IS_IRONLAKE_M(dev)) { 719 if (HAS_PCH_SPLIT(dev)) {
712 ironlake_disable_fbc(dev); 720 ironlake_disable_fbc(dev);
713 I915_WRITE(ILK_DPFC_CB_BASE, dev_priv->saveDPFC_CB_BASE); 721 I915_WRITE(ILK_DPFC_CB_BASE, dev_priv->saveDPFC_CB_BASE);
714 } else if (IS_GM45(dev)) { 722 } else if (IS_GM45(dev)) {
@@ -723,14 +731,15 @@ void i915_restore_display(struct drm_device *dev)
723 } 731 }
724 } 732 }
725 /* VGA state */ 733 /* VGA state */
726 if (IS_IRONLAKE(dev)) 734 if (HAS_PCH_SPLIT(dev))
727 I915_WRITE(CPU_VGACNTRL, dev_priv->saveVGACNTRL); 735 I915_WRITE(CPU_VGACNTRL, dev_priv->saveVGACNTRL);
728 else 736 else
729 I915_WRITE(VGACNTRL, dev_priv->saveVGACNTRL); 737 I915_WRITE(VGACNTRL, dev_priv->saveVGACNTRL);
730 I915_WRITE(VGA0, dev_priv->saveVGA0); 738 I915_WRITE(VGA0, dev_priv->saveVGA0);
731 I915_WRITE(VGA1, dev_priv->saveVGA1); 739 I915_WRITE(VGA1, dev_priv->saveVGA1);
732 I915_WRITE(VGA_PD, dev_priv->saveVGA_PD); 740 I915_WRITE(VGA_PD, dev_priv->saveVGA_PD);
733 DRM_UDELAY(150); 741 POSTING_READ(VGA_PD);
742 udelay(150);
734 743
735 i915_restore_vga(dev); 744 i915_restore_vga(dev);
736} 745}
@@ -748,7 +757,7 @@ int i915_save_state(struct drm_device *dev)
748 i915_save_display(dev); 757 i915_save_display(dev);
749 758
750 /* Interrupt state */ 759 /* Interrupt state */
751 if (IS_IRONLAKE(dev)) { 760 if (HAS_PCH_SPLIT(dev)) {
752 dev_priv->saveDEIER = I915_READ(DEIER); 761 dev_priv->saveDEIER = I915_READ(DEIER);
753 dev_priv->saveDEIMR = I915_READ(DEIMR); 762 dev_priv->saveDEIMR = I915_READ(DEIMR);
754 dev_priv->saveGTIER = I915_READ(GTIER); 763 dev_priv->saveGTIER = I915_READ(GTIER);
@@ -762,7 +771,7 @@ int i915_save_state(struct drm_device *dev)
762 dev_priv->saveIMR = I915_READ(IMR); 771 dev_priv->saveIMR = I915_READ(IMR);
763 } 772 }
764 773
765 if (IS_IRONLAKE_M(dev)) 774 if (HAS_PCH_SPLIT(dev))
766 ironlake_disable_drps(dev); 775 ironlake_disable_drps(dev);
767 776
768 /* Cache mode state */ 777 /* Cache mode state */
@@ -820,7 +829,7 @@ int i915_restore_state(struct drm_device *dev)
820 i915_restore_display(dev); 829 i915_restore_display(dev);
821 830
822 /* Interrupt state */ 831 /* Interrupt state */
823 if (IS_IRONLAKE(dev)) { 832 if (HAS_PCH_SPLIT(dev)) {
824 I915_WRITE(DEIER, dev_priv->saveDEIER); 833 I915_WRITE(DEIER, dev_priv->saveDEIER);
825 I915_WRITE(DEIMR, dev_priv->saveDEIMR); 834 I915_WRITE(DEIMR, dev_priv->saveDEIMR);
826 I915_WRITE(GTIER, dev_priv->saveGTIER); 835 I915_WRITE(GTIER, dev_priv->saveGTIER);
@@ -835,7 +844,7 @@ int i915_restore_state(struct drm_device *dev)
835 /* Clock gating state */ 844 /* Clock gating state */
836 intel_init_clock_gating(dev); 845 intel_init_clock_gating(dev);
837 846
838 if (IS_IRONLAKE_M(dev)) 847 if (HAS_PCH_SPLIT(dev))
839 ironlake_enable_drps(dev); 848 ironlake_enable_drps(dev);
840 849
841 /* Cache mode state */ 850 /* Cache mode state */
diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c
index ee0732b222a1..4b7735196cd5 100644
--- a/drivers/gpu/drm/i915/intel_crt.c
+++ b/drivers/gpu/drm/i915/intel_crt.c
@@ -160,19 +160,20 @@ static bool intel_ironlake_crt_detect_hotplug(struct drm_connector *connector)
160 struct drm_i915_private *dev_priv = dev->dev_private; 160 struct drm_i915_private *dev_priv = dev->dev_private;
161 u32 adpa, temp; 161 u32 adpa, temp;
162 bool ret; 162 bool ret;
163 bool turn_off_dac = false;
163 164
164 temp = adpa = I915_READ(PCH_ADPA); 165 temp = adpa = I915_READ(PCH_ADPA);
165 166
166 if (HAS_PCH_CPT(dev)) { 167 if (HAS_PCH_SPLIT(dev))
167 /* Disable DAC before force detect */ 168 turn_off_dac = true;
168 I915_WRITE(PCH_ADPA, adpa & ~ADPA_DAC_ENABLE); 169
169 (void)I915_READ(PCH_ADPA); 170 adpa &= ~ADPA_CRT_HOTPLUG_MASK;
170 } else { 171 if (turn_off_dac)
171 adpa &= ~ADPA_CRT_HOTPLUG_MASK; 172 adpa &= ~ADPA_DAC_ENABLE;
172 /* disable HPD first */ 173
173 I915_WRITE(PCH_ADPA, adpa); 174 /* disable HPD first */
174 (void)I915_READ(PCH_ADPA); 175 I915_WRITE(PCH_ADPA, adpa);
175 } 176 (void)I915_READ(PCH_ADPA);
176 177
177 adpa |= (ADPA_CRT_HOTPLUG_PERIOD_128 | 178 adpa |= (ADPA_CRT_HOTPLUG_PERIOD_128 |
178 ADPA_CRT_HOTPLUG_WARMUP_10MS | 179 ADPA_CRT_HOTPLUG_WARMUP_10MS |
@@ -185,10 +186,11 @@ static bool intel_ironlake_crt_detect_hotplug(struct drm_connector *connector)
185 DRM_DEBUG_KMS("pch crt adpa 0x%x", adpa); 186 DRM_DEBUG_KMS("pch crt adpa 0x%x", adpa);
186 I915_WRITE(PCH_ADPA, adpa); 187 I915_WRITE(PCH_ADPA, adpa);
187 188
188 while ((I915_READ(PCH_ADPA) & ADPA_CRT_HOTPLUG_FORCE_TRIGGER) != 0) 189 if (wait_for((I915_READ(PCH_ADPA) & ADPA_CRT_HOTPLUG_FORCE_TRIGGER) == 0,
189 ; 190 1000, 1))
191 DRM_ERROR("timed out waiting for FORCE_TRIGGER");
190 192
191 if (HAS_PCH_CPT(dev)) { 193 if (turn_off_dac) {
192 I915_WRITE(PCH_ADPA, temp); 194 I915_WRITE(PCH_ADPA, temp);
193 (void)I915_READ(PCH_ADPA); 195 (void)I915_READ(PCH_ADPA);
194 } 196 }
@@ -237,17 +239,13 @@ static bool intel_crt_detect_hotplug(struct drm_connector *connector)
237 hotplug_en |= CRT_HOTPLUG_FORCE_DETECT; 239 hotplug_en |= CRT_HOTPLUG_FORCE_DETECT;
238 240
239 for (i = 0; i < tries ; i++) { 241 for (i = 0; i < tries ; i++) {
240 unsigned long timeout;
241 /* turn on the FORCE_DETECT */ 242 /* turn on the FORCE_DETECT */
242 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en); 243 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
243 timeout = jiffies + msecs_to_jiffies(1000);
244 /* wait for FORCE_DETECT to go off */ 244 /* wait for FORCE_DETECT to go off */
245 do { 245 if (wait_for((I915_READ(PORT_HOTPLUG_EN) &
246 if (!(I915_READ(PORT_HOTPLUG_EN) & 246 CRT_HOTPLUG_FORCE_DETECT) == 0,
247 CRT_HOTPLUG_FORCE_DETECT)) 247 1000, 1))
248 break; 248 DRM_ERROR("timed out waiting for FORCE_DETECT to go off");
249 msleep(1);
250 } while (time_after(timeout, jiffies));
251 } 249 }
252 250
253 stat = I915_READ(PORT_HOTPLUG_STAT); 251 stat = I915_READ(PORT_HOTPLUG_STAT);
@@ -331,7 +329,7 @@ intel_crt_load_detect(struct drm_crtc *crtc, struct intel_encoder *intel_encoder
331 I915_WRITE(pipeconf_reg, pipeconf | PIPECONF_FORCE_BORDER); 329 I915_WRITE(pipeconf_reg, pipeconf | PIPECONF_FORCE_BORDER);
332 /* Wait for next Vblank to substitue 330 /* Wait for next Vblank to substitue
333 * border color for Color info */ 331 * border color for Color info */
334 intel_wait_for_vblank(dev); 332 intel_wait_for_vblank(dev, pipe);
335 st00 = I915_READ8(VGA_MSR_WRITE); 333 st00 = I915_READ8(VGA_MSR_WRITE);
336 status = ((st00 & (1 << 4)) != 0) ? 334 status = ((st00 & (1 << 4)) != 0) ?
337 connector_status_connected : 335 connector_status_connected :
@@ -508,17 +506,8 @@ static const struct drm_connector_helper_funcs intel_crt_connector_helper_funcs
508 .best_encoder = intel_attached_encoder, 506 .best_encoder = intel_attached_encoder,
509}; 507};
510 508
511static void intel_crt_enc_destroy(struct drm_encoder *encoder)
512{
513 struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
514
515 intel_i2c_destroy(intel_encoder->ddc_bus);
516 drm_encoder_cleanup(encoder);
517 kfree(intel_encoder);
518}
519
520static const struct drm_encoder_funcs intel_crt_enc_funcs = { 509static const struct drm_encoder_funcs intel_crt_enc_funcs = {
521 .destroy = intel_crt_enc_destroy, 510 .destroy = intel_encoder_destroy,
522}; 511};
523 512
524void intel_crt_init(struct drm_device *dev) 513void intel_crt_init(struct drm_device *dev)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 5ec10e02341b..40cc5da264a9 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -29,6 +29,7 @@
29#include <linux/i2c.h> 29#include <linux/i2c.h>
30#include <linux/kernel.h> 30#include <linux/kernel.h>
31#include <linux/slab.h> 31#include <linux/slab.h>
32#include <linux/vgaarb.h>
32#include "drmP.h" 33#include "drmP.h"
33#include "intel_drv.h" 34#include "intel_drv.h"
34#include "i915_drm.h" 35#include "i915_drm.h"
@@ -976,14 +977,70 @@ intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
976 return true; 977 return true;
977} 978}
978 979
979void 980/**
980intel_wait_for_vblank(struct drm_device *dev) 981 * intel_wait_for_vblank - wait for vblank on a given pipe
982 * @dev: drm device
983 * @pipe: pipe to wait for
984 *
985 * Wait for vblank to occur on a given pipe. Needed for various bits of
986 * mode setting code.
987 */
988void intel_wait_for_vblank(struct drm_device *dev, int pipe)
981{ 989{
982 /* Wait for 20ms, i.e. one cycle at 50hz. */ 990 struct drm_i915_private *dev_priv = dev->dev_private;
983 if (in_dbg_master()) 991 int pipestat_reg = (pipe == 0 ? PIPEASTAT : PIPEBSTAT);
984 mdelay(20); /* The kernel debugger cannot call msleep() */ 992
985 else 993 /* Clear existing vblank status. Note this will clear any other
986 msleep(20); 994 * sticky status fields as well.
995 *
996 * This races with i915_driver_irq_handler() with the result
997 * that either function could miss a vblank event. Here it is not
998 * fatal, as we will either wait upon the next vblank interrupt or
999 * timeout. Generally speaking intel_wait_for_vblank() is only
1000 * called during modeset at which time the GPU should be idle and
1001 * should *not* be performing page flips and thus not waiting on
1002 * vblanks...
1003 * Currently, the result of us stealing a vblank from the irq
1004 * handler is that a single frame will be skipped during swapbuffers.
1005 */
1006 I915_WRITE(pipestat_reg,
1007 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
1008
1009 /* Wait for vblank interrupt bit to set */
1010 if (wait_for((I915_READ(pipestat_reg) &
1011 PIPE_VBLANK_INTERRUPT_STATUS),
1012 50, 0))
1013 DRM_DEBUG_KMS("vblank wait timed out\n");
1014}
1015
1016/**
1017 * intel_wait_for_vblank_off - wait for vblank after disabling a pipe
1018 * @dev: drm device
1019 * @pipe: pipe to wait for
1020 *
1021 * After disabling a pipe, we can't wait for vblank in the usual way,
1022 * spinning on the vblank interrupt status bit, since we won't actually
1023 * see an interrupt when the pipe is disabled.
1024 *
1025 * So this function waits for the display line value to settle (it
1026 * usually ends up stopping at the start of the next frame).
1027 */
1028void intel_wait_for_vblank_off(struct drm_device *dev, int pipe)
1029{
1030 struct drm_i915_private *dev_priv = dev->dev_private;
1031 int pipedsl_reg = (pipe == 0 ? PIPEADSL : PIPEBDSL);
1032 unsigned long timeout = jiffies + msecs_to_jiffies(100);
1033 u32 last_line;
1034
1035 /* Wait for the display line to settle */
1036 do {
1037 last_line = I915_READ(pipedsl_reg) & DSL_LINEMASK;
1038 mdelay(5);
1039 } while (((I915_READ(pipedsl_reg) & DSL_LINEMASK) != last_line) &&
1040 time_after(timeout, jiffies));
1041
1042 if (time_after(jiffies, timeout))
1043 DRM_DEBUG_KMS("vblank wait timed out\n");
987} 1044}
988 1045
989/* Parameters have changed, update FBC info */ 1046/* Parameters have changed, update FBC info */
@@ -1037,7 +1094,6 @@ static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1037void i8xx_disable_fbc(struct drm_device *dev) 1094void i8xx_disable_fbc(struct drm_device *dev)
1038{ 1095{
1039 struct drm_i915_private *dev_priv = dev->dev_private; 1096 struct drm_i915_private *dev_priv = dev->dev_private;
1040 unsigned long timeout = jiffies + msecs_to_jiffies(1);
1041 u32 fbc_ctl; 1097 u32 fbc_ctl;
1042 1098
1043 if (!I915_HAS_FBC(dev)) 1099 if (!I915_HAS_FBC(dev))
@@ -1052,16 +1108,11 @@ void i8xx_disable_fbc(struct drm_device *dev)
1052 I915_WRITE(FBC_CONTROL, fbc_ctl); 1108 I915_WRITE(FBC_CONTROL, fbc_ctl);
1053 1109
1054 /* Wait for compressing bit to clear */ 1110 /* Wait for compressing bit to clear */
1055 while (I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) { 1111 if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10, 0)) {
1056 if (time_after(jiffies, timeout)) { 1112 DRM_DEBUG_KMS("FBC idle timed out\n");
1057 DRM_DEBUG_DRIVER("FBC idle timed out\n"); 1113 return;
1058 break;
1059 }
1060 ; /* do nothing */
1061 } 1114 }
1062 1115
1063 intel_wait_for_vblank(dev);
1064
1065 DRM_DEBUG_KMS("disabled FBC\n"); 1116 DRM_DEBUG_KMS("disabled FBC\n");
1066} 1117}
1067 1118
@@ -1118,7 +1169,6 @@ void g4x_disable_fbc(struct drm_device *dev)
1118 dpfc_ctl = I915_READ(DPFC_CONTROL); 1169 dpfc_ctl = I915_READ(DPFC_CONTROL);
1119 dpfc_ctl &= ~DPFC_CTL_EN; 1170 dpfc_ctl &= ~DPFC_CTL_EN;
1120 I915_WRITE(DPFC_CONTROL, dpfc_ctl); 1171 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
1121 intel_wait_for_vblank(dev);
1122 1172
1123 DRM_DEBUG_KMS("disabled FBC\n"); 1173 DRM_DEBUG_KMS("disabled FBC\n");
1124} 1174}
@@ -1179,7 +1229,6 @@ void ironlake_disable_fbc(struct drm_device *dev)
1179 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL); 1229 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
1180 dpfc_ctl &= ~DPFC_CTL_EN; 1230 dpfc_ctl &= ~DPFC_CTL_EN;
1181 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl); 1231 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
1182 intel_wait_for_vblank(dev);
1183 1232
1184 DRM_DEBUG_KMS("disabled FBC\n"); 1233 DRM_DEBUG_KMS("disabled FBC\n");
1185} 1234}
@@ -1453,7 +1502,7 @@ intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1453 dspcntr &= ~DISPPLANE_TILED; 1502 dspcntr &= ~DISPPLANE_TILED;
1454 } 1503 }
1455 1504
1456 if (IS_IRONLAKE(dev)) 1505 if (HAS_PCH_SPLIT(dev))
1457 /* must disable */ 1506 /* must disable */
1458 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; 1507 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
1459 1508
@@ -1462,23 +1511,22 @@ intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1462 Start = obj_priv->gtt_offset; 1511 Start = obj_priv->gtt_offset;
1463 Offset = y * fb->pitch + x * (fb->bits_per_pixel / 8); 1512 Offset = y * fb->pitch + x * (fb->bits_per_pixel / 8);
1464 1513
1465 DRM_DEBUG("Writing base %08lX %08lX %d %d\n", Start, Offset, x, y); 1514 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
1515 Start, Offset, x, y, fb->pitch);
1466 I915_WRITE(dspstride, fb->pitch); 1516 I915_WRITE(dspstride, fb->pitch);
1467 if (IS_I965G(dev)) { 1517 if (IS_I965G(dev)) {
1468 I915_WRITE(dspbase, Offset);
1469 I915_READ(dspbase);
1470 I915_WRITE(dspsurf, Start); 1518 I915_WRITE(dspsurf, Start);
1471 I915_READ(dspsurf);
1472 I915_WRITE(dsptileoff, (y << 16) | x); 1519 I915_WRITE(dsptileoff, (y << 16) | x);
1520 I915_WRITE(dspbase, Offset);
1473 } else { 1521 } else {
1474 I915_WRITE(dspbase, Start + Offset); 1522 I915_WRITE(dspbase, Start + Offset);
1475 I915_READ(dspbase);
1476 } 1523 }
1524 POSTING_READ(dspbase);
1477 1525
1478 if ((IS_I965G(dev) || plane == 0)) 1526 if (IS_I965G(dev) || plane == 0)
1479 intel_update_fbc(crtc, &crtc->mode); 1527 intel_update_fbc(crtc, &crtc->mode);
1480 1528
1481 intel_wait_for_vblank(dev); 1529 intel_wait_for_vblank(dev, intel_crtc->pipe);
1482 intel_increase_pllclock(crtc, true); 1530 intel_increase_pllclock(crtc, true);
1483 1531
1484 return 0; 1532 return 0;
@@ -1489,7 +1537,6 @@ intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
1489 struct drm_framebuffer *old_fb) 1537 struct drm_framebuffer *old_fb)
1490{ 1538{
1491 struct drm_device *dev = crtc->dev; 1539 struct drm_device *dev = crtc->dev;
1492 struct drm_i915_private *dev_priv = dev->dev_private;
1493 struct drm_i915_master_private *master_priv; 1540 struct drm_i915_master_private *master_priv;
1494 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 1541 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1495 struct intel_framebuffer *intel_fb; 1542 struct intel_framebuffer *intel_fb;
@@ -1497,13 +1544,6 @@ intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
1497 struct drm_gem_object *obj; 1544 struct drm_gem_object *obj;
1498 int pipe = intel_crtc->pipe; 1545 int pipe = intel_crtc->pipe;
1499 int plane = intel_crtc->plane; 1546 int plane = intel_crtc->plane;
1500 unsigned long Start, Offset;
1501 int dspbase = (plane == 0 ? DSPAADDR : DSPBADDR);
1502 int dspsurf = (plane == 0 ? DSPASURF : DSPBSURF);
1503 int dspstride = (plane == 0) ? DSPASTRIDE : DSPBSTRIDE;
1504 int dsptileoff = (plane == 0 ? DSPATILEOFF : DSPBTILEOFF);
1505 int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
1506 u32 dspcntr;
1507 int ret; 1547 int ret;
1508 1548
1509 /* no fb bound */ 1549 /* no fb bound */
@@ -1539,73 +1579,18 @@ intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
1539 return ret; 1579 return ret;
1540 } 1580 }
1541 1581
1542 dspcntr = I915_READ(dspcntr_reg); 1582 ret = intel_pipe_set_base_atomic(crtc, crtc->fb, x, y);
1543 /* Mask out pixel format bits in case we change it */ 1583 if (ret) {
1544 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1545 switch (crtc->fb->bits_per_pixel) {
1546 case 8:
1547 dspcntr |= DISPPLANE_8BPP;
1548 break;
1549 case 16:
1550 if (crtc->fb->depth == 15)
1551 dspcntr |= DISPPLANE_15_16BPP;
1552 else
1553 dspcntr |= DISPPLANE_16BPP;
1554 break;
1555 case 24:
1556 case 32:
1557 if (crtc->fb->depth == 30)
1558 dspcntr |= DISPPLANE_32BPP_30BIT_NO_ALPHA;
1559 else
1560 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
1561 break;
1562 default:
1563 DRM_ERROR("Unknown color depth\n");
1564 i915_gem_object_unpin(obj); 1584 i915_gem_object_unpin(obj);
1565 mutex_unlock(&dev->struct_mutex); 1585 mutex_unlock(&dev->struct_mutex);
1566 return -EINVAL; 1586 return ret;
1567 }
1568 if (IS_I965G(dev)) {
1569 if (obj_priv->tiling_mode != I915_TILING_NONE)
1570 dspcntr |= DISPPLANE_TILED;
1571 else
1572 dspcntr &= ~DISPPLANE_TILED;
1573 }
1574
1575 if (HAS_PCH_SPLIT(dev))
1576 /* must disable */
1577 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
1578
1579 I915_WRITE(dspcntr_reg, dspcntr);
1580
1581 Start = obj_priv->gtt_offset;
1582 Offset = y * crtc->fb->pitch + x * (crtc->fb->bits_per_pixel / 8);
1583
1584 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
1585 Start, Offset, x, y, crtc->fb->pitch);
1586 I915_WRITE(dspstride, crtc->fb->pitch);
1587 if (IS_I965G(dev)) {
1588 I915_WRITE(dspbase, Offset);
1589 I915_READ(dspbase);
1590 I915_WRITE(dspsurf, Start);
1591 I915_READ(dspsurf);
1592 I915_WRITE(dsptileoff, (y << 16) | x);
1593 } else {
1594 I915_WRITE(dspbase, Start + Offset);
1595 I915_READ(dspbase);
1596 } 1587 }
1597 1588
1598 if ((IS_I965G(dev) || plane == 0))
1599 intel_update_fbc(crtc, &crtc->mode);
1600
1601 intel_wait_for_vblank(dev);
1602
1603 if (old_fb) { 1589 if (old_fb) {
1604 intel_fb = to_intel_framebuffer(old_fb); 1590 intel_fb = to_intel_framebuffer(old_fb);
1605 obj_priv = to_intel_bo(intel_fb->obj); 1591 obj_priv = to_intel_bo(intel_fb->obj);
1606 i915_gem_object_unpin(intel_fb->obj); 1592 i915_gem_object_unpin(intel_fb->obj);
1607 } 1593 }
1608 intel_increase_pllclock(crtc, true);
1609 1594
1610 mutex_unlock(&dev->struct_mutex); 1595 mutex_unlock(&dev->struct_mutex);
1611 1596
@@ -1627,54 +1612,6 @@ intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
1627 return 0; 1612 return 0;
1628} 1613}
1629 1614
1630/* Disable the VGA plane that we never use */
1631static void i915_disable_vga (struct drm_device *dev)
1632{
1633 struct drm_i915_private *dev_priv = dev->dev_private;
1634 u8 sr1;
1635 u32 vga_reg;
1636
1637 if (HAS_PCH_SPLIT(dev))
1638 vga_reg = CPU_VGACNTRL;
1639 else
1640 vga_reg = VGACNTRL;
1641
1642 if (I915_READ(vga_reg) & VGA_DISP_DISABLE)
1643 return;
1644
1645 I915_WRITE8(VGA_SR_INDEX, 1);
1646 sr1 = I915_READ8(VGA_SR_DATA);
1647 I915_WRITE8(VGA_SR_DATA, sr1 | (1 << 5));
1648 udelay(100);
1649
1650 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
1651}
1652
1653static void ironlake_disable_pll_edp (struct drm_crtc *crtc)
1654{
1655 struct drm_device *dev = crtc->dev;
1656 struct drm_i915_private *dev_priv = dev->dev_private;
1657 u32 dpa_ctl;
1658
1659 DRM_DEBUG_KMS("\n");
1660 dpa_ctl = I915_READ(DP_A);
1661 dpa_ctl &= ~DP_PLL_ENABLE;
1662 I915_WRITE(DP_A, dpa_ctl);
1663}
1664
1665static void ironlake_enable_pll_edp (struct drm_crtc *crtc)
1666{
1667 struct drm_device *dev = crtc->dev;
1668 struct drm_i915_private *dev_priv = dev->dev_private;
1669 u32 dpa_ctl;
1670
1671 dpa_ctl = I915_READ(DP_A);
1672 dpa_ctl |= DP_PLL_ENABLE;
1673 I915_WRITE(DP_A, dpa_ctl);
1674 udelay(200);
1675}
1676
1677
1678static void ironlake_set_pll_edp (struct drm_crtc *crtc, int clock) 1615static void ironlake_set_pll_edp (struct drm_crtc *crtc, int clock)
1679{ 1616{
1680 struct drm_device *dev = crtc->dev; 1617 struct drm_device *dev = crtc->dev;
@@ -1928,9 +1865,6 @@ static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
1928 int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL; 1865 int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL;
1929 int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL; 1866 int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
1930 int transconf_reg = (pipe == 0) ? TRANSACONF : TRANSBCONF; 1867 int transconf_reg = (pipe == 0) ? TRANSACONF : TRANSBCONF;
1931 int pf_ctl_reg = (pipe == 0) ? PFA_CTL_1 : PFB_CTL_1;
1932 int pf_win_size = (pipe == 0) ? PFA_WIN_SZ : PFB_WIN_SZ;
1933 int pf_win_pos = (pipe == 0) ? PFA_WIN_POS : PFB_WIN_POS;
1934 int cpu_htot_reg = (pipe == 0) ? HTOTAL_A : HTOTAL_B; 1868 int cpu_htot_reg = (pipe == 0) ? HTOTAL_A : HTOTAL_B;
1935 int cpu_hblank_reg = (pipe == 0) ? HBLANK_A : HBLANK_B; 1869 int cpu_hblank_reg = (pipe == 0) ? HBLANK_A : HBLANK_B;
1936 int cpu_hsync_reg = (pipe == 0) ? HSYNC_A : HSYNC_B; 1870 int cpu_hsync_reg = (pipe == 0) ? HSYNC_A : HSYNC_B;
@@ -1945,7 +1879,6 @@ static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
1945 int trans_vsync_reg = (pipe == 0) ? TRANS_VSYNC_A : TRANS_VSYNC_B; 1879 int trans_vsync_reg = (pipe == 0) ? TRANS_VSYNC_A : TRANS_VSYNC_B;
1946 int trans_dpll_sel = (pipe == 0) ? 0 : 1; 1880 int trans_dpll_sel = (pipe == 0) ? 0 : 1;
1947 u32 temp; 1881 u32 temp;
1948 int n;
1949 u32 pipe_bpc; 1882 u32 pipe_bpc;
1950 1883
1951 temp = I915_READ(pipeconf_reg); 1884 temp = I915_READ(pipeconf_reg);
@@ -1958,7 +1891,7 @@ static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
1958 case DRM_MODE_DPMS_ON: 1891 case DRM_MODE_DPMS_ON:
1959 case DRM_MODE_DPMS_STANDBY: 1892 case DRM_MODE_DPMS_STANDBY:
1960 case DRM_MODE_DPMS_SUSPEND: 1893 case DRM_MODE_DPMS_SUSPEND:
1961 DRM_DEBUG_KMS("crtc %d dpms on\n", pipe); 1894 DRM_DEBUG_KMS("crtc %d/%d dpms on\n", pipe, plane);
1962 1895
1963 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { 1896 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1964 temp = I915_READ(PCH_LVDS); 1897 temp = I915_READ(PCH_LVDS);
@@ -1968,10 +1901,7 @@ static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
1968 } 1901 }
1969 } 1902 }
1970 1903
1971 if (HAS_eDP) { 1904 if (!HAS_eDP) {
1972 /* enable eDP PLL */
1973 ironlake_enable_pll_edp(crtc);
1974 } else {
1975 1905
1976 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */ 1906 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
1977 temp = I915_READ(fdi_rx_reg); 1907 temp = I915_READ(fdi_rx_reg);
@@ -2003,17 +1933,19 @@ static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
2003 } 1933 }
2004 1934
2005 /* Enable panel fitting for LVDS */ 1935 /* Enable panel fitting for LVDS */
2006 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) 1936 if (dev_priv->pch_pf_size &&
2007 || HAS_eDP || intel_pch_has_edp(crtc)) { 1937 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)
2008 temp = I915_READ(pf_ctl_reg); 1938 || HAS_eDP || intel_pch_has_edp(crtc))) {
2009 I915_WRITE(pf_ctl_reg, temp | PF_ENABLE | PF_FILTER_MED_3x3); 1939 /* Force use of hard-coded filter coefficients
2010 1940 * as some pre-programmed values are broken,
2011 /* currently full aspect */ 1941 * e.g. x201.
2012 I915_WRITE(pf_win_pos, 0); 1942 */
2013 1943 I915_WRITE(pipe ? PFB_CTL_1 : PFA_CTL_1,
2014 I915_WRITE(pf_win_size, 1944 PF_ENABLE | PF_FILTER_MED_3x3);
2015 (dev_priv->panel_fixed_mode->hdisplay << 16) | 1945 I915_WRITE(pipe ? PFB_WIN_POS : PFA_WIN_POS,
2016 (dev_priv->panel_fixed_mode->vdisplay)); 1946 dev_priv->pch_pf_pos);
1947 I915_WRITE(pipe ? PFB_WIN_SZ : PFA_WIN_SZ,
1948 dev_priv->pch_pf_size);
2017 } 1949 }
2018 1950
2019 /* Enable CPU pipe */ 1951 /* Enable CPU pipe */
@@ -2097,9 +2029,10 @@ static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
2097 int reg; 2029 int reg;
2098 2030
2099 reg = I915_READ(trans_dp_ctl); 2031 reg = I915_READ(trans_dp_ctl);
2100 reg &= ~TRANS_DP_PORT_SEL_MASK; 2032 reg &= ~(TRANS_DP_PORT_SEL_MASK |
2101 reg = TRANS_DP_OUTPUT_ENABLE | 2033 TRANS_DP_SYNC_MASK);
2102 TRANS_DP_ENH_FRAMING; 2034 reg |= (TRANS_DP_OUTPUT_ENABLE |
2035 TRANS_DP_ENH_FRAMING);
2103 2036
2104 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC) 2037 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
2105 reg |= TRANS_DP_HSYNC_ACTIVE_HIGH; 2038 reg |= TRANS_DP_HSYNC_ACTIVE_HIGH;
@@ -2137,18 +2070,17 @@ static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
2137 I915_WRITE(transconf_reg, temp | TRANS_ENABLE); 2070 I915_WRITE(transconf_reg, temp | TRANS_ENABLE);
2138 I915_READ(transconf_reg); 2071 I915_READ(transconf_reg);
2139 2072
2140 while ((I915_READ(transconf_reg) & TRANS_STATE_ENABLE) == 0) 2073 if (wait_for(I915_READ(transconf_reg) & TRANS_STATE_ENABLE, 100, 1))
2141 ; 2074 DRM_ERROR("failed to enable transcoder\n");
2142
2143 } 2075 }
2144 2076
2145 intel_crtc_load_lut(crtc); 2077 intel_crtc_load_lut(crtc);
2146 2078
2147 intel_update_fbc(crtc, &crtc->mode); 2079 intel_update_fbc(crtc, &crtc->mode);
2080 break;
2148 2081
2149 break;
2150 case DRM_MODE_DPMS_OFF: 2082 case DRM_MODE_DPMS_OFF:
2151 DRM_DEBUG_KMS("crtc %d dpms off\n", pipe); 2083 DRM_DEBUG_KMS("crtc %d/%d dpms off\n", pipe, plane);
2152 2084
2153 drm_vblank_off(dev, pipe); 2085 drm_vblank_off(dev, pipe);
2154 /* Disable display plane */ 2086 /* Disable display plane */
@@ -2164,40 +2096,22 @@ static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
2164 dev_priv->display.disable_fbc) 2096 dev_priv->display.disable_fbc)
2165 dev_priv->display.disable_fbc(dev); 2097 dev_priv->display.disable_fbc(dev);
2166 2098
2167 i915_disable_vga(dev);
2168
2169 /* disable cpu pipe, disable after all planes disabled */ 2099 /* disable cpu pipe, disable after all planes disabled */
2170 temp = I915_READ(pipeconf_reg); 2100 temp = I915_READ(pipeconf_reg);
2171 if ((temp & PIPEACONF_ENABLE) != 0) { 2101 if ((temp & PIPEACONF_ENABLE) != 0) {
2172 I915_WRITE(pipeconf_reg, temp & ~PIPEACONF_ENABLE); 2102 I915_WRITE(pipeconf_reg, temp & ~PIPEACONF_ENABLE);
2173 I915_READ(pipeconf_reg); 2103
2174 n = 0;
2175 /* wait for cpu pipe off, pipe state */ 2104 /* wait for cpu pipe off, pipe state */
2176 while ((I915_READ(pipeconf_reg) & I965_PIPECONF_ACTIVE) != 0) { 2105 if (wait_for((I915_READ(pipeconf_reg) & I965_PIPECONF_ACTIVE) == 0, 50, 1))
2177 n++; 2106 DRM_ERROR("failed to turn off cpu pipe\n");
2178 if (n < 60) {
2179 udelay(500);
2180 continue;
2181 } else {
2182 DRM_DEBUG_KMS("pipe %d off delay\n",
2183 pipe);
2184 break;
2185 }
2186 }
2187 } else 2107 } else
2188 DRM_DEBUG_KMS("crtc %d is disabled\n", pipe); 2108 DRM_DEBUG_KMS("crtc %d is disabled\n", pipe);
2189 2109
2190 udelay(100); 2110 udelay(100);
2191 2111
2192 /* Disable PF */ 2112 /* Disable PF */
2193 temp = I915_READ(pf_ctl_reg); 2113 I915_WRITE(pipe ? PFB_CTL_1 : PFA_CTL_1, 0);
2194 if ((temp & PF_ENABLE) != 0) { 2114 I915_WRITE(pipe ? PFB_WIN_SZ : PFA_WIN_SZ, 0);
2195 I915_WRITE(pf_ctl_reg, temp & ~PF_ENABLE);
2196 I915_READ(pf_ctl_reg);
2197 }
2198 I915_WRITE(pf_win_size, 0);
2199 POSTING_READ(pf_win_size);
2200
2201 2115
2202 /* disable CPU FDI tx and PCH FDI rx */ 2116 /* disable CPU FDI tx and PCH FDI rx */
2203 temp = I915_READ(fdi_tx_reg); 2117 temp = I915_READ(fdi_tx_reg);
@@ -2244,20 +2158,10 @@ static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
2244 temp = I915_READ(transconf_reg); 2158 temp = I915_READ(transconf_reg);
2245 if ((temp & TRANS_ENABLE) != 0) { 2159 if ((temp & TRANS_ENABLE) != 0) {
2246 I915_WRITE(transconf_reg, temp & ~TRANS_ENABLE); 2160 I915_WRITE(transconf_reg, temp & ~TRANS_ENABLE);
2247 I915_READ(transconf_reg); 2161
2248 n = 0;
2249 /* wait for PCH transcoder off, transcoder state */ 2162 /* wait for PCH transcoder off, transcoder state */
2250 while ((I915_READ(transconf_reg) & TRANS_STATE_ENABLE) != 0) { 2163 if (wait_for((I915_READ(transconf_reg) & TRANS_STATE_ENABLE) == 0, 50, 1))
2251 n++; 2164 DRM_ERROR("failed to disable transcoder\n");
2252 if (n < 60) {
2253 udelay(500);
2254 continue;
2255 } else {
2256 DRM_DEBUG_KMS("transcoder %d off "
2257 "delay\n", pipe);
2258 break;
2259 }
2260 }
2261 } 2165 }
2262 2166
2263 temp = I915_READ(transconf_reg); 2167 temp = I915_READ(transconf_reg);
@@ -2294,10 +2198,6 @@ static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
2294 I915_WRITE(pch_dpll_reg, temp & ~DPLL_VCO_ENABLE); 2198 I915_WRITE(pch_dpll_reg, temp & ~DPLL_VCO_ENABLE);
2295 I915_READ(pch_dpll_reg); 2199 I915_READ(pch_dpll_reg);
2296 2200
2297 if (HAS_eDP) {
2298 ironlake_disable_pll_edp(crtc);
2299 }
2300
2301 /* Switch from PCDclk to Rawclk */ 2201 /* Switch from PCDclk to Rawclk */
2302 temp = I915_READ(fdi_rx_reg); 2202 temp = I915_READ(fdi_rx_reg);
2303 temp &= ~FDI_SEL_PCDCLK; 2203 temp &= ~FDI_SEL_PCDCLK;
@@ -2372,8 +2272,6 @@ static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
2372 case DRM_MODE_DPMS_ON: 2272 case DRM_MODE_DPMS_ON:
2373 case DRM_MODE_DPMS_STANDBY: 2273 case DRM_MODE_DPMS_STANDBY:
2374 case DRM_MODE_DPMS_SUSPEND: 2274 case DRM_MODE_DPMS_SUSPEND:
2375 intel_update_watermarks(dev);
2376
2377 /* Enable the DPLL */ 2275 /* Enable the DPLL */
2378 temp = I915_READ(dpll_reg); 2276 temp = I915_READ(dpll_reg);
2379 if ((temp & DPLL_VCO_ENABLE) == 0) { 2277 if ((temp & DPLL_VCO_ENABLE) == 0) {
@@ -2413,8 +2311,6 @@ static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
2413 intel_crtc_dpms_overlay(intel_crtc, true); 2311 intel_crtc_dpms_overlay(intel_crtc, true);
2414 break; 2312 break;
2415 case DRM_MODE_DPMS_OFF: 2313 case DRM_MODE_DPMS_OFF:
2416 intel_update_watermarks(dev);
2417
2418 /* Give the overlay scaler a chance to disable if it's on this pipe */ 2314 /* Give the overlay scaler a chance to disable if it's on this pipe */
2419 intel_crtc_dpms_overlay(intel_crtc, false); 2315 intel_crtc_dpms_overlay(intel_crtc, false);
2420 drm_vblank_off(dev, pipe); 2316 drm_vblank_off(dev, pipe);
@@ -2423,9 +2319,6 @@ static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
2423 dev_priv->display.disable_fbc) 2319 dev_priv->display.disable_fbc)
2424 dev_priv->display.disable_fbc(dev); 2320 dev_priv->display.disable_fbc(dev);
2425 2321
2426 /* Disable the VGA plane that we never use */
2427 i915_disable_vga(dev);
2428
2429 /* Disable display plane */ 2322 /* Disable display plane */
2430 temp = I915_READ(dspcntr_reg); 2323 temp = I915_READ(dspcntr_reg);
2431 if ((temp & DISPLAY_PLANE_ENABLE) != 0) { 2324 if ((temp & DISPLAY_PLANE_ENABLE) != 0) {
@@ -2435,10 +2328,8 @@ static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
2435 I915_READ(dspbase_reg); 2328 I915_READ(dspbase_reg);
2436 } 2329 }
2437 2330
2438 if (!IS_I9XX(dev)) { 2331 /* Wait for vblank for the disable to take effect */
2439 /* Wait for vblank for the disable to take effect */ 2332 intel_wait_for_vblank_off(dev, pipe);
2440 intel_wait_for_vblank(dev);
2441 }
2442 2333
2443 /* Don't disable pipe A or pipe A PLLs if needed */ 2334 /* Don't disable pipe A or pipe A PLLs if needed */
2444 if (pipeconf_reg == PIPEACONF && 2335 if (pipeconf_reg == PIPEACONF &&
@@ -2453,7 +2344,7 @@ static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
2453 } 2344 }
2454 2345
2455 /* Wait for vblank for the disable to take effect. */ 2346 /* Wait for vblank for the disable to take effect. */
2456 intel_wait_for_vblank(dev); 2347 intel_wait_for_vblank_off(dev, pipe);
2457 2348
2458 temp = I915_READ(dpll_reg); 2349 temp = I915_READ(dpll_reg);
2459 if ((temp & DPLL_VCO_ENABLE) != 0) { 2350 if ((temp & DPLL_VCO_ENABLE) != 0) {
@@ -2469,9 +2360,6 @@ static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
2469 2360
2470/** 2361/**
2471 * Sets the power management mode of the pipe and plane. 2362 * Sets the power management mode of the pipe and plane.
2472 *
2473 * This code should probably grow support for turning the cursor off and back
2474 * on appropriately at the same time as we're turning the pipe off/on.
2475 */ 2363 */
2476static void intel_crtc_dpms(struct drm_crtc *crtc, int mode) 2364static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
2477{ 2365{
@@ -2482,9 +2370,29 @@ static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
2482 int pipe = intel_crtc->pipe; 2370 int pipe = intel_crtc->pipe;
2483 bool enabled; 2371 bool enabled;
2484 2372
2485 dev_priv->display.dpms(crtc, mode); 2373 if (intel_crtc->dpms_mode == mode)
2374 return;
2486 2375
2487 intel_crtc->dpms_mode = mode; 2376 intel_crtc->dpms_mode = mode;
2377 intel_crtc->cursor_on = mode == DRM_MODE_DPMS_ON;
2378
2379 /* When switching on the display, ensure that SR is disabled
2380 * with multiple pipes prior to enabling to new pipe.
2381 *
2382 * When switching off the display, make sure the cursor is
2383 * properly hidden prior to disabling the pipe.
2384 */
2385 if (mode == DRM_MODE_DPMS_ON)
2386 intel_update_watermarks(dev);
2387 else
2388 intel_crtc_update_cursor(crtc);
2389
2390 dev_priv->display.dpms(crtc, mode);
2391
2392 if (mode == DRM_MODE_DPMS_ON)
2393 intel_crtc_update_cursor(crtc);
2394 else
2395 intel_update_watermarks(dev);
2488 2396
2489 if (!dev->primary->master) 2397 if (!dev->primary->master)
2490 return; 2398 return;
@@ -2536,6 +2444,20 @@ void intel_encoder_commit (struct drm_encoder *encoder)
2536 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON); 2444 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
2537} 2445}
2538 2446
2447void intel_encoder_destroy(struct drm_encoder *encoder)
2448{
2449 struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
2450
2451 if (intel_encoder->ddc_bus)
2452 intel_i2c_destroy(intel_encoder->ddc_bus);
2453
2454 if (intel_encoder->i2c_bus)
2455 intel_i2c_destroy(intel_encoder->i2c_bus);
2456
2457 drm_encoder_cleanup(encoder);
2458 kfree(intel_encoder);
2459}
2460
2539static bool intel_crtc_mode_fixup(struct drm_crtc *crtc, 2461static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
2540 struct drm_display_mode *mode, 2462 struct drm_display_mode *mode,
2541 struct drm_display_mode *adjusted_mode) 2463 struct drm_display_mode *adjusted_mode)
@@ -2867,7 +2789,7 @@ struct cxsr_latency {
2867 unsigned long cursor_hpll_disable; 2789 unsigned long cursor_hpll_disable;
2868}; 2790};
2869 2791
2870static struct cxsr_latency cxsr_latency_table[] = { 2792static const struct cxsr_latency cxsr_latency_table[] = {
2871 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */ 2793 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
2872 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */ 2794 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
2873 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */ 2795 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
@@ -2905,11 +2827,13 @@ static struct cxsr_latency cxsr_latency_table[] = {
2905 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */ 2827 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
2906}; 2828};
2907 2829
2908static struct cxsr_latency *intel_get_cxsr_latency(int is_desktop, int is_ddr3, 2830static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
2909 int fsb, int mem) 2831 int is_ddr3,
2832 int fsb,
2833 int mem)
2910{ 2834{
2835 const struct cxsr_latency *latency;
2911 int i; 2836 int i;
2912 struct cxsr_latency *latency;
2913 2837
2914 if (fsb == 0 || mem == 0) 2838 if (fsb == 0 || mem == 0)
2915 return NULL; 2839 return NULL;
@@ -2930,13 +2854,9 @@ static struct cxsr_latency *intel_get_cxsr_latency(int is_desktop, int is_ddr3,
2930static void pineview_disable_cxsr(struct drm_device *dev) 2854static void pineview_disable_cxsr(struct drm_device *dev)
2931{ 2855{
2932 struct drm_i915_private *dev_priv = dev->dev_private; 2856 struct drm_i915_private *dev_priv = dev->dev_private;
2933 u32 reg;
2934 2857
2935 /* deactivate cxsr */ 2858 /* deactivate cxsr */
2936 reg = I915_READ(DSPFW3); 2859 I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN);
2937 reg &= ~(PINEVIEW_SELF_REFRESH_EN);
2938 I915_WRITE(DSPFW3, reg);
2939 DRM_INFO("Big FIFO is disabled\n");
2940} 2860}
2941 2861
2942/* 2862/*
@@ -3024,12 +2944,12 @@ static void pineview_update_wm(struct drm_device *dev, int planea_clock,
3024 int pixel_size) 2944 int pixel_size)
3025{ 2945{
3026 struct drm_i915_private *dev_priv = dev->dev_private; 2946 struct drm_i915_private *dev_priv = dev->dev_private;
2947 const struct cxsr_latency *latency;
3027 u32 reg; 2948 u32 reg;
3028 unsigned long wm; 2949 unsigned long wm;
3029 struct cxsr_latency *latency;
3030 int sr_clock; 2950 int sr_clock;
3031 2951
3032 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3, 2952 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
3033 dev_priv->fsb_freq, dev_priv->mem_freq); 2953 dev_priv->fsb_freq, dev_priv->mem_freq);
3034 if (!latency) { 2954 if (!latency) {
3035 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n"); 2955 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
@@ -3075,9 +2995,8 @@ static void pineview_update_wm(struct drm_device *dev, int planea_clock,
3075 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg); 2995 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
3076 2996
3077 /* activate cxsr */ 2997 /* activate cxsr */
3078 reg = I915_READ(DSPFW3); 2998 I915_WRITE(DSPFW3,
3079 reg |= PINEVIEW_SELF_REFRESH_EN; 2999 I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN);
3080 I915_WRITE(DSPFW3, reg);
3081 DRM_DEBUG_KMS("Self-refresh is enabled\n"); 3000 DRM_DEBUG_KMS("Self-refresh is enabled\n");
3082 } else { 3001 } else {
3083 pineview_disable_cxsr(dev); 3002 pineview_disable_cxsr(dev);
@@ -3354,12 +3273,11 @@ static void ironlake_update_wm(struct drm_device *dev, int planea_clock,
3354 int line_count; 3273 int line_count;
3355 int planea_htotal = 0, planeb_htotal = 0; 3274 int planea_htotal = 0, planeb_htotal = 0;
3356 struct drm_crtc *crtc; 3275 struct drm_crtc *crtc;
3357 struct intel_crtc *intel_crtc;
3358 3276
3359 /* Need htotal for all active display plane */ 3277 /* Need htotal for all active display plane */
3360 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { 3278 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3361 intel_crtc = to_intel_crtc(crtc); 3279 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3362 if (crtc->enabled) { 3280 if (intel_crtc->dpms_mode == DRM_MODE_DPMS_ON) {
3363 if (intel_crtc->plane == 0) 3281 if (intel_crtc->plane == 0)
3364 planea_htotal = crtc->mode.htotal; 3282 planea_htotal = crtc->mode.htotal;
3365 else 3283 else
@@ -3519,7 +3437,6 @@ static void intel_update_watermarks(struct drm_device *dev)
3519{ 3437{
3520 struct drm_i915_private *dev_priv = dev->dev_private; 3438 struct drm_i915_private *dev_priv = dev->dev_private;
3521 struct drm_crtc *crtc; 3439 struct drm_crtc *crtc;
3522 struct intel_crtc *intel_crtc;
3523 int sr_hdisplay = 0; 3440 int sr_hdisplay = 0;
3524 unsigned long planea_clock = 0, planeb_clock = 0, sr_clock = 0; 3441 unsigned long planea_clock = 0, planeb_clock = 0, sr_clock = 0;
3525 int enabled = 0, pixel_size = 0; 3442 int enabled = 0, pixel_size = 0;
@@ -3530,8 +3447,8 @@ static void intel_update_watermarks(struct drm_device *dev)
3530 3447
3531 /* Get the clock config from both planes */ 3448 /* Get the clock config from both planes */
3532 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { 3449 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3533 intel_crtc = to_intel_crtc(crtc); 3450 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3534 if (crtc->enabled) { 3451 if (intel_crtc->dpms_mode == DRM_MODE_DPMS_ON) {
3535 enabled++; 3452 enabled++;
3536 if (intel_crtc->plane == 0) { 3453 if (intel_crtc->plane == 0) {
3537 DRM_DEBUG_KMS("plane A (pipe %d) clock: %d\n", 3454 DRM_DEBUG_KMS("plane A (pipe %d) clock: %d\n",
@@ -3589,10 +3506,9 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
3589 u32 dpll = 0, fp = 0, fp2 = 0, dspcntr, pipeconf; 3506 u32 dpll = 0, fp = 0, fp2 = 0, dspcntr, pipeconf;
3590 bool ok, has_reduced_clock = false, is_sdvo = false, is_dvo = false; 3507 bool ok, has_reduced_clock = false, is_sdvo = false, is_dvo = false;
3591 bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false; 3508 bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
3592 bool is_edp = false; 3509 struct intel_encoder *has_edp_encoder = NULL;
3593 struct drm_mode_config *mode_config = &dev->mode_config; 3510 struct drm_mode_config *mode_config = &dev->mode_config;
3594 struct drm_encoder *encoder; 3511 struct drm_encoder *encoder;
3595 struct intel_encoder *intel_encoder = NULL;
3596 const intel_limit_t *limit; 3512 const intel_limit_t *limit;
3597 int ret; 3513 int ret;
3598 struct fdi_m_n m_n = {0}; 3514 struct fdi_m_n m_n = {0};
@@ -3613,12 +3529,12 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
3613 drm_vblank_pre_modeset(dev, pipe); 3529 drm_vblank_pre_modeset(dev, pipe);
3614 3530
3615 list_for_each_entry(encoder, &mode_config->encoder_list, head) { 3531 list_for_each_entry(encoder, &mode_config->encoder_list, head) {
3532 struct intel_encoder *intel_encoder;
3616 3533
3617 if (!encoder || encoder->crtc != crtc) 3534 if (encoder->crtc != crtc)
3618 continue; 3535 continue;
3619 3536
3620 intel_encoder = enc_to_intel_encoder(encoder); 3537 intel_encoder = enc_to_intel_encoder(encoder);
3621
3622 switch (intel_encoder->type) { 3538 switch (intel_encoder->type) {
3623 case INTEL_OUTPUT_LVDS: 3539 case INTEL_OUTPUT_LVDS:
3624 is_lvds = true; 3540 is_lvds = true;
@@ -3642,7 +3558,7 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
3642 is_dp = true; 3558 is_dp = true;
3643 break; 3559 break;
3644 case INTEL_OUTPUT_EDP: 3560 case INTEL_OUTPUT_EDP:
3645 is_edp = true; 3561 has_edp_encoder = intel_encoder;
3646 break; 3562 break;
3647 } 3563 }
3648 3564
@@ -3720,10 +3636,10 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
3720 int lane = 0, link_bw, bpp; 3636 int lane = 0, link_bw, bpp;
3721 /* eDP doesn't require FDI link, so just set DP M/N 3637 /* eDP doesn't require FDI link, so just set DP M/N
3722 according to current link config */ 3638 according to current link config */
3723 if (is_edp) { 3639 if (has_edp_encoder) {
3724 target_clock = mode->clock; 3640 target_clock = mode->clock;
3725 intel_edp_link_config(intel_encoder, 3641 intel_edp_link_config(has_edp_encoder,
3726 &lane, &link_bw); 3642 &lane, &link_bw);
3727 } else { 3643 } else {
3728 /* DP over FDI requires target mode clock 3644 /* DP over FDI requires target mode clock
3729 instead of link clock */ 3645 instead of link clock */
@@ -3744,7 +3660,7 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
3744 temp |= PIPE_8BPC; 3660 temp |= PIPE_8BPC;
3745 else 3661 else
3746 temp |= PIPE_6BPC; 3662 temp |= PIPE_6BPC;
3747 } else if (is_edp || (is_dp && intel_pch_has_edp(crtc))) { 3663 } else if (has_edp_encoder || (is_dp && intel_pch_has_edp(crtc))) {
3748 switch (dev_priv->edp_bpp/3) { 3664 switch (dev_priv->edp_bpp/3) {
3749 case 8: 3665 case 8:
3750 temp |= PIPE_8BPC; 3666 temp |= PIPE_8BPC;
@@ -3817,7 +3733,7 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
3817 3733
3818 udelay(200); 3734 udelay(200);
3819 3735
3820 if (is_edp) { 3736 if (has_edp_encoder) {
3821 if (dev_priv->lvds_use_ssc) { 3737 if (dev_priv->lvds_use_ssc) {
3822 temp |= DREF_SSC1_ENABLE; 3738 temp |= DREF_SSC1_ENABLE;
3823 I915_WRITE(PCH_DREF_CONTROL, temp); 3739 I915_WRITE(PCH_DREF_CONTROL, temp);
@@ -3966,9 +3882,7 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
3966 dpll_reg = pch_dpll_reg; 3882 dpll_reg = pch_dpll_reg;
3967 } 3883 }
3968 3884
3969 if (is_edp) { 3885 if (!has_edp_encoder) {
3970 ironlake_disable_pll_edp(crtc);
3971 } else if ((dpll & DPLL_VCO_ENABLE)) {
3972 I915_WRITE(fp_reg, fp); 3886 I915_WRITE(fp_reg, fp);
3973 I915_WRITE(dpll_reg, dpll & ~DPLL_VCO_ENABLE); 3887 I915_WRITE(dpll_reg, dpll & ~DPLL_VCO_ENABLE);
3974 I915_READ(dpll_reg); 3888 I915_READ(dpll_reg);
@@ -4063,7 +3977,7 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
4063 } 3977 }
4064 } 3978 }
4065 3979
4066 if (!is_edp) { 3980 if (!has_edp_encoder) {
4067 I915_WRITE(fp_reg, fp); 3981 I915_WRITE(fp_reg, fp);
4068 I915_WRITE(dpll_reg, dpll); 3982 I915_WRITE(dpll_reg, dpll);
4069 I915_READ(dpll_reg); 3983 I915_READ(dpll_reg);
@@ -4142,7 +4056,7 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
4142 I915_WRITE(link_m1_reg, m_n.link_m); 4056 I915_WRITE(link_m1_reg, m_n.link_m);
4143 I915_WRITE(link_n1_reg, m_n.link_n); 4057 I915_WRITE(link_n1_reg, m_n.link_n);
4144 4058
4145 if (is_edp) { 4059 if (has_edp_encoder) {
4146 ironlake_set_pll_edp(crtc, adjusted_mode->clock); 4060 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
4147 } else { 4061 } else {
4148 /* enable FDI RX PLL too */ 4062 /* enable FDI RX PLL too */
@@ -4167,7 +4081,7 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
4167 I915_WRITE(pipeconf_reg, pipeconf); 4081 I915_WRITE(pipeconf_reg, pipeconf);
4168 I915_READ(pipeconf_reg); 4082 I915_READ(pipeconf_reg);
4169 4083
4170 intel_wait_for_vblank(dev); 4084 intel_wait_for_vblank(dev, pipe);
4171 4085
4172 if (IS_IRONLAKE(dev)) { 4086 if (IS_IRONLAKE(dev)) {
4173 /* enable address swizzle for tiling buffer */ 4087 /* enable address swizzle for tiling buffer */
@@ -4180,9 +4094,6 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
4180 /* Flush the plane changes */ 4094 /* Flush the plane changes */
4181 ret = intel_pipe_set_base(crtc, x, y, old_fb); 4095 ret = intel_pipe_set_base(crtc, x, y, old_fb);
4182 4096
4183 if ((IS_I965G(dev) || plane == 0))
4184 intel_update_fbc(crtc, &crtc->mode);
4185
4186 intel_update_watermarks(dev); 4097 intel_update_watermarks(dev);
4187 4098
4188 drm_vblank_post_modeset(dev, pipe); 4099 drm_vblank_post_modeset(dev, pipe);
@@ -4216,6 +4127,62 @@ void intel_crtc_load_lut(struct drm_crtc *crtc)
4216 } 4127 }
4217} 4128}
4218 4129
4130static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
4131{
4132 struct drm_device *dev = crtc->dev;
4133 struct drm_i915_private *dev_priv = dev->dev_private;
4134 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4135 bool visible = base != 0;
4136 u32 cntl;
4137
4138 if (intel_crtc->cursor_visible == visible)
4139 return;
4140
4141 cntl = I915_READ(CURACNTR);
4142 if (visible) {
4143 /* On these chipsets we can only modify the base whilst
4144 * the cursor is disabled.
4145 */
4146 I915_WRITE(CURABASE, base);
4147
4148 cntl &= ~(CURSOR_FORMAT_MASK);
4149 /* XXX width must be 64, stride 256 => 0x00 << 28 */
4150 cntl |= CURSOR_ENABLE |
4151 CURSOR_GAMMA_ENABLE |
4152 CURSOR_FORMAT_ARGB;
4153 } else
4154 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
4155 I915_WRITE(CURACNTR, cntl);
4156
4157 intel_crtc->cursor_visible = visible;
4158}
4159
4160static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
4161{
4162 struct drm_device *dev = crtc->dev;
4163 struct drm_i915_private *dev_priv = dev->dev_private;
4164 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4165 int pipe = intel_crtc->pipe;
4166 bool visible = base != 0;
4167
4168 if (intel_crtc->cursor_visible != visible) {
4169 uint32_t cntl = I915_READ(pipe == 0 ? CURACNTR : CURBCNTR);
4170 if (base) {
4171 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
4172 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
4173 cntl |= pipe << 28; /* Connect to correct pipe */
4174 } else {
4175 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
4176 cntl |= CURSOR_MODE_DISABLE;
4177 }
4178 I915_WRITE(pipe == 0 ? CURACNTR : CURBCNTR, cntl);
4179
4180 intel_crtc->cursor_visible = visible;
4181 }
4182 /* and commit changes on next vblank */
4183 I915_WRITE(pipe == 0 ? CURABASE : CURBBASE, base);
4184}
4185
4219/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */ 4186/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
4220static void intel_crtc_update_cursor(struct drm_crtc *crtc) 4187static void intel_crtc_update_cursor(struct drm_crtc *crtc)
4221{ 4188{
@@ -4225,12 +4192,12 @@ static void intel_crtc_update_cursor(struct drm_crtc *crtc)
4225 int pipe = intel_crtc->pipe; 4192 int pipe = intel_crtc->pipe;
4226 int x = intel_crtc->cursor_x; 4193 int x = intel_crtc->cursor_x;
4227 int y = intel_crtc->cursor_y; 4194 int y = intel_crtc->cursor_y;
4228 uint32_t base, pos; 4195 u32 base, pos;
4229 bool visible; 4196 bool visible;
4230 4197
4231 pos = 0; 4198 pos = 0;
4232 4199
4233 if (crtc->fb) { 4200 if (intel_crtc->cursor_on && crtc->fb) {
4234 base = intel_crtc->cursor_addr; 4201 base = intel_crtc->cursor_addr;
4235 if (x > (int) crtc->fb->width) 4202 if (x > (int) crtc->fb->width)
4236 base = 0; 4203 base = 0;
@@ -4259,37 +4226,14 @@ static void intel_crtc_update_cursor(struct drm_crtc *crtc)
4259 pos |= y << CURSOR_Y_SHIFT; 4226 pos |= y << CURSOR_Y_SHIFT;
4260 4227
4261 visible = base != 0; 4228 visible = base != 0;
4262 if (!visible && !intel_crtc->cursor_visble) 4229 if (!visible && !intel_crtc->cursor_visible)
4263 return; 4230 return;
4264 4231
4265 I915_WRITE(pipe == 0 ? CURAPOS : CURBPOS, pos); 4232 I915_WRITE(pipe == 0 ? CURAPOS : CURBPOS, pos);
4266 if (intel_crtc->cursor_visble != visible) { 4233 if (IS_845G(dev) || IS_I865G(dev))
4267 uint32_t cntl = I915_READ(pipe == 0 ? CURACNTR : CURBCNTR); 4234 i845_update_cursor(crtc, base);
4268 if (base) { 4235 else
4269 /* Hooray for CUR*CNTR differences */ 4236 i9xx_update_cursor(crtc, base);
4270 if (IS_MOBILE(dev) || IS_I9XX(dev)) {
4271 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
4272 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
4273 cntl |= pipe << 28; /* Connect to correct pipe */
4274 } else {
4275 cntl &= ~(CURSOR_FORMAT_MASK);
4276 cntl |= CURSOR_ENABLE;
4277 cntl |= CURSOR_FORMAT_ARGB | CURSOR_GAMMA_ENABLE;
4278 }
4279 } else {
4280 if (IS_MOBILE(dev) || IS_I9XX(dev)) {
4281 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
4282 cntl |= CURSOR_MODE_DISABLE;
4283 } else {
4284 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
4285 }
4286 }
4287 I915_WRITE(pipe == 0 ? CURACNTR : CURBCNTR, cntl);
4288
4289 intel_crtc->cursor_visble = visible;
4290 }
4291 /* and commit changes on next vblank */
4292 I915_WRITE(pipe == 0 ? CURABASE : CURBBASE, base);
4293 4237
4294 if (visible) 4238 if (visible)
4295 intel_mark_busy(dev, to_intel_framebuffer(crtc->fb)->obj); 4239 intel_mark_busy(dev, to_intel_framebuffer(crtc->fb)->obj);
@@ -4354,8 +4298,10 @@ static int intel_crtc_cursor_set(struct drm_crtc *crtc,
4354 4298
4355 addr = obj_priv->gtt_offset; 4299 addr = obj_priv->gtt_offset;
4356 } else { 4300 } else {
4301 int align = IS_I830(dev) ? 16 * 1024 : 256;
4357 ret = i915_gem_attach_phys_object(dev, bo, 4302 ret = i915_gem_attach_phys_object(dev, bo,
4358 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1); 4303 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
4304 align);
4359 if (ret) { 4305 if (ret) {
4360 DRM_ERROR("failed to attach phys object\n"); 4306 DRM_ERROR("failed to attach phys object\n");
4361 goto fail_locked; 4307 goto fail_locked;
@@ -4544,7 +4490,7 @@ struct drm_crtc *intel_get_load_detect_pipe(struct intel_encoder *intel_encoder,
4544 encoder_funcs->commit(encoder); 4490 encoder_funcs->commit(encoder);
4545 } 4491 }
4546 /* let the connector get through one full cycle before testing */ 4492 /* let the connector get through one full cycle before testing */
4547 intel_wait_for_vblank(dev); 4493 intel_wait_for_vblank(dev, intel_crtc->pipe);
4548 4494
4549 return crtc; 4495 return crtc;
4550} 4496}
@@ -4749,7 +4695,7 @@ static void intel_increase_pllclock(struct drm_crtc *crtc, bool schedule)
4749 dpll &= ~DISPLAY_RATE_SELECT_FPA1; 4695 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
4750 I915_WRITE(dpll_reg, dpll); 4696 I915_WRITE(dpll_reg, dpll);
4751 dpll = I915_READ(dpll_reg); 4697 dpll = I915_READ(dpll_reg);
4752 intel_wait_for_vblank(dev); 4698 intel_wait_for_vblank(dev, pipe);
4753 dpll = I915_READ(dpll_reg); 4699 dpll = I915_READ(dpll_reg);
4754 if (dpll & DISPLAY_RATE_SELECT_FPA1) 4700 if (dpll & DISPLAY_RATE_SELECT_FPA1)
4755 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n"); 4701 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
@@ -4793,7 +4739,7 @@ static void intel_decrease_pllclock(struct drm_crtc *crtc)
4793 dpll |= DISPLAY_RATE_SELECT_FPA1; 4739 dpll |= DISPLAY_RATE_SELECT_FPA1;
4794 I915_WRITE(dpll_reg, dpll); 4740 I915_WRITE(dpll_reg, dpll);
4795 dpll = I915_READ(dpll_reg); 4741 dpll = I915_READ(dpll_reg);
4796 intel_wait_for_vblank(dev); 4742 intel_wait_for_vblank(dev, pipe);
4797 dpll = I915_READ(dpll_reg); 4743 dpll = I915_READ(dpll_reg);
4798 if (!(dpll & DISPLAY_RATE_SELECT_FPA1)) 4744 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
4799 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n"); 4745 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
@@ -4916,15 +4862,6 @@ static void intel_crtc_destroy(struct drm_crtc *crtc)
4916 kfree(intel_crtc); 4862 kfree(intel_crtc);
4917} 4863}
4918 4864
4919struct intel_unpin_work {
4920 struct work_struct work;
4921 struct drm_device *dev;
4922 struct drm_gem_object *old_fb_obj;
4923 struct drm_gem_object *pending_flip_obj;
4924 struct drm_pending_vblank_event *event;
4925 int pending;
4926};
4927
4928static void intel_unpin_work_fn(struct work_struct *__work) 4865static void intel_unpin_work_fn(struct work_struct *__work)
4929{ 4866{
4930 struct intel_unpin_work *work = 4867 struct intel_unpin_work *work =
@@ -5012,7 +4949,8 @@ void intel_prepare_page_flip(struct drm_device *dev, int plane)
5012 4949
5013 spin_lock_irqsave(&dev->event_lock, flags); 4950 spin_lock_irqsave(&dev->event_lock, flags);
5014 if (intel_crtc->unpin_work) { 4951 if (intel_crtc->unpin_work) {
5015 intel_crtc->unpin_work->pending = 1; 4952 if ((++intel_crtc->unpin_work->pending) > 1)
4953 DRM_ERROR("Prepared flip multiple times\n");
5016 } else { 4954 } else {
5017 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n"); 4955 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
5018 } 4956 }
@@ -5031,9 +4969,9 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc,
5031 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 4969 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5032 struct intel_unpin_work *work; 4970 struct intel_unpin_work *work;
5033 unsigned long flags, offset; 4971 unsigned long flags, offset;
5034 int pipesrc_reg = (intel_crtc->pipe == 0) ? PIPEASRC : PIPEBSRC; 4972 int pipe = intel_crtc->pipe;
5035 int ret, pipesrc; 4973 u32 pf, pipesrc;
5036 u32 flip_mask; 4974 int ret;
5037 4975
5038 work = kzalloc(sizeof *work, GFP_KERNEL); 4976 work = kzalloc(sizeof *work, GFP_KERNEL);
5039 if (work == NULL) 4977 if (work == NULL)
@@ -5082,34 +5020,73 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc,
5082 atomic_inc(&obj_priv->pending_flip); 5020 atomic_inc(&obj_priv->pending_flip);
5083 work->pending_flip_obj = obj; 5021 work->pending_flip_obj = obj;
5084 5022
5085 if (intel_crtc->plane) 5023 if (IS_GEN3(dev) || IS_GEN2(dev)) {
5086 flip_mask = I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT; 5024 u32 flip_mask;
5087 else
5088 flip_mask = I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT;
5089 5025
5090 /* Wait for any previous flip to finish */ 5026 if (intel_crtc->plane)
5091 if (IS_GEN3(dev)) 5027 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
5092 while (I915_READ(ISR) & flip_mask) 5028 else
5093 ; 5029 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
5030
5031 BEGIN_LP_RING(2);
5032 OUT_RING(MI_WAIT_FOR_EVENT | flip_mask);
5033 OUT_RING(0);
5034 ADVANCE_LP_RING();
5035 }
5036
5037 work->enable_stall_check = true;
5094 5038
5095 /* Offset into the new buffer for cases of shared fbs between CRTCs */ 5039 /* Offset into the new buffer for cases of shared fbs between CRTCs */
5096 offset = obj_priv->gtt_offset; 5040 offset = crtc->y * fb->pitch + crtc->x * fb->bits_per_pixel/8;
5097 offset += (crtc->y * fb->pitch) + (crtc->x * (fb->bits_per_pixel) / 8);
5098 5041
5099 BEGIN_LP_RING(4); 5042 BEGIN_LP_RING(4);
5100 if (IS_I965G(dev)) { 5043 switch(INTEL_INFO(dev)->gen) {
5044 case 2:
5101 OUT_RING(MI_DISPLAY_FLIP | 5045 OUT_RING(MI_DISPLAY_FLIP |
5102 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); 5046 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5103 OUT_RING(fb->pitch); 5047 OUT_RING(fb->pitch);
5104 OUT_RING(offset | obj_priv->tiling_mode); 5048 OUT_RING(obj_priv->gtt_offset + offset);
5105 pipesrc = I915_READ(pipesrc_reg); 5049 OUT_RING(MI_NOOP);
5106 OUT_RING(pipesrc & 0x0fff0fff); 5050 break;
5107 } else { 5051
5052 case 3:
5108 OUT_RING(MI_DISPLAY_FLIP_I915 | 5053 OUT_RING(MI_DISPLAY_FLIP_I915 |
5109 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); 5054 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5110 OUT_RING(fb->pitch); 5055 OUT_RING(fb->pitch);
5111 OUT_RING(offset); 5056 OUT_RING(obj_priv->gtt_offset + offset);
5112 OUT_RING(MI_NOOP); 5057 OUT_RING(MI_NOOP);
5058 break;
5059
5060 case 4:
5061 case 5:
5062 /* i965+ uses the linear or tiled offsets from the
5063 * Display Registers (which do not change across a page-flip)
5064 * so we need only reprogram the base address.
5065 */
5066 OUT_RING(MI_DISPLAY_FLIP |
5067 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5068 OUT_RING(fb->pitch);
5069 OUT_RING(obj_priv->gtt_offset | obj_priv->tiling_mode);
5070
5071 /* XXX Enabling the panel-fitter across page-flip is so far
5072 * untested on non-native modes, so ignore it for now.
5073 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
5074 */
5075 pf = 0;
5076 pipesrc = I915_READ(pipe == 0 ? PIPEASRC : PIPEBSRC) & 0x0fff0fff;
5077 OUT_RING(pf | pipesrc);
5078 break;
5079
5080 case 6:
5081 OUT_RING(MI_DISPLAY_FLIP |
5082 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5083 OUT_RING(fb->pitch | obj_priv->tiling_mode);
5084 OUT_RING(obj_priv->gtt_offset);
5085
5086 pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
5087 pipesrc = I915_READ(pipe == 0 ? PIPEASRC : PIPEBSRC) & 0x0fff0fff;
5088 OUT_RING(pf | pipesrc);
5089 break;
5113 } 5090 }
5114 ADVANCE_LP_RING(); 5091 ADVANCE_LP_RING();
5115 5092
@@ -5190,7 +5167,7 @@ static void intel_crtc_init(struct drm_device *dev, int pipe)
5190 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base; 5167 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
5191 5168
5192 intel_crtc->cursor_addr = 0; 5169 intel_crtc->cursor_addr = 0;
5193 intel_crtc->dpms_mode = DRM_MODE_DPMS_OFF; 5170 intel_crtc->dpms_mode = -1;
5194 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs); 5171 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
5195 5172
5196 intel_crtc->busy = false; 5173 intel_crtc->busy = false;
@@ -5432,37 +5409,37 @@ static const struct drm_mode_config_funcs intel_mode_funcs = {
5432}; 5409};
5433 5410
5434static struct drm_gem_object * 5411static struct drm_gem_object *
5435intel_alloc_power_context(struct drm_device *dev) 5412intel_alloc_context_page(struct drm_device *dev)
5436{ 5413{
5437 struct drm_gem_object *pwrctx; 5414 struct drm_gem_object *ctx;
5438 int ret; 5415 int ret;
5439 5416
5440 pwrctx = i915_gem_alloc_object(dev, 4096); 5417 ctx = i915_gem_alloc_object(dev, 4096);
5441 if (!pwrctx) { 5418 if (!ctx) {
5442 DRM_DEBUG("failed to alloc power context, RC6 disabled\n"); 5419 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
5443 return NULL; 5420 return NULL;
5444 } 5421 }
5445 5422
5446 mutex_lock(&dev->struct_mutex); 5423 mutex_lock(&dev->struct_mutex);
5447 ret = i915_gem_object_pin(pwrctx, 4096); 5424 ret = i915_gem_object_pin(ctx, 4096);
5448 if (ret) { 5425 if (ret) {
5449 DRM_ERROR("failed to pin power context: %d\n", ret); 5426 DRM_ERROR("failed to pin power context: %d\n", ret);
5450 goto err_unref; 5427 goto err_unref;
5451 } 5428 }
5452 5429
5453 ret = i915_gem_object_set_to_gtt_domain(pwrctx, 1); 5430 ret = i915_gem_object_set_to_gtt_domain(ctx, 1);
5454 if (ret) { 5431 if (ret) {
5455 DRM_ERROR("failed to set-domain on power context: %d\n", ret); 5432 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
5456 goto err_unpin; 5433 goto err_unpin;
5457 } 5434 }
5458 mutex_unlock(&dev->struct_mutex); 5435 mutex_unlock(&dev->struct_mutex);
5459 5436
5460 return pwrctx; 5437 return ctx;
5461 5438
5462err_unpin: 5439err_unpin:
5463 i915_gem_object_unpin(pwrctx); 5440 i915_gem_object_unpin(ctx);
5464err_unref: 5441err_unref:
5465 drm_gem_object_unreference(pwrctx); 5442 drm_gem_object_unreference(ctx);
5466 mutex_unlock(&dev->struct_mutex); 5443 mutex_unlock(&dev->struct_mutex);
5467 return NULL; 5444 return NULL;
5468} 5445}
@@ -5494,7 +5471,6 @@ void ironlake_enable_drps(struct drm_device *dev)
5494 struct drm_i915_private *dev_priv = dev->dev_private; 5471 struct drm_i915_private *dev_priv = dev->dev_private;
5495 u32 rgvmodectl = I915_READ(MEMMODECTL); 5472 u32 rgvmodectl = I915_READ(MEMMODECTL);
5496 u8 fmax, fmin, fstart, vstart; 5473 u8 fmax, fmin, fstart, vstart;
5497 int i = 0;
5498 5474
5499 /* 100ms RC evaluation intervals */ 5475 /* 100ms RC evaluation intervals */
5500 I915_WRITE(RCUPEI, 100000); 5476 I915_WRITE(RCUPEI, 100000);
@@ -5538,13 +5514,8 @@ void ironlake_enable_drps(struct drm_device *dev)
5538 rgvmodectl |= MEMMODE_SWMODE_EN; 5514 rgvmodectl |= MEMMODE_SWMODE_EN;
5539 I915_WRITE(MEMMODECTL, rgvmodectl); 5515 I915_WRITE(MEMMODECTL, rgvmodectl);
5540 5516
5541 while (I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) { 5517 if (wait_for((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 1, 0))
5542 if (i++ > 100) { 5518 DRM_ERROR("stuck trying to change perf mode\n");
5543 DRM_ERROR("stuck trying to change perf mode\n");
5544 break;
5545 }
5546 msleep(1);
5547 }
5548 msleep(1); 5519 msleep(1);
5549 5520
5550 ironlake_set_drps(dev, fstart); 5521 ironlake_set_drps(dev, fstart);
@@ -5725,7 +5696,8 @@ void intel_init_clock_gating(struct drm_device *dev)
5725 ILK_DPFC_DIS2 | 5696 ILK_DPFC_DIS2 |
5726 ILK_CLK_FBC); 5697 ILK_CLK_FBC);
5727 } 5698 }
5728 return; 5699 if (IS_GEN6(dev))
5700 return;
5729 } else if (IS_G4X(dev)) { 5701 } else if (IS_G4X(dev)) {
5730 uint32_t dspclk_gate; 5702 uint32_t dspclk_gate;
5731 I915_WRITE(RENCLK_GATE_D1, 0); 5703 I915_WRITE(RENCLK_GATE_D1, 0);
@@ -5768,6 +5740,31 @@ void intel_init_clock_gating(struct drm_device *dev)
5768 * GPU can automatically power down the render unit if given a page 5740 * GPU can automatically power down the render unit if given a page
5769 * to save state. 5741 * to save state.
5770 */ 5742 */
5743 if (IS_IRONLAKE_M(dev)) {
5744 if (dev_priv->renderctx == NULL)
5745 dev_priv->renderctx = intel_alloc_context_page(dev);
5746 if (dev_priv->renderctx) {
5747 struct drm_i915_gem_object *obj_priv;
5748 obj_priv = to_intel_bo(dev_priv->renderctx);
5749 if (obj_priv) {
5750 BEGIN_LP_RING(4);
5751 OUT_RING(MI_SET_CONTEXT);
5752 OUT_RING(obj_priv->gtt_offset |
5753 MI_MM_SPACE_GTT |
5754 MI_SAVE_EXT_STATE_EN |
5755 MI_RESTORE_EXT_STATE_EN |
5756 MI_RESTORE_INHIBIT);
5757 OUT_RING(MI_NOOP);
5758 OUT_RING(MI_FLUSH);
5759 ADVANCE_LP_RING();
5760 }
5761 } else {
5762 DRM_DEBUG_KMS("Failed to allocate render context."
5763 "Disable RC6\n");
5764 return;
5765 }
5766 }
5767
5771 if (I915_HAS_RC6(dev) && drm_core_check_feature(dev, DRIVER_MODESET)) { 5768 if (I915_HAS_RC6(dev) && drm_core_check_feature(dev, DRIVER_MODESET)) {
5772 struct drm_i915_gem_object *obj_priv = NULL; 5769 struct drm_i915_gem_object *obj_priv = NULL;
5773 5770
@@ -5776,7 +5773,7 @@ void intel_init_clock_gating(struct drm_device *dev)
5776 } else { 5773 } else {
5777 struct drm_gem_object *pwrctx; 5774 struct drm_gem_object *pwrctx;
5778 5775
5779 pwrctx = intel_alloc_power_context(dev); 5776 pwrctx = intel_alloc_context_page(dev);
5780 if (pwrctx) { 5777 if (pwrctx) {
5781 dev_priv->pwrctx = pwrctx; 5778 dev_priv->pwrctx = pwrctx;
5782 obj_priv = to_intel_bo(pwrctx); 5779 obj_priv = to_intel_bo(pwrctx);
@@ -5948,6 +5945,29 @@ static void intel_init_quirks(struct drm_device *dev)
5948 } 5945 }
5949} 5946}
5950 5947
5948/* Disable the VGA plane that we never use */
5949static void i915_disable_vga(struct drm_device *dev)
5950{
5951 struct drm_i915_private *dev_priv = dev->dev_private;
5952 u8 sr1;
5953 u32 vga_reg;
5954
5955 if (HAS_PCH_SPLIT(dev))
5956 vga_reg = CPU_VGACNTRL;
5957 else
5958 vga_reg = VGACNTRL;
5959
5960 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
5961 outb(1, VGA_SR_INDEX);
5962 sr1 = inb(VGA_SR_DATA);
5963 outb(sr1 | 1<<5, VGA_SR_DATA);
5964 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
5965 udelay(300);
5966
5967 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
5968 POSTING_READ(vga_reg);
5969}
5970
5951void intel_modeset_init(struct drm_device *dev) 5971void intel_modeset_init(struct drm_device *dev)
5952{ 5972{
5953 struct drm_i915_private *dev_priv = dev->dev_private; 5973 struct drm_i915_private *dev_priv = dev->dev_private;
@@ -5996,6 +6016,9 @@ void intel_modeset_init(struct drm_device *dev)
5996 6016
5997 intel_init_clock_gating(dev); 6017 intel_init_clock_gating(dev);
5998 6018
6019 /* Just disable it once at startup */
6020 i915_disable_vga(dev);
6021
5999 if (IS_IRONLAKE_M(dev)) { 6022 if (IS_IRONLAKE_M(dev)) {
6000 ironlake_enable_drps(dev); 6023 ironlake_enable_drps(dev);
6001 intel_init_emon(dev); 6024 intel_init_emon(dev);
@@ -6034,6 +6057,16 @@ void intel_modeset_cleanup(struct drm_device *dev)
6034 if (dev_priv->display.disable_fbc) 6057 if (dev_priv->display.disable_fbc)
6035 dev_priv->display.disable_fbc(dev); 6058 dev_priv->display.disable_fbc(dev);
6036 6059
6060 if (dev_priv->renderctx) {
6061 struct drm_i915_gem_object *obj_priv;
6062
6063 obj_priv = to_intel_bo(dev_priv->renderctx);
6064 I915_WRITE(CCID, obj_priv->gtt_offset &~ CCID_EN);
6065 I915_READ(CCID);
6066 i915_gem_object_unpin(dev_priv->renderctx);
6067 drm_gem_object_unreference(dev_priv->renderctx);
6068 }
6069
6037 if (dev_priv->pwrctx) { 6070 if (dev_priv->pwrctx) {
6038 struct drm_i915_gem_object *obj_priv; 6071 struct drm_i915_gem_object *obj_priv;
6039 6072
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 40be1fa65be1..51d142939a26 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -42,10 +42,11 @@
42 42
43#define DP_LINK_CONFIGURATION_SIZE 9 43#define DP_LINK_CONFIGURATION_SIZE 9
44 44
45#define IS_eDP(i) ((i)->type == INTEL_OUTPUT_EDP) 45#define IS_eDP(i) ((i)->base.type == INTEL_OUTPUT_EDP)
46#define IS_PCH_eDP(dp_priv) ((dp_priv)->is_pch_edp) 46#define IS_PCH_eDP(i) ((i)->is_pch_edp)
47 47
48struct intel_dp_priv { 48struct intel_dp {
49 struct intel_encoder base;
49 uint32_t output_reg; 50 uint32_t output_reg;
50 uint32_t DP; 51 uint32_t DP;
51 uint8_t link_configuration[DP_LINK_CONFIGURATION_SIZE]; 52 uint8_t link_configuration[DP_LINK_CONFIGURATION_SIZE];
@@ -54,40 +55,39 @@ struct intel_dp_priv {
54 uint8_t link_bw; 55 uint8_t link_bw;
55 uint8_t lane_count; 56 uint8_t lane_count;
56 uint8_t dpcd[4]; 57 uint8_t dpcd[4];
57 struct intel_encoder *intel_encoder;
58 struct i2c_adapter adapter; 58 struct i2c_adapter adapter;
59 struct i2c_algo_dp_aux_data algo; 59 struct i2c_algo_dp_aux_data algo;
60 bool is_pch_edp; 60 bool is_pch_edp;
61}; 61};
62 62
63static void 63static struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
64intel_dp_link_train(struct intel_encoder *intel_encoder, uint32_t DP, 64{
65 uint8_t link_configuration[DP_LINK_CONFIGURATION_SIZE]); 65 return container_of(enc_to_intel_encoder(encoder), struct intel_dp, base);
66}
66 67
67static void 68static void intel_dp_link_train(struct intel_dp *intel_dp);
68intel_dp_link_down(struct intel_encoder *intel_encoder, uint32_t DP); 69static void intel_dp_link_down(struct intel_dp *intel_dp);
69 70
70void 71void
71intel_edp_link_config (struct intel_encoder *intel_encoder, 72intel_edp_link_config (struct intel_encoder *intel_encoder,
72 int *lane_num, int *link_bw) 73 int *lane_num, int *link_bw)
73{ 74{
74 struct intel_dp_priv *dp_priv = intel_encoder->dev_priv; 75 struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base);
75 76
76 *lane_num = dp_priv->lane_count; 77 *lane_num = intel_dp->lane_count;
77 if (dp_priv->link_bw == DP_LINK_BW_1_62) 78 if (intel_dp->link_bw == DP_LINK_BW_1_62)
78 *link_bw = 162000; 79 *link_bw = 162000;
79 else if (dp_priv->link_bw == DP_LINK_BW_2_7) 80 else if (intel_dp->link_bw == DP_LINK_BW_2_7)
80 *link_bw = 270000; 81 *link_bw = 270000;
81} 82}
82 83
83static int 84static int
84intel_dp_max_lane_count(struct intel_encoder *intel_encoder) 85intel_dp_max_lane_count(struct intel_dp *intel_dp)
85{ 86{
86 struct intel_dp_priv *dp_priv = intel_encoder->dev_priv;
87 int max_lane_count = 4; 87 int max_lane_count = 4;
88 88
89 if (dp_priv->dpcd[0] >= 0x11) { 89 if (intel_dp->dpcd[0] >= 0x11) {
90 max_lane_count = dp_priv->dpcd[2] & 0x1f; 90 max_lane_count = intel_dp->dpcd[2] & 0x1f;
91 switch (max_lane_count) { 91 switch (max_lane_count) {
92 case 1: case 2: case 4: 92 case 1: case 2: case 4:
93 break; 93 break;
@@ -99,10 +99,9 @@ intel_dp_max_lane_count(struct intel_encoder *intel_encoder)
99} 99}
100 100
101static int 101static int
102intel_dp_max_link_bw(struct intel_encoder *intel_encoder) 102intel_dp_max_link_bw(struct intel_dp *intel_dp)
103{ 103{
104 struct intel_dp_priv *dp_priv = intel_encoder->dev_priv; 104 int max_link_bw = intel_dp->dpcd[1];
105 int max_link_bw = dp_priv->dpcd[1];
106 105
107 switch (max_link_bw) { 106 switch (max_link_bw) {
108 case DP_LINK_BW_1_62: 107 case DP_LINK_BW_1_62:
@@ -126,13 +125,11 @@ intel_dp_link_clock(uint8_t link_bw)
126 125
127/* I think this is a fiction */ 126/* I think this is a fiction */
128static int 127static int
129intel_dp_link_required(struct drm_device *dev, 128intel_dp_link_required(struct drm_device *dev, struct intel_dp *intel_dp, int pixel_clock)
130 struct intel_encoder *intel_encoder, int pixel_clock)
131{ 129{
132 struct drm_i915_private *dev_priv = dev->dev_private; 130 struct drm_i915_private *dev_priv = dev->dev_private;
133 struct intel_dp_priv *dp_priv = intel_encoder->dev_priv;
134 131
135 if (IS_eDP(intel_encoder) || IS_PCH_eDP(dp_priv)) 132 if (IS_eDP(intel_dp) || IS_PCH_eDP(intel_dp))
136 return (pixel_clock * dev_priv->edp_bpp) / 8; 133 return (pixel_clock * dev_priv->edp_bpp) / 8;
137 else 134 else
138 return pixel_clock * 3; 135 return pixel_clock * 3;
@@ -149,14 +146,13 @@ intel_dp_mode_valid(struct drm_connector *connector,
149 struct drm_display_mode *mode) 146 struct drm_display_mode *mode)
150{ 147{
151 struct drm_encoder *encoder = intel_attached_encoder(connector); 148 struct drm_encoder *encoder = intel_attached_encoder(connector);
152 struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder); 149 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
153 struct intel_dp_priv *dp_priv = intel_encoder->dev_priv;
154 struct drm_device *dev = connector->dev; 150 struct drm_device *dev = connector->dev;
155 struct drm_i915_private *dev_priv = dev->dev_private; 151 struct drm_i915_private *dev_priv = dev->dev_private;
156 int max_link_clock = intel_dp_link_clock(intel_dp_max_link_bw(intel_encoder)); 152 int max_link_clock = intel_dp_link_clock(intel_dp_max_link_bw(intel_dp));
157 int max_lanes = intel_dp_max_lane_count(intel_encoder); 153 int max_lanes = intel_dp_max_lane_count(intel_dp);
158 154
159 if ((IS_eDP(intel_encoder) || IS_PCH_eDP(dp_priv)) && 155 if ((IS_eDP(intel_dp) || IS_PCH_eDP(intel_dp)) &&
160 dev_priv->panel_fixed_mode) { 156 dev_priv->panel_fixed_mode) {
161 if (mode->hdisplay > dev_priv->panel_fixed_mode->hdisplay) 157 if (mode->hdisplay > dev_priv->panel_fixed_mode->hdisplay)
162 return MODE_PANEL; 158 return MODE_PANEL;
@@ -167,8 +163,8 @@ intel_dp_mode_valid(struct drm_connector *connector,
167 163
168 /* only refuse the mode on non eDP since we have seen some wierd eDP panels 164 /* only refuse the mode on non eDP since we have seen some wierd eDP panels
169 which are outside spec tolerances but somehow work by magic */ 165 which are outside spec tolerances but somehow work by magic */
170 if (!IS_eDP(intel_encoder) && 166 if (!IS_eDP(intel_dp) &&
171 (intel_dp_link_required(connector->dev, intel_encoder, mode->clock) 167 (intel_dp_link_required(connector->dev, intel_dp, mode->clock)
172 > intel_dp_max_data_rate(max_link_clock, max_lanes))) 168 > intel_dp_max_data_rate(max_link_clock, max_lanes)))
173 return MODE_CLOCK_HIGH; 169 return MODE_CLOCK_HIGH;
174 170
@@ -232,19 +228,17 @@ intel_hrawclk(struct drm_device *dev)
232} 228}
233 229
234static int 230static int
235intel_dp_aux_ch(struct intel_encoder *intel_encoder, 231intel_dp_aux_ch(struct intel_dp *intel_dp,
236 uint8_t *send, int send_bytes, 232 uint8_t *send, int send_bytes,
237 uint8_t *recv, int recv_size) 233 uint8_t *recv, int recv_size)
238{ 234{
239 struct intel_dp_priv *dp_priv = intel_encoder->dev_priv; 235 uint32_t output_reg = intel_dp->output_reg;
240 uint32_t output_reg = dp_priv->output_reg; 236 struct drm_device *dev = intel_dp->base.enc.dev;
241 struct drm_device *dev = intel_encoder->enc.dev;
242 struct drm_i915_private *dev_priv = dev->dev_private; 237 struct drm_i915_private *dev_priv = dev->dev_private;
243 uint32_t ch_ctl = output_reg + 0x10; 238 uint32_t ch_ctl = output_reg + 0x10;
244 uint32_t ch_data = ch_ctl + 4; 239 uint32_t ch_data = ch_ctl + 4;
245 int i; 240 int i;
246 int recv_bytes; 241 int recv_bytes;
247 uint32_t ctl;
248 uint32_t status; 242 uint32_t status;
249 uint32_t aux_clock_divider; 243 uint32_t aux_clock_divider;
250 int try, precharge; 244 int try, precharge;
@@ -253,7 +247,7 @@ intel_dp_aux_ch(struct intel_encoder *intel_encoder,
253 * and would like to run at 2MHz. So, take the 247 * and would like to run at 2MHz. So, take the
254 * hrawclk value and divide by 2 and use that 248 * hrawclk value and divide by 2 and use that
255 */ 249 */
256 if (IS_eDP(intel_encoder)) { 250 if (IS_eDP(intel_dp)) {
257 if (IS_GEN6(dev)) 251 if (IS_GEN6(dev))
258 aux_clock_divider = 200; /* SNB eDP input clock at 400Mhz */ 252 aux_clock_divider = 200; /* SNB eDP input clock at 400Mhz */
259 else 253 else
@@ -268,41 +262,43 @@ intel_dp_aux_ch(struct intel_encoder *intel_encoder,
268 else 262 else
269 precharge = 5; 263 precharge = 5;
270 264
265 if (I915_READ(ch_ctl) & DP_AUX_CH_CTL_SEND_BUSY) {
266 DRM_ERROR("dp_aux_ch not started status 0x%08x\n",
267 I915_READ(ch_ctl));
268 return -EBUSY;
269 }
270
271 /* Must try at least 3 times according to DP spec */ 271 /* Must try at least 3 times according to DP spec */
272 for (try = 0; try < 5; try++) { 272 for (try = 0; try < 5; try++) {
273 /* Load the send data into the aux channel data registers */ 273 /* Load the send data into the aux channel data registers */
274 for (i = 0; i < send_bytes; i += 4) { 274 for (i = 0; i < send_bytes; i += 4)
275 uint32_t d = pack_aux(send + i, send_bytes - i); 275 I915_WRITE(ch_data + i,
276 276 pack_aux(send + i, send_bytes - i));
277 I915_WRITE(ch_data + i, d);
278 }
279
280 ctl = (DP_AUX_CH_CTL_SEND_BUSY |
281 DP_AUX_CH_CTL_TIME_OUT_400us |
282 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
283 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
284 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) |
285 DP_AUX_CH_CTL_DONE |
286 DP_AUX_CH_CTL_TIME_OUT_ERROR |
287 DP_AUX_CH_CTL_RECEIVE_ERROR);
288 277
289 /* Send the command and wait for it to complete */ 278 /* Send the command and wait for it to complete */
290 I915_WRITE(ch_ctl, ctl); 279 I915_WRITE(ch_ctl,
291 (void) I915_READ(ch_ctl); 280 DP_AUX_CH_CTL_SEND_BUSY |
281 DP_AUX_CH_CTL_TIME_OUT_400us |
282 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
283 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
284 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) |
285 DP_AUX_CH_CTL_DONE |
286 DP_AUX_CH_CTL_TIME_OUT_ERROR |
287 DP_AUX_CH_CTL_RECEIVE_ERROR);
292 for (;;) { 288 for (;;) {
293 udelay(100);
294 status = I915_READ(ch_ctl); 289 status = I915_READ(ch_ctl);
295 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0) 290 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
296 break; 291 break;
292 udelay(100);
297 } 293 }
298 294
299 /* Clear done status and any errors */ 295 /* Clear done status and any errors */
300 I915_WRITE(ch_ctl, (status | 296 I915_WRITE(ch_ctl,
301 DP_AUX_CH_CTL_DONE | 297 status |
302 DP_AUX_CH_CTL_TIME_OUT_ERROR | 298 DP_AUX_CH_CTL_DONE |
303 DP_AUX_CH_CTL_RECEIVE_ERROR)); 299 DP_AUX_CH_CTL_TIME_OUT_ERROR |
304 (void) I915_READ(ch_ctl); 300 DP_AUX_CH_CTL_RECEIVE_ERROR);
305 if ((status & DP_AUX_CH_CTL_TIME_OUT_ERROR) == 0) 301 if (status & DP_AUX_CH_CTL_DONE)
306 break; 302 break;
307 } 303 }
308 304
@@ -329,22 +325,19 @@ intel_dp_aux_ch(struct intel_encoder *intel_encoder,
329 /* Unload any bytes sent back from the other side */ 325 /* Unload any bytes sent back from the other side */
330 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >> 326 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
331 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT); 327 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
332
333 if (recv_bytes > recv_size) 328 if (recv_bytes > recv_size)
334 recv_bytes = recv_size; 329 recv_bytes = recv_size;
335 330
336 for (i = 0; i < recv_bytes; i += 4) { 331 for (i = 0; i < recv_bytes; i += 4)
337 uint32_t d = I915_READ(ch_data + i); 332 unpack_aux(I915_READ(ch_data + i),
338 333 recv + i, recv_bytes - i);
339 unpack_aux(d, recv + i, recv_bytes - i);
340 }
341 334
342 return recv_bytes; 335 return recv_bytes;
343} 336}
344 337
345/* Write data to the aux channel in native mode */ 338/* Write data to the aux channel in native mode */
346static int 339static int
347intel_dp_aux_native_write(struct intel_encoder *intel_encoder, 340intel_dp_aux_native_write(struct intel_dp *intel_dp,
348 uint16_t address, uint8_t *send, int send_bytes) 341 uint16_t address, uint8_t *send, int send_bytes)
349{ 342{
350 int ret; 343 int ret;
@@ -361,7 +354,7 @@ intel_dp_aux_native_write(struct intel_encoder *intel_encoder,
361 memcpy(&msg[4], send, send_bytes); 354 memcpy(&msg[4], send, send_bytes);
362 msg_bytes = send_bytes + 4; 355 msg_bytes = send_bytes + 4;
363 for (;;) { 356 for (;;) {
364 ret = intel_dp_aux_ch(intel_encoder, msg, msg_bytes, &ack, 1); 357 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, &ack, 1);
365 if (ret < 0) 358 if (ret < 0)
366 return ret; 359 return ret;
367 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) 360 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)
@@ -376,15 +369,15 @@ intel_dp_aux_native_write(struct intel_encoder *intel_encoder,
376 369
377/* Write a single byte to the aux channel in native mode */ 370/* Write a single byte to the aux channel in native mode */
378static int 371static int
379intel_dp_aux_native_write_1(struct intel_encoder *intel_encoder, 372intel_dp_aux_native_write_1(struct intel_dp *intel_dp,
380 uint16_t address, uint8_t byte) 373 uint16_t address, uint8_t byte)
381{ 374{
382 return intel_dp_aux_native_write(intel_encoder, address, &byte, 1); 375 return intel_dp_aux_native_write(intel_dp, address, &byte, 1);
383} 376}
384 377
385/* read bytes from a native aux channel */ 378/* read bytes from a native aux channel */
386static int 379static int
387intel_dp_aux_native_read(struct intel_encoder *intel_encoder, 380intel_dp_aux_native_read(struct intel_dp *intel_dp,
388 uint16_t address, uint8_t *recv, int recv_bytes) 381 uint16_t address, uint8_t *recv, int recv_bytes)
389{ 382{
390 uint8_t msg[4]; 383 uint8_t msg[4];
@@ -403,7 +396,7 @@ intel_dp_aux_native_read(struct intel_encoder *intel_encoder,
403 reply_bytes = recv_bytes + 1; 396 reply_bytes = recv_bytes + 1;
404 397
405 for (;;) { 398 for (;;) {
406 ret = intel_dp_aux_ch(intel_encoder, msg, msg_bytes, 399 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes,
407 reply, reply_bytes); 400 reply, reply_bytes);
408 if (ret == 0) 401 if (ret == 0)
409 return -EPROTO; 402 return -EPROTO;
@@ -426,10 +419,9 @@ intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
426 uint8_t write_byte, uint8_t *read_byte) 419 uint8_t write_byte, uint8_t *read_byte)
427{ 420{
428 struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data; 421 struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
429 struct intel_dp_priv *dp_priv = container_of(adapter, 422 struct intel_dp *intel_dp = container_of(adapter,
430 struct intel_dp_priv, 423 struct intel_dp,
431 adapter); 424 adapter);
432 struct intel_encoder *intel_encoder = dp_priv->intel_encoder;
433 uint16_t address = algo_data->address; 425 uint16_t address = algo_data->address;
434 uint8_t msg[5]; 426 uint8_t msg[5];
435 uint8_t reply[2]; 427 uint8_t reply[2];
@@ -468,7 +460,7 @@ intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
468 } 460 }
469 461
470 for (;;) { 462 for (;;) {
471 ret = intel_dp_aux_ch(intel_encoder, 463 ret = intel_dp_aux_ch(intel_dp,
472 msg, msg_bytes, 464 msg, msg_bytes,
473 reply, reply_bytes); 465 reply, reply_bytes);
474 if (ret < 0) { 466 if (ret < 0) {
@@ -496,57 +488,42 @@ intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
496} 488}
497 489
498static int 490static int
499intel_dp_i2c_init(struct intel_encoder *intel_encoder, 491intel_dp_i2c_init(struct intel_dp *intel_dp,
500 struct intel_connector *intel_connector, const char *name) 492 struct intel_connector *intel_connector, const char *name)
501{ 493{
502 struct intel_dp_priv *dp_priv = intel_encoder->dev_priv;
503
504 DRM_DEBUG_KMS("i2c_init %s\n", name); 494 DRM_DEBUG_KMS("i2c_init %s\n", name);
505 dp_priv->algo.running = false; 495 intel_dp->algo.running = false;
506 dp_priv->algo.address = 0; 496 intel_dp->algo.address = 0;
507 dp_priv->algo.aux_ch = intel_dp_i2c_aux_ch; 497 intel_dp->algo.aux_ch = intel_dp_i2c_aux_ch;
508 498
509 memset(&dp_priv->adapter, '\0', sizeof (dp_priv->adapter)); 499 memset(&intel_dp->adapter, '\0', sizeof (intel_dp->adapter));
510 dp_priv->adapter.owner = THIS_MODULE; 500 intel_dp->adapter.owner = THIS_MODULE;
511 dp_priv->adapter.class = I2C_CLASS_DDC; 501 intel_dp->adapter.class = I2C_CLASS_DDC;
512 strncpy (dp_priv->adapter.name, name, sizeof(dp_priv->adapter.name) - 1); 502 strncpy (intel_dp->adapter.name, name, sizeof(intel_dp->adapter.name) - 1);
513 dp_priv->adapter.name[sizeof(dp_priv->adapter.name) - 1] = '\0'; 503 intel_dp->adapter.name[sizeof(intel_dp->adapter.name) - 1] = '\0';
514 dp_priv->adapter.algo_data = &dp_priv->algo; 504 intel_dp->adapter.algo_data = &intel_dp->algo;
515 dp_priv->adapter.dev.parent = &intel_connector->base.kdev; 505 intel_dp->adapter.dev.parent = &intel_connector->base.kdev;
516 506
517 return i2c_dp_aux_add_bus(&dp_priv->adapter); 507 return i2c_dp_aux_add_bus(&intel_dp->adapter);
518} 508}
519 509
520static bool 510static bool
521intel_dp_mode_fixup(struct drm_encoder *encoder, struct drm_display_mode *mode, 511intel_dp_mode_fixup(struct drm_encoder *encoder, struct drm_display_mode *mode,
522 struct drm_display_mode *adjusted_mode) 512 struct drm_display_mode *adjusted_mode)
523{ 513{
524 struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
525 struct intel_dp_priv *dp_priv = intel_encoder->dev_priv;
526 struct drm_device *dev = encoder->dev; 514 struct drm_device *dev = encoder->dev;
527 struct drm_i915_private *dev_priv = dev->dev_private; 515 struct drm_i915_private *dev_priv = dev->dev_private;
516 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
528 int lane_count, clock; 517 int lane_count, clock;
529 int max_lane_count = intel_dp_max_lane_count(intel_encoder); 518 int max_lane_count = intel_dp_max_lane_count(intel_dp);
530 int max_clock = intel_dp_max_link_bw(intel_encoder) == DP_LINK_BW_2_7 ? 1 : 0; 519 int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0;
531 static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 }; 520 static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 };
532 521
533 if ((IS_eDP(intel_encoder) || IS_PCH_eDP(dp_priv)) && 522 if ((IS_eDP(intel_dp) || IS_PCH_eDP(intel_dp)) &&
534 dev_priv->panel_fixed_mode) { 523 dev_priv->panel_fixed_mode) {
535 struct drm_display_mode *fixed_mode = dev_priv->panel_fixed_mode; 524 intel_fixed_panel_mode(dev_priv->panel_fixed_mode, adjusted_mode);
536 525 intel_pch_panel_fitting(dev, DRM_MODE_SCALE_FULLSCREEN,
537 adjusted_mode->hdisplay = fixed_mode->hdisplay; 526 mode, adjusted_mode);
538 adjusted_mode->hsync_start = fixed_mode->hsync_start;
539 adjusted_mode->hsync_end = fixed_mode->hsync_end;
540 adjusted_mode->htotal = fixed_mode->htotal;
541
542 adjusted_mode->vdisplay = fixed_mode->vdisplay;
543 adjusted_mode->vsync_start = fixed_mode->vsync_start;
544 adjusted_mode->vsync_end = fixed_mode->vsync_end;
545 adjusted_mode->vtotal = fixed_mode->vtotal;
546
547 adjusted_mode->clock = fixed_mode->clock;
548 drm_mode_set_crtcinfo(adjusted_mode, CRTC_INTERLACE_HALVE_V);
549
550 /* 527 /*
551 * the mode->clock is used to calculate the Data&Link M/N 528 * the mode->clock is used to calculate the Data&Link M/N
552 * of the pipe. For the eDP the fixed clock should be used. 529 * of the pipe. For the eDP the fixed clock should be used.
@@ -558,31 +535,33 @@ intel_dp_mode_fixup(struct drm_encoder *encoder, struct drm_display_mode *mode,
558 for (clock = 0; clock <= max_clock; clock++) { 535 for (clock = 0; clock <= max_clock; clock++) {
559 int link_avail = intel_dp_max_data_rate(intel_dp_link_clock(bws[clock]), lane_count); 536 int link_avail = intel_dp_max_data_rate(intel_dp_link_clock(bws[clock]), lane_count);
560 537
561 if (intel_dp_link_required(encoder->dev, intel_encoder, mode->clock) 538 if (intel_dp_link_required(encoder->dev, intel_dp, mode->clock)
562 <= link_avail) { 539 <= link_avail) {
563 dp_priv->link_bw = bws[clock]; 540 intel_dp->link_bw = bws[clock];
564 dp_priv->lane_count = lane_count; 541 intel_dp->lane_count = lane_count;
565 adjusted_mode->clock = intel_dp_link_clock(dp_priv->link_bw); 542 adjusted_mode->clock = intel_dp_link_clock(intel_dp->link_bw);
566 DRM_DEBUG_KMS("Display port link bw %02x lane " 543 DRM_DEBUG_KMS("Display port link bw %02x lane "
567 "count %d clock %d\n", 544 "count %d clock %d\n",
568 dp_priv->link_bw, dp_priv->lane_count, 545 intel_dp->link_bw, intel_dp->lane_count,
569 adjusted_mode->clock); 546 adjusted_mode->clock);
570 return true; 547 return true;
571 } 548 }
572 } 549 }
573 } 550 }
574 551
575 if (IS_eDP(intel_encoder) || IS_PCH_eDP(dp_priv)) { 552 if (IS_eDP(intel_dp) || IS_PCH_eDP(intel_dp)) {
576 /* okay we failed just pick the highest */ 553 /* okay we failed just pick the highest */
577 dp_priv->lane_count = max_lane_count; 554 intel_dp->lane_count = max_lane_count;
578 dp_priv->link_bw = bws[max_clock]; 555 intel_dp->link_bw = bws[max_clock];
579 adjusted_mode->clock = intel_dp_link_clock(dp_priv->link_bw); 556 adjusted_mode->clock = intel_dp_link_clock(intel_dp->link_bw);
580 DRM_DEBUG_KMS("Force picking display port link bw %02x lane " 557 DRM_DEBUG_KMS("Force picking display port link bw %02x lane "
581 "count %d clock %d\n", 558 "count %d clock %d\n",
582 dp_priv->link_bw, dp_priv->lane_count, 559 intel_dp->link_bw, intel_dp->lane_count,
583 adjusted_mode->clock); 560 adjusted_mode->clock);
561
584 return true; 562 return true;
585 } 563 }
564
586 return false; 565 return false;
587} 566}
588 567
@@ -626,17 +605,14 @@ bool intel_pch_has_edp(struct drm_crtc *crtc)
626 struct drm_encoder *encoder; 605 struct drm_encoder *encoder;
627 606
628 list_for_each_entry(encoder, &mode_config->encoder_list, head) { 607 list_for_each_entry(encoder, &mode_config->encoder_list, head) {
629 struct intel_encoder *intel_encoder; 608 struct intel_dp *intel_dp;
630 struct intel_dp_priv *dp_priv;
631 609
632 if (!encoder || encoder->crtc != crtc) 610 if (encoder->crtc != crtc)
633 continue; 611 continue;
634 612
635 intel_encoder = enc_to_intel_encoder(encoder); 613 intel_dp = enc_to_intel_dp(encoder);
636 dp_priv = intel_encoder->dev_priv; 614 if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT)
637 615 return intel_dp->is_pch_edp;
638 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT)
639 return dp_priv->is_pch_edp;
640 } 616 }
641 return false; 617 return false;
642} 618}
@@ -657,18 +633,15 @@ intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode,
657 * Find the lane count in the intel_encoder private 633 * Find the lane count in the intel_encoder private
658 */ 634 */
659 list_for_each_entry(encoder, &mode_config->encoder_list, head) { 635 list_for_each_entry(encoder, &mode_config->encoder_list, head) {
660 struct intel_encoder *intel_encoder; 636 struct intel_dp *intel_dp;
661 struct intel_dp_priv *dp_priv;
662 637
663 if (encoder->crtc != crtc) 638 if (encoder->crtc != crtc)
664 continue; 639 continue;
665 640
666 intel_encoder = enc_to_intel_encoder(encoder); 641 intel_dp = enc_to_intel_dp(encoder);
667 dp_priv = intel_encoder->dev_priv; 642 if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT) {
668 643 lane_count = intel_dp->lane_count;
669 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT) { 644 if (IS_PCH_eDP(intel_dp))
670 lane_count = dp_priv->lane_count;
671 if (IS_PCH_eDP(dp_priv))
672 bpp = dev_priv->edp_bpp; 645 bpp = dev_priv->edp_bpp;
673 break; 646 break;
674 } 647 }
@@ -724,107 +697,114 @@ intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
724 struct drm_display_mode *adjusted_mode) 697 struct drm_display_mode *adjusted_mode)
725{ 698{
726 struct drm_device *dev = encoder->dev; 699 struct drm_device *dev = encoder->dev;
727 struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder); 700 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
728 struct intel_dp_priv *dp_priv = intel_encoder->dev_priv; 701 struct drm_crtc *crtc = intel_dp->base.enc.crtc;
729 struct drm_crtc *crtc = intel_encoder->enc.crtc;
730 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 702 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
731 703
732 dp_priv->DP = (DP_VOLTAGE_0_4 | 704 intel_dp->DP = (DP_VOLTAGE_0_4 |
733 DP_PRE_EMPHASIS_0); 705 DP_PRE_EMPHASIS_0);
734 706
735 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) 707 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
736 dp_priv->DP |= DP_SYNC_HS_HIGH; 708 intel_dp->DP |= DP_SYNC_HS_HIGH;
737 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) 709 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
738 dp_priv->DP |= DP_SYNC_VS_HIGH; 710 intel_dp->DP |= DP_SYNC_VS_HIGH;
739 711
740 if (HAS_PCH_CPT(dev) && !IS_eDP(intel_encoder)) 712 if (HAS_PCH_CPT(dev) && !IS_eDP(intel_dp))
741 dp_priv->DP |= DP_LINK_TRAIN_OFF_CPT; 713 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
742 else 714 else
743 dp_priv->DP |= DP_LINK_TRAIN_OFF; 715 intel_dp->DP |= DP_LINK_TRAIN_OFF;
744 716
745 switch (dp_priv->lane_count) { 717 switch (intel_dp->lane_count) {
746 case 1: 718 case 1:
747 dp_priv->DP |= DP_PORT_WIDTH_1; 719 intel_dp->DP |= DP_PORT_WIDTH_1;
748 break; 720 break;
749 case 2: 721 case 2:
750 dp_priv->DP |= DP_PORT_WIDTH_2; 722 intel_dp->DP |= DP_PORT_WIDTH_2;
751 break; 723 break;
752 case 4: 724 case 4:
753 dp_priv->DP |= DP_PORT_WIDTH_4; 725 intel_dp->DP |= DP_PORT_WIDTH_4;
754 break; 726 break;
755 } 727 }
756 if (dp_priv->has_audio) 728 if (intel_dp->has_audio)
757 dp_priv->DP |= DP_AUDIO_OUTPUT_ENABLE; 729 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
758 730
759 memset(dp_priv->link_configuration, 0, DP_LINK_CONFIGURATION_SIZE); 731 memset(intel_dp->link_configuration, 0, DP_LINK_CONFIGURATION_SIZE);
760 dp_priv->link_configuration[0] = dp_priv->link_bw; 732 intel_dp->link_configuration[0] = intel_dp->link_bw;
761 dp_priv->link_configuration[1] = dp_priv->lane_count; 733 intel_dp->link_configuration[1] = intel_dp->lane_count;
762 734
763 /* 735 /*
764 * Check for DPCD version > 1.1 and enhanced framing support 736 * Check for DPCD version > 1.1 and enhanced framing support
765 */ 737 */
766 if (dp_priv->dpcd[0] >= 0x11 && (dp_priv->dpcd[2] & DP_ENHANCED_FRAME_CAP)) { 738 if (intel_dp->dpcd[0] >= 0x11 && (intel_dp->dpcd[2] & DP_ENHANCED_FRAME_CAP)) {
767 dp_priv->link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN; 739 intel_dp->link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
768 dp_priv->DP |= DP_ENHANCED_FRAMING; 740 intel_dp->DP |= DP_ENHANCED_FRAMING;
769 } 741 }
770 742
771 /* CPT DP's pipe select is decided in TRANS_DP_CTL */ 743 /* CPT DP's pipe select is decided in TRANS_DP_CTL */
772 if (intel_crtc->pipe == 1 && !HAS_PCH_CPT(dev)) 744 if (intel_crtc->pipe == 1 && !HAS_PCH_CPT(dev))
773 dp_priv->DP |= DP_PIPEB_SELECT; 745 intel_dp->DP |= DP_PIPEB_SELECT;
774 746
775 if (IS_eDP(intel_encoder)) { 747 if (IS_eDP(intel_dp)) {
776 /* don't miss out required setting for eDP */ 748 /* don't miss out required setting for eDP */
777 dp_priv->DP |= DP_PLL_ENABLE; 749 intel_dp->DP |= DP_PLL_ENABLE;
778 if (adjusted_mode->clock < 200000) 750 if (adjusted_mode->clock < 200000)
779 dp_priv->DP |= DP_PLL_FREQ_160MHZ; 751 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
780 else 752 else
781 dp_priv->DP |= DP_PLL_FREQ_270MHZ; 753 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
782 } 754 }
783} 755}
784 756
785static void ironlake_edp_panel_on (struct drm_device *dev) 757static void ironlake_edp_panel_on (struct drm_device *dev)
786{ 758{
787 struct drm_i915_private *dev_priv = dev->dev_private; 759 struct drm_i915_private *dev_priv = dev->dev_private;
788 unsigned long timeout = jiffies + msecs_to_jiffies(5000); 760 u32 pp;
789 u32 pp, pp_status;
790 761
791 pp_status = I915_READ(PCH_PP_STATUS); 762 if (I915_READ(PCH_PP_STATUS) & PP_ON)
792 if (pp_status & PP_ON)
793 return; 763 return;
794 764
795 pp = I915_READ(PCH_PP_CONTROL); 765 pp = I915_READ(PCH_PP_CONTROL);
766
767 /* ILK workaround: disable reset around power sequence */
768 pp &= ~PANEL_POWER_RESET;
769 I915_WRITE(PCH_PP_CONTROL, pp);
770 POSTING_READ(PCH_PP_CONTROL);
771
796 pp |= PANEL_UNLOCK_REGS | POWER_TARGET_ON; 772 pp |= PANEL_UNLOCK_REGS | POWER_TARGET_ON;
797 I915_WRITE(PCH_PP_CONTROL, pp); 773 I915_WRITE(PCH_PP_CONTROL, pp);
798 do {
799 pp_status = I915_READ(PCH_PP_STATUS);
800 } while (((pp_status & PP_ON) == 0) && !time_after(jiffies, timeout));
801 774
802 if (time_after(jiffies, timeout)) 775 if (wait_for(I915_READ(PCH_PP_STATUS) & PP_ON, 5000, 10))
803 DRM_DEBUG_KMS("panel on wait timed out: 0x%08x\n", pp_status); 776 DRM_ERROR("panel on wait timed out: 0x%08x\n",
777 I915_READ(PCH_PP_STATUS));
804 778
805 pp &= ~(PANEL_UNLOCK_REGS | EDP_FORCE_VDD); 779 pp &= ~(PANEL_UNLOCK_REGS | EDP_FORCE_VDD);
780 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
806 I915_WRITE(PCH_PP_CONTROL, pp); 781 I915_WRITE(PCH_PP_CONTROL, pp);
782 POSTING_READ(PCH_PP_CONTROL);
807} 783}
808 784
809static void ironlake_edp_panel_off (struct drm_device *dev) 785static void ironlake_edp_panel_off (struct drm_device *dev)
810{ 786{
811 struct drm_i915_private *dev_priv = dev->dev_private; 787 struct drm_i915_private *dev_priv = dev->dev_private;
812 unsigned long timeout = jiffies + msecs_to_jiffies(5000); 788 u32 pp;
813 u32 pp, pp_status;
814 789
815 pp = I915_READ(PCH_PP_CONTROL); 790 pp = I915_READ(PCH_PP_CONTROL);
791
792 /* ILK workaround: disable reset around power sequence */
793 pp &= ~PANEL_POWER_RESET;
794 I915_WRITE(PCH_PP_CONTROL, pp);
795 POSTING_READ(PCH_PP_CONTROL);
796
816 pp &= ~POWER_TARGET_ON; 797 pp &= ~POWER_TARGET_ON;
817 I915_WRITE(PCH_PP_CONTROL, pp); 798 I915_WRITE(PCH_PP_CONTROL, pp);
818 do {
819 pp_status = I915_READ(PCH_PP_STATUS);
820 } while ((pp_status & PP_ON) && !time_after(jiffies, timeout));
821 799
822 if (time_after(jiffies, timeout)) 800 if (wait_for((I915_READ(PCH_PP_STATUS) & PP_ON) == 0, 5000, 10))
823 DRM_DEBUG_KMS("panel off wait timed out\n"); 801 DRM_ERROR("panel off wait timed out: 0x%08x\n",
802 I915_READ(PCH_PP_STATUS));
824 803
825 /* Make sure VDD is enabled so DP AUX will work */ 804 /* Make sure VDD is enabled so DP AUX will work */
826 pp |= EDP_FORCE_VDD; 805 pp |= EDP_FORCE_VDD | PANEL_POWER_RESET; /* restore panel reset bit */
827 I915_WRITE(PCH_PP_CONTROL, pp); 806 I915_WRITE(PCH_PP_CONTROL, pp);
807 POSTING_READ(PCH_PP_CONTROL);
828} 808}
829 809
830static void ironlake_edp_backlight_on (struct drm_device *dev) 810static void ironlake_edp_backlight_on (struct drm_device *dev)
@@ -849,33 +829,87 @@ static void ironlake_edp_backlight_off (struct drm_device *dev)
849 I915_WRITE(PCH_PP_CONTROL, pp); 829 I915_WRITE(PCH_PP_CONTROL, pp);
850} 830}
851 831
832static void ironlake_edp_pll_on(struct drm_encoder *encoder)
833{
834 struct drm_device *dev = encoder->dev;
835 struct drm_i915_private *dev_priv = dev->dev_private;
836 u32 dpa_ctl;
837
838 DRM_DEBUG_KMS("\n");
839 dpa_ctl = I915_READ(DP_A);
840 dpa_ctl &= ~DP_PLL_ENABLE;
841 I915_WRITE(DP_A, dpa_ctl);
842}
843
844static void ironlake_edp_pll_off(struct drm_encoder *encoder)
845{
846 struct drm_device *dev = encoder->dev;
847 struct drm_i915_private *dev_priv = dev->dev_private;
848 u32 dpa_ctl;
849
850 dpa_ctl = I915_READ(DP_A);
851 dpa_ctl |= DP_PLL_ENABLE;
852 I915_WRITE(DP_A, dpa_ctl);
853 udelay(200);
854}
855
856static void intel_dp_prepare(struct drm_encoder *encoder)
857{
858 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
859 struct drm_device *dev = encoder->dev;
860 struct drm_i915_private *dev_priv = dev->dev_private;
861 uint32_t dp_reg = I915_READ(intel_dp->output_reg);
862
863 if (IS_eDP(intel_dp)) {
864 ironlake_edp_backlight_off(dev);
865 ironlake_edp_panel_on(dev);
866 ironlake_edp_pll_on(encoder);
867 }
868 if (dp_reg & DP_PORT_EN)
869 intel_dp_link_down(intel_dp);
870}
871
872static void intel_dp_commit(struct drm_encoder *encoder)
873{
874 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
875 struct drm_device *dev = encoder->dev;
876 struct drm_i915_private *dev_priv = dev->dev_private;
877 uint32_t dp_reg = I915_READ(intel_dp->output_reg);
878
879 if (!(dp_reg & DP_PORT_EN)) {
880 intel_dp_link_train(intel_dp);
881 }
882 if (IS_eDP(intel_dp) || IS_PCH_eDP(intel_dp))
883 ironlake_edp_backlight_on(dev);
884}
885
852static void 886static void
853intel_dp_dpms(struct drm_encoder *encoder, int mode) 887intel_dp_dpms(struct drm_encoder *encoder, int mode)
854{ 888{
855 struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder); 889 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
856 struct intel_dp_priv *dp_priv = intel_encoder->dev_priv;
857 struct drm_device *dev = encoder->dev; 890 struct drm_device *dev = encoder->dev;
858 struct drm_i915_private *dev_priv = dev->dev_private; 891 struct drm_i915_private *dev_priv = dev->dev_private;
859 uint32_t dp_reg = I915_READ(dp_priv->output_reg); 892 uint32_t dp_reg = I915_READ(intel_dp->output_reg);
860 893
861 if (mode != DRM_MODE_DPMS_ON) { 894 if (mode != DRM_MODE_DPMS_ON) {
862 if (dp_reg & DP_PORT_EN) { 895 if (IS_eDP(intel_dp) || IS_PCH_eDP(intel_dp)) {
863 intel_dp_link_down(intel_encoder, dp_priv->DP); 896 ironlake_edp_backlight_off(dev);
864 if (IS_eDP(intel_encoder) || IS_PCH_eDP(dp_priv)) { 897 ironlake_edp_panel_off(dev);
865 ironlake_edp_backlight_off(dev);
866 ironlake_edp_panel_off(dev);
867 }
868 } 898 }
899 if (dp_reg & DP_PORT_EN)
900 intel_dp_link_down(intel_dp);
901 if (IS_eDP(intel_dp) || IS_PCH_eDP(intel_dp))
902 ironlake_edp_pll_off(encoder);
869 } else { 903 } else {
870 if (!(dp_reg & DP_PORT_EN)) { 904 if (!(dp_reg & DP_PORT_EN)) {
871 intel_dp_link_train(intel_encoder, dp_priv->DP, dp_priv->link_configuration); 905 if (IS_eDP(intel_dp) || IS_PCH_eDP(intel_dp))
872 if (IS_eDP(intel_encoder) || IS_PCH_eDP(dp_priv)) {
873 ironlake_edp_panel_on(dev); 906 ironlake_edp_panel_on(dev);
907 intel_dp_link_train(intel_dp);
908 if (IS_eDP(intel_dp) || IS_PCH_eDP(intel_dp))
874 ironlake_edp_backlight_on(dev); 909 ironlake_edp_backlight_on(dev);
875 }
876 } 910 }
877 } 911 }
878 dp_priv->dpms_mode = mode; 912 intel_dp->dpms_mode = mode;
879} 913}
880 914
881/* 915/*
@@ -883,12 +917,12 @@ intel_dp_dpms(struct drm_encoder *encoder, int mode)
883 * link status information 917 * link status information
884 */ 918 */
885static bool 919static bool
886intel_dp_get_link_status(struct intel_encoder *intel_encoder, 920intel_dp_get_link_status(struct intel_dp *intel_dp,
887 uint8_t link_status[DP_LINK_STATUS_SIZE]) 921 uint8_t link_status[DP_LINK_STATUS_SIZE])
888{ 922{
889 int ret; 923 int ret;
890 924
891 ret = intel_dp_aux_native_read(intel_encoder, 925 ret = intel_dp_aux_native_read(intel_dp,
892 DP_LANE0_1_STATUS, 926 DP_LANE0_1_STATUS,
893 link_status, DP_LINK_STATUS_SIZE); 927 link_status, DP_LINK_STATUS_SIZE);
894 if (ret != DP_LINK_STATUS_SIZE) 928 if (ret != DP_LINK_STATUS_SIZE)
@@ -965,7 +999,7 @@ intel_dp_pre_emphasis_max(uint8_t voltage_swing)
965} 999}
966 1000
967static void 1001static void
968intel_get_adjust_train(struct intel_encoder *intel_encoder, 1002intel_get_adjust_train(struct intel_dp *intel_dp,
969 uint8_t link_status[DP_LINK_STATUS_SIZE], 1003 uint8_t link_status[DP_LINK_STATUS_SIZE],
970 int lane_count, 1004 int lane_count,
971 uint8_t train_set[4]) 1005 uint8_t train_set[4])
@@ -1101,27 +1135,27 @@ intel_channel_eq_ok(uint8_t link_status[DP_LINK_STATUS_SIZE], int lane_count)
1101} 1135}
1102 1136
1103static bool 1137static bool
1104intel_dp_set_link_train(struct intel_encoder *intel_encoder, 1138intel_dp_set_link_train(struct intel_dp *intel_dp,
1105 uint32_t dp_reg_value, 1139 uint32_t dp_reg_value,
1106 uint8_t dp_train_pat, 1140 uint8_t dp_train_pat,
1107 uint8_t train_set[4], 1141 uint8_t train_set[4],
1108 bool first) 1142 bool first)
1109{ 1143{
1110 struct drm_device *dev = intel_encoder->enc.dev; 1144 struct drm_device *dev = intel_dp->base.enc.dev;
1111 struct drm_i915_private *dev_priv = dev->dev_private; 1145 struct drm_i915_private *dev_priv = dev->dev_private;
1112 struct intel_dp_priv *dp_priv = intel_encoder->dev_priv; 1146 struct intel_crtc *intel_crtc = to_intel_crtc(intel_dp->base.enc.crtc);
1113 int ret; 1147 int ret;
1114 1148
1115 I915_WRITE(dp_priv->output_reg, dp_reg_value); 1149 I915_WRITE(intel_dp->output_reg, dp_reg_value);
1116 POSTING_READ(dp_priv->output_reg); 1150 POSTING_READ(intel_dp->output_reg);
1117 if (first) 1151 if (first)
1118 intel_wait_for_vblank(dev); 1152 intel_wait_for_vblank(dev, intel_crtc->pipe);
1119 1153
1120 intel_dp_aux_native_write_1(intel_encoder, 1154 intel_dp_aux_native_write_1(intel_dp,
1121 DP_TRAINING_PATTERN_SET, 1155 DP_TRAINING_PATTERN_SET,
1122 dp_train_pat); 1156 dp_train_pat);
1123 1157
1124 ret = intel_dp_aux_native_write(intel_encoder, 1158 ret = intel_dp_aux_native_write(intel_dp,
1125 DP_TRAINING_LANE0_SET, train_set, 4); 1159 DP_TRAINING_LANE0_SET, train_set, 4);
1126 if (ret != 4) 1160 if (ret != 4)
1127 return false; 1161 return false;
@@ -1130,12 +1164,10 @@ intel_dp_set_link_train(struct intel_encoder *intel_encoder,
1130} 1164}
1131 1165
1132static void 1166static void
1133intel_dp_link_train(struct intel_encoder *intel_encoder, uint32_t DP, 1167intel_dp_link_train(struct intel_dp *intel_dp)
1134 uint8_t link_configuration[DP_LINK_CONFIGURATION_SIZE])
1135{ 1168{
1136 struct drm_device *dev = intel_encoder->enc.dev; 1169 struct drm_device *dev = intel_dp->base.enc.dev;
1137 struct drm_i915_private *dev_priv = dev->dev_private; 1170 struct drm_i915_private *dev_priv = dev->dev_private;
1138 struct intel_dp_priv *dp_priv = intel_encoder->dev_priv;
1139 uint8_t train_set[4]; 1171 uint8_t train_set[4];
1140 uint8_t link_status[DP_LINK_STATUS_SIZE]; 1172 uint8_t link_status[DP_LINK_STATUS_SIZE];
1141 int i; 1173 int i;
@@ -1145,13 +1177,15 @@ intel_dp_link_train(struct intel_encoder *intel_encoder, uint32_t DP,
1145 bool first = true; 1177 bool first = true;
1146 int tries; 1178 int tries;
1147 u32 reg; 1179 u32 reg;
1180 uint32_t DP = intel_dp->DP;
1148 1181
1149 /* Write the link configuration data */ 1182 /* Write the link configuration data */
1150 intel_dp_aux_native_write(intel_encoder, DP_LINK_BW_SET, 1183 intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET,
1151 link_configuration, DP_LINK_CONFIGURATION_SIZE); 1184 intel_dp->link_configuration,
1185 DP_LINK_CONFIGURATION_SIZE);
1152 1186
1153 DP |= DP_PORT_EN; 1187 DP |= DP_PORT_EN;
1154 if (HAS_PCH_CPT(dev) && !IS_eDP(intel_encoder)) 1188 if (HAS_PCH_CPT(dev) && !IS_eDP(intel_dp))
1155 DP &= ~DP_LINK_TRAIN_MASK_CPT; 1189 DP &= ~DP_LINK_TRAIN_MASK_CPT;
1156 else 1190 else
1157 DP &= ~DP_LINK_TRAIN_MASK; 1191 DP &= ~DP_LINK_TRAIN_MASK;
@@ -1162,39 +1196,39 @@ intel_dp_link_train(struct intel_encoder *intel_encoder, uint32_t DP,
1162 for (;;) { 1196 for (;;) {
1163 /* Use train_set[0] to set the voltage and pre emphasis values */ 1197 /* Use train_set[0] to set the voltage and pre emphasis values */
1164 uint32_t signal_levels; 1198 uint32_t signal_levels;
1165 if (IS_GEN6(dev) && IS_eDP(intel_encoder)) { 1199 if (IS_GEN6(dev) && IS_eDP(intel_dp)) {
1166 signal_levels = intel_gen6_edp_signal_levels(train_set[0]); 1200 signal_levels = intel_gen6_edp_signal_levels(train_set[0]);
1167 DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels; 1201 DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels;
1168 } else { 1202 } else {
1169 signal_levels = intel_dp_signal_levels(train_set[0], dp_priv->lane_count); 1203 signal_levels = intel_dp_signal_levels(train_set[0], intel_dp->lane_count);
1170 DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels; 1204 DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
1171 } 1205 }
1172 1206
1173 if (HAS_PCH_CPT(dev) && !IS_eDP(intel_encoder)) 1207 if (HAS_PCH_CPT(dev) && !IS_eDP(intel_dp))
1174 reg = DP | DP_LINK_TRAIN_PAT_1_CPT; 1208 reg = DP | DP_LINK_TRAIN_PAT_1_CPT;
1175 else 1209 else
1176 reg = DP | DP_LINK_TRAIN_PAT_1; 1210 reg = DP | DP_LINK_TRAIN_PAT_1;
1177 1211
1178 if (!intel_dp_set_link_train(intel_encoder, reg, 1212 if (!intel_dp_set_link_train(intel_dp, reg,
1179 DP_TRAINING_PATTERN_1, train_set, first)) 1213 DP_TRAINING_PATTERN_1, train_set, first))
1180 break; 1214 break;
1181 first = false; 1215 first = false;
1182 /* Set training pattern 1 */ 1216 /* Set training pattern 1 */
1183 1217
1184 udelay(100); 1218 udelay(100);
1185 if (!intel_dp_get_link_status(intel_encoder, link_status)) 1219 if (!intel_dp_get_link_status(intel_dp, link_status))
1186 break; 1220 break;
1187 1221
1188 if (intel_clock_recovery_ok(link_status, dp_priv->lane_count)) { 1222 if (intel_clock_recovery_ok(link_status, intel_dp->lane_count)) {
1189 clock_recovery = true; 1223 clock_recovery = true;
1190 break; 1224 break;
1191 } 1225 }
1192 1226
1193 /* Check to see if we've tried the max voltage */ 1227 /* Check to see if we've tried the max voltage */
1194 for (i = 0; i < dp_priv->lane_count; i++) 1228 for (i = 0; i < intel_dp->lane_count; i++)
1195 if ((train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0) 1229 if ((train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
1196 break; 1230 break;
1197 if (i == dp_priv->lane_count) 1231 if (i == intel_dp->lane_count)
1198 break; 1232 break;
1199 1233
1200 /* Check to see if we've tried the same voltage 5 times */ 1234 /* Check to see if we've tried the same voltage 5 times */
@@ -1207,7 +1241,7 @@ intel_dp_link_train(struct intel_encoder *intel_encoder, uint32_t DP,
1207 voltage = train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK; 1241 voltage = train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
1208 1242
1209 /* Compute new train_set as requested by target */ 1243 /* Compute new train_set as requested by target */
1210 intel_get_adjust_train(intel_encoder, link_status, dp_priv->lane_count, train_set); 1244 intel_get_adjust_train(intel_dp, link_status, intel_dp->lane_count, train_set);
1211 } 1245 }
1212 1246
1213 /* channel equalization */ 1247 /* channel equalization */
@@ -1217,30 +1251,30 @@ intel_dp_link_train(struct intel_encoder *intel_encoder, uint32_t DP,
1217 /* Use train_set[0] to set the voltage and pre emphasis values */ 1251 /* Use train_set[0] to set the voltage and pre emphasis values */
1218 uint32_t signal_levels; 1252 uint32_t signal_levels;
1219 1253
1220 if (IS_GEN6(dev) && IS_eDP(intel_encoder)) { 1254 if (IS_GEN6(dev) && IS_eDP(intel_dp)) {
1221 signal_levels = intel_gen6_edp_signal_levels(train_set[0]); 1255 signal_levels = intel_gen6_edp_signal_levels(train_set[0]);
1222 DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels; 1256 DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels;
1223 } else { 1257 } else {
1224 signal_levels = intel_dp_signal_levels(train_set[0], dp_priv->lane_count); 1258 signal_levels = intel_dp_signal_levels(train_set[0], intel_dp->lane_count);
1225 DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels; 1259 DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
1226 } 1260 }
1227 1261
1228 if (HAS_PCH_CPT(dev) && !IS_eDP(intel_encoder)) 1262 if (HAS_PCH_CPT(dev) && !IS_eDP(intel_dp))
1229 reg = DP | DP_LINK_TRAIN_PAT_2_CPT; 1263 reg = DP | DP_LINK_TRAIN_PAT_2_CPT;
1230 else 1264 else
1231 reg = DP | DP_LINK_TRAIN_PAT_2; 1265 reg = DP | DP_LINK_TRAIN_PAT_2;
1232 1266
1233 /* channel eq pattern */ 1267 /* channel eq pattern */
1234 if (!intel_dp_set_link_train(intel_encoder, reg, 1268 if (!intel_dp_set_link_train(intel_dp, reg,
1235 DP_TRAINING_PATTERN_2, train_set, 1269 DP_TRAINING_PATTERN_2, train_set,
1236 false)) 1270 false))
1237 break; 1271 break;
1238 1272
1239 udelay(400); 1273 udelay(400);
1240 if (!intel_dp_get_link_status(intel_encoder, link_status)) 1274 if (!intel_dp_get_link_status(intel_dp, link_status))
1241 break; 1275 break;
1242 1276
1243 if (intel_channel_eq_ok(link_status, dp_priv->lane_count)) { 1277 if (intel_channel_eq_ok(link_status, intel_dp->lane_count)) {
1244 channel_eq = true; 1278 channel_eq = true;
1245 break; 1279 break;
1246 } 1280 }
@@ -1250,53 +1284,53 @@ intel_dp_link_train(struct intel_encoder *intel_encoder, uint32_t DP,
1250 break; 1284 break;
1251 1285
1252 /* Compute new train_set as requested by target */ 1286 /* Compute new train_set as requested by target */
1253 intel_get_adjust_train(intel_encoder, link_status, dp_priv->lane_count, train_set); 1287 intel_get_adjust_train(intel_dp, link_status, intel_dp->lane_count, train_set);
1254 ++tries; 1288 ++tries;
1255 } 1289 }
1256 1290
1257 if (HAS_PCH_CPT(dev) && !IS_eDP(intel_encoder)) 1291 if (HAS_PCH_CPT(dev) && !IS_eDP(intel_dp))
1258 reg = DP | DP_LINK_TRAIN_OFF_CPT; 1292 reg = DP | DP_LINK_TRAIN_OFF_CPT;
1259 else 1293 else
1260 reg = DP | DP_LINK_TRAIN_OFF; 1294 reg = DP | DP_LINK_TRAIN_OFF;
1261 1295
1262 I915_WRITE(dp_priv->output_reg, reg); 1296 I915_WRITE(intel_dp->output_reg, reg);
1263 POSTING_READ(dp_priv->output_reg); 1297 POSTING_READ(intel_dp->output_reg);
1264 intel_dp_aux_native_write_1(intel_encoder, 1298 intel_dp_aux_native_write_1(intel_dp,
1265 DP_TRAINING_PATTERN_SET, DP_TRAINING_PATTERN_DISABLE); 1299 DP_TRAINING_PATTERN_SET, DP_TRAINING_PATTERN_DISABLE);
1266} 1300}
1267 1301
1268static void 1302static void
1269intel_dp_link_down(struct intel_encoder *intel_encoder, uint32_t DP) 1303intel_dp_link_down(struct intel_dp *intel_dp)
1270{ 1304{
1271 struct drm_device *dev = intel_encoder->enc.dev; 1305 struct drm_device *dev = intel_dp->base.enc.dev;
1272 struct drm_i915_private *dev_priv = dev->dev_private; 1306 struct drm_i915_private *dev_priv = dev->dev_private;
1273 struct intel_dp_priv *dp_priv = intel_encoder->dev_priv; 1307 uint32_t DP = intel_dp->DP;
1274 1308
1275 DRM_DEBUG_KMS("\n"); 1309 DRM_DEBUG_KMS("\n");
1276 1310
1277 if (IS_eDP(intel_encoder)) { 1311 if (IS_eDP(intel_dp)) {
1278 DP &= ~DP_PLL_ENABLE; 1312 DP &= ~DP_PLL_ENABLE;
1279 I915_WRITE(dp_priv->output_reg, DP); 1313 I915_WRITE(intel_dp->output_reg, DP);
1280 POSTING_READ(dp_priv->output_reg); 1314 POSTING_READ(intel_dp->output_reg);
1281 udelay(100); 1315 udelay(100);
1282 } 1316 }
1283 1317
1284 if (HAS_PCH_CPT(dev) && !IS_eDP(intel_encoder)) { 1318 if (HAS_PCH_CPT(dev) && !IS_eDP(intel_dp)) {
1285 DP &= ~DP_LINK_TRAIN_MASK_CPT; 1319 DP &= ~DP_LINK_TRAIN_MASK_CPT;
1286 I915_WRITE(dp_priv->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT); 1320 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
1287 POSTING_READ(dp_priv->output_reg); 1321 POSTING_READ(intel_dp->output_reg);
1288 } else { 1322 } else {
1289 DP &= ~DP_LINK_TRAIN_MASK; 1323 DP &= ~DP_LINK_TRAIN_MASK;
1290 I915_WRITE(dp_priv->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE); 1324 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
1291 POSTING_READ(dp_priv->output_reg); 1325 POSTING_READ(intel_dp->output_reg);
1292 } 1326 }
1293 1327
1294 udelay(17000); 1328 udelay(17000);
1295 1329
1296 if (IS_eDP(intel_encoder)) 1330 if (IS_eDP(intel_dp))
1297 DP |= DP_LINK_TRAIN_OFF; 1331 DP |= DP_LINK_TRAIN_OFF;
1298 I915_WRITE(dp_priv->output_reg, DP & ~DP_PORT_EN); 1332 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
1299 POSTING_READ(dp_priv->output_reg); 1333 POSTING_READ(intel_dp->output_reg);
1300} 1334}
1301 1335
1302/* 1336/*
@@ -1309,41 +1343,39 @@ intel_dp_link_down(struct intel_encoder *intel_encoder, uint32_t DP)
1309 */ 1343 */
1310 1344
1311static void 1345static void
1312intel_dp_check_link_status(struct intel_encoder *intel_encoder) 1346intel_dp_check_link_status(struct intel_dp *intel_dp)
1313{ 1347{
1314 struct intel_dp_priv *dp_priv = intel_encoder->dev_priv;
1315 uint8_t link_status[DP_LINK_STATUS_SIZE]; 1348 uint8_t link_status[DP_LINK_STATUS_SIZE];
1316 1349
1317 if (!intel_encoder->enc.crtc) 1350 if (!intel_dp->base.enc.crtc)
1318 return; 1351 return;
1319 1352
1320 if (!intel_dp_get_link_status(intel_encoder, link_status)) { 1353 if (!intel_dp_get_link_status(intel_dp, link_status)) {
1321 intel_dp_link_down(intel_encoder, dp_priv->DP); 1354 intel_dp_link_down(intel_dp);
1322 return; 1355 return;
1323 } 1356 }
1324 1357
1325 if (!intel_channel_eq_ok(link_status, dp_priv->lane_count)) 1358 if (!intel_channel_eq_ok(link_status, intel_dp->lane_count))
1326 intel_dp_link_train(intel_encoder, dp_priv->DP, dp_priv->link_configuration); 1359 intel_dp_link_train(intel_dp);
1327} 1360}
1328 1361
1329static enum drm_connector_status 1362static enum drm_connector_status
1330ironlake_dp_detect(struct drm_connector *connector) 1363ironlake_dp_detect(struct drm_connector *connector)
1331{ 1364{
1332 struct drm_encoder *encoder = intel_attached_encoder(connector); 1365 struct drm_encoder *encoder = intel_attached_encoder(connector);
1333 struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder); 1366 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1334 struct intel_dp_priv *dp_priv = intel_encoder->dev_priv;
1335 enum drm_connector_status status; 1367 enum drm_connector_status status;
1336 1368
1337 status = connector_status_disconnected; 1369 status = connector_status_disconnected;
1338 if (intel_dp_aux_native_read(intel_encoder, 1370 if (intel_dp_aux_native_read(intel_dp,
1339 0x000, dp_priv->dpcd, 1371 0x000, intel_dp->dpcd,
1340 sizeof (dp_priv->dpcd)) == sizeof (dp_priv->dpcd)) 1372 sizeof (intel_dp->dpcd)) == sizeof (intel_dp->dpcd))
1341 { 1373 {
1342 if (dp_priv->dpcd[0] != 0) 1374 if (intel_dp->dpcd[0] != 0)
1343 status = connector_status_connected; 1375 status = connector_status_connected;
1344 } 1376 }
1345 DRM_DEBUG_KMS("DPCD: %hx%hx%hx%hx\n", dp_priv->dpcd[0], 1377 DRM_DEBUG_KMS("DPCD: %hx%hx%hx%hx\n", intel_dp->dpcd[0],
1346 dp_priv->dpcd[1], dp_priv->dpcd[2], dp_priv->dpcd[3]); 1378 intel_dp->dpcd[1], intel_dp->dpcd[2], intel_dp->dpcd[3]);
1347 return status; 1379 return status;
1348} 1380}
1349 1381
@@ -1357,19 +1389,18 @@ static enum drm_connector_status
1357intel_dp_detect(struct drm_connector *connector) 1389intel_dp_detect(struct drm_connector *connector)
1358{ 1390{
1359 struct drm_encoder *encoder = intel_attached_encoder(connector); 1391 struct drm_encoder *encoder = intel_attached_encoder(connector);
1360 struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder); 1392 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1361 struct drm_device *dev = intel_encoder->enc.dev; 1393 struct drm_device *dev = intel_dp->base.enc.dev;
1362 struct drm_i915_private *dev_priv = dev->dev_private; 1394 struct drm_i915_private *dev_priv = dev->dev_private;
1363 struct intel_dp_priv *dp_priv = intel_encoder->dev_priv;
1364 uint32_t temp, bit; 1395 uint32_t temp, bit;
1365 enum drm_connector_status status; 1396 enum drm_connector_status status;
1366 1397
1367 dp_priv->has_audio = false; 1398 intel_dp->has_audio = false;
1368 1399
1369 if (HAS_PCH_SPLIT(dev)) 1400 if (HAS_PCH_SPLIT(dev))
1370 return ironlake_dp_detect(connector); 1401 return ironlake_dp_detect(connector);
1371 1402
1372 switch (dp_priv->output_reg) { 1403 switch (intel_dp->output_reg) {
1373 case DP_B: 1404 case DP_B:
1374 bit = DPB_HOTPLUG_INT_STATUS; 1405 bit = DPB_HOTPLUG_INT_STATUS;
1375 break; 1406 break;
@@ -1389,11 +1420,11 @@ intel_dp_detect(struct drm_connector *connector)
1389 return connector_status_disconnected; 1420 return connector_status_disconnected;
1390 1421
1391 status = connector_status_disconnected; 1422 status = connector_status_disconnected;
1392 if (intel_dp_aux_native_read(intel_encoder, 1423 if (intel_dp_aux_native_read(intel_dp,
1393 0x000, dp_priv->dpcd, 1424 0x000, intel_dp->dpcd,
1394 sizeof (dp_priv->dpcd)) == sizeof (dp_priv->dpcd)) 1425 sizeof (intel_dp->dpcd)) == sizeof (intel_dp->dpcd))
1395 { 1426 {
1396 if (dp_priv->dpcd[0] != 0) 1427 if (intel_dp->dpcd[0] != 0)
1397 status = connector_status_connected; 1428 status = connector_status_connected;
1398 } 1429 }
1399 return status; 1430 return status;
@@ -1402,18 +1433,17 @@ intel_dp_detect(struct drm_connector *connector)
1402static int intel_dp_get_modes(struct drm_connector *connector) 1433static int intel_dp_get_modes(struct drm_connector *connector)
1403{ 1434{
1404 struct drm_encoder *encoder = intel_attached_encoder(connector); 1435 struct drm_encoder *encoder = intel_attached_encoder(connector);
1405 struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder); 1436 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1406 struct drm_device *dev = intel_encoder->enc.dev; 1437 struct drm_device *dev = intel_dp->base.enc.dev;
1407 struct drm_i915_private *dev_priv = dev->dev_private; 1438 struct drm_i915_private *dev_priv = dev->dev_private;
1408 struct intel_dp_priv *dp_priv = intel_encoder->dev_priv;
1409 int ret; 1439 int ret;
1410 1440
1411 /* We should parse the EDID data and find out if it has an audio sink 1441 /* We should parse the EDID data and find out if it has an audio sink
1412 */ 1442 */
1413 1443
1414 ret = intel_ddc_get_modes(connector, intel_encoder->ddc_bus); 1444 ret = intel_ddc_get_modes(connector, intel_dp->base.ddc_bus);
1415 if (ret) { 1445 if (ret) {
1416 if ((IS_eDP(intel_encoder) || IS_PCH_eDP(dp_priv)) && 1446 if ((IS_eDP(intel_dp) || IS_PCH_eDP(intel_dp)) &&
1417 !dev_priv->panel_fixed_mode) { 1447 !dev_priv->panel_fixed_mode) {
1418 struct drm_display_mode *newmode; 1448 struct drm_display_mode *newmode;
1419 list_for_each_entry(newmode, &connector->probed_modes, 1449 list_for_each_entry(newmode, &connector->probed_modes,
@@ -1430,7 +1460,7 @@ static int intel_dp_get_modes(struct drm_connector *connector)
1430 } 1460 }
1431 1461
1432 /* if eDP has no EDID, try to use fixed panel mode from VBT */ 1462 /* if eDP has no EDID, try to use fixed panel mode from VBT */
1433 if (IS_eDP(intel_encoder) || IS_PCH_eDP(dp_priv)) { 1463 if (IS_eDP(intel_dp) || IS_PCH_eDP(intel_dp)) {
1434 if (dev_priv->panel_fixed_mode != NULL) { 1464 if (dev_priv->panel_fixed_mode != NULL) {
1435 struct drm_display_mode *mode; 1465 struct drm_display_mode *mode;
1436 mode = drm_mode_duplicate(dev, dev_priv->panel_fixed_mode); 1466 mode = drm_mode_duplicate(dev, dev_priv->panel_fixed_mode);
@@ -1452,9 +1482,9 @@ intel_dp_destroy (struct drm_connector *connector)
1452static const struct drm_encoder_helper_funcs intel_dp_helper_funcs = { 1482static const struct drm_encoder_helper_funcs intel_dp_helper_funcs = {
1453 .dpms = intel_dp_dpms, 1483 .dpms = intel_dp_dpms,
1454 .mode_fixup = intel_dp_mode_fixup, 1484 .mode_fixup = intel_dp_mode_fixup,
1455 .prepare = intel_encoder_prepare, 1485 .prepare = intel_dp_prepare,
1456 .mode_set = intel_dp_mode_set, 1486 .mode_set = intel_dp_mode_set,
1457 .commit = intel_encoder_commit, 1487 .commit = intel_dp_commit,
1458}; 1488};
1459 1489
1460static const struct drm_connector_funcs intel_dp_connector_funcs = { 1490static const struct drm_connector_funcs intel_dp_connector_funcs = {
@@ -1470,27 +1500,17 @@ static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs =
1470 .best_encoder = intel_attached_encoder, 1500 .best_encoder = intel_attached_encoder,
1471}; 1501};
1472 1502
1473static void intel_dp_enc_destroy(struct drm_encoder *encoder)
1474{
1475 struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
1476
1477 if (intel_encoder->i2c_bus)
1478 intel_i2c_destroy(intel_encoder->i2c_bus);
1479 drm_encoder_cleanup(encoder);
1480 kfree(intel_encoder);
1481}
1482
1483static const struct drm_encoder_funcs intel_dp_enc_funcs = { 1503static const struct drm_encoder_funcs intel_dp_enc_funcs = {
1484 .destroy = intel_dp_enc_destroy, 1504 .destroy = intel_encoder_destroy,
1485}; 1505};
1486 1506
1487void 1507void
1488intel_dp_hot_plug(struct intel_encoder *intel_encoder) 1508intel_dp_hot_plug(struct intel_encoder *intel_encoder)
1489{ 1509{
1490 struct intel_dp_priv *dp_priv = intel_encoder->dev_priv; 1510 struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base);
1491 1511
1492 if (dp_priv->dpms_mode == DRM_MODE_DPMS_ON) 1512 if (intel_dp->dpms_mode == DRM_MODE_DPMS_ON)
1493 intel_dp_check_link_status(intel_encoder); 1513 intel_dp_check_link_status(intel_dp);
1494} 1514}
1495 1515
1496/* Return which DP Port should be selected for Transcoder DP control */ 1516/* Return which DP Port should be selected for Transcoder DP control */
@@ -1500,18 +1520,18 @@ intel_trans_dp_port_sel (struct drm_crtc *crtc)
1500 struct drm_device *dev = crtc->dev; 1520 struct drm_device *dev = crtc->dev;
1501 struct drm_mode_config *mode_config = &dev->mode_config; 1521 struct drm_mode_config *mode_config = &dev->mode_config;
1502 struct drm_encoder *encoder; 1522 struct drm_encoder *encoder;
1503 struct intel_encoder *intel_encoder = NULL;
1504 1523
1505 list_for_each_entry(encoder, &mode_config->encoder_list, head) { 1524 list_for_each_entry(encoder, &mode_config->encoder_list, head) {
1525 struct intel_dp *intel_dp;
1526
1506 if (encoder->crtc != crtc) 1527 if (encoder->crtc != crtc)
1507 continue; 1528 continue;
1508 1529
1509 intel_encoder = enc_to_intel_encoder(encoder); 1530 intel_dp = enc_to_intel_dp(encoder);
1510 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT) { 1531 if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT)
1511 struct intel_dp_priv *dp_priv = intel_encoder->dev_priv; 1532 return intel_dp->output_reg;
1512 return dp_priv->output_reg;
1513 }
1514 } 1533 }
1534
1515 return -1; 1535 return -1;
1516} 1536}
1517 1537
@@ -1540,30 +1560,28 @@ intel_dp_init(struct drm_device *dev, int output_reg)
1540{ 1560{
1541 struct drm_i915_private *dev_priv = dev->dev_private; 1561 struct drm_i915_private *dev_priv = dev->dev_private;
1542 struct drm_connector *connector; 1562 struct drm_connector *connector;
1563 struct intel_dp *intel_dp;
1543 struct intel_encoder *intel_encoder; 1564 struct intel_encoder *intel_encoder;
1544 struct intel_connector *intel_connector; 1565 struct intel_connector *intel_connector;
1545 struct intel_dp_priv *dp_priv;
1546 const char *name = NULL; 1566 const char *name = NULL;
1547 int type; 1567 int type;
1548 1568
1549 intel_encoder = kcalloc(sizeof(struct intel_encoder) + 1569 intel_dp = kzalloc(sizeof(struct intel_dp), GFP_KERNEL);
1550 sizeof(struct intel_dp_priv), 1, GFP_KERNEL); 1570 if (!intel_dp)
1551 if (!intel_encoder)
1552 return; 1571 return;
1553 1572
1554 intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL); 1573 intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
1555 if (!intel_connector) { 1574 if (!intel_connector) {
1556 kfree(intel_encoder); 1575 kfree(intel_dp);
1557 return; 1576 return;
1558 } 1577 }
1578 intel_encoder = &intel_dp->base;
1559 1579
1560 dp_priv = (struct intel_dp_priv *)(intel_encoder + 1); 1580 if (HAS_PCH_SPLIT(dev) && output_reg == PCH_DP_D)
1561
1562 if (HAS_PCH_SPLIT(dev) && (output_reg == PCH_DP_D))
1563 if (intel_dpd_is_edp(dev)) 1581 if (intel_dpd_is_edp(dev))
1564 dp_priv->is_pch_edp = true; 1582 intel_dp->is_pch_edp = true;
1565 1583
1566 if (output_reg == DP_A || IS_PCH_eDP(dp_priv)) { 1584 if (output_reg == DP_A || IS_PCH_eDP(intel_dp)) {
1567 type = DRM_MODE_CONNECTOR_eDP; 1585 type = DRM_MODE_CONNECTOR_eDP;
1568 intel_encoder->type = INTEL_OUTPUT_EDP; 1586 intel_encoder->type = INTEL_OUTPUT_EDP;
1569 } else { 1587 } else {
@@ -1584,18 +1602,16 @@ intel_dp_init(struct drm_device *dev, int output_reg)
1584 else if (output_reg == DP_D || output_reg == PCH_DP_D) 1602 else if (output_reg == DP_D || output_reg == PCH_DP_D)
1585 intel_encoder->clone_mask = (1 << INTEL_DP_D_CLONE_BIT); 1603 intel_encoder->clone_mask = (1 << INTEL_DP_D_CLONE_BIT);
1586 1604
1587 if (IS_eDP(intel_encoder)) 1605 if (IS_eDP(intel_dp))
1588 intel_encoder->clone_mask = (1 << INTEL_EDP_CLONE_BIT); 1606 intel_encoder->clone_mask = (1 << INTEL_EDP_CLONE_BIT);
1589 1607
1590 intel_encoder->crtc_mask = (1 << 0) | (1 << 1); 1608 intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
1591 connector->interlace_allowed = true; 1609 connector->interlace_allowed = true;
1592 connector->doublescan_allowed = 0; 1610 connector->doublescan_allowed = 0;
1593 1611
1594 dp_priv->intel_encoder = intel_encoder; 1612 intel_dp->output_reg = output_reg;
1595 dp_priv->output_reg = output_reg; 1613 intel_dp->has_audio = false;
1596 dp_priv->has_audio = false; 1614 intel_dp->dpms_mode = DRM_MODE_DPMS_ON;
1597 dp_priv->dpms_mode = DRM_MODE_DPMS_ON;
1598 intel_encoder->dev_priv = dp_priv;
1599 1615
1600 drm_encoder_init(dev, &intel_encoder->enc, &intel_dp_enc_funcs, 1616 drm_encoder_init(dev, &intel_encoder->enc, &intel_dp_enc_funcs,
1601 DRM_MODE_ENCODER_TMDS); 1617 DRM_MODE_ENCODER_TMDS);
@@ -1630,12 +1646,12 @@ intel_dp_init(struct drm_device *dev, int output_reg)
1630 break; 1646 break;
1631 } 1647 }
1632 1648
1633 intel_dp_i2c_init(intel_encoder, intel_connector, name); 1649 intel_dp_i2c_init(intel_dp, intel_connector, name);
1634 1650
1635 intel_encoder->ddc_bus = &dp_priv->adapter; 1651 intel_encoder->ddc_bus = &intel_dp->adapter;
1636 intel_encoder->hot_plug = intel_dp_hot_plug; 1652 intel_encoder->hot_plug = intel_dp_hot_plug;
1637 1653
1638 if (output_reg == DP_A || IS_PCH_eDP(dp_priv)) { 1654 if (output_reg == DP_A || IS_PCH_eDP(intel_dp)) {
1639 /* initialize panel mode from VBT if available for eDP */ 1655 /* initialize panel mode from VBT if available for eDP */
1640 if (dev_priv->lfp_lvds_vbt_mode) { 1656 if (dev_priv->lfp_lvds_vbt_mode) {
1641 dev_priv->panel_fixed_mode = 1657 dev_priv->panel_fixed_mode =
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index b2190148703a..ad312ca6b3e5 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -32,6 +32,20 @@
32#include "drm_crtc.h" 32#include "drm_crtc.h"
33 33
34#include "drm_crtc_helper.h" 34#include "drm_crtc_helper.h"
35
36#define wait_for(COND, MS, W) ({ \
37 unsigned long timeout__ = jiffies + msecs_to_jiffies(MS); \
38 int ret__ = 0; \
39 while (! (COND)) { \
40 if (time_after(jiffies, timeout__)) { \
41 ret__ = -ETIMEDOUT; \
42 break; \
43 } \
44 if (W) msleep(W); \
45 } \
46 ret__; \
47})
48
35/* 49/*
36 * Display related stuff 50 * Display related stuff
37 */ 51 */
@@ -102,7 +116,6 @@ struct intel_encoder {
102 struct i2c_adapter *ddc_bus; 116 struct i2c_adapter *ddc_bus;
103 bool load_detect_temp; 117 bool load_detect_temp;
104 bool needs_tv_clock; 118 bool needs_tv_clock;
105 void *dev_priv;
106 void (*hot_plug)(struct intel_encoder *); 119 void (*hot_plug)(struct intel_encoder *);
107 int crtc_mask; 120 int crtc_mask;
108 int clone_mask; 121 int clone_mask;
@@ -110,7 +123,6 @@ struct intel_encoder {
110 123
111struct intel_connector { 124struct intel_connector {
112 struct drm_connector base; 125 struct drm_connector base;
113 void *dev_priv;
114}; 126};
115 127
116struct intel_crtc; 128struct intel_crtc;
@@ -156,7 +168,7 @@ struct intel_crtc {
156 uint32_t cursor_addr; 168 uint32_t cursor_addr;
157 int16_t cursor_x, cursor_y; 169 int16_t cursor_x, cursor_y;
158 int16_t cursor_width, cursor_height; 170 int16_t cursor_width, cursor_height;
159 bool cursor_visble; 171 bool cursor_visible, cursor_on;
160}; 172};
161 173
162#define to_intel_crtc(x) container_of(x, struct intel_crtc, base) 174#define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
@@ -164,6 +176,16 @@ struct intel_crtc {
164#define enc_to_intel_encoder(x) container_of(x, struct intel_encoder, enc) 176#define enc_to_intel_encoder(x) container_of(x, struct intel_encoder, enc)
165#define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base) 177#define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
166 178
179struct intel_unpin_work {
180 struct work_struct work;
181 struct drm_device *dev;
182 struct drm_gem_object *old_fb_obj;
183 struct drm_gem_object *pending_flip_obj;
184 struct drm_pending_vblank_event *event;
185 int pending;
186 bool enable_stall_check;
187};
188
167struct i2c_adapter *intel_i2c_create(struct drm_device *dev, const u32 reg, 189struct i2c_adapter *intel_i2c_create(struct drm_device *dev, const u32 reg,
168 const char *name); 190 const char *name);
169void intel_i2c_destroy(struct i2c_adapter *adapter); 191void intel_i2c_destroy(struct i2c_adapter *adapter);
@@ -188,10 +210,18 @@ extern bool intel_dpd_is_edp(struct drm_device *dev);
188extern void intel_edp_link_config (struct intel_encoder *, int *, int *); 210extern void intel_edp_link_config (struct intel_encoder *, int *, int *);
189 211
190 212
213extern void intel_fixed_panel_mode(struct drm_display_mode *fixed_mode,
214 struct drm_display_mode *adjusted_mode);
215extern void intel_pch_panel_fitting(struct drm_device *dev,
216 int fitting_mode,
217 struct drm_display_mode *mode,
218 struct drm_display_mode *adjusted_mode);
219
191extern int intel_panel_fitter_pipe (struct drm_device *dev); 220extern int intel_panel_fitter_pipe (struct drm_device *dev);
192extern void intel_crtc_load_lut(struct drm_crtc *crtc); 221extern void intel_crtc_load_lut(struct drm_crtc *crtc);
193extern void intel_encoder_prepare (struct drm_encoder *encoder); 222extern void intel_encoder_prepare (struct drm_encoder *encoder);
194extern void intel_encoder_commit (struct drm_encoder *encoder); 223extern void intel_encoder_commit (struct drm_encoder *encoder);
224extern void intel_encoder_destroy(struct drm_encoder *encoder);
195 225
196extern struct drm_encoder *intel_attached_encoder(struct drm_connector *connector); 226extern struct drm_encoder *intel_attached_encoder(struct drm_connector *connector);
197 227
@@ -199,7 +229,8 @@ extern struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
199 struct drm_crtc *crtc); 229 struct drm_crtc *crtc);
200int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data, 230int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
201 struct drm_file *file_priv); 231 struct drm_file *file_priv);
202extern void intel_wait_for_vblank(struct drm_device *dev); 232extern void intel_wait_for_vblank_off(struct drm_device *dev, int pipe);
233extern void intel_wait_for_vblank(struct drm_device *dev, int pipe);
203extern struct drm_crtc *intel_get_crtc_from_pipe(struct drm_device *dev, int pipe); 234extern struct drm_crtc *intel_get_crtc_from_pipe(struct drm_device *dev, int pipe);
204extern struct drm_crtc *intel_get_load_detect_pipe(struct intel_encoder *intel_encoder, 235extern struct drm_crtc *intel_get_load_detect_pipe(struct intel_encoder *intel_encoder,
205 struct drm_connector *connector, 236 struct drm_connector *connector,
diff --git a/drivers/gpu/drm/i915/intel_dvo.c b/drivers/gpu/drm/i915/intel_dvo.c
index 227feca7cf8d..a399f4b2c1c5 100644
--- a/drivers/gpu/drm/i915/intel_dvo.c
+++ b/drivers/gpu/drm/i915/intel_dvo.c
@@ -38,7 +38,7 @@
38#define CH7xxx_ADDR 0x76 38#define CH7xxx_ADDR 0x76
39#define TFP410_ADDR 0x38 39#define TFP410_ADDR 0x38
40 40
41static struct intel_dvo_device intel_dvo_devices[] = { 41static const struct intel_dvo_device intel_dvo_devices[] = {
42 { 42 {
43 .type = INTEL_DVO_CHIP_TMDS, 43 .type = INTEL_DVO_CHIP_TMDS,
44 .name = "sil164", 44 .name = "sil164",
@@ -77,20 +77,33 @@ static struct intel_dvo_device intel_dvo_devices[] = {
77 } 77 }
78}; 78};
79 79
80struct intel_dvo {
81 struct intel_encoder base;
82
83 struct intel_dvo_device dev;
84
85 struct drm_display_mode *panel_fixed_mode;
86 bool panel_wants_dither;
87};
88
89static struct intel_dvo *enc_to_intel_dvo(struct drm_encoder *encoder)
90{
91 return container_of(enc_to_intel_encoder(encoder), struct intel_dvo, base);
92}
93
80static void intel_dvo_dpms(struct drm_encoder *encoder, int mode) 94static void intel_dvo_dpms(struct drm_encoder *encoder, int mode)
81{ 95{
82 struct drm_i915_private *dev_priv = encoder->dev->dev_private; 96 struct drm_i915_private *dev_priv = encoder->dev->dev_private;
83 struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder); 97 struct intel_dvo *intel_dvo = enc_to_intel_dvo(encoder);
84 struct intel_dvo_device *dvo = intel_encoder->dev_priv; 98 u32 dvo_reg = intel_dvo->dev.dvo_reg;
85 u32 dvo_reg = dvo->dvo_reg;
86 u32 temp = I915_READ(dvo_reg); 99 u32 temp = I915_READ(dvo_reg);
87 100
88 if (mode == DRM_MODE_DPMS_ON) { 101 if (mode == DRM_MODE_DPMS_ON) {
89 I915_WRITE(dvo_reg, temp | DVO_ENABLE); 102 I915_WRITE(dvo_reg, temp | DVO_ENABLE);
90 I915_READ(dvo_reg); 103 I915_READ(dvo_reg);
91 dvo->dev_ops->dpms(dvo, mode); 104 intel_dvo->dev.dev_ops->dpms(&intel_dvo->dev, mode);
92 } else { 105 } else {
93 dvo->dev_ops->dpms(dvo, mode); 106 intel_dvo->dev.dev_ops->dpms(&intel_dvo->dev, mode);
94 I915_WRITE(dvo_reg, temp & ~DVO_ENABLE); 107 I915_WRITE(dvo_reg, temp & ~DVO_ENABLE);
95 I915_READ(dvo_reg); 108 I915_READ(dvo_reg);
96 } 109 }
@@ -100,38 +113,36 @@ static int intel_dvo_mode_valid(struct drm_connector *connector,
100 struct drm_display_mode *mode) 113 struct drm_display_mode *mode)
101{ 114{
102 struct drm_encoder *encoder = intel_attached_encoder(connector); 115 struct drm_encoder *encoder = intel_attached_encoder(connector);
103 struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder); 116 struct intel_dvo *intel_dvo = enc_to_intel_dvo(encoder);
104 struct intel_dvo_device *dvo = intel_encoder->dev_priv;
105 117
106 if (mode->flags & DRM_MODE_FLAG_DBLSCAN) 118 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
107 return MODE_NO_DBLESCAN; 119 return MODE_NO_DBLESCAN;
108 120
109 /* XXX: Validate clock range */ 121 /* XXX: Validate clock range */
110 122
111 if (dvo->panel_fixed_mode) { 123 if (intel_dvo->panel_fixed_mode) {
112 if (mode->hdisplay > dvo->panel_fixed_mode->hdisplay) 124 if (mode->hdisplay > intel_dvo->panel_fixed_mode->hdisplay)
113 return MODE_PANEL; 125 return MODE_PANEL;
114 if (mode->vdisplay > dvo->panel_fixed_mode->vdisplay) 126 if (mode->vdisplay > intel_dvo->panel_fixed_mode->vdisplay)
115 return MODE_PANEL; 127 return MODE_PANEL;
116 } 128 }
117 129
118 return dvo->dev_ops->mode_valid(dvo, mode); 130 return intel_dvo->dev.dev_ops->mode_valid(&intel_dvo->dev, mode);
119} 131}
120 132
121static bool intel_dvo_mode_fixup(struct drm_encoder *encoder, 133static bool intel_dvo_mode_fixup(struct drm_encoder *encoder,
122 struct drm_display_mode *mode, 134 struct drm_display_mode *mode,
123 struct drm_display_mode *adjusted_mode) 135 struct drm_display_mode *adjusted_mode)
124{ 136{
125 struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder); 137 struct intel_dvo *intel_dvo = enc_to_intel_dvo(encoder);
126 struct intel_dvo_device *dvo = intel_encoder->dev_priv;
127 138
128 /* If we have timings from the BIOS for the panel, put them in 139 /* If we have timings from the BIOS for the panel, put them in
129 * to the adjusted mode. The CRTC will be set up for this mode, 140 * to the adjusted mode. The CRTC will be set up for this mode,
130 * with the panel scaling set up to source from the H/VDisplay 141 * with the panel scaling set up to source from the H/VDisplay
131 * of the original mode. 142 * of the original mode.
132 */ 143 */
133 if (dvo->panel_fixed_mode != NULL) { 144 if (intel_dvo->panel_fixed_mode != NULL) {
134#define C(x) adjusted_mode->x = dvo->panel_fixed_mode->x 145#define C(x) adjusted_mode->x = intel_dvo->panel_fixed_mode->x
135 C(hdisplay); 146 C(hdisplay);
136 C(hsync_start); 147 C(hsync_start);
137 C(hsync_end); 148 C(hsync_end);
@@ -145,8 +156,8 @@ static bool intel_dvo_mode_fixup(struct drm_encoder *encoder,
145#undef C 156#undef C
146 } 157 }
147 158
148 if (dvo->dev_ops->mode_fixup) 159 if (intel_dvo->dev.dev_ops->mode_fixup)
149 return dvo->dev_ops->mode_fixup(dvo, mode, adjusted_mode); 160 return intel_dvo->dev.dev_ops->mode_fixup(&intel_dvo->dev, mode, adjusted_mode);
150 161
151 return true; 162 return true;
152} 163}
@@ -158,11 +169,10 @@ static void intel_dvo_mode_set(struct drm_encoder *encoder,
158 struct drm_device *dev = encoder->dev; 169 struct drm_device *dev = encoder->dev;
159 struct drm_i915_private *dev_priv = dev->dev_private; 170 struct drm_i915_private *dev_priv = dev->dev_private;
160 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); 171 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
161 struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder); 172 struct intel_dvo *intel_dvo = enc_to_intel_dvo(encoder);
162 struct intel_dvo_device *dvo = intel_encoder->dev_priv;
163 int pipe = intel_crtc->pipe; 173 int pipe = intel_crtc->pipe;
164 u32 dvo_val; 174 u32 dvo_val;
165 u32 dvo_reg = dvo->dvo_reg, dvo_srcdim_reg; 175 u32 dvo_reg = intel_dvo->dev.dvo_reg, dvo_srcdim_reg;
166 int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B; 176 int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
167 177
168 switch (dvo_reg) { 178 switch (dvo_reg) {
@@ -178,7 +188,7 @@ static void intel_dvo_mode_set(struct drm_encoder *encoder,
178 break; 188 break;
179 } 189 }
180 190
181 dvo->dev_ops->mode_set(dvo, mode, adjusted_mode); 191 intel_dvo->dev.dev_ops->mode_set(&intel_dvo->dev, mode, adjusted_mode);
182 192
183 /* Save the data order, since I don't know what it should be set to. */ 193 /* Save the data order, since I don't know what it should be set to. */
184 dvo_val = I915_READ(dvo_reg) & 194 dvo_val = I915_READ(dvo_reg) &
@@ -214,40 +224,38 @@ static void intel_dvo_mode_set(struct drm_encoder *encoder,
214static enum drm_connector_status intel_dvo_detect(struct drm_connector *connector) 224static enum drm_connector_status intel_dvo_detect(struct drm_connector *connector)
215{ 225{
216 struct drm_encoder *encoder = intel_attached_encoder(connector); 226 struct drm_encoder *encoder = intel_attached_encoder(connector);
217 struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder); 227 struct intel_dvo *intel_dvo = enc_to_intel_dvo(encoder);
218 struct intel_dvo_device *dvo = intel_encoder->dev_priv;
219 228
220 return dvo->dev_ops->detect(dvo); 229 return intel_dvo->dev.dev_ops->detect(&intel_dvo->dev);
221} 230}
222 231
223static int intel_dvo_get_modes(struct drm_connector *connector) 232static int intel_dvo_get_modes(struct drm_connector *connector)
224{ 233{
225 struct drm_encoder *encoder = intel_attached_encoder(connector); 234 struct drm_encoder *encoder = intel_attached_encoder(connector);
226 struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder); 235 struct intel_dvo *intel_dvo = enc_to_intel_dvo(encoder);
227 struct intel_dvo_device *dvo = intel_encoder->dev_priv;
228 236
229 /* We should probably have an i2c driver get_modes function for those 237 /* We should probably have an i2c driver get_modes function for those
230 * devices which will have a fixed set of modes determined by the chip 238 * devices which will have a fixed set of modes determined by the chip
231 * (TV-out, for example), but for now with just TMDS and LVDS, 239 * (TV-out, for example), but for now with just TMDS and LVDS,
232 * that's not the case. 240 * that's not the case.
233 */ 241 */
234 intel_ddc_get_modes(connector, intel_encoder->ddc_bus); 242 intel_ddc_get_modes(connector, intel_dvo->base.ddc_bus);
235 if (!list_empty(&connector->probed_modes)) 243 if (!list_empty(&connector->probed_modes))
236 return 1; 244 return 1;
237 245
238 246 if (intel_dvo->panel_fixed_mode != NULL) {
239 if (dvo->panel_fixed_mode != NULL) {
240 struct drm_display_mode *mode; 247 struct drm_display_mode *mode;
241 mode = drm_mode_duplicate(connector->dev, dvo->panel_fixed_mode); 248 mode = drm_mode_duplicate(connector->dev, intel_dvo->panel_fixed_mode);
242 if (mode) { 249 if (mode) {
243 drm_mode_probed_add(connector, mode); 250 drm_mode_probed_add(connector, mode);
244 return 1; 251 return 1;
245 } 252 }
246 } 253 }
254
247 return 0; 255 return 0;
248} 256}
249 257
250static void intel_dvo_destroy (struct drm_connector *connector) 258static void intel_dvo_destroy(struct drm_connector *connector)
251{ 259{
252 drm_sysfs_connector_remove(connector); 260 drm_sysfs_connector_remove(connector);
253 drm_connector_cleanup(connector); 261 drm_connector_cleanup(connector);
@@ -277,28 +285,20 @@ static const struct drm_connector_helper_funcs intel_dvo_connector_helper_funcs
277 285
278static void intel_dvo_enc_destroy(struct drm_encoder *encoder) 286static void intel_dvo_enc_destroy(struct drm_encoder *encoder)
279{ 287{
280 struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder); 288 struct intel_dvo *intel_dvo = enc_to_intel_dvo(encoder);
281 struct intel_dvo_device *dvo = intel_encoder->dev_priv; 289
282 290 if (intel_dvo->dev.dev_ops->destroy)
283 if (dvo) { 291 intel_dvo->dev.dev_ops->destroy(&intel_dvo->dev);
284 if (dvo->dev_ops->destroy) 292
285 dvo->dev_ops->destroy(dvo); 293 kfree(intel_dvo->panel_fixed_mode);
286 if (dvo->panel_fixed_mode) 294
287 kfree(dvo->panel_fixed_mode); 295 intel_encoder_destroy(encoder);
288 }
289 if (intel_encoder->i2c_bus)
290 intel_i2c_destroy(intel_encoder->i2c_bus);
291 if (intel_encoder->ddc_bus)
292 intel_i2c_destroy(intel_encoder->ddc_bus);
293 drm_encoder_cleanup(encoder);
294 kfree(intel_encoder);
295} 296}
296 297
297static const struct drm_encoder_funcs intel_dvo_enc_funcs = { 298static const struct drm_encoder_funcs intel_dvo_enc_funcs = {
298 .destroy = intel_dvo_enc_destroy, 299 .destroy = intel_dvo_enc_destroy,
299}; 300};
300 301
301
302/** 302/**
303 * Attempts to get a fixed panel timing for LVDS (currently only the i830). 303 * Attempts to get a fixed panel timing for LVDS (currently only the i830).
304 * 304 *
@@ -306,15 +306,13 @@ static const struct drm_encoder_funcs intel_dvo_enc_funcs = {
306 * chip being on DVOB/C and having multiple pipes. 306 * chip being on DVOB/C and having multiple pipes.
307 */ 307 */
308static struct drm_display_mode * 308static struct drm_display_mode *
309intel_dvo_get_current_mode (struct drm_connector *connector) 309intel_dvo_get_current_mode(struct drm_connector *connector)
310{ 310{
311 struct drm_device *dev = connector->dev; 311 struct drm_device *dev = connector->dev;
312 struct drm_i915_private *dev_priv = dev->dev_private; 312 struct drm_i915_private *dev_priv = dev->dev_private;
313 struct drm_encoder *encoder = intel_attached_encoder(connector); 313 struct drm_encoder *encoder = intel_attached_encoder(connector);
314 struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder); 314 struct intel_dvo *intel_dvo = enc_to_intel_dvo(encoder);
315 struct intel_dvo_device *dvo = intel_encoder->dev_priv; 315 uint32_t dvo_val = I915_READ(intel_dvo->dev.dvo_reg);
316 uint32_t dvo_reg = dvo->dvo_reg;
317 uint32_t dvo_val = I915_READ(dvo_reg);
318 struct drm_display_mode *mode = NULL; 316 struct drm_display_mode *mode = NULL;
319 317
320 /* If the DVO port is active, that'll be the LVDS, so we can pull out 318 /* If the DVO port is active, that'll be the LVDS, so we can pull out
@@ -327,7 +325,6 @@ intel_dvo_get_current_mode (struct drm_connector *connector)
327 crtc = intel_get_crtc_from_pipe(dev, pipe); 325 crtc = intel_get_crtc_from_pipe(dev, pipe);
328 if (crtc) { 326 if (crtc) {
329 mode = intel_crtc_mode_get(dev, crtc); 327 mode = intel_crtc_mode_get(dev, crtc);
330
331 if (mode) { 328 if (mode) {
332 mode->type |= DRM_MODE_TYPE_PREFERRED; 329 mode->type |= DRM_MODE_TYPE_PREFERRED;
333 if (dvo_val & DVO_HSYNC_ACTIVE_HIGH) 330 if (dvo_val & DVO_HSYNC_ACTIVE_HIGH)
@@ -337,28 +334,32 @@ intel_dvo_get_current_mode (struct drm_connector *connector)
337 } 334 }
338 } 335 }
339 } 336 }
337
340 return mode; 338 return mode;
341} 339}
342 340
343void intel_dvo_init(struct drm_device *dev) 341void intel_dvo_init(struct drm_device *dev)
344{ 342{
345 struct intel_encoder *intel_encoder; 343 struct intel_encoder *intel_encoder;
344 struct intel_dvo *intel_dvo;
346 struct intel_connector *intel_connector; 345 struct intel_connector *intel_connector;
347 struct intel_dvo_device *dvo;
348 struct i2c_adapter *i2cbus = NULL; 346 struct i2c_adapter *i2cbus = NULL;
349 int ret = 0; 347 int ret = 0;
350 int i; 348 int i;
351 int encoder_type = DRM_MODE_ENCODER_NONE; 349 int encoder_type = DRM_MODE_ENCODER_NONE;
352 intel_encoder = kzalloc (sizeof(struct intel_encoder), GFP_KERNEL); 350
353 if (!intel_encoder) 351 intel_dvo = kzalloc(sizeof(struct intel_dvo), GFP_KERNEL);
352 if (!intel_dvo)
354 return; 353 return;
355 354
356 intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL); 355 intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
357 if (!intel_connector) { 356 if (!intel_connector) {
358 kfree(intel_encoder); 357 kfree(intel_dvo);
359 return; 358 return;
360 } 359 }
361 360
361 intel_encoder = &intel_dvo->base;
362
362 /* Set up the DDC bus */ 363 /* Set up the DDC bus */
363 intel_encoder->ddc_bus = intel_i2c_create(dev, GPIOD, "DVODDC_D"); 364 intel_encoder->ddc_bus = intel_i2c_create(dev, GPIOD, "DVODDC_D");
364 if (!intel_encoder->ddc_bus) 365 if (!intel_encoder->ddc_bus)
@@ -367,10 +368,9 @@ void intel_dvo_init(struct drm_device *dev)
367 /* Now, try to find a controller */ 368 /* Now, try to find a controller */
368 for (i = 0; i < ARRAY_SIZE(intel_dvo_devices); i++) { 369 for (i = 0; i < ARRAY_SIZE(intel_dvo_devices); i++) {
369 struct drm_connector *connector = &intel_connector->base; 370 struct drm_connector *connector = &intel_connector->base;
371 const struct intel_dvo_device *dvo = &intel_dvo_devices[i];
370 int gpio; 372 int gpio;
371 373
372 dvo = &intel_dvo_devices[i];
373
374 /* Allow the I2C driver info to specify the GPIO to be used in 374 /* Allow the I2C driver info to specify the GPIO to be used in
375 * special cases, but otherwise default to what's defined 375 * special cases, but otherwise default to what's defined
376 * in the spec. 376 * in the spec.
@@ -393,11 +393,8 @@ void intel_dvo_init(struct drm_device *dev)
393 continue; 393 continue;
394 } 394 }
395 395
396 if (dvo->dev_ops!= NULL) 396 intel_dvo->dev = *dvo;
397 ret = dvo->dev_ops->init(dvo, i2cbus); 397 ret = dvo->dev_ops->init(&intel_dvo->dev, i2cbus);
398 else
399 ret = false;
400
401 if (!ret) 398 if (!ret)
402 continue; 399 continue;
403 400
@@ -429,9 +426,6 @@ void intel_dvo_init(struct drm_device *dev)
429 connector->interlace_allowed = false; 426 connector->interlace_allowed = false;
430 connector->doublescan_allowed = false; 427 connector->doublescan_allowed = false;
431 428
432 intel_encoder->dev_priv = dvo;
433 intel_encoder->i2c_bus = i2cbus;
434
435 drm_encoder_init(dev, &intel_encoder->enc, 429 drm_encoder_init(dev, &intel_encoder->enc,
436 &intel_dvo_enc_funcs, encoder_type); 430 &intel_dvo_enc_funcs, encoder_type);
437 drm_encoder_helper_add(&intel_encoder->enc, 431 drm_encoder_helper_add(&intel_encoder->enc,
@@ -447,9 +441,9 @@ void intel_dvo_init(struct drm_device *dev)
447 * headers, likely), so for now, just get the current 441 * headers, likely), so for now, just get the current
448 * mode being output through DVO. 442 * mode being output through DVO.
449 */ 443 */
450 dvo->panel_fixed_mode = 444 intel_dvo->panel_fixed_mode =
451 intel_dvo_get_current_mode(connector); 445 intel_dvo_get_current_mode(connector);
452 dvo->panel_wants_dither = true; 446 intel_dvo->panel_wants_dither = true;
453 } 447 }
454 448
455 drm_sysfs_connector_add(connector); 449 drm_sysfs_connector_add(connector);
@@ -461,6 +455,6 @@ void intel_dvo_init(struct drm_device *dev)
461 if (i2cbus != NULL) 455 if (i2cbus != NULL)
462 intel_i2c_destroy(i2cbus); 456 intel_i2c_destroy(i2cbus);
463free_intel: 457free_intel:
464 kfree(intel_encoder); 458 kfree(intel_dvo);
465 kfree(intel_connector); 459 kfree(intel_connector);
466} 460}
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
index 197887ed1823..ccd4c97e6524 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -37,11 +37,17 @@
37#include "i915_drm.h" 37#include "i915_drm.h"
38#include "i915_drv.h" 38#include "i915_drv.h"
39 39
40struct intel_hdmi_priv { 40struct intel_hdmi {
41 struct intel_encoder base;
41 u32 sdvox_reg; 42 u32 sdvox_reg;
42 bool has_hdmi_sink; 43 bool has_hdmi_sink;
43}; 44};
44 45
46static struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder)
47{
48 return container_of(enc_to_intel_encoder(encoder), struct intel_hdmi, base);
49}
50
45static void intel_hdmi_mode_set(struct drm_encoder *encoder, 51static void intel_hdmi_mode_set(struct drm_encoder *encoder,
46 struct drm_display_mode *mode, 52 struct drm_display_mode *mode,
47 struct drm_display_mode *adjusted_mode) 53 struct drm_display_mode *adjusted_mode)
@@ -50,8 +56,7 @@ static void intel_hdmi_mode_set(struct drm_encoder *encoder,
50 struct drm_i915_private *dev_priv = dev->dev_private; 56 struct drm_i915_private *dev_priv = dev->dev_private;
51 struct drm_crtc *crtc = encoder->crtc; 57 struct drm_crtc *crtc = encoder->crtc;
52 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 58 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
53 struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder); 59 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
54 struct intel_hdmi_priv *hdmi_priv = intel_encoder->dev_priv;
55 u32 sdvox; 60 u32 sdvox;
56 61
57 sdvox = SDVO_ENCODING_HDMI | SDVO_BORDER_ENABLE; 62 sdvox = SDVO_ENCODING_HDMI | SDVO_BORDER_ENABLE;
@@ -60,7 +65,7 @@ static void intel_hdmi_mode_set(struct drm_encoder *encoder,
60 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) 65 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
61 sdvox |= SDVO_HSYNC_ACTIVE_HIGH; 66 sdvox |= SDVO_HSYNC_ACTIVE_HIGH;
62 67
63 if (hdmi_priv->has_hdmi_sink) { 68 if (intel_hdmi->has_hdmi_sink) {
64 sdvox |= SDVO_AUDIO_ENABLE; 69 sdvox |= SDVO_AUDIO_ENABLE;
65 if (HAS_PCH_CPT(dev)) 70 if (HAS_PCH_CPT(dev))
66 sdvox |= HDMI_MODE_SELECT; 71 sdvox |= HDMI_MODE_SELECT;
@@ -73,26 +78,25 @@ static void intel_hdmi_mode_set(struct drm_encoder *encoder,
73 sdvox |= SDVO_PIPE_B_SELECT; 78 sdvox |= SDVO_PIPE_B_SELECT;
74 } 79 }
75 80
76 I915_WRITE(hdmi_priv->sdvox_reg, sdvox); 81 I915_WRITE(intel_hdmi->sdvox_reg, sdvox);
77 POSTING_READ(hdmi_priv->sdvox_reg); 82 POSTING_READ(intel_hdmi->sdvox_reg);
78} 83}
79 84
80static void intel_hdmi_dpms(struct drm_encoder *encoder, int mode) 85static void intel_hdmi_dpms(struct drm_encoder *encoder, int mode)
81{ 86{
82 struct drm_device *dev = encoder->dev; 87 struct drm_device *dev = encoder->dev;
83 struct drm_i915_private *dev_priv = dev->dev_private; 88 struct drm_i915_private *dev_priv = dev->dev_private;
84 struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder); 89 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
85 struct intel_hdmi_priv *hdmi_priv = intel_encoder->dev_priv;
86 u32 temp; 90 u32 temp;
87 91
88 temp = I915_READ(hdmi_priv->sdvox_reg); 92 temp = I915_READ(intel_hdmi->sdvox_reg);
89 93
90 /* HW workaround, need to toggle enable bit off and on for 12bpc, but 94 /* HW workaround, need to toggle enable bit off and on for 12bpc, but
91 * we do this anyway which shows more stable in testing. 95 * we do this anyway which shows more stable in testing.
92 */ 96 */
93 if (HAS_PCH_SPLIT(dev)) { 97 if (HAS_PCH_SPLIT(dev)) {
94 I915_WRITE(hdmi_priv->sdvox_reg, temp & ~SDVO_ENABLE); 98 I915_WRITE(intel_hdmi->sdvox_reg, temp & ~SDVO_ENABLE);
95 POSTING_READ(hdmi_priv->sdvox_reg); 99 POSTING_READ(intel_hdmi->sdvox_reg);
96 } 100 }
97 101
98 if (mode != DRM_MODE_DPMS_ON) { 102 if (mode != DRM_MODE_DPMS_ON) {
@@ -101,15 +105,15 @@ static void intel_hdmi_dpms(struct drm_encoder *encoder, int mode)
101 temp |= SDVO_ENABLE; 105 temp |= SDVO_ENABLE;
102 } 106 }
103 107
104 I915_WRITE(hdmi_priv->sdvox_reg, temp); 108 I915_WRITE(intel_hdmi->sdvox_reg, temp);
105 POSTING_READ(hdmi_priv->sdvox_reg); 109 POSTING_READ(intel_hdmi->sdvox_reg);
106 110
107 /* HW workaround, need to write this twice for issue that may result 111 /* HW workaround, need to write this twice for issue that may result
108 * in first write getting masked. 112 * in first write getting masked.
109 */ 113 */
110 if (HAS_PCH_SPLIT(dev)) { 114 if (HAS_PCH_SPLIT(dev)) {
111 I915_WRITE(hdmi_priv->sdvox_reg, temp); 115 I915_WRITE(intel_hdmi->sdvox_reg, temp);
112 POSTING_READ(hdmi_priv->sdvox_reg); 116 POSTING_READ(intel_hdmi->sdvox_reg);
113 } 117 }
114} 118}
115 119
@@ -138,19 +142,17 @@ static enum drm_connector_status
138intel_hdmi_detect(struct drm_connector *connector) 142intel_hdmi_detect(struct drm_connector *connector)
139{ 143{
140 struct drm_encoder *encoder = intel_attached_encoder(connector); 144 struct drm_encoder *encoder = intel_attached_encoder(connector);
141 struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder); 145 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
142 struct intel_hdmi_priv *hdmi_priv = intel_encoder->dev_priv;
143 struct edid *edid = NULL; 146 struct edid *edid = NULL;
144 enum drm_connector_status status = connector_status_disconnected; 147 enum drm_connector_status status = connector_status_disconnected;
145 148
146 hdmi_priv->has_hdmi_sink = false; 149 intel_hdmi->has_hdmi_sink = false;
147 edid = drm_get_edid(connector, 150 edid = drm_get_edid(connector, intel_hdmi->base.ddc_bus);
148 intel_encoder->ddc_bus);
149 151
150 if (edid) { 152 if (edid) {
151 if (edid->input & DRM_EDID_INPUT_DIGITAL) { 153 if (edid->input & DRM_EDID_INPUT_DIGITAL) {
152 status = connector_status_connected; 154 status = connector_status_connected;
153 hdmi_priv->has_hdmi_sink = drm_detect_hdmi_monitor(edid); 155 intel_hdmi->has_hdmi_sink = drm_detect_hdmi_monitor(edid);
154 } 156 }
155 connector->display_info.raw_edid = NULL; 157 connector->display_info.raw_edid = NULL;
156 kfree(edid); 158 kfree(edid);
@@ -162,13 +164,13 @@ intel_hdmi_detect(struct drm_connector *connector)
162static int intel_hdmi_get_modes(struct drm_connector *connector) 164static int intel_hdmi_get_modes(struct drm_connector *connector)
163{ 165{
164 struct drm_encoder *encoder = intel_attached_encoder(connector); 166 struct drm_encoder *encoder = intel_attached_encoder(connector);
165 struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder); 167 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
166 168
167 /* We should parse the EDID data and find out if it's an HDMI sink so 169 /* We should parse the EDID data and find out if it's an HDMI sink so
168 * we can send audio to it. 170 * we can send audio to it.
169 */ 171 */
170 172
171 return intel_ddc_get_modes(connector, intel_encoder->ddc_bus); 173 return intel_ddc_get_modes(connector, intel_hdmi->base.ddc_bus);
172} 174}
173 175
174static void intel_hdmi_destroy(struct drm_connector *connector) 176static void intel_hdmi_destroy(struct drm_connector *connector)
@@ -199,18 +201,8 @@ static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs
199 .best_encoder = intel_attached_encoder, 201 .best_encoder = intel_attached_encoder,
200}; 202};
201 203
202static void intel_hdmi_enc_destroy(struct drm_encoder *encoder)
203{
204 struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
205
206 if (intel_encoder->i2c_bus)
207 intel_i2c_destroy(intel_encoder->i2c_bus);
208 drm_encoder_cleanup(encoder);
209 kfree(intel_encoder);
210}
211
212static const struct drm_encoder_funcs intel_hdmi_enc_funcs = { 204static const struct drm_encoder_funcs intel_hdmi_enc_funcs = {
213 .destroy = intel_hdmi_enc_destroy, 205 .destroy = intel_encoder_destroy,
214}; 206};
215 207
216void intel_hdmi_init(struct drm_device *dev, int sdvox_reg) 208void intel_hdmi_init(struct drm_device *dev, int sdvox_reg)
@@ -219,21 +211,19 @@ void intel_hdmi_init(struct drm_device *dev, int sdvox_reg)
219 struct drm_connector *connector; 211 struct drm_connector *connector;
220 struct intel_encoder *intel_encoder; 212 struct intel_encoder *intel_encoder;
221 struct intel_connector *intel_connector; 213 struct intel_connector *intel_connector;
222 struct intel_hdmi_priv *hdmi_priv; 214 struct intel_hdmi *intel_hdmi;
223 215
224 intel_encoder = kcalloc(sizeof(struct intel_encoder) + 216 intel_hdmi = kzalloc(sizeof(struct intel_hdmi), GFP_KERNEL);
225 sizeof(struct intel_hdmi_priv), 1, GFP_KERNEL); 217 if (!intel_hdmi)
226 if (!intel_encoder)
227 return; 218 return;
228 219
229 intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL); 220 intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
230 if (!intel_connector) { 221 if (!intel_connector) {
231 kfree(intel_encoder); 222 kfree(intel_hdmi);
232 return; 223 return;
233 } 224 }
234 225
235 hdmi_priv = (struct intel_hdmi_priv *)(intel_encoder + 1); 226 intel_encoder = &intel_hdmi->base;
236
237 connector = &intel_connector->base; 227 connector = &intel_connector->base;
238 drm_connector_init(dev, connector, &intel_hdmi_connector_funcs, 228 drm_connector_init(dev, connector, &intel_hdmi_connector_funcs,
239 DRM_MODE_CONNECTOR_HDMIA); 229 DRM_MODE_CONNECTOR_HDMIA);
@@ -274,8 +264,7 @@ void intel_hdmi_init(struct drm_device *dev, int sdvox_reg)
274 if (!intel_encoder->ddc_bus) 264 if (!intel_encoder->ddc_bus)
275 goto err_connector; 265 goto err_connector;
276 266
277 hdmi_priv->sdvox_reg = sdvox_reg; 267 intel_hdmi->sdvox_reg = sdvox_reg;
278 intel_encoder->dev_priv = hdmi_priv;
279 268
280 drm_encoder_init(dev, &intel_encoder->enc, &intel_hdmi_enc_funcs, 269 drm_encoder_init(dev, &intel_encoder->enc, &intel_hdmi_enc_funcs,
281 DRM_MODE_ENCODER_TMDS); 270 DRM_MODE_ENCODER_TMDS);
@@ -298,7 +287,7 @@ void intel_hdmi_init(struct drm_device *dev, int sdvox_reg)
298 287
299err_connector: 288err_connector:
300 drm_connector_cleanup(connector); 289 drm_connector_cleanup(connector);
301 kfree(intel_encoder); 290 kfree(intel_hdmi);
302 kfree(intel_connector); 291 kfree(intel_connector);
303 292
304 return; 293 return;
diff --git a/drivers/gpu/drm/i915/intel_lvds.c b/drivers/gpu/drm/i915/intel_lvds.c
index 0a2e60059fb3..b819c1081147 100644
--- a/drivers/gpu/drm/i915/intel_lvds.c
+++ b/drivers/gpu/drm/i915/intel_lvds.c
@@ -41,12 +41,18 @@
41#include <linux/acpi.h> 41#include <linux/acpi.h>
42 42
43/* Private structure for the integrated LVDS support */ 43/* Private structure for the integrated LVDS support */
44struct intel_lvds_priv { 44struct intel_lvds {
45 struct intel_encoder base;
45 int fitting_mode; 46 int fitting_mode;
46 u32 pfit_control; 47 u32 pfit_control;
47 u32 pfit_pgm_ratios; 48 u32 pfit_pgm_ratios;
48}; 49};
49 50
51static struct intel_lvds *enc_to_intel_lvds(struct drm_encoder *encoder)
52{
53 return container_of(enc_to_intel_encoder(encoder), struct intel_lvds, base);
54}
55
50/** 56/**
51 * Sets the backlight level. 57 * Sets the backlight level.
52 * 58 *
@@ -90,7 +96,7 @@ static u32 intel_lvds_get_max_backlight(struct drm_device *dev)
90static void intel_lvds_set_power(struct drm_device *dev, bool on) 96static void intel_lvds_set_power(struct drm_device *dev, bool on)
91{ 97{
92 struct drm_i915_private *dev_priv = dev->dev_private; 98 struct drm_i915_private *dev_priv = dev->dev_private;
93 u32 pp_status, ctl_reg, status_reg, lvds_reg; 99 u32 ctl_reg, status_reg, lvds_reg;
94 100
95 if (HAS_PCH_SPLIT(dev)) { 101 if (HAS_PCH_SPLIT(dev)) {
96 ctl_reg = PCH_PP_CONTROL; 102 ctl_reg = PCH_PP_CONTROL;
@@ -108,9 +114,8 @@ static void intel_lvds_set_power(struct drm_device *dev, bool on)
108 114
109 I915_WRITE(ctl_reg, I915_READ(ctl_reg) | 115 I915_WRITE(ctl_reg, I915_READ(ctl_reg) |
110 POWER_TARGET_ON); 116 POWER_TARGET_ON);
111 do { 117 if (wait_for(I915_READ(status_reg) & PP_ON, 1000, 0))
112 pp_status = I915_READ(status_reg); 118 DRM_ERROR("timed out waiting to enable LVDS pipe");
113 } while ((pp_status & PP_ON) == 0);
114 119
115 intel_lvds_set_backlight(dev, dev_priv->backlight_duty_cycle); 120 intel_lvds_set_backlight(dev, dev_priv->backlight_duty_cycle);
116 } else { 121 } else {
@@ -118,9 +123,8 @@ static void intel_lvds_set_power(struct drm_device *dev, bool on)
118 123
119 I915_WRITE(ctl_reg, I915_READ(ctl_reg) & 124 I915_WRITE(ctl_reg, I915_READ(ctl_reg) &
120 ~POWER_TARGET_ON); 125 ~POWER_TARGET_ON);
121 do { 126 if (wait_for((I915_READ(status_reg) & PP_ON) == 0, 1000, 0))
122 pp_status = I915_READ(status_reg); 127 DRM_ERROR("timed out waiting for LVDS pipe to turn off");
123 } while (pp_status & PP_ON);
124 128
125 I915_WRITE(lvds_reg, I915_READ(lvds_reg) & ~LVDS_PORT_EN); 129 I915_WRITE(lvds_reg, I915_READ(lvds_reg) & ~LVDS_PORT_EN);
126 POSTING_READ(lvds_reg); 130 POSTING_READ(lvds_reg);
@@ -219,9 +223,8 @@ static bool intel_lvds_mode_fixup(struct drm_encoder *encoder,
219 struct drm_device *dev = encoder->dev; 223 struct drm_device *dev = encoder->dev;
220 struct drm_i915_private *dev_priv = dev->dev_private; 224 struct drm_i915_private *dev_priv = dev->dev_private;
221 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); 225 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
226 struct intel_lvds *intel_lvds = enc_to_intel_lvds(encoder);
222 struct drm_encoder *tmp_encoder; 227 struct drm_encoder *tmp_encoder;
223 struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
224 struct intel_lvds_priv *lvds_priv = intel_encoder->dev_priv;
225 u32 pfit_control = 0, pfit_pgm_ratios = 0, border = 0; 228 u32 pfit_control = 0, pfit_pgm_ratios = 0, border = 0;
226 229
227 /* Should never happen!! */ 230 /* Should never happen!! */
@@ -241,26 +244,20 @@ static bool intel_lvds_mode_fixup(struct drm_encoder *encoder,
241 /* If we don't have a panel mode, there is nothing we can do */ 244 /* If we don't have a panel mode, there is nothing we can do */
242 if (dev_priv->panel_fixed_mode == NULL) 245 if (dev_priv->panel_fixed_mode == NULL)
243 return true; 246 return true;
247
244 /* 248 /*
245 * We have timings from the BIOS for the panel, put them in 249 * We have timings from the BIOS for the panel, put them in
246 * to the adjusted mode. The CRTC will be set up for this mode, 250 * to the adjusted mode. The CRTC will be set up for this mode,
247 * with the panel scaling set up to source from the H/VDisplay 251 * with the panel scaling set up to source from the H/VDisplay
248 * of the original mode. 252 * of the original mode.
249 */ 253 */
250 adjusted_mode->hdisplay = dev_priv->panel_fixed_mode->hdisplay; 254 intel_fixed_panel_mode(dev_priv->panel_fixed_mode, adjusted_mode);
251 adjusted_mode->hsync_start = 255
252 dev_priv->panel_fixed_mode->hsync_start; 256 if (HAS_PCH_SPLIT(dev)) {
253 adjusted_mode->hsync_end = 257 intel_pch_panel_fitting(dev, intel_lvds->fitting_mode,
254 dev_priv->panel_fixed_mode->hsync_end; 258 mode, adjusted_mode);
255 adjusted_mode->htotal = dev_priv->panel_fixed_mode->htotal; 259 return true;
256 adjusted_mode->vdisplay = dev_priv->panel_fixed_mode->vdisplay; 260 }
257 adjusted_mode->vsync_start =
258 dev_priv->panel_fixed_mode->vsync_start;
259 adjusted_mode->vsync_end =
260 dev_priv->panel_fixed_mode->vsync_end;
261 adjusted_mode->vtotal = dev_priv->panel_fixed_mode->vtotal;
262 adjusted_mode->clock = dev_priv->panel_fixed_mode->clock;
263 drm_mode_set_crtcinfo(adjusted_mode, CRTC_INTERLACE_HALVE_V);
264 261
265 /* Make sure pre-965s set dither correctly */ 262 /* Make sure pre-965s set dither correctly */
266 if (!IS_I965G(dev)) { 263 if (!IS_I965G(dev)) {
@@ -273,10 +270,6 @@ static bool intel_lvds_mode_fixup(struct drm_encoder *encoder,
273 adjusted_mode->vdisplay == mode->vdisplay) 270 adjusted_mode->vdisplay == mode->vdisplay)
274 goto out; 271 goto out;
275 272
276 /* full screen scale for now */
277 if (HAS_PCH_SPLIT(dev))
278 goto out;
279
280 /* 965+ wants fuzzy fitting */ 273 /* 965+ wants fuzzy fitting */
281 if (IS_I965G(dev)) 274 if (IS_I965G(dev))
282 pfit_control |= ((intel_crtc->pipe << PFIT_PIPE_SHIFT) | 275 pfit_control |= ((intel_crtc->pipe << PFIT_PIPE_SHIFT) |
@@ -288,12 +281,10 @@ static bool intel_lvds_mode_fixup(struct drm_encoder *encoder,
288 * to register description and PRM. 281 * to register description and PRM.
289 * Change the value here to see the borders for debugging 282 * Change the value here to see the borders for debugging
290 */ 283 */
291 if (!HAS_PCH_SPLIT(dev)) { 284 I915_WRITE(BCLRPAT_A, 0);
292 I915_WRITE(BCLRPAT_A, 0); 285 I915_WRITE(BCLRPAT_B, 0);
293 I915_WRITE(BCLRPAT_B, 0);
294 }
295 286
296 switch (lvds_priv->fitting_mode) { 287 switch (intel_lvds->fitting_mode) {
297 case DRM_MODE_SCALE_CENTER: 288 case DRM_MODE_SCALE_CENTER:
298 /* 289 /*
299 * For centered modes, we have to calculate border widths & 290 * For centered modes, we have to calculate border widths &
@@ -378,8 +369,8 @@ static bool intel_lvds_mode_fixup(struct drm_encoder *encoder,
378 } 369 }
379 370
380out: 371out:
381 lvds_priv->pfit_control = pfit_control; 372 intel_lvds->pfit_control = pfit_control;
382 lvds_priv->pfit_pgm_ratios = pfit_pgm_ratios; 373 intel_lvds->pfit_pgm_ratios = pfit_pgm_ratios;
383 dev_priv->lvds_border_bits = border; 374 dev_priv->lvds_border_bits = border;
384 375
385 /* 376 /*
@@ -427,8 +418,7 @@ static void intel_lvds_mode_set(struct drm_encoder *encoder,
427{ 418{
428 struct drm_device *dev = encoder->dev; 419 struct drm_device *dev = encoder->dev;
429 struct drm_i915_private *dev_priv = dev->dev_private; 420 struct drm_i915_private *dev_priv = dev->dev_private;
430 struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder); 421 struct intel_lvds *intel_lvds = enc_to_intel_lvds(encoder);
431 struct intel_lvds_priv *lvds_priv = intel_encoder->dev_priv;
432 422
433 /* 423 /*
434 * The LVDS pin pair will already have been turned on in the 424 * The LVDS pin pair will already have been turned on in the
@@ -444,8 +434,8 @@ static void intel_lvds_mode_set(struct drm_encoder *encoder,
444 * screen. Should be enabled before the pipe is enabled, according to 434 * screen. Should be enabled before the pipe is enabled, according to
445 * register description and PRM. 435 * register description and PRM.
446 */ 436 */
447 I915_WRITE(PFIT_PGM_RATIOS, lvds_priv->pfit_pgm_ratios); 437 I915_WRITE(PFIT_PGM_RATIOS, intel_lvds->pfit_pgm_ratios);
448 I915_WRITE(PFIT_CONTROL, lvds_priv->pfit_control); 438 I915_WRITE(PFIT_CONTROL, intel_lvds->pfit_control);
449} 439}
450 440
451/** 441/**
@@ -600,18 +590,17 @@ static int intel_lvds_set_property(struct drm_connector *connector,
600 connector->encoder) { 590 connector->encoder) {
601 struct drm_crtc *crtc = connector->encoder->crtc; 591 struct drm_crtc *crtc = connector->encoder->crtc;
602 struct drm_encoder *encoder = connector->encoder; 592 struct drm_encoder *encoder = connector->encoder;
603 struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder); 593 struct intel_lvds *intel_lvds = enc_to_intel_lvds(encoder);
604 struct intel_lvds_priv *lvds_priv = intel_encoder->dev_priv;
605 594
606 if (value == DRM_MODE_SCALE_NONE) { 595 if (value == DRM_MODE_SCALE_NONE) {
607 DRM_DEBUG_KMS("no scaling not supported\n"); 596 DRM_DEBUG_KMS("no scaling not supported\n");
608 return 0; 597 return 0;
609 } 598 }
610 if (lvds_priv->fitting_mode == value) { 599 if (intel_lvds->fitting_mode == value) {
611 /* the LVDS scaling property is not changed */ 600 /* the LVDS scaling property is not changed */
612 return 0; 601 return 0;
613 } 602 }
614 lvds_priv->fitting_mode = value; 603 intel_lvds->fitting_mode = value;
615 if (crtc && crtc->enabled) { 604 if (crtc && crtc->enabled) {
616 /* 605 /*
617 * If the CRTC is enabled, the display will be changed 606 * If the CRTC is enabled, the display will be changed
@@ -647,19 +636,8 @@ static const struct drm_connector_funcs intel_lvds_connector_funcs = {
647 .destroy = intel_lvds_destroy, 636 .destroy = intel_lvds_destroy,
648}; 637};
649 638
650
651static void intel_lvds_enc_destroy(struct drm_encoder *encoder)
652{
653 struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
654
655 if (intel_encoder->ddc_bus)
656 intel_i2c_destroy(intel_encoder->ddc_bus);
657 drm_encoder_cleanup(encoder);
658 kfree(intel_encoder);
659}
660
661static const struct drm_encoder_funcs intel_lvds_enc_funcs = { 639static const struct drm_encoder_funcs intel_lvds_enc_funcs = {
662 .destroy = intel_lvds_enc_destroy, 640 .destroy = intel_encoder_destroy,
663}; 641};
664 642
665static int __init intel_no_lvds_dmi_callback(const struct dmi_system_id *id) 643static int __init intel_no_lvds_dmi_callback(const struct dmi_system_id *id)
@@ -843,13 +821,13 @@ static int lvds_is_present_in_vbt(struct drm_device *dev)
843void intel_lvds_init(struct drm_device *dev) 821void intel_lvds_init(struct drm_device *dev)
844{ 822{
845 struct drm_i915_private *dev_priv = dev->dev_private; 823 struct drm_i915_private *dev_priv = dev->dev_private;
824 struct intel_lvds *intel_lvds;
846 struct intel_encoder *intel_encoder; 825 struct intel_encoder *intel_encoder;
847 struct intel_connector *intel_connector; 826 struct intel_connector *intel_connector;
848 struct drm_connector *connector; 827 struct drm_connector *connector;
849 struct drm_encoder *encoder; 828 struct drm_encoder *encoder;
850 struct drm_display_mode *scan; /* *modes, *bios_mode; */ 829 struct drm_display_mode *scan; /* *modes, *bios_mode; */
851 struct drm_crtc *crtc; 830 struct drm_crtc *crtc;
852 struct intel_lvds_priv *lvds_priv;
853 u32 lvds; 831 u32 lvds;
854 int pipe, gpio = GPIOC; 832 int pipe, gpio = GPIOC;
855 833
@@ -872,20 +850,20 @@ void intel_lvds_init(struct drm_device *dev)
872 gpio = PCH_GPIOC; 850 gpio = PCH_GPIOC;
873 } 851 }
874 852
875 intel_encoder = kzalloc(sizeof(struct intel_encoder) + 853 intel_lvds = kzalloc(sizeof(struct intel_lvds), GFP_KERNEL);
876 sizeof(struct intel_lvds_priv), GFP_KERNEL); 854 if (!intel_lvds) {
877 if (!intel_encoder) {
878 return; 855 return;
879 } 856 }
880 857
881 intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL); 858 intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
882 if (!intel_connector) { 859 if (!intel_connector) {
883 kfree(intel_encoder); 860 kfree(intel_lvds);
884 return; 861 return;
885 } 862 }
886 863
887 connector = &intel_connector->base; 864 intel_encoder = &intel_lvds->base;
888 encoder = &intel_encoder->enc; 865 encoder = &intel_encoder->enc;
866 connector = &intel_connector->base;
889 drm_connector_init(dev, &intel_connector->base, &intel_lvds_connector_funcs, 867 drm_connector_init(dev, &intel_connector->base, &intel_lvds_connector_funcs,
890 DRM_MODE_CONNECTOR_LVDS); 868 DRM_MODE_CONNECTOR_LVDS);
891 869
@@ -905,8 +883,6 @@ void intel_lvds_init(struct drm_device *dev)
905 connector->interlace_allowed = false; 883 connector->interlace_allowed = false;
906 connector->doublescan_allowed = false; 884 connector->doublescan_allowed = false;
907 885
908 lvds_priv = (struct intel_lvds_priv *)(intel_encoder + 1);
909 intel_encoder->dev_priv = lvds_priv;
910 /* create the scaling mode property */ 886 /* create the scaling mode property */
911 drm_mode_create_scaling_mode_property(dev); 887 drm_mode_create_scaling_mode_property(dev);
912 /* 888 /*
@@ -916,7 +892,7 @@ void intel_lvds_init(struct drm_device *dev)
916 drm_connector_attach_property(&intel_connector->base, 892 drm_connector_attach_property(&intel_connector->base,
917 dev->mode_config.scaling_mode_property, 893 dev->mode_config.scaling_mode_property,
918 DRM_MODE_SCALE_ASPECT); 894 DRM_MODE_SCALE_ASPECT);
919 lvds_priv->fitting_mode = DRM_MODE_SCALE_ASPECT; 895 intel_lvds->fitting_mode = DRM_MODE_SCALE_ASPECT;
920 /* 896 /*
921 * LVDS discovery: 897 * LVDS discovery:
922 * 1) check for EDID on DDC 898 * 1) check for EDID on DDC
@@ -1024,6 +1000,6 @@ failed:
1024 intel_i2c_destroy(intel_encoder->ddc_bus); 1000 intel_i2c_destroy(intel_encoder->ddc_bus);
1025 drm_connector_cleanup(connector); 1001 drm_connector_cleanup(connector);
1026 drm_encoder_cleanup(encoder); 1002 drm_encoder_cleanup(encoder);
1027 kfree(intel_encoder); 1003 kfree(intel_lvds);
1028 kfree(intel_connector); 1004 kfree(intel_connector);
1029} 1005}
diff --git a/drivers/gpu/drm/i915/intel_overlay.c b/drivers/gpu/drm/i915/intel_overlay.c
index d39aea24eabe..1d306a458be6 100644
--- a/drivers/gpu/drm/i915/intel_overlay.c
+++ b/drivers/gpu/drm/i915/intel_overlay.c
@@ -25,6 +25,8 @@
25 * 25 *
26 * Derived from Xorg ddx, xf86-video-intel, src/i830_video.c 26 * Derived from Xorg ddx, xf86-video-intel, src/i830_video.c
27 */ 27 */
28
29#include <linux/seq_file.h>
28#include "drmP.h" 30#include "drmP.h"
29#include "drm.h" 31#include "drm.h"
30#include "i915_drm.h" 32#include "i915_drm.h"
@@ -1367,7 +1369,8 @@ void intel_setup_overlay(struct drm_device *dev)
1367 overlay->flip_addr = overlay->reg_bo->gtt_offset; 1369 overlay->flip_addr = overlay->reg_bo->gtt_offset;
1368 } else { 1370 } else {
1369 ret = i915_gem_attach_phys_object(dev, reg_bo, 1371 ret = i915_gem_attach_phys_object(dev, reg_bo,
1370 I915_GEM_PHYS_OVERLAY_REGS); 1372 I915_GEM_PHYS_OVERLAY_REGS,
1373 0);
1371 if (ret) { 1374 if (ret) {
1372 DRM_ERROR("failed to attach phys overlay regs\n"); 1375 DRM_ERROR("failed to attach phys overlay regs\n");
1373 goto out_free_bo; 1376 goto out_free_bo;
@@ -1416,3 +1419,99 @@ void intel_cleanup_overlay(struct drm_device *dev)
1416 kfree(dev_priv->overlay); 1419 kfree(dev_priv->overlay);
1417 } 1420 }
1418} 1421}
1422
1423struct intel_overlay_error_state {
1424 struct overlay_registers regs;
1425 unsigned long base;
1426 u32 dovsta;
1427 u32 isr;
1428};
1429
1430struct intel_overlay_error_state *
1431intel_overlay_capture_error_state(struct drm_device *dev)
1432{
1433 drm_i915_private_t *dev_priv = dev->dev_private;
1434 struct intel_overlay *overlay = dev_priv->overlay;
1435 struct intel_overlay_error_state *error;
1436 struct overlay_registers __iomem *regs;
1437
1438 if (!overlay || !overlay->active)
1439 return NULL;
1440
1441 error = kmalloc(sizeof(*error), GFP_ATOMIC);
1442 if (error == NULL)
1443 return NULL;
1444
1445 error->dovsta = I915_READ(DOVSTA);
1446 error->isr = I915_READ(ISR);
1447 if (OVERLAY_NONPHYSICAL(overlay->dev))
1448 error->base = (long) overlay->reg_bo->gtt_offset;
1449 else
1450 error->base = (long) overlay->reg_bo->phys_obj->handle->vaddr;
1451
1452 regs = intel_overlay_map_regs_atomic(overlay);
1453 if (!regs)
1454 goto err;
1455
1456 memcpy_fromio(&error->regs, regs, sizeof(struct overlay_registers));
1457 intel_overlay_unmap_regs_atomic(overlay);
1458
1459 return error;
1460
1461err:
1462 kfree(error);
1463 return NULL;
1464}
1465
1466void
1467intel_overlay_print_error_state(struct seq_file *m, struct intel_overlay_error_state *error)
1468{
1469 seq_printf(m, "Overlay, status: 0x%08x, interrupt: 0x%08x\n",
1470 error->dovsta, error->isr);
1471 seq_printf(m, " Register file at 0x%08lx:\n",
1472 error->base);
1473
1474#define P(x) seq_printf(m, " " #x ": 0x%08x\n", error->regs.x)
1475 P(OBUF_0Y);
1476 P(OBUF_1Y);
1477 P(OBUF_0U);
1478 P(OBUF_0V);
1479 P(OBUF_1U);
1480 P(OBUF_1V);
1481 P(OSTRIDE);
1482 P(YRGB_VPH);
1483 P(UV_VPH);
1484 P(HORZ_PH);
1485 P(INIT_PHS);
1486 P(DWINPOS);
1487 P(DWINSZ);
1488 P(SWIDTH);
1489 P(SWIDTHSW);
1490 P(SHEIGHT);
1491 P(YRGBSCALE);
1492 P(UVSCALE);
1493 P(OCLRC0);
1494 P(OCLRC1);
1495 P(DCLRKV);
1496 P(DCLRKM);
1497 P(SCLRKVH);
1498 P(SCLRKVL);
1499 P(SCLRKEN);
1500 P(OCONFIG);
1501 P(OCMD);
1502 P(OSTART_0Y);
1503 P(OSTART_1Y);
1504 P(OSTART_0U);
1505 P(OSTART_0V);
1506 P(OSTART_1U);
1507 P(OSTART_1V);
1508 P(OTILEOFF_0Y);
1509 P(OTILEOFF_1Y);
1510 P(OTILEOFF_0U);
1511 P(OTILEOFF_0V);
1512 P(OTILEOFF_1U);
1513 P(OTILEOFF_1V);
1514 P(FASTHSCALE);
1515 P(UVSCALEV);
1516#undef P
1517}
diff --git a/drivers/gpu/drm/i915/intel_panel.c b/drivers/gpu/drm/i915/intel_panel.c
new file mode 100644
index 000000000000..e7f5299d9d57
--- /dev/null
+++ b/drivers/gpu/drm/i915/intel_panel.c
@@ -0,0 +1,111 @@
1/*
2 * Copyright © 2006-2010 Intel Corporation
3 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
23 *
24 * Authors:
25 * Eric Anholt <eric@anholt.net>
26 * Dave Airlie <airlied@linux.ie>
27 * Jesse Barnes <jesse.barnes@intel.com>
28 * Chris Wilson <chris@chris-wilson.co.uk>
29 */
30
31#include "intel_drv.h"
32
33void
34intel_fixed_panel_mode(struct drm_display_mode *fixed_mode,
35 struct drm_display_mode *adjusted_mode)
36{
37 adjusted_mode->hdisplay = fixed_mode->hdisplay;
38 adjusted_mode->hsync_start = fixed_mode->hsync_start;
39 adjusted_mode->hsync_end = fixed_mode->hsync_end;
40 adjusted_mode->htotal = fixed_mode->htotal;
41
42 adjusted_mode->vdisplay = fixed_mode->vdisplay;
43 adjusted_mode->vsync_start = fixed_mode->vsync_start;
44 adjusted_mode->vsync_end = fixed_mode->vsync_end;
45 adjusted_mode->vtotal = fixed_mode->vtotal;
46
47 adjusted_mode->clock = fixed_mode->clock;
48
49 drm_mode_set_crtcinfo(adjusted_mode, CRTC_INTERLACE_HALVE_V);
50}
51
52/* adjusted_mode has been preset to be the panel's fixed mode */
53void
54intel_pch_panel_fitting(struct drm_device *dev,
55 int fitting_mode,
56 struct drm_display_mode *mode,
57 struct drm_display_mode *adjusted_mode)
58{
59 struct drm_i915_private *dev_priv = dev->dev_private;
60 int x, y, width, height;
61
62 x = y = width = height = 0;
63
64 /* Native modes don't need fitting */
65 if (adjusted_mode->hdisplay == mode->hdisplay &&
66 adjusted_mode->vdisplay == mode->vdisplay)
67 goto done;
68
69 switch (fitting_mode) {
70 case DRM_MODE_SCALE_CENTER:
71 width = mode->hdisplay;
72 height = mode->vdisplay;
73 x = (adjusted_mode->hdisplay - width + 1)/2;
74 y = (adjusted_mode->vdisplay - height + 1)/2;
75 break;
76
77 case DRM_MODE_SCALE_ASPECT:
78 /* Scale but preserve the aspect ratio */
79 {
80 u32 scaled_width = adjusted_mode->hdisplay * mode->vdisplay;
81 u32 scaled_height = mode->hdisplay * adjusted_mode->vdisplay;
82 if (scaled_width > scaled_height) { /* pillar */
83 width = scaled_height / mode->vdisplay;
84 x = (adjusted_mode->hdisplay - width + 1) / 2;
85 y = 0;
86 height = adjusted_mode->vdisplay;
87 } else if (scaled_width < scaled_height) { /* letter */
88 height = scaled_width / mode->hdisplay;
89 y = (adjusted_mode->vdisplay - height + 1) / 2;
90 x = 0;
91 width = adjusted_mode->hdisplay;
92 } else {
93 x = y = 0;
94 width = adjusted_mode->hdisplay;
95 height = adjusted_mode->vdisplay;
96 }
97 }
98 break;
99
100 default:
101 case DRM_MODE_SCALE_FULLSCREEN:
102 x = y = 0;
103 width = adjusted_mode->hdisplay;
104 height = adjusted_mode->vdisplay;
105 break;
106 }
107
108done:
109 dev_priv->pch_pf_pos = (x << 16) | y;
110 dev_priv->pch_pf_size = (width << 16) | height;
111}
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 26362f8495a8..cb3508f78bc3 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -33,18 +33,35 @@
33#include "i915_drm.h" 33#include "i915_drm.h"
34#include "i915_trace.h" 34#include "i915_trace.h"
35 35
36static u32 i915_gem_get_seqno(struct drm_device *dev)
37{
38 drm_i915_private_t *dev_priv = dev->dev_private;
39 u32 seqno;
40
41 seqno = dev_priv->next_seqno;
42
43 /* reserve 0 for non-seqno */
44 if (++dev_priv->next_seqno == 0)
45 dev_priv->next_seqno = 1;
46
47 return seqno;
48}
49
36static void 50static void
37render_ring_flush(struct drm_device *dev, 51render_ring_flush(struct drm_device *dev,
38 struct intel_ring_buffer *ring, 52 struct intel_ring_buffer *ring,
39 u32 invalidate_domains, 53 u32 invalidate_domains,
40 u32 flush_domains) 54 u32 flush_domains)
41{ 55{
56 drm_i915_private_t *dev_priv = dev->dev_private;
57 u32 cmd;
58
42#if WATCH_EXEC 59#if WATCH_EXEC
43 DRM_INFO("%s: invalidate %08x flush %08x\n", __func__, 60 DRM_INFO("%s: invalidate %08x flush %08x\n", __func__,
44 invalidate_domains, flush_domains); 61 invalidate_domains, flush_domains);
45#endif 62#endif
46 u32 cmd; 63
47 trace_i915_gem_request_flush(dev, ring->next_seqno, 64 trace_i915_gem_request_flush(dev, dev_priv->next_seqno,
48 invalidate_domains, flush_domains); 65 invalidate_domains, flush_domains);
49 66
50 if ((invalidate_domains | flush_domains) & I915_GEM_GPU_DOMAINS) { 67 if ((invalidate_domains | flush_domains) & I915_GEM_GPU_DOMAINS) {
@@ -203,9 +220,13 @@ static int init_render_ring(struct drm_device *dev,
203{ 220{
204 drm_i915_private_t *dev_priv = dev->dev_private; 221 drm_i915_private_t *dev_priv = dev->dev_private;
205 int ret = init_ring_common(dev, ring); 222 int ret = init_ring_common(dev, ring);
223 int mode;
224
206 if (IS_I9XX(dev) && !IS_GEN3(dev)) { 225 if (IS_I9XX(dev) && !IS_GEN3(dev)) {
207 I915_WRITE(MI_MODE, 226 mode = VS_TIMER_DISPATCH << 16 | VS_TIMER_DISPATCH;
208 (VS_TIMER_DISPATCH) << 16 | VS_TIMER_DISPATCH); 227 if (IS_GEN6(dev))
228 mode |= MI_FLUSH_ENABLE << 16 | MI_FLUSH_ENABLE;
229 I915_WRITE(MI_MODE, mode);
209 } 230 }
210 return ret; 231 return ret;
211} 232}
@@ -233,9 +254,10 @@ render_ring_add_request(struct drm_device *dev,
233 struct drm_file *file_priv, 254 struct drm_file *file_priv,
234 u32 flush_domains) 255 u32 flush_domains)
235{ 256{
236 u32 seqno;
237 drm_i915_private_t *dev_priv = dev->dev_private; 257 drm_i915_private_t *dev_priv = dev->dev_private;
238 seqno = intel_ring_get_seqno(dev, ring); 258 u32 seqno;
259
260 seqno = i915_gem_get_seqno(dev);
239 261
240 if (IS_GEN6(dev)) { 262 if (IS_GEN6(dev)) {
241 BEGIN_LP_RING(6); 263 BEGIN_LP_RING(6);
@@ -405,7 +427,9 @@ bsd_ring_add_request(struct drm_device *dev,
405 u32 flush_domains) 427 u32 flush_domains)
406{ 428{
407 u32 seqno; 429 u32 seqno;
408 seqno = intel_ring_get_seqno(dev, ring); 430
431 seqno = i915_gem_get_seqno(dev);
432
409 intel_ring_begin(dev, ring, 4); 433 intel_ring_begin(dev, ring, 4);
410 intel_ring_emit(dev, ring, MI_STORE_DWORD_INDEX); 434 intel_ring_emit(dev, ring, MI_STORE_DWORD_INDEX);
411 intel_ring_emit(dev, ring, 435 intel_ring_emit(dev, ring,
@@ -479,7 +503,7 @@ render_ring_dispatch_gem_execbuffer(struct drm_device *dev,
479 exec_start = (uint32_t) exec_offset + exec->batch_start_offset; 503 exec_start = (uint32_t) exec_offset + exec->batch_start_offset;
480 exec_len = (uint32_t) exec->batch_len; 504 exec_len = (uint32_t) exec->batch_len;
481 505
482 trace_i915_gem_request_submit(dev, dev_priv->mm.next_gem_seqno + 1); 506 trace_i915_gem_request_submit(dev, dev_priv->next_seqno + 1);
483 507
484 count = nbox ? nbox : 1; 508 count = nbox ? nbox : 1;
485 509
@@ -515,7 +539,16 @@ render_ring_dispatch_gem_execbuffer(struct drm_device *dev,
515 intel_ring_advance(dev, ring); 539 intel_ring_advance(dev, ring);
516 } 540 }
517 541
542 if (IS_G4X(dev) || IS_IRONLAKE(dev)) {
543 intel_ring_begin(dev, ring, 2);
544 intel_ring_emit(dev, ring, MI_FLUSH |
545 MI_NO_WRITE_FLUSH |
546 MI_INVALIDATE_ISP );
547 intel_ring_emit(dev, ring, MI_NOOP);
548 intel_ring_advance(dev, ring);
549 }
518 /* XXX breadcrumb */ 550 /* XXX breadcrumb */
551
519 return 0; 552 return 0;
520} 553}
521 554
@@ -588,9 +621,10 @@ err:
588int intel_init_ring_buffer(struct drm_device *dev, 621int intel_init_ring_buffer(struct drm_device *dev,
589 struct intel_ring_buffer *ring) 622 struct intel_ring_buffer *ring)
590{ 623{
591 int ret;
592 struct drm_i915_gem_object *obj_priv; 624 struct drm_i915_gem_object *obj_priv;
593 struct drm_gem_object *obj; 625 struct drm_gem_object *obj;
626 int ret;
627
594 ring->dev = dev; 628 ring->dev = dev;
595 629
596 if (I915_NEED_GFX_HWS(dev)) { 630 if (I915_NEED_GFX_HWS(dev)) {
@@ -603,16 +637,14 @@ int intel_init_ring_buffer(struct drm_device *dev,
603 if (obj == NULL) { 637 if (obj == NULL) {
604 DRM_ERROR("Failed to allocate ringbuffer\n"); 638 DRM_ERROR("Failed to allocate ringbuffer\n");
605 ret = -ENOMEM; 639 ret = -ENOMEM;
606 goto cleanup; 640 goto err_hws;
607 } 641 }
608 642
609 ring->gem_object = obj; 643 ring->gem_object = obj;
610 644
611 ret = i915_gem_object_pin(obj, ring->alignment); 645 ret = i915_gem_object_pin(obj, ring->alignment);
612 if (ret != 0) { 646 if (ret)
613 drm_gem_object_unreference(obj); 647 goto err_unref;
614 goto cleanup;
615 }
616 648
617 obj_priv = to_intel_bo(obj); 649 obj_priv = to_intel_bo(obj);
618 ring->map.size = ring->size; 650 ring->map.size = ring->size;
@@ -624,18 +656,14 @@ int intel_init_ring_buffer(struct drm_device *dev,
624 drm_core_ioremap_wc(&ring->map, dev); 656 drm_core_ioremap_wc(&ring->map, dev);
625 if (ring->map.handle == NULL) { 657 if (ring->map.handle == NULL) {
626 DRM_ERROR("Failed to map ringbuffer.\n"); 658 DRM_ERROR("Failed to map ringbuffer.\n");
627 i915_gem_object_unpin(obj);
628 drm_gem_object_unreference(obj);
629 ret = -EINVAL; 659 ret = -EINVAL;
630 goto cleanup; 660 goto err_unpin;
631 } 661 }
632 662
633 ring->virtual_start = ring->map.handle; 663 ring->virtual_start = ring->map.handle;
634 ret = ring->init(dev, ring); 664 ret = ring->init(dev, ring);
635 if (ret != 0) { 665 if (ret)
636 intel_cleanup_ring_buffer(dev, ring); 666 goto err_unmap;
637 return ret;
638 }
639 667
640 if (!drm_core_check_feature(dev, DRIVER_MODESET)) 668 if (!drm_core_check_feature(dev, DRIVER_MODESET))
641 i915_kernel_lost_context(dev); 669 i915_kernel_lost_context(dev);
@@ -649,7 +677,15 @@ int intel_init_ring_buffer(struct drm_device *dev,
649 INIT_LIST_HEAD(&ring->active_list); 677 INIT_LIST_HEAD(&ring->active_list);
650 INIT_LIST_HEAD(&ring->request_list); 678 INIT_LIST_HEAD(&ring->request_list);
651 return ret; 679 return ret;
652cleanup: 680
681err_unmap:
682 drm_core_ioremapfree(&ring->map, dev);
683err_unpin:
684 i915_gem_object_unpin(obj);
685err_unref:
686 drm_gem_object_unreference(obj);
687 ring->gem_object = NULL;
688err_hws:
653 cleanup_status_page(dev, ring); 689 cleanup_status_page(dev, ring);
654 return ret; 690 return ret;
655} 691}
@@ -682,9 +718,11 @@ int intel_wrap_ring_buffer(struct drm_device *dev,
682 } 718 }
683 719
684 virt = (unsigned int *)(ring->virtual_start + ring->tail); 720 virt = (unsigned int *)(ring->virtual_start + ring->tail);
685 rem /= 4; 721 rem /= 8;
686 while (rem--) 722 while (rem--) {
723 *virt++ = MI_NOOP;
687 *virt++ = MI_NOOP; 724 *virt++ = MI_NOOP;
725 }
688 726
689 ring->tail = 0; 727 ring->tail = 0;
690 ring->space = ring->head - 8; 728 ring->space = ring->head - 8;
@@ -729,21 +767,14 @@ void intel_ring_begin(struct drm_device *dev,
729 intel_wrap_ring_buffer(dev, ring); 767 intel_wrap_ring_buffer(dev, ring);
730 if (unlikely(ring->space < n)) 768 if (unlikely(ring->space < n))
731 intel_wait_ring_buffer(dev, ring, n); 769 intel_wait_ring_buffer(dev, ring, n);
732}
733 770
734void intel_ring_emit(struct drm_device *dev, 771 ring->space -= n;
735 struct intel_ring_buffer *ring, unsigned int data)
736{
737 unsigned int *virt = ring->virtual_start + ring->tail;
738 *virt = data;
739 ring->tail += 4;
740 ring->tail &= ring->size - 1;
741 ring->space -= 4;
742} 772}
743 773
744void intel_ring_advance(struct drm_device *dev, 774void intel_ring_advance(struct drm_device *dev,
745 struct intel_ring_buffer *ring) 775 struct intel_ring_buffer *ring)
746{ 776{
777 ring->tail &= ring->size - 1;
747 ring->advance_ring(dev, ring); 778 ring->advance_ring(dev, ring);
748} 779}
749 780
@@ -762,18 +793,6 @@ void intel_fill_struct(struct drm_device *dev,
762 intel_ring_advance(dev, ring); 793 intel_ring_advance(dev, ring);
763} 794}
764 795
765u32 intel_ring_get_seqno(struct drm_device *dev,
766 struct intel_ring_buffer *ring)
767{
768 u32 seqno;
769 seqno = ring->next_seqno;
770
771 /* reserve 0 for non-seqno */
772 if (++ring->next_seqno == 0)
773 ring->next_seqno = 1;
774 return seqno;
775}
776
777struct intel_ring_buffer render_ring = { 796struct intel_ring_buffer render_ring = {
778 .name = "render ring", 797 .name = "render ring",
779 .regs = { 798 .regs = {
@@ -791,7 +810,6 @@ struct intel_ring_buffer render_ring = {
791 .head = 0, 810 .head = 0,
792 .tail = 0, 811 .tail = 0,
793 .space = 0, 812 .space = 0,
794 .next_seqno = 1,
795 .user_irq_refcount = 0, 813 .user_irq_refcount = 0,
796 .irq_gem_seqno = 0, 814 .irq_gem_seqno = 0,
797 .waiting_gem_seqno = 0, 815 .waiting_gem_seqno = 0,
@@ -830,7 +848,6 @@ struct intel_ring_buffer bsd_ring = {
830 .head = 0, 848 .head = 0,
831 .tail = 0, 849 .tail = 0,
832 .space = 0, 850 .space = 0,
833 .next_seqno = 1,
834 .user_irq_refcount = 0, 851 .user_irq_refcount = 0,
835 .irq_gem_seqno = 0, 852 .irq_gem_seqno = 0,
836 .waiting_gem_seqno = 0, 853 .waiting_gem_seqno = 0,
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h
index d5568d3766de..525e7d3edda8 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.h
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
@@ -26,7 +26,6 @@ struct intel_ring_buffer {
26 unsigned int head; 26 unsigned int head;
27 unsigned int tail; 27 unsigned int tail;
28 unsigned int space; 28 unsigned int space;
29 u32 next_seqno;
30 struct intel_hw_status_page status_page; 29 struct intel_hw_status_page status_page;
31 30
32 u32 irq_gem_seqno; /* last seq seem at irq time */ 31 u32 irq_gem_seqno; /* last seq seem at irq time */
@@ -106,8 +105,16 @@ int intel_wrap_ring_buffer(struct drm_device *dev,
106 struct intel_ring_buffer *ring); 105 struct intel_ring_buffer *ring);
107void intel_ring_begin(struct drm_device *dev, 106void intel_ring_begin(struct drm_device *dev,
108 struct intel_ring_buffer *ring, int n); 107 struct intel_ring_buffer *ring, int n);
109void intel_ring_emit(struct drm_device *dev, 108
110 struct intel_ring_buffer *ring, u32 data); 109static inline void intel_ring_emit(struct drm_device *dev,
110 struct intel_ring_buffer *ring,
111 unsigned int data)
112{
113 unsigned int *virt = ring->virtual_start + ring->tail;
114 *virt = data;
115 ring->tail += 4;
116}
117
111void intel_fill_struct(struct drm_device *dev, 118void intel_fill_struct(struct drm_device *dev,
112 struct intel_ring_buffer *ring, 119 struct intel_ring_buffer *ring,
113 void *data, 120 void *data,
diff --git a/drivers/gpu/drm/i915/intel_sdvo.c b/drivers/gpu/drm/i915/intel_sdvo.c
index d9d4d51aa89e..e3b7a7ee39cb 100644
--- a/drivers/gpu/drm/i915/intel_sdvo.c
+++ b/drivers/gpu/drm/i915/intel_sdvo.c
@@ -31,8 +31,8 @@
31#include "drmP.h" 31#include "drmP.h"
32#include "drm.h" 32#include "drm.h"
33#include "drm_crtc.h" 33#include "drm_crtc.h"
34#include "intel_drv.h"
35#include "drm_edid.h" 34#include "drm_edid.h"
35#include "intel_drv.h"
36#include "i915_drm.h" 36#include "i915_drm.h"
37#include "i915_drv.h" 37#include "i915_drv.h"
38#include "intel_sdvo_regs.h" 38#include "intel_sdvo_regs.h"
@@ -47,9 +47,10 @@
47 47
48#define IS_TV(c) (c->output_flag & SDVO_TV_MASK) 48#define IS_TV(c) (c->output_flag & SDVO_TV_MASK)
49#define IS_LVDS(c) (c->output_flag & SDVO_LVDS_MASK) 49#define IS_LVDS(c) (c->output_flag & SDVO_LVDS_MASK)
50#define IS_TV_OR_LVDS(c) (c->output_flag & (SDVO_TV_MASK | SDVO_LVDS_MASK))
50 51
51 52
52static char *tv_format_names[] = { 53static const char *tv_format_names[] = {
53 "NTSC_M" , "NTSC_J" , "NTSC_443", 54 "NTSC_M" , "NTSC_J" , "NTSC_443",
54 "PAL_B" , "PAL_D" , "PAL_G" , 55 "PAL_B" , "PAL_D" , "PAL_G" ,
55 "PAL_H" , "PAL_I" , "PAL_M" , 56 "PAL_H" , "PAL_I" , "PAL_M" ,
@@ -61,7 +62,9 @@ static char *tv_format_names[] = {
61 62
62#define TV_FORMAT_NUM (sizeof(tv_format_names) / sizeof(*tv_format_names)) 63#define TV_FORMAT_NUM (sizeof(tv_format_names) / sizeof(*tv_format_names))
63 64
64struct intel_sdvo_priv { 65struct intel_sdvo {
66 struct intel_encoder base;
67
65 u8 slave_addr; 68 u8 slave_addr;
66 69
67 /* Register for the SDVO device: SDVOB or SDVOC */ 70 /* Register for the SDVO device: SDVOB or SDVOC */
@@ -95,7 +98,7 @@ struct intel_sdvo_priv {
95 bool is_tv; 98 bool is_tv;
96 99
97 /* This is for current tv format name */ 100 /* This is for current tv format name */
98 char *tv_format_name; 101 int tv_format_index;
99 102
100 /** 103 /**
101 * This is set if we treat the device as HDMI, instead of DVI. 104 * This is set if we treat the device as HDMI, instead of DVI.
@@ -132,37 +135,40 @@ struct intel_sdvo_priv {
132}; 135};
133 136
134struct intel_sdvo_connector { 137struct intel_sdvo_connector {
138 struct intel_connector base;
139
135 /* Mark the type of connector */ 140 /* Mark the type of connector */
136 uint16_t output_flag; 141 uint16_t output_flag;
137 142
138 /* This contains all current supported TV format */ 143 /* This contains all current supported TV format */
139 char *tv_format_supported[TV_FORMAT_NUM]; 144 u8 tv_format_supported[TV_FORMAT_NUM];
140 int format_supported_num; 145 int format_supported_num;
141 struct drm_property *tv_format_property; 146 struct drm_property *tv_format;
142 struct drm_property *tv_format_name_property[TV_FORMAT_NUM];
143
144 /**
145 * Returned SDTV resolutions allowed for the current format, if the
146 * device reported it.
147 */
148 struct intel_sdvo_sdtv_resolution_reply sdtv_resolutions;
149 147
150 /* add the property for the SDVO-TV */ 148 /* add the property for the SDVO-TV */
151 struct drm_property *left_property; 149 struct drm_property *left;
152 struct drm_property *right_property; 150 struct drm_property *right;
153 struct drm_property *top_property; 151 struct drm_property *top;
154 struct drm_property *bottom_property; 152 struct drm_property *bottom;
155 struct drm_property *hpos_property; 153 struct drm_property *hpos;
156 struct drm_property *vpos_property; 154 struct drm_property *vpos;
155 struct drm_property *contrast;
156 struct drm_property *saturation;
157 struct drm_property *hue;
158 struct drm_property *sharpness;
159 struct drm_property *flicker_filter;
160 struct drm_property *flicker_filter_adaptive;
161 struct drm_property *flicker_filter_2d;
162 struct drm_property *tv_chroma_filter;
163 struct drm_property *tv_luma_filter;
164 struct drm_property *dot_crawl;
157 165
158 /* add the property for the SDVO-TV/LVDS */ 166 /* add the property for the SDVO-TV/LVDS */
159 struct drm_property *brightness_property; 167 struct drm_property *brightness;
160 struct drm_property *contrast_property;
161 struct drm_property *saturation_property;
162 struct drm_property *hue_property;
163 168
164 /* Add variable to record current setting for the above property */ 169 /* Add variable to record current setting for the above property */
165 u32 left_margin, right_margin, top_margin, bottom_margin; 170 u32 left_margin, right_margin, top_margin, bottom_margin;
171
166 /* this is to get the range of margin.*/ 172 /* this is to get the range of margin.*/
167 u32 max_hscan, max_vscan; 173 u32 max_hscan, max_vscan;
168 u32 max_hpos, cur_hpos; 174 u32 max_hpos, cur_hpos;
@@ -171,36 +177,54 @@ struct intel_sdvo_connector {
171 u32 cur_contrast, max_contrast; 177 u32 cur_contrast, max_contrast;
172 u32 cur_saturation, max_saturation; 178 u32 cur_saturation, max_saturation;
173 u32 cur_hue, max_hue; 179 u32 cur_hue, max_hue;
180 u32 cur_sharpness, max_sharpness;
181 u32 cur_flicker_filter, max_flicker_filter;
182 u32 cur_flicker_filter_adaptive, max_flicker_filter_adaptive;
183 u32 cur_flicker_filter_2d, max_flicker_filter_2d;
184 u32 cur_tv_chroma_filter, max_tv_chroma_filter;
185 u32 cur_tv_luma_filter, max_tv_luma_filter;
186 u32 cur_dot_crawl, max_dot_crawl;
174}; 187};
175 188
189static struct intel_sdvo *enc_to_intel_sdvo(struct drm_encoder *encoder)
190{
191 return container_of(enc_to_intel_encoder(encoder), struct intel_sdvo, base);
192}
193
194static struct intel_sdvo_connector *to_intel_sdvo_connector(struct drm_connector *connector)
195{
196 return container_of(to_intel_connector(connector), struct intel_sdvo_connector, base);
197}
198
176static bool 199static bool
177intel_sdvo_output_setup(struct intel_encoder *intel_encoder, 200intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo, uint16_t flags);
178 uint16_t flags); 201static bool
179static void 202intel_sdvo_tv_create_property(struct intel_sdvo *intel_sdvo,
180intel_sdvo_tv_create_property(struct drm_connector *connector, int type); 203 struct intel_sdvo_connector *intel_sdvo_connector,
181static void 204 int type);
182intel_sdvo_create_enhance_property(struct drm_connector *connector); 205static bool
206intel_sdvo_create_enhance_property(struct intel_sdvo *intel_sdvo,
207 struct intel_sdvo_connector *intel_sdvo_connector);
183 208
184/** 209/**
185 * Writes the SDVOB or SDVOC with the given value, but always writes both 210 * Writes the SDVOB or SDVOC with the given value, but always writes both
186 * SDVOB and SDVOC to work around apparent hardware issues (according to 211 * SDVOB and SDVOC to work around apparent hardware issues (according to
187 * comments in the BIOS). 212 * comments in the BIOS).
188 */ 213 */
189static void intel_sdvo_write_sdvox(struct intel_encoder *intel_encoder, u32 val) 214static void intel_sdvo_write_sdvox(struct intel_sdvo *intel_sdvo, u32 val)
190{ 215{
191 struct drm_device *dev = intel_encoder->enc.dev; 216 struct drm_device *dev = intel_sdvo->base.enc.dev;
192 struct drm_i915_private *dev_priv = dev->dev_private; 217 struct drm_i915_private *dev_priv = dev->dev_private;
193 struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv;
194 u32 bval = val, cval = val; 218 u32 bval = val, cval = val;
195 int i; 219 int i;
196 220
197 if (sdvo_priv->sdvo_reg == PCH_SDVOB) { 221 if (intel_sdvo->sdvo_reg == PCH_SDVOB) {
198 I915_WRITE(sdvo_priv->sdvo_reg, val); 222 I915_WRITE(intel_sdvo->sdvo_reg, val);
199 I915_READ(sdvo_priv->sdvo_reg); 223 I915_READ(intel_sdvo->sdvo_reg);
200 return; 224 return;
201 } 225 }
202 226
203 if (sdvo_priv->sdvo_reg == SDVOB) { 227 if (intel_sdvo->sdvo_reg == SDVOB) {
204 cval = I915_READ(SDVOC); 228 cval = I915_READ(SDVOC);
205 } else { 229 } else {
206 bval = I915_READ(SDVOB); 230 bval = I915_READ(SDVOB);
@@ -219,33 +243,27 @@ static void intel_sdvo_write_sdvox(struct intel_encoder *intel_encoder, u32 val)
219 } 243 }
220} 244}
221 245
222static bool intel_sdvo_read_byte(struct intel_encoder *intel_encoder, u8 addr, 246static bool intel_sdvo_read_byte(struct intel_sdvo *intel_sdvo, u8 addr, u8 *ch)
223 u8 *ch)
224{ 247{
225 struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv; 248 u8 out_buf[2] = { addr, 0 };
226 u8 out_buf[2];
227 u8 buf[2]; 249 u8 buf[2];
228 int ret;
229
230 struct i2c_msg msgs[] = { 250 struct i2c_msg msgs[] = {
231 { 251 {
232 .addr = sdvo_priv->slave_addr >> 1, 252 .addr = intel_sdvo->slave_addr >> 1,
233 .flags = 0, 253 .flags = 0,
234 .len = 1, 254 .len = 1,
235 .buf = out_buf, 255 .buf = out_buf,
236 }, 256 },
237 { 257 {
238 .addr = sdvo_priv->slave_addr >> 1, 258 .addr = intel_sdvo->slave_addr >> 1,
239 .flags = I2C_M_RD, 259 .flags = I2C_M_RD,
240 .len = 1, 260 .len = 1,
241 .buf = buf, 261 .buf = buf,
242 } 262 }
243 }; 263 };
264 int ret;
244 265
245 out_buf[0] = addr; 266 if ((ret = i2c_transfer(intel_sdvo->base.i2c_bus, msgs, 2)) == 2)
246 out_buf[1] = 0;
247
248 if ((ret = i2c_transfer(intel_encoder->i2c_bus, msgs, 2)) == 2)
249 { 267 {
250 *ch = buf[0]; 268 *ch = buf[0];
251 return true; 269 return true;
@@ -255,35 +273,26 @@ static bool intel_sdvo_read_byte(struct intel_encoder *intel_encoder, u8 addr,
255 return false; 273 return false;
256} 274}
257 275
258static bool intel_sdvo_write_byte(struct intel_encoder *intel_encoder, int addr, 276static bool intel_sdvo_write_byte(struct intel_sdvo *intel_sdvo, int addr, u8 ch)
259 u8 ch)
260{ 277{
261 struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv; 278 u8 out_buf[2] = { addr, ch };
262 u8 out_buf[2];
263 struct i2c_msg msgs[] = { 279 struct i2c_msg msgs[] = {
264 { 280 {
265 .addr = sdvo_priv->slave_addr >> 1, 281 .addr = intel_sdvo->slave_addr >> 1,
266 .flags = 0, 282 .flags = 0,
267 .len = 2, 283 .len = 2,
268 .buf = out_buf, 284 .buf = out_buf,
269 } 285 }
270 }; 286 };
271 287
272 out_buf[0] = addr; 288 return i2c_transfer(intel_sdvo->base.i2c_bus, msgs, 1) == 1;
273 out_buf[1] = ch;
274
275 if (i2c_transfer(intel_encoder->i2c_bus, msgs, 1) == 1)
276 {
277 return true;
278 }
279 return false;
280} 289}
281 290
282#define SDVO_CMD_NAME_ENTRY(cmd) {cmd, #cmd} 291#define SDVO_CMD_NAME_ENTRY(cmd) {cmd, #cmd}
283/** Mapping of command numbers to names, for debug output */ 292/** Mapping of command numbers to names, for debug output */
284static const struct _sdvo_cmd_name { 293static const struct _sdvo_cmd_name {
285 u8 cmd; 294 u8 cmd;
286 char *name; 295 const char *name;
287} sdvo_cmd_names[] = { 296} sdvo_cmd_names[] = {
288 SDVO_CMD_NAME_ENTRY(SDVO_CMD_RESET), 297 SDVO_CMD_NAME_ENTRY(SDVO_CMD_RESET),
289 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DEVICE_CAPS), 298 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DEVICE_CAPS),
@@ -328,13 +337,14 @@ static const struct _sdvo_cmd_name {
328 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT), 337 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT),
329 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SCALED_HDTV_RESOLUTION_SUPPORT), 338 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SCALED_HDTV_RESOLUTION_SUPPORT),
330 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS), 339 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS),
340
331 /* Add the op code for SDVO enhancements */ 341 /* Add the op code for SDVO enhancements */
332 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_POSITION_H), 342 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_HPOS),
333 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_POSITION_H), 343 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HPOS),
334 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_POSITION_H), 344 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HPOS),
335 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_POSITION_V), 345 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_VPOS),
336 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_POSITION_V), 346 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_VPOS),
337 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_POSITION_V), 347 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_VPOS),
338 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_SATURATION), 348 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_SATURATION),
339 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SATURATION), 349 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SATURATION),
340 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_SATURATION), 350 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_SATURATION),
@@ -353,6 +363,27 @@ static const struct _sdvo_cmd_name {
353 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_OVERSCAN_V), 363 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_OVERSCAN_V),
354 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OVERSCAN_V), 364 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OVERSCAN_V),
355 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OVERSCAN_V), 365 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OVERSCAN_V),
366 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER),
367 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER),
368 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER),
369 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER_ADAPTIVE),
370 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER_ADAPTIVE),
371 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER_ADAPTIVE),
372 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER_2D),
373 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER_2D),
374 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER_2D),
375 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_SHARPNESS),
376 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SHARPNESS),
377 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_SHARPNESS),
378 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DOT_CRAWL),
379 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_DOT_CRAWL),
380 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_TV_CHROMA_FILTER),
381 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_CHROMA_FILTER),
382 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_CHROMA_FILTER),
383 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_TV_LUMA_FILTER),
384 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_LUMA_FILTER),
385 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_LUMA_FILTER),
386
356 /* HDMI op code */ 387 /* HDMI op code */
357 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPP_ENCODE), 388 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPP_ENCODE),
358 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ENCODE), 389 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ENCODE),
@@ -377,17 +408,15 @@ static const struct _sdvo_cmd_name {
377}; 408};
378 409
379#define IS_SDVOB(reg) (reg == SDVOB || reg == PCH_SDVOB) 410#define IS_SDVOB(reg) (reg == SDVOB || reg == PCH_SDVOB)
380#define SDVO_NAME(dev_priv) (IS_SDVOB((dev_priv)->sdvo_reg) ? "SDVOB" : "SDVOC") 411#define SDVO_NAME(svdo) (IS_SDVOB((svdo)->sdvo_reg) ? "SDVOB" : "SDVOC")
381#define SDVO_PRIV(encoder) ((struct intel_sdvo_priv *) (encoder)->dev_priv)
382 412
383static void intel_sdvo_debug_write(struct intel_encoder *intel_encoder, u8 cmd, 413static void intel_sdvo_debug_write(struct intel_sdvo *intel_sdvo, u8 cmd,
384 void *args, int args_len) 414 const void *args, int args_len)
385{ 415{
386 struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv;
387 int i; 416 int i;
388 417
389 DRM_DEBUG_KMS("%s: W: %02X ", 418 DRM_DEBUG_KMS("%s: W: %02X ",
390 SDVO_NAME(sdvo_priv), cmd); 419 SDVO_NAME(intel_sdvo), cmd);
391 for (i = 0; i < args_len; i++) 420 for (i = 0; i < args_len; i++)
392 DRM_LOG_KMS("%02X ", ((u8 *)args)[i]); 421 DRM_LOG_KMS("%02X ", ((u8 *)args)[i]);
393 for (; i < 8; i++) 422 for (; i < 8; i++)
@@ -403,19 +432,20 @@ static void intel_sdvo_debug_write(struct intel_encoder *intel_encoder, u8 cmd,
403 DRM_LOG_KMS("\n"); 432 DRM_LOG_KMS("\n");
404} 433}
405 434
406static void intel_sdvo_write_cmd(struct intel_encoder *intel_encoder, u8 cmd, 435static bool intel_sdvo_write_cmd(struct intel_sdvo *intel_sdvo, u8 cmd,
407 void *args, int args_len) 436 const void *args, int args_len)
408{ 437{
409 int i; 438 int i;
410 439
411 intel_sdvo_debug_write(intel_encoder, cmd, args, args_len); 440 intel_sdvo_debug_write(intel_sdvo, cmd, args, args_len);
412 441
413 for (i = 0; i < args_len; i++) { 442 for (i = 0; i < args_len; i++) {
414 intel_sdvo_write_byte(intel_encoder, SDVO_I2C_ARG_0 - i, 443 if (!intel_sdvo_write_byte(intel_sdvo, SDVO_I2C_ARG_0 - i,
415 ((u8*)args)[i]); 444 ((u8*)args)[i]))
445 return false;
416 } 446 }
417 447
418 intel_sdvo_write_byte(intel_encoder, SDVO_I2C_OPCODE, cmd); 448 return intel_sdvo_write_byte(intel_sdvo, SDVO_I2C_OPCODE, cmd);
419} 449}
420 450
421static const char *cmd_status_names[] = { 451static const char *cmd_status_names[] = {
@@ -428,14 +458,13 @@ static const char *cmd_status_names[] = {
428 "Scaling not supported" 458 "Scaling not supported"
429}; 459};
430 460
431static void intel_sdvo_debug_response(struct intel_encoder *intel_encoder, 461static void intel_sdvo_debug_response(struct intel_sdvo *intel_sdvo,
432 void *response, int response_len, 462 void *response, int response_len,
433 u8 status) 463 u8 status)
434{ 464{
435 struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv;
436 int i; 465 int i;
437 466
438 DRM_DEBUG_KMS("%s: R: ", SDVO_NAME(sdvo_priv)); 467 DRM_DEBUG_KMS("%s: R: ", SDVO_NAME(intel_sdvo));
439 for (i = 0; i < response_len; i++) 468 for (i = 0; i < response_len; i++)
440 DRM_LOG_KMS("%02X ", ((u8 *)response)[i]); 469 DRM_LOG_KMS("%02X ", ((u8 *)response)[i]);
441 for (; i < 8; i++) 470 for (; i < 8; i++)
@@ -447,8 +476,8 @@ static void intel_sdvo_debug_response(struct intel_encoder *intel_encoder,
447 DRM_LOG_KMS("\n"); 476 DRM_LOG_KMS("\n");
448} 477}
449 478
450static u8 intel_sdvo_read_response(struct intel_encoder *intel_encoder, 479static bool intel_sdvo_read_response(struct intel_sdvo *intel_sdvo,
451 void *response, int response_len) 480 void *response, int response_len)
452{ 481{
453 int i; 482 int i;
454 u8 status; 483 u8 status;
@@ -457,24 +486,26 @@ static u8 intel_sdvo_read_response(struct intel_encoder *intel_encoder,
457 while (retry--) { 486 while (retry--) {
458 /* Read the command response */ 487 /* Read the command response */
459 for (i = 0; i < response_len; i++) { 488 for (i = 0; i < response_len; i++) {
460 intel_sdvo_read_byte(intel_encoder, 489 if (!intel_sdvo_read_byte(intel_sdvo,
461 SDVO_I2C_RETURN_0 + i, 490 SDVO_I2C_RETURN_0 + i,
462 &((u8 *)response)[i]); 491 &((u8 *)response)[i]))
492 return false;
463 } 493 }
464 494
465 /* read the return status */ 495 /* read the return status */
466 intel_sdvo_read_byte(intel_encoder, SDVO_I2C_CMD_STATUS, 496 if (!intel_sdvo_read_byte(intel_sdvo, SDVO_I2C_CMD_STATUS,
467 &status); 497 &status))
498 return false;
468 499
469 intel_sdvo_debug_response(intel_encoder, response, response_len, 500 intel_sdvo_debug_response(intel_sdvo, response, response_len,
470 status); 501 status);
471 if (status != SDVO_CMD_STATUS_PENDING) 502 if (status != SDVO_CMD_STATUS_PENDING)
472 return status; 503 break;
473 504
474 mdelay(50); 505 mdelay(50);
475 } 506 }
476 507
477 return status; 508 return status == SDVO_CMD_STATUS_SUCCESS;
478} 509}
479 510
480static int intel_sdvo_get_pixel_multiplier(struct drm_display_mode *mode) 511static int intel_sdvo_get_pixel_multiplier(struct drm_display_mode *mode)
@@ -494,37 +525,36 @@ static int intel_sdvo_get_pixel_multiplier(struct drm_display_mode *mode)
494 * another I2C transaction after issuing the DDC bus switch, it will be 525 * another I2C transaction after issuing the DDC bus switch, it will be
495 * switched to the internal SDVO register. 526 * switched to the internal SDVO register.
496 */ 527 */
497static void intel_sdvo_set_control_bus_switch(struct intel_encoder *intel_encoder, 528static void intel_sdvo_set_control_bus_switch(struct intel_sdvo *intel_sdvo,
498 u8 target) 529 u8 target)
499{ 530{
500 struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv;
501 u8 out_buf[2], cmd_buf[2], ret_value[2], ret; 531 u8 out_buf[2], cmd_buf[2], ret_value[2], ret;
502 struct i2c_msg msgs[] = { 532 struct i2c_msg msgs[] = {
503 { 533 {
504 .addr = sdvo_priv->slave_addr >> 1, 534 .addr = intel_sdvo->slave_addr >> 1,
505 .flags = 0, 535 .flags = 0,
506 .len = 2, 536 .len = 2,
507 .buf = out_buf, 537 .buf = out_buf,
508 }, 538 },
509 /* the following two are to read the response */ 539 /* the following two are to read the response */
510 { 540 {
511 .addr = sdvo_priv->slave_addr >> 1, 541 .addr = intel_sdvo->slave_addr >> 1,
512 .flags = 0, 542 .flags = 0,
513 .len = 1, 543 .len = 1,
514 .buf = cmd_buf, 544 .buf = cmd_buf,
515 }, 545 },
516 { 546 {
517 .addr = sdvo_priv->slave_addr >> 1, 547 .addr = intel_sdvo->slave_addr >> 1,
518 .flags = I2C_M_RD, 548 .flags = I2C_M_RD,
519 .len = 1, 549 .len = 1,
520 .buf = ret_value, 550 .buf = ret_value,
521 }, 551 },
522 }; 552 };
523 553
524 intel_sdvo_debug_write(intel_encoder, SDVO_CMD_SET_CONTROL_BUS_SWITCH, 554 intel_sdvo_debug_write(intel_sdvo, SDVO_CMD_SET_CONTROL_BUS_SWITCH,
525 &target, 1); 555 &target, 1);
526 /* write the DDC switch command argument */ 556 /* write the DDC switch command argument */
527 intel_sdvo_write_byte(intel_encoder, SDVO_I2C_ARG_0, target); 557 intel_sdvo_write_byte(intel_sdvo, SDVO_I2C_ARG_0, target);
528 558
529 out_buf[0] = SDVO_I2C_OPCODE; 559 out_buf[0] = SDVO_I2C_OPCODE;
530 out_buf[1] = SDVO_CMD_SET_CONTROL_BUS_SWITCH; 560 out_buf[1] = SDVO_CMD_SET_CONTROL_BUS_SWITCH;
@@ -533,7 +563,7 @@ static void intel_sdvo_set_control_bus_switch(struct intel_encoder *intel_encode
533 ret_value[0] = 0; 563 ret_value[0] = 0;
534 ret_value[1] = 0; 564 ret_value[1] = 0;
535 565
536 ret = i2c_transfer(intel_encoder->i2c_bus, msgs, 3); 566 ret = i2c_transfer(intel_sdvo->base.i2c_bus, msgs, 3);
537 if (ret != 3) { 567 if (ret != 3) {
538 /* failure in I2C transfer */ 568 /* failure in I2C transfer */
539 DRM_DEBUG_KMS("I2c transfer returned %d\n", ret); 569 DRM_DEBUG_KMS("I2c transfer returned %d\n", ret);
@@ -547,23 +577,29 @@ static void intel_sdvo_set_control_bus_switch(struct intel_encoder *intel_encode
547 return; 577 return;
548} 578}
549 579
550static bool intel_sdvo_set_target_input(struct intel_encoder *intel_encoder, bool target_0, bool target_1) 580static bool intel_sdvo_set_value(struct intel_sdvo *intel_sdvo, u8 cmd, const void *data, int len)
551{ 581{
552 struct intel_sdvo_set_target_input_args targets = {0}; 582 if (!intel_sdvo_write_cmd(intel_sdvo, cmd, data, len))
553 u8 status; 583 return false;
554
555 if (target_0 && target_1)
556 return SDVO_CMD_STATUS_NOTSUPP;
557 584
558 if (target_1) 585 return intel_sdvo_read_response(intel_sdvo, NULL, 0);
559 targets.target_1 = 1; 586}
560 587
561 intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_SET_TARGET_INPUT, &targets, 588static bool
562 sizeof(targets)); 589intel_sdvo_get_value(struct intel_sdvo *intel_sdvo, u8 cmd, void *value, int len)
590{
591 if (!intel_sdvo_write_cmd(intel_sdvo, cmd, NULL, 0))
592 return false;
563 593
564 status = intel_sdvo_read_response(intel_encoder, NULL, 0); 594 return intel_sdvo_read_response(intel_sdvo, value, len);
595}
565 596
566 return (status == SDVO_CMD_STATUS_SUCCESS); 597static bool intel_sdvo_set_target_input(struct intel_sdvo *intel_sdvo)
598{
599 struct intel_sdvo_set_target_input_args targets = {0};
600 return intel_sdvo_set_value(intel_sdvo,
601 SDVO_CMD_SET_TARGET_INPUT,
602 &targets, sizeof(targets));
567} 603}
568 604
569/** 605/**
@@ -572,14 +608,12 @@ static bool intel_sdvo_set_target_input(struct intel_encoder *intel_encoder, boo
572 * This function is making an assumption about the layout of the response, 608 * This function is making an assumption about the layout of the response,
573 * which should be checked against the docs. 609 * which should be checked against the docs.
574 */ 610 */
575static bool intel_sdvo_get_trained_inputs(struct intel_encoder *intel_encoder, bool *input_1, bool *input_2) 611static bool intel_sdvo_get_trained_inputs(struct intel_sdvo *intel_sdvo, bool *input_1, bool *input_2)
576{ 612{
577 struct intel_sdvo_get_trained_inputs_response response; 613 struct intel_sdvo_get_trained_inputs_response response;
578 u8 status;
579 614
580 intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_GET_TRAINED_INPUTS, NULL, 0); 615 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_TRAINED_INPUTS,
581 status = intel_sdvo_read_response(intel_encoder, &response, sizeof(response)); 616 &response, sizeof(response)))
582 if (status != SDVO_CMD_STATUS_SUCCESS)
583 return false; 617 return false;
584 618
585 *input_1 = response.input0_trained; 619 *input_1 = response.input0_trained;
@@ -587,21 +621,18 @@ static bool intel_sdvo_get_trained_inputs(struct intel_encoder *intel_encoder, b
587 return true; 621 return true;
588} 622}
589 623
590static bool intel_sdvo_set_active_outputs(struct intel_encoder *intel_encoder, 624static bool intel_sdvo_set_active_outputs(struct intel_sdvo *intel_sdvo,
591 u16 outputs) 625 u16 outputs)
592{ 626{
593 u8 status; 627 return intel_sdvo_set_value(intel_sdvo,
594 628 SDVO_CMD_SET_ACTIVE_OUTPUTS,
595 intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_SET_ACTIVE_OUTPUTS, &outputs, 629 &outputs, sizeof(outputs));
596 sizeof(outputs));
597 status = intel_sdvo_read_response(intel_encoder, NULL, 0);
598 return (status == SDVO_CMD_STATUS_SUCCESS);
599} 630}
600 631
601static bool intel_sdvo_set_encoder_power_state(struct intel_encoder *intel_encoder, 632static bool intel_sdvo_set_encoder_power_state(struct intel_sdvo *intel_sdvo,
602 int mode) 633 int mode)
603{ 634{
604 u8 status, state = SDVO_ENCODER_STATE_ON; 635 u8 state = SDVO_ENCODER_STATE_ON;
605 636
606 switch (mode) { 637 switch (mode) {
607 case DRM_MODE_DPMS_ON: 638 case DRM_MODE_DPMS_ON:
@@ -618,88 +649,63 @@ static bool intel_sdvo_set_encoder_power_state(struct intel_encoder *intel_encod
618 break; 649 break;
619 } 650 }
620 651
621 intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_SET_ENCODER_POWER_STATE, &state, 652 return intel_sdvo_set_value(intel_sdvo,
622 sizeof(state)); 653 SDVO_CMD_SET_ENCODER_POWER_STATE, &state, sizeof(state));
623 status = intel_sdvo_read_response(intel_encoder, NULL, 0);
624
625 return (status == SDVO_CMD_STATUS_SUCCESS);
626} 654}
627 655
628static bool intel_sdvo_get_input_pixel_clock_range(struct intel_encoder *intel_encoder, 656static bool intel_sdvo_get_input_pixel_clock_range(struct intel_sdvo *intel_sdvo,
629 int *clock_min, 657 int *clock_min,
630 int *clock_max) 658 int *clock_max)
631{ 659{
632 struct intel_sdvo_pixel_clock_range clocks; 660 struct intel_sdvo_pixel_clock_range clocks;
633 u8 status;
634
635 intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE,
636 NULL, 0);
637
638 status = intel_sdvo_read_response(intel_encoder, &clocks, sizeof(clocks));
639 661
640 if (status != SDVO_CMD_STATUS_SUCCESS) 662 if (!intel_sdvo_get_value(intel_sdvo,
663 SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE,
664 &clocks, sizeof(clocks)))
641 return false; 665 return false;
642 666
643 /* Convert the values from units of 10 kHz to kHz. */ 667 /* Convert the values from units of 10 kHz to kHz. */
644 *clock_min = clocks.min * 10; 668 *clock_min = clocks.min * 10;
645 *clock_max = clocks.max * 10; 669 *clock_max = clocks.max * 10;
646
647 return true; 670 return true;
648} 671}
649 672
650static bool intel_sdvo_set_target_output(struct intel_encoder *intel_encoder, 673static bool intel_sdvo_set_target_output(struct intel_sdvo *intel_sdvo,
651 u16 outputs) 674 u16 outputs)
652{ 675{
653 u8 status; 676 return intel_sdvo_set_value(intel_sdvo,
654 677 SDVO_CMD_SET_TARGET_OUTPUT,
655 intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_SET_TARGET_OUTPUT, &outputs, 678 &outputs, sizeof(outputs));
656 sizeof(outputs));
657
658 status = intel_sdvo_read_response(intel_encoder, NULL, 0);
659 return (status == SDVO_CMD_STATUS_SUCCESS);
660} 679}
661 680
662static bool intel_sdvo_set_timing(struct intel_encoder *intel_encoder, u8 cmd, 681static bool intel_sdvo_set_timing(struct intel_sdvo *intel_sdvo, u8 cmd,
663 struct intel_sdvo_dtd *dtd) 682 struct intel_sdvo_dtd *dtd)
664{ 683{
665 u8 status; 684 return intel_sdvo_set_value(intel_sdvo, cmd, &dtd->part1, sizeof(dtd->part1)) &&
666 685 intel_sdvo_set_value(intel_sdvo, cmd + 1, &dtd->part2, sizeof(dtd->part2));
667 intel_sdvo_write_cmd(intel_encoder, cmd, &dtd->part1, sizeof(dtd->part1));
668 status = intel_sdvo_read_response(intel_encoder, NULL, 0);
669 if (status != SDVO_CMD_STATUS_SUCCESS)
670 return false;
671
672 intel_sdvo_write_cmd(intel_encoder, cmd + 1, &dtd->part2, sizeof(dtd->part2));
673 status = intel_sdvo_read_response(intel_encoder, NULL, 0);
674 if (status != SDVO_CMD_STATUS_SUCCESS)
675 return false;
676
677 return true;
678} 686}
679 687
680static bool intel_sdvo_set_input_timing(struct intel_encoder *intel_encoder, 688static bool intel_sdvo_set_input_timing(struct intel_sdvo *intel_sdvo,
681 struct intel_sdvo_dtd *dtd) 689 struct intel_sdvo_dtd *dtd)
682{ 690{
683 return intel_sdvo_set_timing(intel_encoder, 691 return intel_sdvo_set_timing(intel_sdvo,
684 SDVO_CMD_SET_INPUT_TIMINGS_PART1, dtd); 692 SDVO_CMD_SET_INPUT_TIMINGS_PART1, dtd);
685} 693}
686 694
687static bool intel_sdvo_set_output_timing(struct intel_encoder *intel_encoder, 695static bool intel_sdvo_set_output_timing(struct intel_sdvo *intel_sdvo,
688 struct intel_sdvo_dtd *dtd) 696 struct intel_sdvo_dtd *dtd)
689{ 697{
690 return intel_sdvo_set_timing(intel_encoder, 698 return intel_sdvo_set_timing(intel_sdvo,
691 SDVO_CMD_SET_OUTPUT_TIMINGS_PART1, dtd); 699 SDVO_CMD_SET_OUTPUT_TIMINGS_PART1, dtd);
692} 700}
693 701
694static bool 702static bool
695intel_sdvo_create_preferred_input_timing(struct intel_encoder *intel_encoder, 703intel_sdvo_create_preferred_input_timing(struct intel_sdvo *intel_sdvo,
696 uint16_t clock, 704 uint16_t clock,
697 uint16_t width, 705 uint16_t width,
698 uint16_t height) 706 uint16_t height)
699{ 707{
700 struct intel_sdvo_preferred_input_timing_args args; 708 struct intel_sdvo_preferred_input_timing_args args;
701 struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv;
702 uint8_t status;
703 709
704 memset(&args, 0, sizeof(args)); 710 memset(&args, 0, sizeof(args));
705 args.clock = clock; 711 args.clock = clock;
@@ -707,59 +713,32 @@ intel_sdvo_create_preferred_input_timing(struct intel_encoder *intel_encoder,
707 args.height = height; 713 args.height = height;
708 args.interlace = 0; 714 args.interlace = 0;
709 715
710 if (sdvo_priv->is_lvds && 716 if (intel_sdvo->is_lvds &&
711 (sdvo_priv->sdvo_lvds_fixed_mode->hdisplay != width || 717 (intel_sdvo->sdvo_lvds_fixed_mode->hdisplay != width ||
712 sdvo_priv->sdvo_lvds_fixed_mode->vdisplay != height)) 718 intel_sdvo->sdvo_lvds_fixed_mode->vdisplay != height))
713 args.scaled = 1; 719 args.scaled = 1;
714 720
715 intel_sdvo_write_cmd(intel_encoder, 721 return intel_sdvo_set_value(intel_sdvo,
716 SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING, 722 SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING,
717 &args, sizeof(args)); 723 &args, sizeof(args));
718 status = intel_sdvo_read_response(intel_encoder, NULL, 0);
719 if (status != SDVO_CMD_STATUS_SUCCESS)
720 return false;
721
722 return true;
723} 724}
724 725
725static bool intel_sdvo_get_preferred_input_timing(struct intel_encoder *intel_encoder, 726static bool intel_sdvo_get_preferred_input_timing(struct intel_sdvo *intel_sdvo,
726 struct intel_sdvo_dtd *dtd) 727 struct intel_sdvo_dtd *dtd)
727{ 728{
728 bool status; 729 return intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1,
729 730 &dtd->part1, sizeof(dtd->part1)) &&
730 intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1, 731 intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2,
731 NULL, 0); 732 &dtd->part2, sizeof(dtd->part2));
732
733 status = intel_sdvo_read_response(intel_encoder, &dtd->part1,
734 sizeof(dtd->part1));
735 if (status != SDVO_CMD_STATUS_SUCCESS)
736 return false;
737
738 intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2,
739 NULL, 0);
740
741 status = intel_sdvo_read_response(intel_encoder, &dtd->part2,
742 sizeof(dtd->part2));
743 if (status != SDVO_CMD_STATUS_SUCCESS)
744 return false;
745
746 return false;
747} 733}
748 734
749static bool intel_sdvo_set_clock_rate_mult(struct intel_encoder *intel_encoder, u8 val) 735static bool intel_sdvo_set_clock_rate_mult(struct intel_sdvo *intel_sdvo, u8 val)
750{ 736{
751 u8 status; 737 return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_CLOCK_RATE_MULT, &val, 1);
752
753 intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_SET_CLOCK_RATE_MULT, &val, 1);
754 status = intel_sdvo_read_response(intel_encoder, NULL, 0);
755 if (status != SDVO_CMD_STATUS_SUCCESS)
756 return false;
757
758 return true;
759} 738}
760 739
761static void intel_sdvo_get_dtd_from_mode(struct intel_sdvo_dtd *dtd, 740static void intel_sdvo_get_dtd_from_mode(struct intel_sdvo_dtd *dtd,
762 struct drm_display_mode *mode) 741 const struct drm_display_mode *mode)
763{ 742{
764 uint16_t width, height; 743 uint16_t width, height;
765 uint16_t h_blank_len, h_sync_len, v_blank_len, v_sync_len; 744 uint16_t h_blank_len, h_sync_len, v_blank_len, v_sync_len;
@@ -808,7 +787,7 @@ static void intel_sdvo_get_dtd_from_mode(struct intel_sdvo_dtd *dtd,
808} 787}
809 788
810static void intel_sdvo_get_mode_from_dtd(struct drm_display_mode * mode, 789static void intel_sdvo_get_mode_from_dtd(struct drm_display_mode * mode,
811 struct intel_sdvo_dtd *dtd) 790 const struct intel_sdvo_dtd *dtd)
812{ 791{
813 mode->hdisplay = dtd->part1.h_active; 792 mode->hdisplay = dtd->part1.h_active;
814 mode->hdisplay += ((dtd->part1.h_high >> 4) & 0x0f) << 8; 793 mode->hdisplay += ((dtd->part1.h_high >> 4) & 0x0f) << 8;
@@ -840,45 +819,33 @@ static void intel_sdvo_get_mode_from_dtd(struct drm_display_mode * mode,
840 mode->flags |= DRM_MODE_FLAG_PVSYNC; 819 mode->flags |= DRM_MODE_FLAG_PVSYNC;
841} 820}
842 821
843static bool intel_sdvo_get_supp_encode(struct intel_encoder *intel_encoder, 822static bool intel_sdvo_get_supp_encode(struct intel_sdvo *intel_sdvo,
844 struct intel_sdvo_encode *encode) 823 struct intel_sdvo_encode *encode)
845{ 824{
846 uint8_t status; 825 if (intel_sdvo_get_value(intel_sdvo,
847 826 SDVO_CMD_GET_SUPP_ENCODE,
848 intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_GET_SUPP_ENCODE, NULL, 0); 827 encode, sizeof(*encode)))
849 status = intel_sdvo_read_response(intel_encoder, encode, sizeof(*encode)); 828 return true;
850 if (status != SDVO_CMD_STATUS_SUCCESS) { /* non-support means DVI */
851 memset(encode, 0, sizeof(*encode));
852 return false;
853 }
854 829
855 return true; 830 /* non-support means DVI */
831 memset(encode, 0, sizeof(*encode));
832 return false;
856} 833}
857 834
858static bool intel_sdvo_set_encode(struct intel_encoder *intel_encoder, 835static bool intel_sdvo_set_encode(struct intel_sdvo *intel_sdvo,
859 uint8_t mode) 836 uint8_t mode)
860{ 837{
861 uint8_t status; 838 return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_ENCODE, &mode, 1);
862
863 intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_SET_ENCODE, &mode, 1);
864 status = intel_sdvo_read_response(intel_encoder, NULL, 0);
865
866 return (status == SDVO_CMD_STATUS_SUCCESS);
867} 839}
868 840
869static bool intel_sdvo_set_colorimetry(struct intel_encoder *intel_encoder, 841static bool intel_sdvo_set_colorimetry(struct intel_sdvo *intel_sdvo,
870 uint8_t mode) 842 uint8_t mode)
871{ 843{
872 uint8_t status; 844 return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_COLORIMETRY, &mode, 1);
873
874 intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_SET_COLORIMETRY, &mode, 1);
875 status = intel_sdvo_read_response(intel_encoder, NULL, 0);
876
877 return (status == SDVO_CMD_STATUS_SUCCESS);
878} 845}
879 846
880#if 0 847#if 0
881static void intel_sdvo_dump_hdmi_buf(struct intel_encoder *intel_encoder) 848static void intel_sdvo_dump_hdmi_buf(struct intel_sdvo *intel_sdvo)
882{ 849{
883 int i, j; 850 int i, j;
884 uint8_t set_buf_index[2]; 851 uint8_t set_buf_index[2];
@@ -887,8 +854,7 @@ static void intel_sdvo_dump_hdmi_buf(struct intel_encoder *intel_encoder)
887 uint8_t buf[48]; 854 uint8_t buf[48];
888 uint8_t *pos; 855 uint8_t *pos;
889 856
890 intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_AV_SPLIT, NULL, 0); 857 intel_sdvo_get_value(encoder, SDVO_CMD_GET_HBUF_AV_SPLIT, &av_split, 1);
891 intel_sdvo_read_response(encoder, &av_split, 1);
892 858
893 for (i = 0; i <= av_split; i++) { 859 for (i = 0; i <= av_split; i++) {
894 set_buf_index[0] = i; set_buf_index[1] = 0; 860 set_buf_index[0] = i; set_buf_index[1] = 0;
@@ -908,7 +874,7 @@ static void intel_sdvo_dump_hdmi_buf(struct intel_encoder *intel_encoder)
908} 874}
909#endif 875#endif
910 876
911static void intel_sdvo_set_hdmi_buf(struct intel_encoder *intel_encoder, 877static bool intel_sdvo_set_hdmi_buf(struct intel_sdvo *intel_sdvo,
912 int index, 878 int index,
913 uint8_t *data, int8_t size, uint8_t tx_rate) 879 uint8_t *data, int8_t size, uint8_t tx_rate)
914{ 880{
@@ -917,15 +883,18 @@ static void intel_sdvo_set_hdmi_buf(struct intel_encoder *intel_encoder,
917 set_buf_index[0] = index; 883 set_buf_index[0] = index;
918 set_buf_index[1] = 0; 884 set_buf_index[1] = 0;
919 885
920 intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_SET_HBUF_INDEX, 886 if (!intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_SET_HBUF_INDEX,
921 set_buf_index, 2); 887 set_buf_index, 2))
888 return false;
922 889
923 for (; size > 0; size -= 8) { 890 for (; size > 0; size -= 8) {
924 intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_SET_HBUF_DATA, data, 8); 891 if (!intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_SET_HBUF_DATA, data, 8))
892 return false;
893
925 data += 8; 894 data += 8;
926 } 895 }
927 896
928 intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_SET_HBUF_TXRATE, &tx_rate, 1); 897 return intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_SET_HBUF_TXRATE, &tx_rate, 1);
929} 898}
930 899
931static uint8_t intel_sdvo_calc_hbuf_csum(uint8_t *data, uint8_t size) 900static uint8_t intel_sdvo_calc_hbuf_csum(uint8_t *data, uint8_t size)
@@ -1000,7 +969,7 @@ struct dip_infoframe {
1000 } __attribute__ ((packed)) u; 969 } __attribute__ ((packed)) u;
1001} __attribute__((packed)); 970} __attribute__((packed));
1002 971
1003static void intel_sdvo_set_avi_infoframe(struct intel_encoder *intel_encoder, 972static bool intel_sdvo_set_avi_infoframe(struct intel_sdvo *intel_sdvo,
1004 struct drm_display_mode * mode) 973 struct drm_display_mode * mode)
1005{ 974{
1006 struct dip_infoframe avi_if = { 975 struct dip_infoframe avi_if = {
@@ -1011,133 +980,107 @@ static void intel_sdvo_set_avi_infoframe(struct intel_encoder *intel_encoder,
1011 980
1012 avi_if.checksum = intel_sdvo_calc_hbuf_csum((uint8_t *)&avi_if, 981 avi_if.checksum = intel_sdvo_calc_hbuf_csum((uint8_t *)&avi_if,
1013 4 + avi_if.len); 982 4 + avi_if.len);
1014 intel_sdvo_set_hdmi_buf(intel_encoder, 1, (uint8_t *)&avi_if, 983 return intel_sdvo_set_hdmi_buf(intel_sdvo, 1, (uint8_t *)&avi_if,
1015 4 + avi_if.len, 984 4 + avi_if.len,
1016 SDVO_HBUF_TX_VSYNC); 985 SDVO_HBUF_TX_VSYNC);
1017} 986}
1018 987
1019static void intel_sdvo_set_tv_format(struct intel_encoder *intel_encoder) 988static bool intel_sdvo_set_tv_format(struct intel_sdvo *intel_sdvo)
1020{ 989{
1021
1022 struct intel_sdvo_tv_format format; 990 struct intel_sdvo_tv_format format;
1023 struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv; 991 uint32_t format_map;
1024 uint32_t format_map, i;
1025 uint8_t status;
1026
1027 for (i = 0; i < TV_FORMAT_NUM; i++)
1028 if (tv_format_names[i] == sdvo_priv->tv_format_name)
1029 break;
1030 992
1031 format_map = 1 << i; 993 format_map = 1 << intel_sdvo->tv_format_index;
1032 memset(&format, 0, sizeof(format)); 994 memset(&format, 0, sizeof(format));
1033 memcpy(&format, &format_map, sizeof(format_map) > sizeof(format) ? 995 memcpy(&format, &format_map, min(sizeof(format), sizeof(format_map)));
1034 sizeof(format) : sizeof(format_map));
1035 996
1036 intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_SET_TV_FORMAT, &format, 997 BUILD_BUG_ON(sizeof(format) != 6);
1037 sizeof(format)); 998 return intel_sdvo_set_value(intel_sdvo,
1038 999 SDVO_CMD_SET_TV_FORMAT,
1039 status = intel_sdvo_read_response(intel_encoder, NULL, 0); 1000 &format, sizeof(format));
1040 if (status != SDVO_CMD_STATUS_SUCCESS)
1041 DRM_DEBUG_KMS("%s: Failed to set TV format\n",
1042 SDVO_NAME(sdvo_priv));
1043} 1001}
1044 1002
1045static bool intel_sdvo_mode_fixup(struct drm_encoder *encoder, 1003static bool
1046 struct drm_display_mode *mode, 1004intel_sdvo_set_output_timings_from_mode(struct intel_sdvo *intel_sdvo,
1047 struct drm_display_mode *adjusted_mode) 1005 struct drm_display_mode *mode)
1048{ 1006{
1049 struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder); 1007 struct intel_sdvo_dtd output_dtd;
1050 struct intel_sdvo_priv *dev_priv = intel_encoder->dev_priv;
1051 1008
1052 if (dev_priv->is_tv) { 1009 if (!intel_sdvo_set_target_output(intel_sdvo,
1053 struct intel_sdvo_dtd output_dtd; 1010 intel_sdvo->attached_output))
1054 bool success; 1011 return false;
1055 1012
1056 /* We need to construct preferred input timings based on our 1013 intel_sdvo_get_dtd_from_mode(&output_dtd, mode);
1057 * output timings. To do that, we have to set the output 1014 if (!intel_sdvo_set_output_timing(intel_sdvo, &output_dtd))
1058 * timings, even though this isn't really the right place in 1015 return false;
1059 * the sequence to do it. Oh well.
1060 */
1061 1016
1017 return true;
1018}
1062 1019
1063 /* Set output timings */ 1020static bool
1064 intel_sdvo_get_dtd_from_mode(&output_dtd, mode); 1021intel_sdvo_set_input_timings_for_mode(struct intel_sdvo *intel_sdvo,
1065 intel_sdvo_set_target_output(intel_encoder, 1022 struct drm_display_mode *mode,
1066 dev_priv->attached_output); 1023 struct drm_display_mode *adjusted_mode)
1067 intel_sdvo_set_output_timing(intel_encoder, &output_dtd); 1024{
1025 struct intel_sdvo_dtd input_dtd;
1068 1026
1069 /* Set the input timing to the screen. Assume always input 0. */ 1027 /* Reset the input timing to the screen. Assume always input 0. */
1070 intel_sdvo_set_target_input(intel_encoder, true, false); 1028 if (!intel_sdvo_set_target_input(intel_sdvo))
1029 return false;
1071 1030
1031 if (!intel_sdvo_create_preferred_input_timing(intel_sdvo,
1032 mode->clock / 10,
1033 mode->hdisplay,
1034 mode->vdisplay))
1035 return false;
1072 1036
1073 success = intel_sdvo_create_preferred_input_timing(intel_encoder, 1037 if (!intel_sdvo_get_preferred_input_timing(intel_sdvo,
1074 mode->clock / 10, 1038 &input_dtd))
1075 mode->hdisplay, 1039 return false;
1076 mode->vdisplay);
1077 if (success) {
1078 struct intel_sdvo_dtd input_dtd;
1079 1040
1080 intel_sdvo_get_preferred_input_timing(intel_encoder, 1041 intel_sdvo_get_mode_from_dtd(adjusted_mode, &input_dtd);
1081 &input_dtd); 1042 intel_sdvo->sdvo_flags = input_dtd.part2.sdvo_flags;
1082 intel_sdvo_get_mode_from_dtd(adjusted_mode, &input_dtd);
1083 dev_priv->sdvo_flags = input_dtd.part2.sdvo_flags;
1084 1043
1085 drm_mode_set_crtcinfo(adjusted_mode, 0); 1044 drm_mode_set_crtcinfo(adjusted_mode, 0);
1045 mode->clock = adjusted_mode->clock;
1046 return true;
1047}
1086 1048
1087 mode->clock = adjusted_mode->clock; 1049static bool intel_sdvo_mode_fixup(struct drm_encoder *encoder,
1050 struct drm_display_mode *mode,
1051 struct drm_display_mode *adjusted_mode)
1052{
1053 struct intel_sdvo *intel_sdvo = enc_to_intel_sdvo(encoder);
1088 1054
1089 adjusted_mode->clock *= 1055 /* We need to construct preferred input timings based on our
1090 intel_sdvo_get_pixel_multiplier(mode); 1056 * output timings. To do that, we have to set the output
1091 } else { 1057 * timings, even though this isn't really the right place in
1058 * the sequence to do it. Oh well.
1059 */
1060 if (intel_sdvo->is_tv) {
1061 if (!intel_sdvo_set_output_timings_from_mode(intel_sdvo, mode))
1092 return false; 1062 return false;
1093 }
1094 } else if (dev_priv->is_lvds) {
1095 struct intel_sdvo_dtd output_dtd;
1096 bool success;
1097
1098 drm_mode_set_crtcinfo(dev_priv->sdvo_lvds_fixed_mode, 0);
1099 /* Set output timings */
1100 intel_sdvo_get_dtd_from_mode(&output_dtd,
1101 dev_priv->sdvo_lvds_fixed_mode);
1102
1103 intel_sdvo_set_target_output(intel_encoder,
1104 dev_priv->attached_output);
1105 intel_sdvo_set_output_timing(intel_encoder, &output_dtd);
1106
1107 /* Set the input timing to the screen. Assume always input 0. */
1108 intel_sdvo_set_target_input(intel_encoder, true, false);
1109
1110
1111 success = intel_sdvo_create_preferred_input_timing(
1112 intel_encoder,
1113 mode->clock / 10,
1114 mode->hdisplay,
1115 mode->vdisplay);
1116
1117 if (success) {
1118 struct intel_sdvo_dtd input_dtd;
1119
1120 intel_sdvo_get_preferred_input_timing(intel_encoder,
1121 &input_dtd);
1122 intel_sdvo_get_mode_from_dtd(adjusted_mode, &input_dtd);
1123 dev_priv->sdvo_flags = input_dtd.part2.sdvo_flags;
1124 1063
1125 drm_mode_set_crtcinfo(adjusted_mode, 0); 1064 (void) intel_sdvo_set_input_timings_for_mode(intel_sdvo,
1065 mode,
1066 adjusted_mode);
1067 } else if (intel_sdvo->is_lvds) {
1068 drm_mode_set_crtcinfo(intel_sdvo->sdvo_lvds_fixed_mode, 0);
1126 1069
1127 mode->clock = adjusted_mode->clock; 1070 if (!intel_sdvo_set_output_timings_from_mode(intel_sdvo,
1128 1071 intel_sdvo->sdvo_lvds_fixed_mode))
1129 adjusted_mode->clock *=
1130 intel_sdvo_get_pixel_multiplier(mode);
1131 } else {
1132 return false; 1072 return false;
1133 }
1134 1073
1135 } else { 1074 (void) intel_sdvo_set_input_timings_for_mode(intel_sdvo,
1136 /* Make the CRTC code factor in the SDVO pixel multiplier. The 1075 mode,
1137 * SDVO device will be told of the multiplier during mode_set. 1076 adjusted_mode);
1138 */
1139 adjusted_mode->clock *= intel_sdvo_get_pixel_multiplier(mode);
1140 } 1077 }
1078
1079 /* Make the CRTC code factor in the SDVO pixel multiplier. The
1080 * SDVO device will be told of the multiplier during mode_set.
1081 */
1082 adjusted_mode->clock *= intel_sdvo_get_pixel_multiplier(mode);
1083
1141 return true; 1084 return true;
1142} 1085}
1143 1086
@@ -1149,13 +1092,11 @@ static void intel_sdvo_mode_set(struct drm_encoder *encoder,
1149 struct drm_i915_private *dev_priv = dev->dev_private; 1092 struct drm_i915_private *dev_priv = dev->dev_private;
1150 struct drm_crtc *crtc = encoder->crtc; 1093 struct drm_crtc *crtc = encoder->crtc;
1151 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 1094 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1152 struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder); 1095 struct intel_sdvo *intel_sdvo = enc_to_intel_sdvo(encoder);
1153 struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv;
1154 u32 sdvox = 0; 1096 u32 sdvox = 0;
1155 int sdvo_pixel_multiply; 1097 int sdvo_pixel_multiply, rate;
1156 struct intel_sdvo_in_out_map in_out; 1098 struct intel_sdvo_in_out_map in_out;
1157 struct intel_sdvo_dtd input_dtd; 1099 struct intel_sdvo_dtd input_dtd;
1158 u8 status;
1159 1100
1160 if (!mode) 1101 if (!mode)
1161 return; 1102 return;
@@ -1166,41 +1107,46 @@ static void intel_sdvo_mode_set(struct drm_encoder *encoder,
1166 * channel on the motherboard. In a two-input device, the first input 1107 * channel on the motherboard. In a two-input device, the first input
1167 * will be SDVOB and the second SDVOC. 1108 * will be SDVOB and the second SDVOC.
1168 */ 1109 */
1169 in_out.in0 = sdvo_priv->attached_output; 1110 in_out.in0 = intel_sdvo->attached_output;
1170 in_out.in1 = 0; 1111 in_out.in1 = 0;
1171 1112
1172 intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_SET_IN_OUT_MAP, 1113 intel_sdvo_set_value(intel_sdvo,
1114 SDVO_CMD_SET_IN_OUT_MAP,
1173 &in_out, sizeof(in_out)); 1115 &in_out, sizeof(in_out));
1174 status = intel_sdvo_read_response(intel_encoder, NULL, 0);
1175 1116
1176 if (sdvo_priv->is_hdmi) { 1117 if (intel_sdvo->is_hdmi) {
1177 intel_sdvo_set_avi_infoframe(intel_encoder, mode); 1118 if (!intel_sdvo_set_avi_infoframe(intel_sdvo, mode))
1119 return;
1120
1178 sdvox |= SDVO_AUDIO_ENABLE; 1121 sdvox |= SDVO_AUDIO_ENABLE;
1179 } 1122 }
1180 1123
1181 /* We have tried to get input timing in mode_fixup, and filled into 1124 /* We have tried to get input timing in mode_fixup, and filled into
1182 adjusted_mode */ 1125 adjusted_mode */
1183 if (sdvo_priv->is_tv || sdvo_priv->is_lvds) { 1126 intel_sdvo_get_dtd_from_mode(&input_dtd, adjusted_mode);
1184 intel_sdvo_get_dtd_from_mode(&input_dtd, adjusted_mode); 1127 if (intel_sdvo->is_tv || intel_sdvo->is_lvds)
1185 input_dtd.part2.sdvo_flags = sdvo_priv->sdvo_flags; 1128 input_dtd.part2.sdvo_flags = intel_sdvo->sdvo_flags;
1186 } else
1187 intel_sdvo_get_dtd_from_mode(&input_dtd, mode);
1188 1129
1189 /* If it's a TV, we already set the output timing in mode_fixup. 1130 /* If it's a TV, we already set the output timing in mode_fixup.
1190 * Otherwise, the output timing is equal to the input timing. 1131 * Otherwise, the output timing is equal to the input timing.
1191 */ 1132 */
1192 if (!sdvo_priv->is_tv && !sdvo_priv->is_lvds) { 1133 if (!intel_sdvo->is_tv && !intel_sdvo->is_lvds) {
1193 /* Set the output timing to the screen */ 1134 /* Set the output timing to the screen */
1194 intel_sdvo_set_target_output(intel_encoder, 1135 if (!intel_sdvo_set_target_output(intel_sdvo,
1195 sdvo_priv->attached_output); 1136 intel_sdvo->attached_output))
1196 intel_sdvo_set_output_timing(intel_encoder, &input_dtd); 1137 return;
1138
1139 (void) intel_sdvo_set_output_timing(intel_sdvo, &input_dtd);
1197 } 1140 }
1198 1141
1199 /* Set the input timing to the screen. Assume always input 0. */ 1142 /* Set the input timing to the screen. Assume always input 0. */
1200 intel_sdvo_set_target_input(intel_encoder, true, false); 1143 if (!intel_sdvo_set_target_input(intel_sdvo))
1144 return;
1201 1145
1202 if (sdvo_priv->is_tv) 1146 if (intel_sdvo->is_tv) {
1203 intel_sdvo_set_tv_format(intel_encoder); 1147 if (!intel_sdvo_set_tv_format(intel_sdvo))
1148 return;
1149 }
1204 1150
1205 /* We would like to use intel_sdvo_create_preferred_input_timing() to 1151 /* We would like to use intel_sdvo_create_preferred_input_timing() to
1206 * provide the device with a timing it can support, if it supports that 1152 * provide the device with a timing it can support, if it supports that
@@ -1217,23 +1163,17 @@ static void intel_sdvo_mode_set(struct drm_encoder *encoder,
1217 intel_sdvo_set_input_timing(encoder, &input_dtd); 1163 intel_sdvo_set_input_timing(encoder, &input_dtd);
1218 } 1164 }
1219#else 1165#else
1220 intel_sdvo_set_input_timing(intel_encoder, &input_dtd); 1166 (void) intel_sdvo_set_input_timing(intel_sdvo, &input_dtd);
1221#endif 1167#endif
1222 1168
1223 switch (intel_sdvo_get_pixel_multiplier(mode)) { 1169 sdvo_pixel_multiply = intel_sdvo_get_pixel_multiplier(mode);
1224 case 1: 1170 switch (sdvo_pixel_multiply) {
1225 intel_sdvo_set_clock_rate_mult(intel_encoder, 1171 case 1: rate = SDVO_CLOCK_RATE_MULT_1X; break;
1226 SDVO_CLOCK_RATE_MULT_1X); 1172 case 2: rate = SDVO_CLOCK_RATE_MULT_2X; break;
1227 break; 1173 case 4: rate = SDVO_CLOCK_RATE_MULT_4X; break;
1228 case 2:
1229 intel_sdvo_set_clock_rate_mult(intel_encoder,
1230 SDVO_CLOCK_RATE_MULT_2X);
1231 break;
1232 case 4:
1233 intel_sdvo_set_clock_rate_mult(intel_encoder,
1234 SDVO_CLOCK_RATE_MULT_4X);
1235 break;
1236 } 1174 }
1175 if (!intel_sdvo_set_clock_rate_mult(intel_sdvo, rate))
1176 return;
1237 1177
1238 /* Set the SDVO control regs. */ 1178 /* Set the SDVO control regs. */
1239 if (IS_I965G(dev)) { 1179 if (IS_I965G(dev)) {
@@ -1243,8 +1183,8 @@ static void intel_sdvo_mode_set(struct drm_encoder *encoder,
1243 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) 1183 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1244 sdvox |= SDVO_HSYNC_ACTIVE_HIGH; 1184 sdvox |= SDVO_HSYNC_ACTIVE_HIGH;
1245 } else { 1185 } else {
1246 sdvox |= I915_READ(sdvo_priv->sdvo_reg); 1186 sdvox |= I915_READ(intel_sdvo->sdvo_reg);
1247 switch (sdvo_priv->sdvo_reg) { 1187 switch (intel_sdvo->sdvo_reg) {
1248 case SDVOB: 1188 case SDVOB:
1249 sdvox &= SDVOB_PRESERVE_MASK; 1189 sdvox &= SDVOB_PRESERVE_MASK;
1250 break; 1190 break;
@@ -1257,7 +1197,6 @@ static void intel_sdvo_mode_set(struct drm_encoder *encoder,
1257 if (intel_crtc->pipe == 1) 1197 if (intel_crtc->pipe == 1)
1258 sdvox |= SDVO_PIPE_B_SELECT; 1198 sdvox |= SDVO_PIPE_B_SELECT;
1259 1199
1260 sdvo_pixel_multiply = intel_sdvo_get_pixel_multiplier(mode);
1261 if (IS_I965G(dev)) { 1200 if (IS_I965G(dev)) {
1262 /* done in crtc_mode_set as the dpll_md reg must be written early */ 1201 /* done in crtc_mode_set as the dpll_md reg must be written early */
1263 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) { 1202 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
@@ -1266,28 +1205,28 @@ static void intel_sdvo_mode_set(struct drm_encoder *encoder,
1266 sdvox |= (sdvo_pixel_multiply - 1) << SDVO_PORT_MULTIPLY_SHIFT; 1205 sdvox |= (sdvo_pixel_multiply - 1) << SDVO_PORT_MULTIPLY_SHIFT;
1267 } 1206 }
1268 1207
1269 if (sdvo_priv->sdvo_flags & SDVO_NEED_TO_STALL) 1208 if (intel_sdvo->sdvo_flags & SDVO_NEED_TO_STALL)
1270 sdvox |= SDVO_STALL_SELECT; 1209 sdvox |= SDVO_STALL_SELECT;
1271 intel_sdvo_write_sdvox(intel_encoder, sdvox); 1210 intel_sdvo_write_sdvox(intel_sdvo, sdvox);
1272} 1211}
1273 1212
1274static void intel_sdvo_dpms(struct drm_encoder *encoder, int mode) 1213static void intel_sdvo_dpms(struct drm_encoder *encoder, int mode)
1275{ 1214{
1276 struct drm_device *dev = encoder->dev; 1215 struct drm_device *dev = encoder->dev;
1277 struct drm_i915_private *dev_priv = dev->dev_private; 1216 struct drm_i915_private *dev_priv = dev->dev_private;
1278 struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder); 1217 struct intel_sdvo *intel_sdvo = enc_to_intel_sdvo(encoder);
1279 struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv; 1218 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
1280 u32 temp; 1219 u32 temp;
1281 1220
1282 if (mode != DRM_MODE_DPMS_ON) { 1221 if (mode != DRM_MODE_DPMS_ON) {
1283 intel_sdvo_set_active_outputs(intel_encoder, 0); 1222 intel_sdvo_set_active_outputs(intel_sdvo, 0);
1284 if (0) 1223 if (0)
1285 intel_sdvo_set_encoder_power_state(intel_encoder, mode); 1224 intel_sdvo_set_encoder_power_state(intel_sdvo, mode);
1286 1225
1287 if (mode == DRM_MODE_DPMS_OFF) { 1226 if (mode == DRM_MODE_DPMS_OFF) {
1288 temp = I915_READ(sdvo_priv->sdvo_reg); 1227 temp = I915_READ(intel_sdvo->sdvo_reg);
1289 if ((temp & SDVO_ENABLE) != 0) { 1228 if ((temp & SDVO_ENABLE) != 0) {
1290 intel_sdvo_write_sdvox(intel_encoder, temp & ~SDVO_ENABLE); 1229 intel_sdvo_write_sdvox(intel_sdvo, temp & ~SDVO_ENABLE);
1291 } 1230 }
1292 } 1231 }
1293 } else { 1232 } else {
@@ -1295,28 +1234,25 @@ static void intel_sdvo_dpms(struct drm_encoder *encoder, int mode)
1295 int i; 1234 int i;
1296 u8 status; 1235 u8 status;
1297 1236
1298 temp = I915_READ(sdvo_priv->sdvo_reg); 1237 temp = I915_READ(intel_sdvo->sdvo_reg);
1299 if ((temp & SDVO_ENABLE) == 0) 1238 if ((temp & SDVO_ENABLE) == 0)
1300 intel_sdvo_write_sdvox(intel_encoder, temp | SDVO_ENABLE); 1239 intel_sdvo_write_sdvox(intel_sdvo, temp | SDVO_ENABLE);
1301 for (i = 0; i < 2; i++) 1240 for (i = 0; i < 2; i++)
1302 intel_wait_for_vblank(dev); 1241 intel_wait_for_vblank(dev, intel_crtc->pipe);
1303
1304 status = intel_sdvo_get_trained_inputs(intel_encoder, &input1,
1305 &input2);
1306
1307 1242
1243 status = intel_sdvo_get_trained_inputs(intel_sdvo, &input1, &input2);
1308 /* Warn if the device reported failure to sync. 1244 /* Warn if the device reported failure to sync.
1309 * A lot of SDVO devices fail to notify of sync, but it's 1245 * A lot of SDVO devices fail to notify of sync, but it's
1310 * a given it the status is a success, we succeeded. 1246 * a given it the status is a success, we succeeded.
1311 */ 1247 */
1312 if (status == SDVO_CMD_STATUS_SUCCESS && !input1) { 1248 if (status == SDVO_CMD_STATUS_SUCCESS && !input1) {
1313 DRM_DEBUG_KMS("First %s output reported failure to " 1249 DRM_DEBUG_KMS("First %s output reported failure to "
1314 "sync\n", SDVO_NAME(sdvo_priv)); 1250 "sync\n", SDVO_NAME(intel_sdvo));
1315 } 1251 }
1316 1252
1317 if (0) 1253 if (0)
1318 intel_sdvo_set_encoder_power_state(intel_encoder, mode); 1254 intel_sdvo_set_encoder_power_state(intel_sdvo, mode);
1319 intel_sdvo_set_active_outputs(intel_encoder, sdvo_priv->attached_output); 1255 intel_sdvo_set_active_outputs(intel_sdvo, intel_sdvo->attached_output);
1320 } 1256 }
1321 return; 1257 return;
1322} 1258}
@@ -1325,42 +1261,31 @@ static int intel_sdvo_mode_valid(struct drm_connector *connector,
1325 struct drm_display_mode *mode) 1261 struct drm_display_mode *mode)
1326{ 1262{
1327 struct drm_encoder *encoder = intel_attached_encoder(connector); 1263 struct drm_encoder *encoder = intel_attached_encoder(connector);
1328 struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder); 1264 struct intel_sdvo *intel_sdvo = enc_to_intel_sdvo(encoder);
1329 struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv;
1330 1265
1331 if (mode->flags & DRM_MODE_FLAG_DBLSCAN) 1266 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
1332 return MODE_NO_DBLESCAN; 1267 return MODE_NO_DBLESCAN;
1333 1268
1334 if (sdvo_priv->pixel_clock_min > mode->clock) 1269 if (intel_sdvo->pixel_clock_min > mode->clock)
1335 return MODE_CLOCK_LOW; 1270 return MODE_CLOCK_LOW;
1336 1271
1337 if (sdvo_priv->pixel_clock_max < mode->clock) 1272 if (intel_sdvo->pixel_clock_max < mode->clock)
1338 return MODE_CLOCK_HIGH; 1273 return MODE_CLOCK_HIGH;
1339 1274
1340 if (sdvo_priv->is_lvds == true) { 1275 if (intel_sdvo->is_lvds) {
1341 if (sdvo_priv->sdvo_lvds_fixed_mode == NULL) 1276 if (mode->hdisplay > intel_sdvo->sdvo_lvds_fixed_mode->hdisplay)
1342 return MODE_PANEL; 1277 return MODE_PANEL;
1343 1278
1344 if (mode->hdisplay > sdvo_priv->sdvo_lvds_fixed_mode->hdisplay) 1279 if (mode->vdisplay > intel_sdvo->sdvo_lvds_fixed_mode->vdisplay)
1345 return MODE_PANEL;
1346
1347 if (mode->vdisplay > sdvo_priv->sdvo_lvds_fixed_mode->vdisplay)
1348 return MODE_PANEL; 1280 return MODE_PANEL;
1349 } 1281 }
1350 1282
1351 return MODE_OK; 1283 return MODE_OK;
1352} 1284}
1353 1285
1354static bool intel_sdvo_get_capabilities(struct intel_encoder *intel_encoder, struct intel_sdvo_caps *caps) 1286static bool intel_sdvo_get_capabilities(struct intel_sdvo *intel_sdvo, struct intel_sdvo_caps *caps)
1355{ 1287{
1356 u8 status; 1288 return intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_DEVICE_CAPS, caps, sizeof(*caps));
1357
1358 intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_GET_DEVICE_CAPS, NULL, 0);
1359 status = intel_sdvo_read_response(intel_encoder, caps, sizeof(*caps));
1360 if (status != SDVO_CMD_STATUS_SUCCESS)
1361 return false;
1362
1363 return true;
1364} 1289}
1365 1290
1366/* No use! */ 1291/* No use! */
@@ -1368,12 +1293,12 @@ static bool intel_sdvo_get_capabilities(struct intel_encoder *intel_encoder, str
1368struct drm_connector* intel_sdvo_find(struct drm_device *dev, int sdvoB) 1293struct drm_connector* intel_sdvo_find(struct drm_device *dev, int sdvoB)
1369{ 1294{
1370 struct drm_connector *connector = NULL; 1295 struct drm_connector *connector = NULL;
1371 struct intel_encoder *iout = NULL; 1296 struct intel_sdvo *iout = NULL;
1372 struct intel_sdvo_priv *sdvo; 1297 struct intel_sdvo *sdvo;
1373 1298
1374 /* find the sdvo connector */ 1299 /* find the sdvo connector */
1375 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 1300 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1376 iout = to_intel_encoder(connector); 1301 iout = to_intel_sdvo(connector);
1377 1302
1378 if (iout->type != INTEL_OUTPUT_SDVO) 1303 if (iout->type != INTEL_OUTPUT_SDVO)
1379 continue; 1304 continue;
@@ -1395,75 +1320,69 @@ int intel_sdvo_supports_hotplug(struct drm_connector *connector)
1395{ 1320{
1396 u8 response[2]; 1321 u8 response[2];
1397 u8 status; 1322 u8 status;
1398 struct intel_encoder *intel_encoder; 1323 struct intel_sdvo *intel_sdvo;
1399 DRM_DEBUG_KMS("\n"); 1324 DRM_DEBUG_KMS("\n");
1400 1325
1401 if (!connector) 1326 if (!connector)
1402 return 0; 1327 return 0;
1403 1328
1404 intel_encoder = to_intel_encoder(connector); 1329 intel_sdvo = to_intel_sdvo(connector);
1405
1406 intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_GET_HOT_PLUG_SUPPORT, NULL, 0);
1407 status = intel_sdvo_read_response(intel_encoder, &response, 2);
1408
1409 if (response[0] !=0)
1410 return 1;
1411 1330
1412 return 0; 1331 return intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_HOT_PLUG_SUPPORT,
1332 &response, 2) && response[0];
1413} 1333}
1414 1334
1415void intel_sdvo_set_hotplug(struct drm_connector *connector, int on) 1335void intel_sdvo_set_hotplug(struct drm_connector *connector, int on)
1416{ 1336{
1417 u8 response[2]; 1337 u8 response[2];
1418 u8 status; 1338 u8 status;
1419 struct intel_encoder *intel_encoder = to_intel_encoder(connector); 1339 struct intel_sdvo *intel_sdvo = to_intel_sdvo(connector);
1420 1340
1421 intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_GET_ACTIVE_HOT_PLUG, NULL, 0); 1341 intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_GET_ACTIVE_HOT_PLUG, NULL, 0);
1422 intel_sdvo_read_response(intel_encoder, &response, 2); 1342 intel_sdvo_read_response(intel_sdvo, &response, 2);
1423 1343
1424 if (on) { 1344 if (on) {
1425 intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_GET_HOT_PLUG_SUPPORT, NULL, 0); 1345 intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_GET_HOT_PLUG_SUPPORT, NULL, 0);
1426 status = intel_sdvo_read_response(intel_encoder, &response, 2); 1346 status = intel_sdvo_read_response(intel_sdvo, &response, 2);
1427 1347
1428 intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_SET_ACTIVE_HOT_PLUG, &response, 2); 1348 intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_SET_ACTIVE_HOT_PLUG, &response, 2);
1429 } else { 1349 } else {
1430 response[0] = 0; 1350 response[0] = 0;
1431 response[1] = 0; 1351 response[1] = 0;
1432 intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_SET_ACTIVE_HOT_PLUG, &response, 2); 1352 intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_SET_ACTIVE_HOT_PLUG, &response, 2);
1433 } 1353 }
1434 1354
1435 intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_GET_ACTIVE_HOT_PLUG, NULL, 0); 1355 intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_GET_ACTIVE_HOT_PLUG, NULL, 0);
1436 intel_sdvo_read_response(intel_encoder, &response, 2); 1356 intel_sdvo_read_response(intel_sdvo, &response, 2);
1437} 1357}
1438#endif 1358#endif
1439 1359
1440static bool 1360static bool
1441intel_sdvo_multifunc_encoder(struct intel_encoder *intel_encoder) 1361intel_sdvo_multifunc_encoder(struct intel_sdvo *intel_sdvo)
1442{ 1362{
1443 struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv;
1444 int caps = 0; 1363 int caps = 0;
1445 1364
1446 if (sdvo_priv->caps.output_flags & 1365 if (intel_sdvo->caps.output_flags &
1447 (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_TMDS1)) 1366 (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_TMDS1))
1448 caps++; 1367 caps++;
1449 if (sdvo_priv->caps.output_flags & 1368 if (intel_sdvo->caps.output_flags &
1450 (SDVO_OUTPUT_RGB0 | SDVO_OUTPUT_RGB1)) 1369 (SDVO_OUTPUT_RGB0 | SDVO_OUTPUT_RGB1))
1451 caps++; 1370 caps++;
1452 if (sdvo_priv->caps.output_flags & 1371 if (intel_sdvo->caps.output_flags &
1453 (SDVO_OUTPUT_SVID0 | SDVO_OUTPUT_SVID1)) 1372 (SDVO_OUTPUT_SVID0 | SDVO_OUTPUT_SVID1))
1454 caps++; 1373 caps++;
1455 if (sdvo_priv->caps.output_flags & 1374 if (intel_sdvo->caps.output_flags &
1456 (SDVO_OUTPUT_CVBS0 | SDVO_OUTPUT_CVBS1)) 1375 (SDVO_OUTPUT_CVBS0 | SDVO_OUTPUT_CVBS1))
1457 caps++; 1376 caps++;
1458 if (sdvo_priv->caps.output_flags & 1377 if (intel_sdvo->caps.output_flags &
1459 (SDVO_OUTPUT_YPRPB0 | SDVO_OUTPUT_YPRPB1)) 1378 (SDVO_OUTPUT_YPRPB0 | SDVO_OUTPUT_YPRPB1))
1460 caps++; 1379 caps++;
1461 1380
1462 if (sdvo_priv->caps.output_flags & 1381 if (intel_sdvo->caps.output_flags &
1463 (SDVO_OUTPUT_SCART0 | SDVO_OUTPUT_SCART1)) 1382 (SDVO_OUTPUT_SCART0 | SDVO_OUTPUT_SCART1))
1464 caps++; 1383 caps++;
1465 1384
1466 if (sdvo_priv->caps.output_flags & 1385 if (intel_sdvo->caps.output_flags &
1467 (SDVO_OUTPUT_LVDS0 | SDVO_OUTPUT_LVDS1)) 1386 (SDVO_OUTPUT_LVDS0 | SDVO_OUTPUT_LVDS1))
1468 caps++; 1387 caps++;
1469 1388
@@ -1475,11 +1394,11 @@ intel_find_analog_connector(struct drm_device *dev)
1475{ 1394{
1476 struct drm_connector *connector; 1395 struct drm_connector *connector;
1477 struct drm_encoder *encoder; 1396 struct drm_encoder *encoder;
1478 struct intel_encoder *intel_encoder; 1397 struct intel_sdvo *intel_sdvo;
1479 1398
1480 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 1399 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1481 intel_encoder = enc_to_intel_encoder(encoder); 1400 intel_sdvo = enc_to_intel_sdvo(encoder);
1482 if (intel_encoder->type == INTEL_OUTPUT_ANALOG) { 1401 if (intel_sdvo->base.type == INTEL_OUTPUT_ANALOG) {
1483 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 1402 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1484 if (encoder == intel_attached_encoder(connector)) 1403 if (encoder == intel_attached_encoder(connector))
1485 return connector; 1404 return connector;
@@ -1493,8 +1412,8 @@ static int
1493intel_analog_is_connected(struct drm_device *dev) 1412intel_analog_is_connected(struct drm_device *dev)
1494{ 1413{
1495 struct drm_connector *analog_connector; 1414 struct drm_connector *analog_connector;
1496 analog_connector = intel_find_analog_connector(dev);
1497 1415
1416 analog_connector = intel_find_analog_connector(dev);
1498 if (!analog_connector) 1417 if (!analog_connector)
1499 return false; 1418 return false;
1500 1419
@@ -1509,54 +1428,52 @@ enum drm_connector_status
1509intel_sdvo_hdmi_sink_detect(struct drm_connector *connector) 1428intel_sdvo_hdmi_sink_detect(struct drm_connector *connector)
1510{ 1429{
1511 struct drm_encoder *encoder = intel_attached_encoder(connector); 1430 struct drm_encoder *encoder = intel_attached_encoder(connector);
1512 struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder); 1431 struct intel_sdvo *intel_sdvo = enc_to_intel_sdvo(encoder);
1513 struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv; 1432 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
1514 struct intel_connector *intel_connector = to_intel_connector(connector);
1515 struct intel_sdvo_connector *sdvo_connector = intel_connector->dev_priv;
1516 enum drm_connector_status status = connector_status_connected; 1433 enum drm_connector_status status = connector_status_connected;
1517 struct edid *edid = NULL; 1434 struct edid *edid = NULL;
1518 1435
1519 edid = drm_get_edid(connector, intel_encoder->ddc_bus); 1436 edid = drm_get_edid(connector, intel_sdvo->base.ddc_bus);
1520 1437
1521 /* This is only applied to SDVO cards with multiple outputs */ 1438 /* This is only applied to SDVO cards with multiple outputs */
1522 if (edid == NULL && intel_sdvo_multifunc_encoder(intel_encoder)) { 1439 if (edid == NULL && intel_sdvo_multifunc_encoder(intel_sdvo)) {
1523 uint8_t saved_ddc, temp_ddc; 1440 uint8_t saved_ddc, temp_ddc;
1524 saved_ddc = sdvo_priv->ddc_bus; 1441 saved_ddc = intel_sdvo->ddc_bus;
1525 temp_ddc = sdvo_priv->ddc_bus >> 1; 1442 temp_ddc = intel_sdvo->ddc_bus >> 1;
1526 /* 1443 /*
1527 * Don't use the 1 as the argument of DDC bus switch to get 1444 * Don't use the 1 as the argument of DDC bus switch to get
1528 * the EDID. It is used for SDVO SPD ROM. 1445 * the EDID. It is used for SDVO SPD ROM.
1529 */ 1446 */
1530 while(temp_ddc > 1) { 1447 while(temp_ddc > 1) {
1531 sdvo_priv->ddc_bus = temp_ddc; 1448 intel_sdvo->ddc_bus = temp_ddc;
1532 edid = drm_get_edid(connector, intel_encoder->ddc_bus); 1449 edid = drm_get_edid(connector, intel_sdvo->base.ddc_bus);
1533 if (edid) { 1450 if (edid) {
1534 /* 1451 /*
1535 * When we can get the EDID, maybe it is the 1452 * When we can get the EDID, maybe it is the
1536 * correct DDC bus. Update it. 1453 * correct DDC bus. Update it.
1537 */ 1454 */
1538 sdvo_priv->ddc_bus = temp_ddc; 1455 intel_sdvo->ddc_bus = temp_ddc;
1539 break; 1456 break;
1540 } 1457 }
1541 temp_ddc >>= 1; 1458 temp_ddc >>= 1;
1542 } 1459 }
1543 if (edid == NULL) 1460 if (edid == NULL)
1544 sdvo_priv->ddc_bus = saved_ddc; 1461 intel_sdvo->ddc_bus = saved_ddc;
1545 } 1462 }
1546 /* when there is no edid and no monitor is connected with VGA 1463 /* when there is no edid and no monitor is connected with VGA
1547 * port, try to use the CRT ddc to read the EDID for DVI-connector 1464 * port, try to use the CRT ddc to read the EDID for DVI-connector
1548 */ 1465 */
1549 if (edid == NULL && sdvo_priv->analog_ddc_bus && 1466 if (edid == NULL && intel_sdvo->analog_ddc_bus &&
1550 !intel_analog_is_connected(connector->dev)) 1467 !intel_analog_is_connected(connector->dev))
1551 edid = drm_get_edid(connector, sdvo_priv->analog_ddc_bus); 1468 edid = drm_get_edid(connector, intel_sdvo->analog_ddc_bus);
1552 1469
1553 if (edid != NULL) { 1470 if (edid != NULL) {
1554 bool is_digital = !!(edid->input & DRM_EDID_INPUT_DIGITAL); 1471 bool is_digital = !!(edid->input & DRM_EDID_INPUT_DIGITAL);
1555 bool need_digital = !!(sdvo_connector->output_flag & SDVO_TMDS_MASK); 1472 bool need_digital = !!(intel_sdvo_connector->output_flag & SDVO_TMDS_MASK);
1556 1473
1557 /* DDC bus is shared, match EDID to connector type */ 1474 /* DDC bus is shared, match EDID to connector type */
1558 if (is_digital && need_digital) 1475 if (is_digital && need_digital)
1559 sdvo_priv->is_hdmi = drm_detect_hdmi_monitor(edid); 1476 intel_sdvo->is_hdmi = drm_detect_hdmi_monitor(edid);
1560 else if (is_digital != need_digital) 1477 else if (is_digital != need_digital)
1561 status = connector_status_disconnected; 1478 status = connector_status_disconnected;
1562 1479
@@ -1572,33 +1489,29 @@ intel_sdvo_hdmi_sink_detect(struct drm_connector *connector)
1572static enum drm_connector_status intel_sdvo_detect(struct drm_connector *connector) 1489static enum drm_connector_status intel_sdvo_detect(struct drm_connector *connector)
1573{ 1490{
1574 uint16_t response; 1491 uint16_t response;
1575 u8 status;
1576 struct drm_encoder *encoder = intel_attached_encoder(connector); 1492 struct drm_encoder *encoder = intel_attached_encoder(connector);
1577 struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder); 1493 struct intel_sdvo *intel_sdvo = enc_to_intel_sdvo(encoder);
1578 struct intel_connector *intel_connector = to_intel_connector(connector); 1494 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
1579 struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv;
1580 struct intel_sdvo_connector *sdvo_connector = intel_connector->dev_priv;
1581 enum drm_connector_status ret; 1495 enum drm_connector_status ret;
1582 1496
1583 intel_sdvo_write_cmd(intel_encoder, 1497 if (!intel_sdvo_write_cmd(intel_sdvo,
1584 SDVO_CMD_GET_ATTACHED_DISPLAYS, NULL, 0); 1498 SDVO_CMD_GET_ATTACHED_DISPLAYS, NULL, 0))
1585 if (sdvo_priv->is_tv) { 1499 return connector_status_unknown;
1500 if (intel_sdvo->is_tv) {
1586 /* add 30ms delay when the output type is SDVO-TV */ 1501 /* add 30ms delay when the output type is SDVO-TV */
1587 mdelay(30); 1502 mdelay(30);
1588 } 1503 }
1589 status = intel_sdvo_read_response(intel_encoder, &response, 2); 1504 if (!intel_sdvo_read_response(intel_sdvo, &response, 2))
1505 return connector_status_unknown;
1590 1506
1591 DRM_DEBUG_KMS("SDVO response %d %d\n", response & 0xff, response >> 8); 1507 DRM_DEBUG_KMS("SDVO response %d %d\n", response & 0xff, response >> 8);
1592 1508
1593 if (status != SDVO_CMD_STATUS_SUCCESS)
1594 return connector_status_unknown;
1595
1596 if (response == 0) 1509 if (response == 0)
1597 return connector_status_disconnected; 1510 return connector_status_disconnected;
1598 1511
1599 sdvo_priv->attached_output = response; 1512 intel_sdvo->attached_output = response;
1600 1513
1601 if ((sdvo_connector->output_flag & response) == 0) 1514 if ((intel_sdvo_connector->output_flag & response) == 0)
1602 ret = connector_status_disconnected; 1515 ret = connector_status_disconnected;
1603 else if (response & SDVO_TMDS_MASK) 1516 else if (response & SDVO_TMDS_MASK)
1604 ret = intel_sdvo_hdmi_sink_detect(connector); 1517 ret = intel_sdvo_hdmi_sink_detect(connector);
@@ -1607,16 +1520,16 @@ static enum drm_connector_status intel_sdvo_detect(struct drm_connector *connect
1607 1520
1608 /* May update encoder flag for like clock for SDVO TV, etc.*/ 1521 /* May update encoder flag for like clock for SDVO TV, etc.*/
1609 if (ret == connector_status_connected) { 1522 if (ret == connector_status_connected) {
1610 sdvo_priv->is_tv = false; 1523 intel_sdvo->is_tv = false;
1611 sdvo_priv->is_lvds = false; 1524 intel_sdvo->is_lvds = false;
1612 intel_encoder->needs_tv_clock = false; 1525 intel_sdvo->base.needs_tv_clock = false;
1613 1526
1614 if (response & SDVO_TV_MASK) { 1527 if (response & SDVO_TV_MASK) {
1615 sdvo_priv->is_tv = true; 1528 intel_sdvo->is_tv = true;
1616 intel_encoder->needs_tv_clock = true; 1529 intel_sdvo->base.needs_tv_clock = true;
1617 } 1530 }
1618 if (response & SDVO_LVDS_MASK) 1531 if (response & SDVO_LVDS_MASK)
1619 sdvo_priv->is_lvds = true; 1532 intel_sdvo->is_lvds = intel_sdvo->sdvo_lvds_fixed_mode != NULL;
1620 } 1533 }
1621 1534
1622 return ret; 1535 return ret;
@@ -1625,12 +1538,11 @@ static enum drm_connector_status intel_sdvo_detect(struct drm_connector *connect
1625static void intel_sdvo_get_ddc_modes(struct drm_connector *connector) 1538static void intel_sdvo_get_ddc_modes(struct drm_connector *connector)
1626{ 1539{
1627 struct drm_encoder *encoder = intel_attached_encoder(connector); 1540 struct drm_encoder *encoder = intel_attached_encoder(connector);
1628 struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder); 1541 struct intel_sdvo *intel_sdvo = enc_to_intel_sdvo(encoder);
1629 struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv;
1630 int num_modes; 1542 int num_modes;
1631 1543
1632 /* set the bus switch and get the modes */ 1544 /* set the bus switch and get the modes */
1633 num_modes = intel_ddc_get_modes(connector, intel_encoder->ddc_bus); 1545 num_modes = intel_ddc_get_modes(connector, intel_sdvo->base.ddc_bus);
1634 1546
1635 /* 1547 /*
1636 * Mac mini hack. On this device, the DVI-I connector shares one DDC 1548 * Mac mini hack. On this device, the DVI-I connector shares one DDC
@@ -1639,11 +1551,11 @@ static void intel_sdvo_get_ddc_modes(struct drm_connector *connector)
1639 * which case we'll look there for the digital DDC data. 1551 * which case we'll look there for the digital DDC data.
1640 */ 1552 */
1641 if (num_modes == 0 && 1553 if (num_modes == 0 &&
1642 sdvo_priv->analog_ddc_bus && 1554 intel_sdvo->analog_ddc_bus &&
1643 !intel_analog_is_connected(connector->dev)) { 1555 !intel_analog_is_connected(connector->dev)) {
1644 /* Switch to the analog ddc bus and try that 1556 /* Switch to the analog ddc bus and try that
1645 */ 1557 */
1646 (void) intel_ddc_get_modes(connector, sdvo_priv->analog_ddc_bus); 1558 (void) intel_ddc_get_modes(connector, intel_sdvo->analog_ddc_bus);
1647 } 1559 }
1648} 1560}
1649 1561
@@ -1715,52 +1627,43 @@ struct drm_display_mode sdvo_tv_modes[] = {
1715static void intel_sdvo_get_tv_modes(struct drm_connector *connector) 1627static void intel_sdvo_get_tv_modes(struct drm_connector *connector)
1716{ 1628{
1717 struct drm_encoder *encoder = intel_attached_encoder(connector); 1629 struct drm_encoder *encoder = intel_attached_encoder(connector);
1718 struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder); 1630 struct intel_sdvo *intel_sdvo = enc_to_intel_sdvo(encoder);
1719 struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv;
1720 struct intel_sdvo_sdtv_resolution_request tv_res; 1631 struct intel_sdvo_sdtv_resolution_request tv_res;
1721 uint32_t reply = 0, format_map = 0; 1632 uint32_t reply = 0, format_map = 0;
1722 int i; 1633 int i;
1723 uint8_t status;
1724
1725 1634
1726 /* Read the list of supported input resolutions for the selected TV 1635 /* Read the list of supported input resolutions for the selected TV
1727 * format. 1636 * format.
1728 */ 1637 */
1729 for (i = 0; i < TV_FORMAT_NUM; i++) 1638 format_map = 1 << intel_sdvo->tv_format_index;
1730 if (tv_format_names[i] == sdvo_priv->tv_format_name)
1731 break;
1732
1733 format_map = (1 << i);
1734 memcpy(&tv_res, &format_map, 1639 memcpy(&tv_res, &format_map,
1735 sizeof(struct intel_sdvo_sdtv_resolution_request) > 1640 min(sizeof(format_map), sizeof(struct intel_sdvo_sdtv_resolution_request)));
1736 sizeof(format_map) ? sizeof(format_map) :
1737 sizeof(struct intel_sdvo_sdtv_resolution_request));
1738 1641
1739 intel_sdvo_set_target_output(intel_encoder, sdvo_priv->attached_output); 1642 if (!intel_sdvo_set_target_output(intel_sdvo, intel_sdvo->attached_output))
1643 return;
1740 1644
1741 intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT, 1645 BUILD_BUG_ON(sizeof(tv_res) != 3);
1742 &tv_res, sizeof(tv_res)); 1646 if (!intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT,
1743 status = intel_sdvo_read_response(intel_encoder, &reply, 3); 1647 &tv_res, sizeof(tv_res)))
1744 if (status != SDVO_CMD_STATUS_SUCCESS) 1648 return;
1649 if (!intel_sdvo_read_response(intel_sdvo, &reply, 3))
1745 return; 1650 return;
1746 1651
1747 for (i = 0; i < ARRAY_SIZE(sdvo_tv_modes); i++) 1652 for (i = 0; i < ARRAY_SIZE(sdvo_tv_modes); i++)
1748 if (reply & (1 << i)) { 1653 if (reply & (1 << i)) {
1749 struct drm_display_mode *nmode; 1654 struct drm_display_mode *nmode;
1750 nmode = drm_mode_duplicate(connector->dev, 1655 nmode = drm_mode_duplicate(connector->dev,
1751 &sdvo_tv_modes[i]); 1656 &sdvo_tv_modes[i]);
1752 if (nmode) 1657 if (nmode)
1753 drm_mode_probed_add(connector, nmode); 1658 drm_mode_probed_add(connector, nmode);
1754 } 1659 }
1755
1756} 1660}
1757 1661
1758static void intel_sdvo_get_lvds_modes(struct drm_connector *connector) 1662static void intel_sdvo_get_lvds_modes(struct drm_connector *connector)
1759{ 1663{
1760 struct drm_encoder *encoder = intel_attached_encoder(connector); 1664 struct drm_encoder *encoder = intel_attached_encoder(connector);
1761 struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder); 1665 struct intel_sdvo *intel_sdvo = enc_to_intel_sdvo(encoder);
1762 struct drm_i915_private *dev_priv = connector->dev->dev_private; 1666 struct drm_i915_private *dev_priv = connector->dev->dev_private;
1763 struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv;
1764 struct drm_display_mode *newmode; 1667 struct drm_display_mode *newmode;
1765 1668
1766 /* 1669 /*
@@ -1768,7 +1671,7 @@ static void intel_sdvo_get_lvds_modes(struct drm_connector *connector)
1768 * Assume that the preferred modes are 1671 * Assume that the preferred modes are
1769 * arranged in priority order. 1672 * arranged in priority order.
1770 */ 1673 */
1771 intel_ddc_get_modes(connector, intel_encoder->ddc_bus); 1674 intel_ddc_get_modes(connector, intel_sdvo->base.ddc_bus);
1772 if (list_empty(&connector->probed_modes) == false) 1675 if (list_empty(&connector->probed_modes) == false)
1773 goto end; 1676 goto end;
1774 1677
@@ -1787,8 +1690,9 @@ static void intel_sdvo_get_lvds_modes(struct drm_connector *connector)
1787end: 1690end:
1788 list_for_each_entry(newmode, &connector->probed_modes, head) { 1691 list_for_each_entry(newmode, &connector->probed_modes, head) {
1789 if (newmode->type & DRM_MODE_TYPE_PREFERRED) { 1692 if (newmode->type & DRM_MODE_TYPE_PREFERRED) {
1790 sdvo_priv->sdvo_lvds_fixed_mode = 1693 intel_sdvo->sdvo_lvds_fixed_mode =
1791 drm_mode_duplicate(connector->dev, newmode); 1694 drm_mode_duplicate(connector->dev, newmode);
1695 intel_sdvo->is_lvds = true;
1792 break; 1696 break;
1793 } 1697 }
1794 } 1698 }
@@ -1797,66 +1701,67 @@ end:
1797 1701
1798static int intel_sdvo_get_modes(struct drm_connector *connector) 1702static int intel_sdvo_get_modes(struct drm_connector *connector)
1799{ 1703{
1800 struct intel_connector *intel_connector = to_intel_connector(connector); 1704 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
1801 struct intel_sdvo_connector *sdvo_connector = intel_connector->dev_priv;
1802 1705
1803 if (IS_TV(sdvo_connector)) 1706 if (IS_TV(intel_sdvo_connector))
1804 intel_sdvo_get_tv_modes(connector); 1707 intel_sdvo_get_tv_modes(connector);
1805 else if (IS_LVDS(sdvo_connector)) 1708 else if (IS_LVDS(intel_sdvo_connector))
1806 intel_sdvo_get_lvds_modes(connector); 1709 intel_sdvo_get_lvds_modes(connector);
1807 else 1710 else
1808 intel_sdvo_get_ddc_modes(connector); 1711 intel_sdvo_get_ddc_modes(connector);
1809 1712
1810 if (list_empty(&connector->probed_modes)) 1713 return !list_empty(&connector->probed_modes);
1811 return 0;
1812 return 1;
1813} 1714}
1814 1715
1815static 1716static void
1816void intel_sdvo_destroy_enhance_property(struct drm_connector *connector) 1717intel_sdvo_destroy_enhance_property(struct drm_connector *connector)
1817{ 1718{
1818 struct intel_connector *intel_connector = to_intel_connector(connector); 1719 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
1819 struct intel_sdvo_connector *sdvo_priv = intel_connector->dev_priv;
1820 struct drm_device *dev = connector->dev; 1720 struct drm_device *dev = connector->dev;
1821 1721
1822 if (IS_TV(sdvo_priv)) { 1722 if (intel_sdvo_connector->left)
1823 if (sdvo_priv->left_property) 1723 drm_property_destroy(dev, intel_sdvo_connector->left);
1824 drm_property_destroy(dev, sdvo_priv->left_property); 1724 if (intel_sdvo_connector->right)
1825 if (sdvo_priv->right_property) 1725 drm_property_destroy(dev, intel_sdvo_connector->right);
1826 drm_property_destroy(dev, sdvo_priv->right_property); 1726 if (intel_sdvo_connector->top)
1827 if (sdvo_priv->top_property) 1727 drm_property_destroy(dev, intel_sdvo_connector->top);
1828 drm_property_destroy(dev, sdvo_priv->top_property); 1728 if (intel_sdvo_connector->bottom)
1829 if (sdvo_priv->bottom_property) 1729 drm_property_destroy(dev, intel_sdvo_connector->bottom);
1830 drm_property_destroy(dev, sdvo_priv->bottom_property); 1730 if (intel_sdvo_connector->hpos)
1831 if (sdvo_priv->hpos_property) 1731 drm_property_destroy(dev, intel_sdvo_connector->hpos);
1832 drm_property_destroy(dev, sdvo_priv->hpos_property); 1732 if (intel_sdvo_connector->vpos)
1833 if (sdvo_priv->vpos_property) 1733 drm_property_destroy(dev, intel_sdvo_connector->vpos);
1834 drm_property_destroy(dev, sdvo_priv->vpos_property); 1734 if (intel_sdvo_connector->saturation)
1835 if (sdvo_priv->saturation_property) 1735 drm_property_destroy(dev, intel_sdvo_connector->saturation);
1836 drm_property_destroy(dev, 1736 if (intel_sdvo_connector->contrast)
1837 sdvo_priv->saturation_property); 1737 drm_property_destroy(dev, intel_sdvo_connector->contrast);
1838 if (sdvo_priv->contrast_property) 1738 if (intel_sdvo_connector->hue)
1839 drm_property_destroy(dev, 1739 drm_property_destroy(dev, intel_sdvo_connector->hue);
1840 sdvo_priv->contrast_property); 1740 if (intel_sdvo_connector->sharpness)
1841 if (sdvo_priv->hue_property) 1741 drm_property_destroy(dev, intel_sdvo_connector->sharpness);
1842 drm_property_destroy(dev, sdvo_priv->hue_property); 1742 if (intel_sdvo_connector->flicker_filter)
1843 } 1743 drm_property_destroy(dev, intel_sdvo_connector->flicker_filter);
1844 if (IS_TV(sdvo_priv) || IS_LVDS(sdvo_priv)) { 1744 if (intel_sdvo_connector->flicker_filter_2d)
1845 if (sdvo_priv->brightness_property) 1745 drm_property_destroy(dev, intel_sdvo_connector->flicker_filter_2d);
1846 drm_property_destroy(dev, 1746 if (intel_sdvo_connector->flicker_filter_adaptive)
1847 sdvo_priv->brightness_property); 1747 drm_property_destroy(dev, intel_sdvo_connector->flicker_filter_adaptive);
1848 } 1748 if (intel_sdvo_connector->tv_luma_filter)
1849 return; 1749 drm_property_destroy(dev, intel_sdvo_connector->tv_luma_filter);
1750 if (intel_sdvo_connector->tv_chroma_filter)
1751 drm_property_destroy(dev, intel_sdvo_connector->tv_chroma_filter);
1752 if (intel_sdvo_connector->dot_crawl)
1753 drm_property_destroy(dev, intel_sdvo_connector->dot_crawl);
1754 if (intel_sdvo_connector->brightness)
1755 drm_property_destroy(dev, intel_sdvo_connector->brightness);
1850} 1756}
1851 1757
1852static void intel_sdvo_destroy(struct drm_connector *connector) 1758static void intel_sdvo_destroy(struct drm_connector *connector)
1853{ 1759{
1854 struct intel_connector *intel_connector = to_intel_connector(connector); 1760 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
1855 struct intel_sdvo_connector *sdvo_connector = intel_connector->dev_priv;
1856 1761
1857 if (sdvo_connector->tv_format_property) 1762 if (intel_sdvo_connector->tv_format)
1858 drm_property_destroy(connector->dev, 1763 drm_property_destroy(connector->dev,
1859 sdvo_connector->tv_format_property); 1764 intel_sdvo_connector->tv_format);
1860 1765
1861 intel_sdvo_destroy_enhance_property(connector); 1766 intel_sdvo_destroy_enhance_property(connector);
1862 drm_sysfs_connector_remove(connector); 1767 drm_sysfs_connector_remove(connector);
@@ -1870,132 +1775,118 @@ intel_sdvo_set_property(struct drm_connector *connector,
1870 uint64_t val) 1775 uint64_t val)
1871{ 1776{
1872 struct drm_encoder *encoder = intel_attached_encoder(connector); 1777 struct drm_encoder *encoder = intel_attached_encoder(connector);
1873 struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder); 1778 struct intel_sdvo *intel_sdvo = enc_to_intel_sdvo(encoder);
1874 struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv; 1779 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
1875 struct intel_connector *intel_connector = to_intel_connector(connector);
1876 struct intel_sdvo_connector *sdvo_connector = intel_connector->dev_priv;
1877 struct drm_crtc *crtc = encoder->crtc;
1878 int ret = 0;
1879 bool changed = false;
1880 uint8_t cmd, status;
1881 uint16_t temp_value; 1780 uint16_t temp_value;
1781 uint8_t cmd;
1782 int ret;
1882 1783
1883 ret = drm_connector_property_set_value(connector, property, val); 1784 ret = drm_connector_property_set_value(connector, property, val);
1884 if (ret < 0) 1785 if (ret)
1885 goto out; 1786 return ret;
1787
1788#define CHECK_PROPERTY(name, NAME) \
1789 if (intel_sdvo_connector->name == property) { \
1790 if (intel_sdvo_connector->cur_##name == temp_value) return 0; \
1791 if (intel_sdvo_connector->max_##name < temp_value) return -EINVAL; \
1792 cmd = SDVO_CMD_SET_##NAME; \
1793 intel_sdvo_connector->cur_##name = temp_value; \
1794 goto set_value; \
1795 }
1886 1796
1887 if (property == sdvo_connector->tv_format_property) { 1797 if (property == intel_sdvo_connector->tv_format) {
1888 if (val >= TV_FORMAT_NUM) { 1798 if (val >= TV_FORMAT_NUM)
1889 ret = -EINVAL; 1799 return -EINVAL;
1890 goto out;
1891 }
1892 if (sdvo_priv->tv_format_name ==
1893 sdvo_connector->tv_format_supported[val])
1894 goto out;
1895 1800
1896 sdvo_priv->tv_format_name = sdvo_connector->tv_format_supported[val]; 1801 if (intel_sdvo->tv_format_index ==
1897 changed = true; 1802 intel_sdvo_connector->tv_format_supported[val])
1898 } 1803 return 0;
1899 1804
1900 if (IS_TV(sdvo_connector) || IS_LVDS(sdvo_connector)) { 1805 intel_sdvo->tv_format_index = intel_sdvo_connector->tv_format_supported[val];
1901 cmd = 0; 1806 goto done;
1807 } else if (IS_TV_OR_LVDS(intel_sdvo_connector)) {
1902 temp_value = val; 1808 temp_value = val;
1903 if (sdvo_connector->left_property == property) { 1809 if (intel_sdvo_connector->left == property) {
1904 drm_connector_property_set_value(connector, 1810 drm_connector_property_set_value(connector,
1905 sdvo_connector->right_property, val); 1811 intel_sdvo_connector->right, val);
1906 if (sdvo_connector->left_margin == temp_value) 1812 if (intel_sdvo_connector->left_margin == temp_value)
1907 goto out; 1813 return 0;
1908 1814
1909 sdvo_connector->left_margin = temp_value; 1815 intel_sdvo_connector->left_margin = temp_value;
1910 sdvo_connector->right_margin = temp_value; 1816 intel_sdvo_connector->right_margin = temp_value;
1911 temp_value = sdvo_connector->max_hscan - 1817 temp_value = intel_sdvo_connector->max_hscan -
1912 sdvo_connector->left_margin; 1818 intel_sdvo_connector->left_margin;
1913 cmd = SDVO_CMD_SET_OVERSCAN_H; 1819 cmd = SDVO_CMD_SET_OVERSCAN_H;
1914 } else if (sdvo_connector->right_property == property) { 1820 goto set_value;
1821 } else if (intel_sdvo_connector->right == property) {
1915 drm_connector_property_set_value(connector, 1822 drm_connector_property_set_value(connector,
1916 sdvo_connector->left_property, val); 1823 intel_sdvo_connector->left, val);
1917 if (sdvo_connector->right_margin == temp_value) 1824 if (intel_sdvo_connector->right_margin == temp_value)
1918 goto out; 1825 return 0;
1919 1826
1920 sdvo_connector->left_margin = temp_value; 1827 intel_sdvo_connector->left_margin = temp_value;
1921 sdvo_connector->right_margin = temp_value; 1828 intel_sdvo_connector->right_margin = temp_value;
1922 temp_value = sdvo_connector->max_hscan - 1829 temp_value = intel_sdvo_connector->max_hscan -
1923 sdvo_connector->left_margin; 1830 intel_sdvo_connector->left_margin;
1924 cmd = SDVO_CMD_SET_OVERSCAN_H; 1831 cmd = SDVO_CMD_SET_OVERSCAN_H;
1925 } else if (sdvo_connector->top_property == property) { 1832 goto set_value;
1833 } else if (intel_sdvo_connector->top == property) {
1926 drm_connector_property_set_value(connector, 1834 drm_connector_property_set_value(connector,
1927 sdvo_connector->bottom_property, val); 1835 intel_sdvo_connector->bottom, val);
1928 if (sdvo_connector->top_margin == temp_value) 1836 if (intel_sdvo_connector->top_margin == temp_value)
1929 goto out; 1837 return 0;
1930 1838
1931 sdvo_connector->top_margin = temp_value; 1839 intel_sdvo_connector->top_margin = temp_value;
1932 sdvo_connector->bottom_margin = temp_value; 1840 intel_sdvo_connector->bottom_margin = temp_value;
1933 temp_value = sdvo_connector->max_vscan - 1841 temp_value = intel_sdvo_connector->max_vscan -
1934 sdvo_connector->top_margin; 1842 intel_sdvo_connector->top_margin;
1935 cmd = SDVO_CMD_SET_OVERSCAN_V; 1843 cmd = SDVO_CMD_SET_OVERSCAN_V;
1936 } else if (sdvo_connector->bottom_property == property) { 1844 goto set_value;
1845 } else if (intel_sdvo_connector->bottom == property) {
1937 drm_connector_property_set_value(connector, 1846 drm_connector_property_set_value(connector,
1938 sdvo_connector->top_property, val); 1847 intel_sdvo_connector->top, val);
1939 if (sdvo_connector->bottom_margin == temp_value) 1848 if (intel_sdvo_connector->bottom_margin == temp_value)
1940 goto out; 1849 return 0;
1941 sdvo_connector->top_margin = temp_value; 1850
1942 sdvo_connector->bottom_margin = temp_value; 1851 intel_sdvo_connector->top_margin = temp_value;
1943 temp_value = sdvo_connector->max_vscan - 1852 intel_sdvo_connector->bottom_margin = temp_value;
1944 sdvo_connector->top_margin; 1853 temp_value = intel_sdvo_connector->max_vscan -
1854 intel_sdvo_connector->top_margin;
1945 cmd = SDVO_CMD_SET_OVERSCAN_V; 1855 cmd = SDVO_CMD_SET_OVERSCAN_V;
1946 } else if (sdvo_connector->hpos_property == property) { 1856 goto set_value;
1947 if (sdvo_connector->cur_hpos == temp_value)
1948 goto out;
1949
1950 cmd = SDVO_CMD_SET_POSITION_H;
1951 sdvo_connector->cur_hpos = temp_value;
1952 } else if (sdvo_connector->vpos_property == property) {
1953 if (sdvo_connector->cur_vpos == temp_value)
1954 goto out;
1955
1956 cmd = SDVO_CMD_SET_POSITION_V;
1957 sdvo_connector->cur_vpos = temp_value;
1958 } else if (sdvo_connector->saturation_property == property) {
1959 if (sdvo_connector->cur_saturation == temp_value)
1960 goto out;
1961
1962 cmd = SDVO_CMD_SET_SATURATION;
1963 sdvo_connector->cur_saturation = temp_value;
1964 } else if (sdvo_connector->contrast_property == property) {
1965 if (sdvo_connector->cur_contrast == temp_value)
1966 goto out;
1967
1968 cmd = SDVO_CMD_SET_CONTRAST;
1969 sdvo_connector->cur_contrast = temp_value;
1970 } else if (sdvo_connector->hue_property == property) {
1971 if (sdvo_connector->cur_hue == temp_value)
1972 goto out;
1973
1974 cmd = SDVO_CMD_SET_HUE;
1975 sdvo_connector->cur_hue = temp_value;
1976 } else if (sdvo_connector->brightness_property == property) {
1977 if (sdvo_connector->cur_brightness == temp_value)
1978 goto out;
1979
1980 cmd = SDVO_CMD_SET_BRIGHTNESS;
1981 sdvo_connector->cur_brightness = temp_value;
1982 }
1983 if (cmd) {
1984 intel_sdvo_write_cmd(intel_encoder, cmd, &temp_value, 2);
1985 status = intel_sdvo_read_response(intel_encoder,
1986 NULL, 0);
1987 if (status != SDVO_CMD_STATUS_SUCCESS) {
1988 DRM_DEBUG_KMS("Incorrect SDVO command \n");
1989 return -EINVAL;
1990 }
1991 changed = true;
1992 } 1857 }
1858 CHECK_PROPERTY(hpos, HPOS)
1859 CHECK_PROPERTY(vpos, VPOS)
1860 CHECK_PROPERTY(saturation, SATURATION)
1861 CHECK_PROPERTY(contrast, CONTRAST)
1862 CHECK_PROPERTY(hue, HUE)
1863 CHECK_PROPERTY(brightness, BRIGHTNESS)
1864 CHECK_PROPERTY(sharpness, SHARPNESS)
1865 CHECK_PROPERTY(flicker_filter, FLICKER_FILTER)
1866 CHECK_PROPERTY(flicker_filter_2d, FLICKER_FILTER_2D)
1867 CHECK_PROPERTY(flicker_filter_adaptive, FLICKER_FILTER_ADAPTIVE)
1868 CHECK_PROPERTY(tv_chroma_filter, TV_CHROMA_FILTER)
1869 CHECK_PROPERTY(tv_luma_filter, TV_LUMA_FILTER)
1870 CHECK_PROPERTY(dot_crawl, DOT_CRAWL)
1993 } 1871 }
1994 if (changed && crtc) 1872
1873 return -EINVAL; /* unknown property */
1874
1875set_value:
1876 if (!intel_sdvo_set_value(intel_sdvo, cmd, &temp_value, 2))
1877 return -EIO;
1878
1879
1880done:
1881 if (encoder->crtc) {
1882 struct drm_crtc *crtc = encoder->crtc;
1883
1995 drm_crtc_helper_set_mode(crtc, &crtc->mode, crtc->x, 1884 drm_crtc_helper_set_mode(crtc, &crtc->mode, crtc->x,
1996 crtc->y, crtc->fb); 1885 crtc->y, crtc->fb);
1997out: 1886 }
1998 return ret; 1887
1888 return 0;
1889#undef CHECK_PROPERTY
1999} 1890}
2000 1891
2001static const struct drm_encoder_helper_funcs intel_sdvo_helper_funcs = { 1892static const struct drm_encoder_helper_funcs intel_sdvo_helper_funcs = {
@@ -2022,28 +1913,57 @@ static const struct drm_connector_helper_funcs intel_sdvo_connector_helper_funcs
2022 1913
2023static void intel_sdvo_enc_destroy(struct drm_encoder *encoder) 1914static void intel_sdvo_enc_destroy(struct drm_encoder *encoder)
2024{ 1915{
2025 struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder); 1916 struct intel_sdvo *intel_sdvo = enc_to_intel_sdvo(encoder);
2026 struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv;
2027 1917
2028 if (intel_encoder->i2c_bus) 1918 if (intel_sdvo->analog_ddc_bus)
2029 intel_i2c_destroy(intel_encoder->i2c_bus); 1919 intel_i2c_destroy(intel_sdvo->analog_ddc_bus);
2030 if (intel_encoder->ddc_bus)
2031 intel_i2c_destroy(intel_encoder->ddc_bus);
2032 if (sdvo_priv->analog_ddc_bus)
2033 intel_i2c_destroy(sdvo_priv->analog_ddc_bus);
2034 1920
2035 if (sdvo_priv->sdvo_lvds_fixed_mode != NULL) 1921 if (intel_sdvo->sdvo_lvds_fixed_mode != NULL)
2036 drm_mode_destroy(encoder->dev, 1922 drm_mode_destroy(encoder->dev,
2037 sdvo_priv->sdvo_lvds_fixed_mode); 1923 intel_sdvo->sdvo_lvds_fixed_mode);
2038 1924
2039 drm_encoder_cleanup(encoder); 1925 intel_encoder_destroy(encoder);
2040 kfree(intel_encoder);
2041} 1926}
2042 1927
2043static const struct drm_encoder_funcs intel_sdvo_enc_funcs = { 1928static const struct drm_encoder_funcs intel_sdvo_enc_funcs = {
2044 .destroy = intel_sdvo_enc_destroy, 1929 .destroy = intel_sdvo_enc_destroy,
2045}; 1930};
2046 1931
1932static void
1933intel_sdvo_guess_ddc_bus(struct intel_sdvo *sdvo)
1934{
1935 uint16_t mask = 0;
1936 unsigned int num_bits;
1937
1938 /* Make a mask of outputs less than or equal to our own priority in the
1939 * list.
1940 */
1941 switch (sdvo->controlled_output) {
1942 case SDVO_OUTPUT_LVDS1:
1943 mask |= SDVO_OUTPUT_LVDS1;
1944 case SDVO_OUTPUT_LVDS0:
1945 mask |= SDVO_OUTPUT_LVDS0;
1946 case SDVO_OUTPUT_TMDS1:
1947 mask |= SDVO_OUTPUT_TMDS1;
1948 case SDVO_OUTPUT_TMDS0:
1949 mask |= SDVO_OUTPUT_TMDS0;
1950 case SDVO_OUTPUT_RGB1:
1951 mask |= SDVO_OUTPUT_RGB1;
1952 case SDVO_OUTPUT_RGB0:
1953 mask |= SDVO_OUTPUT_RGB0;
1954 break;
1955 }
1956
1957 /* Count bits to find what number we are in the priority list. */
1958 mask &= sdvo->caps.output_flags;
1959 num_bits = hweight16(mask);
1960 /* If more than 3 outputs, default to DDC bus 3 for now. */
1961 if (num_bits > 3)
1962 num_bits = 3;
1963
1964 /* Corresponds to SDVO_CONTROL_BUS_DDCx */
1965 sdvo->ddc_bus = 1 << num_bits;
1966}
2047 1967
2048/** 1968/**
2049 * Choose the appropriate DDC bus for control bus switch command for this 1969 * Choose the appropriate DDC bus for control bus switch command for this
@@ -2054,7 +1974,7 @@ static const struct drm_encoder_funcs intel_sdvo_enc_funcs = {
2054 */ 1974 */
2055static void 1975static void
2056intel_sdvo_select_ddc_bus(struct drm_i915_private *dev_priv, 1976intel_sdvo_select_ddc_bus(struct drm_i915_private *dev_priv,
2057 struct intel_sdvo_priv *sdvo, u32 reg) 1977 struct intel_sdvo *sdvo, u32 reg)
2058{ 1978{
2059 struct sdvo_device_mapping *mapping; 1979 struct sdvo_device_mapping *mapping;
2060 1980
@@ -2063,61 +1983,53 @@ intel_sdvo_select_ddc_bus(struct drm_i915_private *dev_priv,
2063 else 1983 else
2064 mapping = &(dev_priv->sdvo_mappings[1]); 1984 mapping = &(dev_priv->sdvo_mappings[1]);
2065 1985
2066 sdvo->ddc_bus = 1 << ((mapping->ddc_pin & 0xf0) >> 4); 1986 if (mapping->initialized)
1987 sdvo->ddc_bus = 1 << ((mapping->ddc_pin & 0xf0) >> 4);
1988 else
1989 intel_sdvo_guess_ddc_bus(sdvo);
2067} 1990}
2068 1991
2069static bool 1992static bool
2070intel_sdvo_get_digital_encoding_mode(struct intel_encoder *output, int device) 1993intel_sdvo_get_digital_encoding_mode(struct intel_sdvo *intel_sdvo, int device)
2071{ 1994{
2072 struct intel_sdvo_priv *sdvo_priv = output->dev_priv; 1995 return intel_sdvo_set_target_output(intel_sdvo,
2073 uint8_t status; 1996 device == 0 ? SDVO_OUTPUT_TMDS0 : SDVO_OUTPUT_TMDS1) &&
2074 1997 intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_ENCODE,
2075 if (device == 0) 1998 &intel_sdvo->is_hdmi, 1);
2076 intel_sdvo_set_target_output(output, SDVO_OUTPUT_TMDS0);
2077 else
2078 intel_sdvo_set_target_output(output, SDVO_OUTPUT_TMDS1);
2079
2080 intel_sdvo_write_cmd(output, SDVO_CMD_GET_ENCODE, NULL, 0);
2081 status = intel_sdvo_read_response(output, &sdvo_priv->is_hdmi, 1);
2082 if (status != SDVO_CMD_STATUS_SUCCESS)
2083 return false;
2084 return true;
2085} 1999}
2086 2000
2087static struct intel_encoder * 2001static struct intel_sdvo *
2088intel_sdvo_chan_to_intel_encoder(struct intel_i2c_chan *chan) 2002intel_sdvo_chan_to_intel_sdvo(struct intel_i2c_chan *chan)
2089{ 2003{
2090 struct drm_device *dev = chan->drm_dev; 2004 struct drm_device *dev = chan->drm_dev;
2091 struct drm_encoder *encoder; 2005 struct drm_encoder *encoder;
2092 struct intel_encoder *intel_encoder = NULL;
2093 2006
2094 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 2007 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2095 intel_encoder = enc_to_intel_encoder(encoder); 2008 struct intel_sdvo *intel_sdvo = enc_to_intel_sdvo(encoder);
2096 if (intel_encoder->ddc_bus == &chan->adapter) 2009 if (intel_sdvo->base.ddc_bus == &chan->adapter)
2097 break; 2010 return intel_sdvo;
2098 } 2011 }
2099 return intel_encoder; 2012
2013 return NULL;
2100} 2014}
2101 2015
2102static int intel_sdvo_master_xfer(struct i2c_adapter *i2c_adap, 2016static int intel_sdvo_master_xfer(struct i2c_adapter *i2c_adap,
2103 struct i2c_msg msgs[], int num) 2017 struct i2c_msg msgs[], int num)
2104{ 2018{
2105 struct intel_encoder *intel_encoder; 2019 struct intel_sdvo *intel_sdvo;
2106 struct intel_sdvo_priv *sdvo_priv;
2107 struct i2c_algo_bit_data *algo_data; 2020 struct i2c_algo_bit_data *algo_data;
2108 const struct i2c_algorithm *algo; 2021 const struct i2c_algorithm *algo;
2109 2022
2110 algo_data = (struct i2c_algo_bit_data *)i2c_adap->algo_data; 2023 algo_data = (struct i2c_algo_bit_data *)i2c_adap->algo_data;
2111 intel_encoder = 2024 intel_sdvo =
2112 intel_sdvo_chan_to_intel_encoder( 2025 intel_sdvo_chan_to_intel_sdvo((struct intel_i2c_chan *)
2113 (struct intel_i2c_chan *)(algo_data->data)); 2026 (algo_data->data));
2114 if (intel_encoder == NULL) 2027 if (intel_sdvo == NULL)
2115 return -EINVAL; 2028 return -EINVAL;
2116 2029
2117 sdvo_priv = intel_encoder->dev_priv; 2030 algo = intel_sdvo->base.i2c_bus->algo;
2118 algo = intel_encoder->i2c_bus->algo;
2119 2031
2120 intel_sdvo_set_control_bus_switch(intel_encoder, sdvo_priv->ddc_bus); 2032 intel_sdvo_set_control_bus_switch(intel_sdvo, intel_sdvo->ddc_bus);
2121 return algo->master_xfer(i2c_adap, msgs, num); 2033 return algo->master_xfer(i2c_adap, msgs, num);
2122} 2034}
2123 2035
@@ -2162,27 +2074,9 @@ intel_sdvo_get_slave_addr(struct drm_device *dev, int sdvo_reg)
2162 return 0x72; 2074 return 0x72;
2163} 2075}
2164 2076
2165static bool
2166intel_sdvo_connector_alloc (struct intel_connector **ret)
2167{
2168 struct intel_connector *intel_connector;
2169 struct intel_sdvo_connector *sdvo_connector;
2170
2171 *ret = kzalloc(sizeof(*intel_connector) +
2172 sizeof(*sdvo_connector), GFP_KERNEL);
2173 if (!*ret)
2174 return false;
2175
2176 intel_connector = *ret;
2177 sdvo_connector = (struct intel_sdvo_connector *)(intel_connector + 1);
2178 intel_connector->dev_priv = sdvo_connector;
2179
2180 return true;
2181}
2182
2183static void 2077static void
2184intel_sdvo_connector_create (struct drm_encoder *encoder, 2078intel_sdvo_connector_init(struct drm_encoder *encoder,
2185 struct drm_connector *connector) 2079 struct drm_connector *connector)
2186{ 2080{
2187 drm_connector_init(encoder->dev, connector, &intel_sdvo_connector_funcs, 2081 drm_connector_init(encoder->dev, connector, &intel_sdvo_connector_funcs,
2188 connector->connector_type); 2082 connector->connector_type);
@@ -2198,582 +2092,470 @@ intel_sdvo_connector_create (struct drm_encoder *encoder,
2198} 2092}
2199 2093
2200static bool 2094static bool
2201intel_sdvo_dvi_init(struct intel_encoder *intel_encoder, int device) 2095intel_sdvo_dvi_init(struct intel_sdvo *intel_sdvo, int device)
2202{ 2096{
2203 struct drm_encoder *encoder = &intel_encoder->enc; 2097 struct drm_encoder *encoder = &intel_sdvo->base.enc;
2204 struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv;
2205 struct drm_connector *connector; 2098 struct drm_connector *connector;
2206 struct intel_connector *intel_connector; 2099 struct intel_connector *intel_connector;
2207 struct intel_sdvo_connector *sdvo_connector; 2100 struct intel_sdvo_connector *intel_sdvo_connector;
2208 2101
2209 if (!intel_sdvo_connector_alloc(&intel_connector)) 2102 intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL);
2103 if (!intel_sdvo_connector)
2210 return false; 2104 return false;
2211 2105
2212 sdvo_connector = intel_connector->dev_priv;
2213
2214 if (device == 0) { 2106 if (device == 0) {
2215 sdvo_priv->controlled_output |= SDVO_OUTPUT_TMDS0; 2107 intel_sdvo->controlled_output |= SDVO_OUTPUT_TMDS0;
2216 sdvo_connector->output_flag = SDVO_OUTPUT_TMDS0; 2108 intel_sdvo_connector->output_flag = SDVO_OUTPUT_TMDS0;
2217 } else if (device == 1) { 2109 } else if (device == 1) {
2218 sdvo_priv->controlled_output |= SDVO_OUTPUT_TMDS1; 2110 intel_sdvo->controlled_output |= SDVO_OUTPUT_TMDS1;
2219 sdvo_connector->output_flag = SDVO_OUTPUT_TMDS1; 2111 intel_sdvo_connector->output_flag = SDVO_OUTPUT_TMDS1;
2220 } 2112 }
2221 2113
2114 intel_connector = &intel_sdvo_connector->base;
2222 connector = &intel_connector->base; 2115 connector = &intel_connector->base;
2223 connector->polled = DRM_CONNECTOR_POLL_CONNECT | DRM_CONNECTOR_POLL_DISCONNECT; 2116 connector->polled = DRM_CONNECTOR_POLL_CONNECT | DRM_CONNECTOR_POLL_DISCONNECT;
2224 encoder->encoder_type = DRM_MODE_ENCODER_TMDS; 2117 encoder->encoder_type = DRM_MODE_ENCODER_TMDS;
2225 connector->connector_type = DRM_MODE_CONNECTOR_DVID; 2118 connector->connector_type = DRM_MODE_CONNECTOR_DVID;
2226 2119
2227 if (intel_sdvo_get_supp_encode(intel_encoder, &sdvo_priv->encode) 2120 if (intel_sdvo_get_supp_encode(intel_sdvo, &intel_sdvo->encode)
2228 && intel_sdvo_get_digital_encoding_mode(intel_encoder, device) 2121 && intel_sdvo_get_digital_encoding_mode(intel_sdvo, device)
2229 && sdvo_priv->is_hdmi) { 2122 && intel_sdvo->is_hdmi) {
2230 /* enable hdmi encoding mode if supported */ 2123 /* enable hdmi encoding mode if supported */
2231 intel_sdvo_set_encode(intel_encoder, SDVO_ENCODE_HDMI); 2124 intel_sdvo_set_encode(intel_sdvo, SDVO_ENCODE_HDMI);
2232 intel_sdvo_set_colorimetry(intel_encoder, 2125 intel_sdvo_set_colorimetry(intel_sdvo,
2233 SDVO_COLORIMETRY_RGB256); 2126 SDVO_COLORIMETRY_RGB256);
2234 connector->connector_type = DRM_MODE_CONNECTOR_HDMIA; 2127 connector->connector_type = DRM_MODE_CONNECTOR_HDMIA;
2235 } 2128 }
2236 intel_encoder->clone_mask = (1 << INTEL_SDVO_NON_TV_CLONE_BIT) | 2129 intel_sdvo->base.clone_mask = ((1 << INTEL_SDVO_NON_TV_CLONE_BIT) |
2237 (1 << INTEL_ANALOG_CLONE_BIT); 2130 (1 << INTEL_ANALOG_CLONE_BIT));
2238 2131
2239 intel_sdvo_connector_create(encoder, connector); 2132 intel_sdvo_connector_init(encoder, connector);
2240 2133
2241 return true; 2134 return true;
2242} 2135}
2243 2136
2244static bool 2137static bool
2245intel_sdvo_tv_init(struct intel_encoder *intel_encoder, int type) 2138intel_sdvo_tv_init(struct intel_sdvo *intel_sdvo, int type)
2246{ 2139{
2247 struct drm_encoder *encoder = &intel_encoder->enc; 2140 struct drm_encoder *encoder = &intel_sdvo->base.enc;
2248 struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv;
2249 struct drm_connector *connector; 2141 struct drm_connector *connector;
2250 struct intel_connector *intel_connector; 2142 struct intel_connector *intel_connector;
2251 struct intel_sdvo_connector *sdvo_connector; 2143 struct intel_sdvo_connector *intel_sdvo_connector;
2252 2144
2253 if (!intel_sdvo_connector_alloc(&intel_connector)) 2145 intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL);
2254 return false; 2146 if (!intel_sdvo_connector)
2147 return false;
2255 2148
2149 intel_connector = &intel_sdvo_connector->base;
2256 connector = &intel_connector->base; 2150 connector = &intel_connector->base;
2257 encoder->encoder_type = DRM_MODE_ENCODER_TVDAC; 2151 encoder->encoder_type = DRM_MODE_ENCODER_TVDAC;
2258 connector->connector_type = DRM_MODE_CONNECTOR_SVIDEO; 2152 connector->connector_type = DRM_MODE_CONNECTOR_SVIDEO;
2259 sdvo_connector = intel_connector->dev_priv;
2260 2153
2261 sdvo_priv->controlled_output |= type; 2154 intel_sdvo->controlled_output |= type;
2262 sdvo_connector->output_flag = type; 2155 intel_sdvo_connector->output_flag = type;
2263 2156
2264 sdvo_priv->is_tv = true; 2157 intel_sdvo->is_tv = true;
2265 intel_encoder->needs_tv_clock = true; 2158 intel_sdvo->base.needs_tv_clock = true;
2266 intel_encoder->clone_mask = 1 << INTEL_SDVO_TV_CLONE_BIT; 2159 intel_sdvo->base.clone_mask = 1 << INTEL_SDVO_TV_CLONE_BIT;
2267 2160
2268 intel_sdvo_connector_create(encoder, connector); 2161 intel_sdvo_connector_init(encoder, connector);
2269 2162
2270 intel_sdvo_tv_create_property(connector, type); 2163 if (!intel_sdvo_tv_create_property(intel_sdvo, intel_sdvo_connector, type))
2164 goto err;
2271 2165
2272 intel_sdvo_create_enhance_property(connector); 2166 if (!intel_sdvo_create_enhance_property(intel_sdvo, intel_sdvo_connector))
2167 goto err;
2273 2168
2274 return true; 2169 return true;
2170
2171err:
2172 intel_sdvo_destroy_enhance_property(connector);
2173 kfree(intel_sdvo_connector);
2174 return false;
2275} 2175}
2276 2176
2277static bool 2177static bool
2278intel_sdvo_analog_init(struct intel_encoder *intel_encoder, int device) 2178intel_sdvo_analog_init(struct intel_sdvo *intel_sdvo, int device)
2279{ 2179{
2280 struct drm_encoder *encoder = &intel_encoder->enc; 2180 struct drm_encoder *encoder = &intel_sdvo->base.enc;
2281 struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv;
2282 struct drm_connector *connector; 2181 struct drm_connector *connector;
2283 struct intel_connector *intel_connector; 2182 struct intel_connector *intel_connector;
2284 struct intel_sdvo_connector *sdvo_connector; 2183 struct intel_sdvo_connector *intel_sdvo_connector;
2285 2184
2286 if (!intel_sdvo_connector_alloc(&intel_connector)) 2185 intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL);
2287 return false; 2186 if (!intel_sdvo_connector)
2187 return false;
2288 2188
2189 intel_connector = &intel_sdvo_connector->base;
2289 connector = &intel_connector->base; 2190 connector = &intel_connector->base;
2290 connector->polled = DRM_CONNECTOR_POLL_CONNECT; 2191 connector->polled = DRM_CONNECTOR_POLL_CONNECT;
2291 encoder->encoder_type = DRM_MODE_ENCODER_DAC; 2192 encoder->encoder_type = DRM_MODE_ENCODER_DAC;
2292 connector->connector_type = DRM_MODE_CONNECTOR_VGA; 2193 connector->connector_type = DRM_MODE_CONNECTOR_VGA;
2293 sdvo_connector = intel_connector->dev_priv;
2294 2194
2295 if (device == 0) { 2195 if (device == 0) {
2296 sdvo_priv->controlled_output |= SDVO_OUTPUT_RGB0; 2196 intel_sdvo->controlled_output |= SDVO_OUTPUT_RGB0;
2297 sdvo_connector->output_flag = SDVO_OUTPUT_RGB0; 2197 intel_sdvo_connector->output_flag = SDVO_OUTPUT_RGB0;
2298 } else if (device == 1) { 2198 } else if (device == 1) {
2299 sdvo_priv->controlled_output |= SDVO_OUTPUT_RGB1; 2199 intel_sdvo->controlled_output |= SDVO_OUTPUT_RGB1;
2300 sdvo_connector->output_flag = SDVO_OUTPUT_RGB1; 2200 intel_sdvo_connector->output_flag = SDVO_OUTPUT_RGB1;
2301 } 2201 }
2302 2202
2303 intel_encoder->clone_mask = (1 << INTEL_SDVO_NON_TV_CLONE_BIT) | 2203 intel_sdvo->base.clone_mask = ((1 << INTEL_SDVO_NON_TV_CLONE_BIT) |
2304 (1 << INTEL_ANALOG_CLONE_BIT); 2204 (1 << INTEL_ANALOG_CLONE_BIT));
2305 2205
2306 intel_sdvo_connector_create(encoder, connector); 2206 intel_sdvo_connector_init(encoder, connector);
2307 return true; 2207 return true;
2308} 2208}
2309 2209
2310static bool 2210static bool
2311intel_sdvo_lvds_init(struct intel_encoder *intel_encoder, int device) 2211intel_sdvo_lvds_init(struct intel_sdvo *intel_sdvo, int device)
2312{ 2212{
2313 struct drm_encoder *encoder = &intel_encoder->enc; 2213 struct drm_encoder *encoder = &intel_sdvo->base.enc;
2314 struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv;
2315 struct drm_connector *connector; 2214 struct drm_connector *connector;
2316 struct intel_connector *intel_connector; 2215 struct intel_connector *intel_connector;
2317 struct intel_sdvo_connector *sdvo_connector; 2216 struct intel_sdvo_connector *intel_sdvo_connector;
2318 2217
2319 if (!intel_sdvo_connector_alloc(&intel_connector)) 2218 intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL);
2320 return false; 2219 if (!intel_sdvo_connector)
2220 return false;
2321 2221
2322 connector = &intel_connector->base; 2222 intel_connector = &intel_sdvo_connector->base;
2223 connector = &intel_connector->base;
2323 encoder->encoder_type = DRM_MODE_ENCODER_LVDS; 2224 encoder->encoder_type = DRM_MODE_ENCODER_LVDS;
2324 connector->connector_type = DRM_MODE_CONNECTOR_LVDS; 2225 connector->connector_type = DRM_MODE_CONNECTOR_LVDS;
2325 sdvo_connector = intel_connector->dev_priv;
2326
2327 sdvo_priv->is_lvds = true;
2328 2226
2329 if (device == 0) { 2227 if (device == 0) {
2330 sdvo_priv->controlled_output |= SDVO_OUTPUT_LVDS0; 2228 intel_sdvo->controlled_output |= SDVO_OUTPUT_LVDS0;
2331 sdvo_connector->output_flag = SDVO_OUTPUT_LVDS0; 2229 intel_sdvo_connector->output_flag = SDVO_OUTPUT_LVDS0;
2332 } else if (device == 1) { 2230 } else if (device == 1) {
2333 sdvo_priv->controlled_output |= SDVO_OUTPUT_LVDS1; 2231 intel_sdvo->controlled_output |= SDVO_OUTPUT_LVDS1;
2334 sdvo_connector->output_flag = SDVO_OUTPUT_LVDS1; 2232 intel_sdvo_connector->output_flag = SDVO_OUTPUT_LVDS1;
2335 } 2233 }
2336 2234
2337 intel_encoder->clone_mask = (1 << INTEL_ANALOG_CLONE_BIT) | 2235 intel_sdvo->base.clone_mask = ((1 << INTEL_ANALOG_CLONE_BIT) |
2338 (1 << INTEL_SDVO_LVDS_CLONE_BIT); 2236 (1 << INTEL_SDVO_LVDS_CLONE_BIT));
2339 2237
2340 intel_sdvo_connector_create(encoder, connector); 2238 intel_sdvo_connector_init(encoder, connector);
2341 intel_sdvo_create_enhance_property(connector); 2239 if (!intel_sdvo_create_enhance_property(intel_sdvo, intel_sdvo_connector))
2342 return true; 2240 goto err;
2241
2242 return true;
2243
2244err:
2245 intel_sdvo_destroy_enhance_property(connector);
2246 kfree(intel_sdvo_connector);
2247 return false;
2343} 2248}
2344 2249
2345static bool 2250static bool
2346intel_sdvo_output_setup(struct intel_encoder *intel_encoder, uint16_t flags) 2251intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo, uint16_t flags)
2347{ 2252{
2348 struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv; 2253 intel_sdvo->is_tv = false;
2349 2254 intel_sdvo->base.needs_tv_clock = false;
2350 sdvo_priv->is_tv = false; 2255 intel_sdvo->is_lvds = false;
2351 intel_encoder->needs_tv_clock = false;
2352 sdvo_priv->is_lvds = false;
2353 2256
2354 /* SDVO requires XXX1 function may not exist unless it has XXX0 function.*/ 2257 /* SDVO requires XXX1 function may not exist unless it has XXX0 function.*/
2355 2258
2356 if (flags & SDVO_OUTPUT_TMDS0) 2259 if (flags & SDVO_OUTPUT_TMDS0)
2357 if (!intel_sdvo_dvi_init(intel_encoder, 0)) 2260 if (!intel_sdvo_dvi_init(intel_sdvo, 0))
2358 return false; 2261 return false;
2359 2262
2360 if ((flags & SDVO_TMDS_MASK) == SDVO_TMDS_MASK) 2263 if ((flags & SDVO_TMDS_MASK) == SDVO_TMDS_MASK)
2361 if (!intel_sdvo_dvi_init(intel_encoder, 1)) 2264 if (!intel_sdvo_dvi_init(intel_sdvo, 1))
2362 return false; 2265 return false;
2363 2266
2364 /* TV has no XXX1 function block */ 2267 /* TV has no XXX1 function block */
2365 if (flags & SDVO_OUTPUT_SVID0) 2268 if (flags & SDVO_OUTPUT_SVID0)
2366 if (!intel_sdvo_tv_init(intel_encoder, SDVO_OUTPUT_SVID0)) 2269 if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_SVID0))
2367 return false; 2270 return false;
2368 2271
2369 if (flags & SDVO_OUTPUT_CVBS0) 2272 if (flags & SDVO_OUTPUT_CVBS0)
2370 if (!intel_sdvo_tv_init(intel_encoder, SDVO_OUTPUT_CVBS0)) 2273 if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_CVBS0))
2371 return false; 2274 return false;
2372 2275
2373 if (flags & SDVO_OUTPUT_RGB0) 2276 if (flags & SDVO_OUTPUT_RGB0)
2374 if (!intel_sdvo_analog_init(intel_encoder, 0)) 2277 if (!intel_sdvo_analog_init(intel_sdvo, 0))
2375 return false; 2278 return false;
2376 2279
2377 if ((flags & SDVO_RGB_MASK) == SDVO_RGB_MASK) 2280 if ((flags & SDVO_RGB_MASK) == SDVO_RGB_MASK)
2378 if (!intel_sdvo_analog_init(intel_encoder, 1)) 2281 if (!intel_sdvo_analog_init(intel_sdvo, 1))
2379 return false; 2282 return false;
2380 2283
2381 if (flags & SDVO_OUTPUT_LVDS0) 2284 if (flags & SDVO_OUTPUT_LVDS0)
2382 if (!intel_sdvo_lvds_init(intel_encoder, 0)) 2285 if (!intel_sdvo_lvds_init(intel_sdvo, 0))
2383 return false; 2286 return false;
2384 2287
2385 if ((flags & SDVO_LVDS_MASK) == SDVO_LVDS_MASK) 2288 if ((flags & SDVO_LVDS_MASK) == SDVO_LVDS_MASK)
2386 if (!intel_sdvo_lvds_init(intel_encoder, 1)) 2289 if (!intel_sdvo_lvds_init(intel_sdvo, 1))
2387 return false; 2290 return false;
2388 2291
2389 if ((flags & SDVO_OUTPUT_MASK) == 0) { 2292 if ((flags & SDVO_OUTPUT_MASK) == 0) {
2390 unsigned char bytes[2]; 2293 unsigned char bytes[2];
2391 2294
2392 sdvo_priv->controlled_output = 0; 2295 intel_sdvo->controlled_output = 0;
2393 memcpy(bytes, &sdvo_priv->caps.output_flags, 2); 2296 memcpy(bytes, &intel_sdvo->caps.output_flags, 2);
2394 DRM_DEBUG_KMS("%s: Unknown SDVO output type (0x%02x%02x)\n", 2297 DRM_DEBUG_KMS("%s: Unknown SDVO output type (0x%02x%02x)\n",
2395 SDVO_NAME(sdvo_priv), 2298 SDVO_NAME(intel_sdvo),
2396 bytes[0], bytes[1]); 2299 bytes[0], bytes[1]);
2397 return false; 2300 return false;
2398 } 2301 }
2399 intel_encoder->crtc_mask = (1 << 0) | (1 << 1); 2302 intel_sdvo->base.crtc_mask = (1 << 0) | (1 << 1);
2400 2303
2401 return true; 2304 return true;
2402} 2305}
2403 2306
2404static void intel_sdvo_tv_create_property(struct drm_connector *connector, int type) 2307static bool intel_sdvo_tv_create_property(struct intel_sdvo *intel_sdvo,
2308 struct intel_sdvo_connector *intel_sdvo_connector,
2309 int type)
2405{ 2310{
2406 struct drm_encoder *encoder = intel_attached_encoder(connector); 2311 struct drm_device *dev = intel_sdvo->base.enc.dev;
2407 struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
2408 struct intel_sdvo_priv *sdvo_priv = intel_encoder->dev_priv;
2409 struct intel_connector *intel_connector = to_intel_connector(connector);
2410 struct intel_sdvo_connector *sdvo_connector = intel_connector->dev_priv;
2411 struct intel_sdvo_tv_format format; 2312 struct intel_sdvo_tv_format format;
2412 uint32_t format_map, i; 2313 uint32_t format_map, i;
2413 uint8_t status;
2414 2314
2415 intel_sdvo_set_target_output(intel_encoder, type); 2315 if (!intel_sdvo_set_target_output(intel_sdvo, type))
2316 return false;
2416 2317
2417 intel_sdvo_write_cmd(intel_encoder, 2318 if (!intel_sdvo_get_value(intel_sdvo,
2418 SDVO_CMD_GET_SUPPORTED_TV_FORMATS, NULL, 0); 2319 SDVO_CMD_GET_SUPPORTED_TV_FORMATS,
2419 status = intel_sdvo_read_response(intel_encoder, 2320 &format, sizeof(format)))
2420 &format, sizeof(format)); 2321 return false;
2421 if (status != SDVO_CMD_STATUS_SUCCESS)
2422 return;
2423 2322
2424 memcpy(&format_map, &format, sizeof(format) > sizeof(format_map) ? 2323 memcpy(&format_map, &format, min(sizeof(format_map), sizeof(format)));
2425 sizeof(format_map) : sizeof(format));
2426 2324
2427 if (format_map == 0) 2325 if (format_map == 0)
2428 return; 2326 return false;
2429 2327
2430 sdvo_connector->format_supported_num = 0; 2328 intel_sdvo_connector->format_supported_num = 0;
2431 for (i = 0 ; i < TV_FORMAT_NUM; i++) 2329 for (i = 0 ; i < TV_FORMAT_NUM; i++)
2432 if (format_map & (1 << i)) { 2330 if (format_map & (1 << i))
2433 sdvo_connector->tv_format_supported 2331 intel_sdvo_connector->tv_format_supported[intel_sdvo_connector->format_supported_num++] = i;
2434 [sdvo_connector->format_supported_num++] =
2435 tv_format_names[i];
2436 }
2437 2332
2438 2333
2439 sdvo_connector->tv_format_property = 2334 intel_sdvo_connector->tv_format =
2440 drm_property_create( 2335 drm_property_create(dev, DRM_MODE_PROP_ENUM,
2441 connector->dev, DRM_MODE_PROP_ENUM, 2336 "mode", intel_sdvo_connector->format_supported_num);
2442 "mode", sdvo_connector->format_supported_num); 2337 if (!intel_sdvo_connector->tv_format)
2338 return false;
2443 2339
2444 for (i = 0; i < sdvo_connector->format_supported_num; i++) 2340 for (i = 0; i < intel_sdvo_connector->format_supported_num; i++)
2445 drm_property_add_enum( 2341 drm_property_add_enum(
2446 sdvo_connector->tv_format_property, i, 2342 intel_sdvo_connector->tv_format, i,
2447 i, sdvo_connector->tv_format_supported[i]); 2343 i, tv_format_names[intel_sdvo_connector->tv_format_supported[i]]);
2448 2344
2449 sdvo_priv->tv_format_name = sdvo_connector->tv_format_supported[0]; 2345 intel_sdvo->tv_format_index = intel_sdvo_connector->tv_format_supported[0];
2450 drm_connector_attach_property( 2346 drm_connector_attach_property(&intel_sdvo_connector->base.base,
2451 connector, sdvo_connector->tv_format_property, 0); 2347 intel_sdvo_connector->tv_format, 0);
2348 return true;
2452 2349
2453} 2350}
2454 2351
2455static void intel_sdvo_create_enhance_property(struct drm_connector *connector) 2352#define ENHANCEMENT(name, NAME) do { \
2353 if (enhancements.name) { \
2354 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_MAX_##NAME, &data_value, 4) || \
2355 !intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_##NAME, &response, 2)) \
2356 return false; \
2357 intel_sdvo_connector->max_##name = data_value[0]; \
2358 intel_sdvo_connector->cur_##name = response; \
2359 intel_sdvo_connector->name = \
2360 drm_property_create(dev, DRM_MODE_PROP_RANGE, #name, 2); \
2361 if (!intel_sdvo_connector->name) return false; \
2362 intel_sdvo_connector->name->values[0] = 0; \
2363 intel_sdvo_connector->name->values[1] = data_value[0]; \
2364 drm_connector_attach_property(connector, \
2365 intel_sdvo_connector->name, \
2366 intel_sdvo_connector->cur_##name); \
2367 DRM_DEBUG_KMS(#name ": max %d, default %d, current %d\n", \
2368 data_value[0], data_value[1], response); \
2369 } \
2370} while(0)
2371
2372static bool
2373intel_sdvo_create_enhance_property_tv(struct intel_sdvo *intel_sdvo,
2374 struct intel_sdvo_connector *intel_sdvo_connector,
2375 struct intel_sdvo_enhancements_reply enhancements)
2456{ 2376{
2457 struct drm_encoder *encoder = intel_attached_encoder(connector); 2377 struct drm_device *dev = intel_sdvo->base.enc.dev;
2458 struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder); 2378 struct drm_connector *connector = &intel_sdvo_connector->base.base;
2459 struct intel_connector *intel_connector = to_intel_connector(connector);
2460 struct intel_sdvo_connector *sdvo_priv = intel_connector->dev_priv;
2461 struct intel_sdvo_enhancements_reply sdvo_data;
2462 struct drm_device *dev = connector->dev;
2463 uint8_t status;
2464 uint16_t response, data_value[2]; 2379 uint16_t response, data_value[2];
2465 2380
2466 intel_sdvo_write_cmd(intel_encoder, SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS, 2381 /* when horizontal overscan is supported, Add the left/right property */
2467 NULL, 0); 2382 if (enhancements.overscan_h) {
2468 status = intel_sdvo_read_response(intel_encoder, &sdvo_data, 2383 if (!intel_sdvo_get_value(intel_sdvo,
2469 sizeof(sdvo_data)); 2384 SDVO_CMD_GET_MAX_OVERSCAN_H,
2470 if (status != SDVO_CMD_STATUS_SUCCESS) { 2385 &data_value, 4))
2471 DRM_DEBUG_KMS(" incorrect response is returned\n"); 2386 return false;
2472 return; 2387
2388 if (!intel_sdvo_get_value(intel_sdvo,
2389 SDVO_CMD_GET_OVERSCAN_H,
2390 &response, 2))
2391 return false;
2392
2393 intel_sdvo_connector->max_hscan = data_value[0];
2394 intel_sdvo_connector->left_margin = data_value[0] - response;
2395 intel_sdvo_connector->right_margin = intel_sdvo_connector->left_margin;
2396 intel_sdvo_connector->left =
2397 drm_property_create(dev, DRM_MODE_PROP_RANGE,
2398 "left_margin", 2);
2399 if (!intel_sdvo_connector->left)
2400 return false;
2401
2402 intel_sdvo_connector->left->values[0] = 0;
2403 intel_sdvo_connector->left->values[1] = data_value[0];
2404 drm_connector_attach_property(connector,
2405 intel_sdvo_connector->left,
2406 intel_sdvo_connector->left_margin);
2407
2408 intel_sdvo_connector->right =
2409 drm_property_create(dev, DRM_MODE_PROP_RANGE,
2410 "right_margin", 2);
2411 if (!intel_sdvo_connector->right)
2412 return false;
2413
2414 intel_sdvo_connector->right->values[0] = 0;
2415 intel_sdvo_connector->right->values[1] = data_value[0];
2416 drm_connector_attach_property(connector,
2417 intel_sdvo_connector->right,
2418 intel_sdvo_connector->right_margin);
2419 DRM_DEBUG_KMS("h_overscan: max %d, "
2420 "default %d, current %d\n",
2421 data_value[0], data_value[1], response);
2473 } 2422 }
2474 response = *((uint16_t *)&sdvo_data); 2423
2475 if (!response) { 2424 if (enhancements.overscan_v) {
2476 DRM_DEBUG_KMS("No enhancement is supported\n"); 2425 if (!intel_sdvo_get_value(intel_sdvo,
2477 return; 2426 SDVO_CMD_GET_MAX_OVERSCAN_V,
2427 &data_value, 4))
2428 return false;
2429
2430 if (!intel_sdvo_get_value(intel_sdvo,
2431 SDVO_CMD_GET_OVERSCAN_V,
2432 &response, 2))
2433 return false;
2434
2435 intel_sdvo_connector->max_vscan = data_value[0];
2436 intel_sdvo_connector->top_margin = data_value[0] - response;
2437 intel_sdvo_connector->bottom_margin = intel_sdvo_connector->top_margin;
2438 intel_sdvo_connector->top =
2439 drm_property_create(dev, DRM_MODE_PROP_RANGE,
2440 "top_margin", 2);
2441 if (!intel_sdvo_connector->top)
2442 return false;
2443
2444 intel_sdvo_connector->top->values[0] = 0;
2445 intel_sdvo_connector->top->values[1] = data_value[0];
2446 drm_connector_attach_property(connector,
2447 intel_sdvo_connector->top,
2448 intel_sdvo_connector->top_margin);
2449
2450 intel_sdvo_connector->bottom =
2451 drm_property_create(dev, DRM_MODE_PROP_RANGE,
2452 "bottom_margin", 2);
2453 if (!intel_sdvo_connector->bottom)
2454 return false;
2455
2456 intel_sdvo_connector->bottom->values[0] = 0;
2457 intel_sdvo_connector->bottom->values[1] = data_value[0];
2458 drm_connector_attach_property(connector,
2459 intel_sdvo_connector->bottom,
2460 intel_sdvo_connector->bottom_margin);
2461 DRM_DEBUG_KMS("v_overscan: max %d, "
2462 "default %d, current %d\n",
2463 data_value[0], data_value[1], response);
2478 } 2464 }
2479 if (IS_TV(sdvo_priv)) { 2465
2480 /* when horizontal overscan is supported, Add the left/right 2466 ENHANCEMENT(hpos, HPOS);
2481 * property 2467 ENHANCEMENT(vpos, VPOS);
2482 */ 2468 ENHANCEMENT(saturation, SATURATION);
2483 if (sdvo_data.overscan_h) { 2469 ENHANCEMENT(contrast, CONTRAST);
2484 intel_sdvo_write_cmd(intel_encoder, 2470 ENHANCEMENT(hue, HUE);
2485 SDVO_CMD_GET_MAX_OVERSCAN_H, NULL, 0); 2471 ENHANCEMENT(sharpness, SHARPNESS);
2486 status = intel_sdvo_read_response(intel_encoder, 2472 ENHANCEMENT(brightness, BRIGHTNESS);
2487 &data_value, 4); 2473 ENHANCEMENT(flicker_filter, FLICKER_FILTER);
2488 if (status != SDVO_CMD_STATUS_SUCCESS) { 2474 ENHANCEMENT(flicker_filter_adaptive, FLICKER_FILTER_ADAPTIVE);
2489 DRM_DEBUG_KMS("Incorrect SDVO max " 2475 ENHANCEMENT(flicker_filter_2d, FLICKER_FILTER_2D);
2490 "h_overscan\n"); 2476 ENHANCEMENT(tv_chroma_filter, TV_CHROMA_FILTER);
2491 return; 2477 ENHANCEMENT(tv_luma_filter, TV_LUMA_FILTER);
2492 } 2478
2493 intel_sdvo_write_cmd(intel_encoder, 2479 if (enhancements.dot_crawl) {
2494 SDVO_CMD_GET_OVERSCAN_H, NULL, 0); 2480 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_DOT_CRAWL, &response, 2))
2495 status = intel_sdvo_read_response(intel_encoder, 2481 return false;
2496 &response, 2); 2482
2497 if (status != SDVO_CMD_STATUS_SUCCESS) { 2483 intel_sdvo_connector->max_dot_crawl = 1;
2498 DRM_DEBUG_KMS("Incorrect SDVO h_overscan\n"); 2484 intel_sdvo_connector->cur_dot_crawl = response & 0x1;
2499 return; 2485 intel_sdvo_connector->dot_crawl =
2500 } 2486 drm_property_create(dev, DRM_MODE_PROP_RANGE, "dot_crawl", 2);
2501 sdvo_priv->max_hscan = data_value[0]; 2487 if (!intel_sdvo_connector->dot_crawl)
2502 sdvo_priv->left_margin = data_value[0] - response; 2488 return false;
2503 sdvo_priv->right_margin = sdvo_priv->left_margin; 2489
2504 sdvo_priv->left_property = 2490 intel_sdvo_connector->dot_crawl->values[0] = 0;
2505 drm_property_create(dev, DRM_MODE_PROP_RANGE, 2491 intel_sdvo_connector->dot_crawl->values[1] = 1;
2506 "left_margin", 2); 2492 drm_connector_attach_property(connector,
2507 sdvo_priv->left_property->values[0] = 0; 2493 intel_sdvo_connector->dot_crawl,
2508 sdvo_priv->left_property->values[1] = data_value[0]; 2494 intel_sdvo_connector->cur_dot_crawl);
2509 drm_connector_attach_property(connector, 2495 DRM_DEBUG_KMS("dot crawl: current %d\n", response);
2510 sdvo_priv->left_property,
2511 sdvo_priv->left_margin);
2512 sdvo_priv->right_property =
2513 drm_property_create(dev, DRM_MODE_PROP_RANGE,
2514 "right_margin", 2);
2515 sdvo_priv->right_property->values[0] = 0;
2516 sdvo_priv->right_property->values[1] = data_value[0];
2517 drm_connector_attach_property(connector,
2518 sdvo_priv->right_property,
2519 sdvo_priv->right_margin);
2520 DRM_DEBUG_KMS("h_overscan: max %d, "
2521 "default %d, current %d\n",
2522 data_value[0], data_value[1], response);
2523 }
2524 if (sdvo_data.overscan_v) {
2525 intel_sdvo_write_cmd(intel_encoder,
2526 SDVO_CMD_GET_MAX_OVERSCAN_V, NULL, 0);
2527 status = intel_sdvo_read_response(intel_encoder,
2528 &data_value, 4);
2529 if (status != SDVO_CMD_STATUS_SUCCESS) {
2530 DRM_DEBUG_KMS("Incorrect SDVO max "
2531 "v_overscan\n");
2532 return;
2533 }
2534 intel_sdvo_write_cmd(intel_encoder,
2535 SDVO_CMD_GET_OVERSCAN_V, NULL, 0);
2536 status = intel_sdvo_read_response(intel_encoder,
2537 &response, 2);
2538 if (status != SDVO_CMD_STATUS_SUCCESS) {
2539 DRM_DEBUG_KMS("Incorrect SDVO v_overscan\n");
2540 return;
2541 }
2542 sdvo_priv->max_vscan = data_value[0];
2543 sdvo_priv->top_margin = data_value[0] - response;
2544 sdvo_priv->bottom_margin = sdvo_priv->top_margin;
2545 sdvo_priv->top_property =
2546 drm_property_create(dev, DRM_MODE_PROP_RANGE,
2547 "top_margin", 2);
2548 sdvo_priv->top_property->values[0] = 0;
2549 sdvo_priv->top_property->values[1] = data_value[0];
2550 drm_connector_attach_property(connector,
2551 sdvo_priv->top_property,
2552 sdvo_priv->top_margin);
2553 sdvo_priv->bottom_property =
2554 drm_property_create(dev, DRM_MODE_PROP_RANGE,
2555 "bottom_margin", 2);
2556 sdvo_priv->bottom_property->values[0] = 0;
2557 sdvo_priv->bottom_property->values[1] = data_value[0];
2558 drm_connector_attach_property(connector,
2559 sdvo_priv->bottom_property,
2560 sdvo_priv->bottom_margin);
2561 DRM_DEBUG_KMS("v_overscan: max %d, "
2562 "default %d, current %d\n",
2563 data_value[0], data_value[1], response);
2564 }
2565 if (sdvo_data.position_h) {
2566 intel_sdvo_write_cmd(intel_encoder,
2567 SDVO_CMD_GET_MAX_POSITION_H, NULL, 0);
2568 status = intel_sdvo_read_response(intel_encoder,
2569 &data_value, 4);
2570 if (status != SDVO_CMD_STATUS_SUCCESS) {
2571 DRM_DEBUG_KMS("Incorrect SDVO Max h_pos\n");
2572 return;
2573 }
2574 intel_sdvo_write_cmd(intel_encoder,
2575 SDVO_CMD_GET_POSITION_H, NULL, 0);
2576 status = intel_sdvo_read_response(intel_encoder,
2577 &response, 2);
2578 if (status != SDVO_CMD_STATUS_SUCCESS) {
2579 DRM_DEBUG_KMS("Incorrect SDVO get h_postion\n");
2580 return;
2581 }
2582 sdvo_priv->max_hpos = data_value[0];
2583 sdvo_priv->cur_hpos = response;
2584 sdvo_priv->hpos_property =
2585 drm_property_create(dev, DRM_MODE_PROP_RANGE,
2586 "hpos", 2);
2587 sdvo_priv->hpos_property->values[0] = 0;
2588 sdvo_priv->hpos_property->values[1] = data_value[0];
2589 drm_connector_attach_property(connector,
2590 sdvo_priv->hpos_property,
2591 sdvo_priv->cur_hpos);
2592 DRM_DEBUG_KMS("h_position: max %d, "
2593 "default %d, current %d\n",
2594 data_value[0], data_value[1], response);
2595 }
2596 if (sdvo_data.position_v) {
2597 intel_sdvo_write_cmd(intel_encoder,
2598 SDVO_CMD_GET_MAX_POSITION_V, NULL, 0);
2599 status = intel_sdvo_read_response(intel_encoder,
2600 &data_value, 4);
2601 if (status != SDVO_CMD_STATUS_SUCCESS) {
2602 DRM_DEBUG_KMS("Incorrect SDVO Max v_pos\n");
2603 return;
2604 }
2605 intel_sdvo_write_cmd(intel_encoder,
2606 SDVO_CMD_GET_POSITION_V, NULL, 0);
2607 status = intel_sdvo_read_response(intel_encoder,
2608 &response, 2);
2609 if (status != SDVO_CMD_STATUS_SUCCESS) {
2610 DRM_DEBUG_KMS("Incorrect SDVO get v_postion\n");
2611 return;
2612 }
2613 sdvo_priv->max_vpos = data_value[0];
2614 sdvo_priv->cur_vpos = response;
2615 sdvo_priv->vpos_property =
2616 drm_property_create(dev, DRM_MODE_PROP_RANGE,
2617 "vpos", 2);
2618 sdvo_priv->vpos_property->values[0] = 0;
2619 sdvo_priv->vpos_property->values[1] = data_value[0];
2620 drm_connector_attach_property(connector,
2621 sdvo_priv->vpos_property,
2622 sdvo_priv->cur_vpos);
2623 DRM_DEBUG_KMS("v_position: max %d, "
2624 "default %d, current %d\n",
2625 data_value[0], data_value[1], response);
2626 }
2627 if (sdvo_data.saturation) {
2628 intel_sdvo_write_cmd(intel_encoder,
2629 SDVO_CMD_GET_MAX_SATURATION, NULL, 0);
2630 status = intel_sdvo_read_response(intel_encoder,
2631 &data_value, 4);
2632 if (status != SDVO_CMD_STATUS_SUCCESS) {
2633 DRM_DEBUG_KMS("Incorrect SDVO Max sat\n");
2634 return;
2635 }
2636 intel_sdvo_write_cmd(intel_encoder,
2637 SDVO_CMD_GET_SATURATION, NULL, 0);
2638 status = intel_sdvo_read_response(intel_encoder,
2639 &response, 2);
2640 if (status != SDVO_CMD_STATUS_SUCCESS) {
2641 DRM_DEBUG_KMS("Incorrect SDVO get sat\n");
2642 return;
2643 }
2644 sdvo_priv->max_saturation = data_value[0];
2645 sdvo_priv->cur_saturation = response;
2646 sdvo_priv->saturation_property =
2647 drm_property_create(dev, DRM_MODE_PROP_RANGE,
2648 "saturation", 2);
2649 sdvo_priv->saturation_property->values[0] = 0;
2650 sdvo_priv->saturation_property->values[1] =
2651 data_value[0];
2652 drm_connector_attach_property(connector,
2653 sdvo_priv->saturation_property,
2654 sdvo_priv->cur_saturation);
2655 DRM_DEBUG_KMS("saturation: max %d, "
2656 "default %d, current %d\n",
2657 data_value[0], data_value[1], response);
2658 }
2659 if (sdvo_data.contrast) {
2660 intel_sdvo_write_cmd(intel_encoder,
2661 SDVO_CMD_GET_MAX_CONTRAST, NULL, 0);
2662 status = intel_sdvo_read_response(intel_encoder,
2663 &data_value, 4);
2664 if (status != SDVO_CMD_STATUS_SUCCESS) {
2665 DRM_DEBUG_KMS("Incorrect SDVO Max contrast\n");
2666 return;
2667 }
2668 intel_sdvo_write_cmd(intel_encoder,
2669 SDVO_CMD_GET_CONTRAST, NULL, 0);
2670 status = intel_sdvo_read_response(intel_encoder,
2671 &response, 2);
2672 if (status != SDVO_CMD_STATUS_SUCCESS) {
2673 DRM_DEBUG_KMS("Incorrect SDVO get contrast\n");
2674 return;
2675 }
2676 sdvo_priv->max_contrast = data_value[0];
2677 sdvo_priv->cur_contrast = response;
2678 sdvo_priv->contrast_property =
2679 drm_property_create(dev, DRM_MODE_PROP_RANGE,
2680 "contrast", 2);
2681 sdvo_priv->contrast_property->values[0] = 0;
2682 sdvo_priv->contrast_property->values[1] = data_value[0];
2683 drm_connector_attach_property(connector,
2684 sdvo_priv->contrast_property,
2685 sdvo_priv->cur_contrast);
2686 DRM_DEBUG_KMS("contrast: max %d, "
2687 "default %d, current %d\n",
2688 data_value[0], data_value[1], response);
2689 }
2690 if (sdvo_data.hue) {
2691 intel_sdvo_write_cmd(intel_encoder,
2692 SDVO_CMD_GET_MAX_HUE, NULL, 0);
2693 status = intel_sdvo_read_response(intel_encoder,
2694 &data_value, 4);
2695 if (status != SDVO_CMD_STATUS_SUCCESS) {
2696 DRM_DEBUG_KMS("Incorrect SDVO Max hue\n");
2697 return;
2698 }
2699 intel_sdvo_write_cmd(intel_encoder,
2700 SDVO_CMD_GET_HUE, NULL, 0);
2701 status = intel_sdvo_read_response(intel_encoder,
2702 &response, 2);
2703 if (status != SDVO_CMD_STATUS_SUCCESS) {
2704 DRM_DEBUG_KMS("Incorrect SDVO get hue\n");
2705 return;
2706 }
2707 sdvo_priv->max_hue = data_value[0];
2708 sdvo_priv->cur_hue = response;
2709 sdvo_priv->hue_property =
2710 drm_property_create(dev, DRM_MODE_PROP_RANGE,
2711 "hue", 2);
2712 sdvo_priv->hue_property->values[0] = 0;
2713 sdvo_priv->hue_property->values[1] =
2714 data_value[0];
2715 drm_connector_attach_property(connector,
2716 sdvo_priv->hue_property,
2717 sdvo_priv->cur_hue);
2718 DRM_DEBUG_KMS("hue: max %d, default %d, current %d\n",
2719 data_value[0], data_value[1], response);
2720 }
2721 } 2496 }
2722 if (IS_TV(sdvo_priv) || IS_LVDS(sdvo_priv)) { 2497
2723 if (sdvo_data.brightness) { 2498 return true;
2724 intel_sdvo_write_cmd(intel_encoder, 2499}
2725 SDVO_CMD_GET_MAX_BRIGHTNESS, NULL, 0); 2500
2726 status = intel_sdvo_read_response(intel_encoder, 2501static bool
2727 &data_value, 4); 2502intel_sdvo_create_enhance_property_lvds(struct intel_sdvo *intel_sdvo,
2728 if (status != SDVO_CMD_STATUS_SUCCESS) { 2503 struct intel_sdvo_connector *intel_sdvo_connector,
2729 DRM_DEBUG_KMS("Incorrect SDVO Max bright\n"); 2504 struct intel_sdvo_enhancements_reply enhancements)
2730 return; 2505{
2731 } 2506 struct drm_device *dev = intel_sdvo->base.enc.dev;
2732 intel_sdvo_write_cmd(intel_encoder, 2507 struct drm_connector *connector = &intel_sdvo_connector->base.base;
2733 SDVO_CMD_GET_BRIGHTNESS, NULL, 0); 2508 uint16_t response, data_value[2];
2734 status = intel_sdvo_read_response(intel_encoder, 2509
2735 &response, 2); 2510 ENHANCEMENT(brightness, BRIGHTNESS);
2736 if (status != SDVO_CMD_STATUS_SUCCESS) { 2511
2737 DRM_DEBUG_KMS("Incorrect SDVO get brigh\n"); 2512 return true;
2738 return; 2513}
2739 } 2514#undef ENHANCEMENT
2740 sdvo_priv->max_brightness = data_value[0]; 2515
2741 sdvo_priv->cur_brightness = response; 2516static bool intel_sdvo_create_enhance_property(struct intel_sdvo *intel_sdvo,
2742 sdvo_priv->brightness_property = 2517 struct intel_sdvo_connector *intel_sdvo_connector)
2743 drm_property_create(dev, DRM_MODE_PROP_RANGE, 2518{
2744 "brightness", 2); 2519 union {
2745 sdvo_priv->brightness_property->values[0] = 0; 2520 struct intel_sdvo_enhancements_reply reply;
2746 sdvo_priv->brightness_property->values[1] = 2521 uint16_t response;
2747 data_value[0]; 2522 } enhancements;
2748 drm_connector_attach_property(connector, 2523
2749 sdvo_priv->brightness_property, 2524 if (!intel_sdvo_get_value(intel_sdvo,
2750 sdvo_priv->cur_brightness); 2525 SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS,
2751 DRM_DEBUG_KMS("brightness: max %d, " 2526 &enhancements, sizeof(enhancements)))
2752 "default %d, current %d\n", 2527 return false;
2753 data_value[0], data_value[1], response); 2528
2754 } 2529 if (enhancements.response == 0) {
2530 DRM_DEBUG_KMS("No enhancement is supported\n");
2531 return true;
2755 } 2532 }
2756 return; 2533
2534 if (IS_TV(intel_sdvo_connector))
2535 return intel_sdvo_create_enhance_property_tv(intel_sdvo, intel_sdvo_connector, enhancements.reply);
2536 else if(IS_LVDS(intel_sdvo_connector))
2537 return intel_sdvo_create_enhance_property_lvds(intel_sdvo, intel_sdvo_connector, enhancements.reply);
2538 else
2539 return true;
2540
2757} 2541}
2758 2542
2759bool intel_sdvo_init(struct drm_device *dev, int sdvo_reg) 2543bool intel_sdvo_init(struct drm_device *dev, int sdvo_reg)
2760{ 2544{
2761 struct drm_i915_private *dev_priv = dev->dev_private; 2545 struct drm_i915_private *dev_priv = dev->dev_private;
2762 struct intel_encoder *intel_encoder; 2546 struct intel_encoder *intel_encoder;
2763 struct intel_sdvo_priv *sdvo_priv; 2547 struct intel_sdvo *intel_sdvo;
2764 u8 ch[0x40]; 2548 u8 ch[0x40];
2765 int i; 2549 int i;
2766 u32 i2c_reg, ddc_reg, analog_ddc_reg; 2550 u32 i2c_reg, ddc_reg, analog_ddc_reg;
2767 2551
2768 intel_encoder = kcalloc(sizeof(struct intel_encoder)+sizeof(struct intel_sdvo_priv), 1, GFP_KERNEL); 2552 intel_sdvo = kzalloc(sizeof(struct intel_sdvo), GFP_KERNEL);
2769 if (!intel_encoder) { 2553 if (!intel_sdvo)
2770 return false; 2554 return false;
2771 }
2772 2555
2773 sdvo_priv = (struct intel_sdvo_priv *)(intel_encoder + 1); 2556 intel_sdvo->sdvo_reg = sdvo_reg;
2774 sdvo_priv->sdvo_reg = sdvo_reg;
2775 2557
2776 intel_encoder->dev_priv = sdvo_priv; 2558 intel_encoder = &intel_sdvo->base;
2777 intel_encoder->type = INTEL_OUTPUT_SDVO; 2559 intel_encoder->type = INTEL_OUTPUT_SDVO;
2778 2560
2779 if (HAS_PCH_SPLIT(dev)) { 2561 if (HAS_PCH_SPLIT(dev)) {
@@ -2795,14 +2577,14 @@ bool intel_sdvo_init(struct drm_device *dev, int sdvo_reg)
2795 if (!intel_encoder->i2c_bus) 2577 if (!intel_encoder->i2c_bus)
2796 goto err_inteloutput; 2578 goto err_inteloutput;
2797 2579
2798 sdvo_priv->slave_addr = intel_sdvo_get_slave_addr(dev, sdvo_reg); 2580 intel_sdvo->slave_addr = intel_sdvo_get_slave_addr(dev, sdvo_reg);
2799 2581
2800 /* Save the bit-banging i2c functionality for use by the DDC wrapper */ 2582 /* Save the bit-banging i2c functionality for use by the DDC wrapper */
2801 intel_sdvo_i2c_bit_algo.functionality = intel_encoder->i2c_bus->algo->functionality; 2583 intel_sdvo_i2c_bit_algo.functionality = intel_encoder->i2c_bus->algo->functionality;
2802 2584
2803 /* Read the regs to test if we can talk to the device */ 2585 /* Read the regs to test if we can talk to the device */
2804 for (i = 0; i < 0x40; i++) { 2586 for (i = 0; i < 0x40; i++) {
2805 if (!intel_sdvo_read_byte(intel_encoder, i, &ch[i])) { 2587 if (!intel_sdvo_read_byte(intel_sdvo, i, &ch[i])) {
2806 DRM_DEBUG_KMS("No SDVO device found on SDVO%c\n", 2588 DRM_DEBUG_KMS("No SDVO device found on SDVO%c\n",
2807 IS_SDVOB(sdvo_reg) ? 'B' : 'C'); 2589 IS_SDVOB(sdvo_reg) ? 'B' : 'C');
2808 goto err_i2c; 2590 goto err_i2c;
@@ -2812,17 +2594,16 @@ bool intel_sdvo_init(struct drm_device *dev, int sdvo_reg)
2812 /* setup the DDC bus. */ 2594 /* setup the DDC bus. */
2813 if (IS_SDVOB(sdvo_reg)) { 2595 if (IS_SDVOB(sdvo_reg)) {
2814 intel_encoder->ddc_bus = intel_i2c_create(dev, ddc_reg, "SDVOB DDC BUS"); 2596 intel_encoder->ddc_bus = intel_i2c_create(dev, ddc_reg, "SDVOB DDC BUS");
2815 sdvo_priv->analog_ddc_bus = intel_i2c_create(dev, analog_ddc_reg, 2597 intel_sdvo->analog_ddc_bus = intel_i2c_create(dev, analog_ddc_reg,
2816 "SDVOB/VGA DDC BUS"); 2598 "SDVOB/VGA DDC BUS");
2817 dev_priv->hotplug_supported_mask |= SDVOB_HOTPLUG_INT_STATUS; 2599 dev_priv->hotplug_supported_mask |= SDVOB_HOTPLUG_INT_STATUS;
2818 } else { 2600 } else {
2819 intel_encoder->ddc_bus = intel_i2c_create(dev, ddc_reg, "SDVOC DDC BUS"); 2601 intel_encoder->ddc_bus = intel_i2c_create(dev, ddc_reg, "SDVOC DDC BUS");
2820 sdvo_priv->analog_ddc_bus = intel_i2c_create(dev, analog_ddc_reg, 2602 intel_sdvo->analog_ddc_bus = intel_i2c_create(dev, analog_ddc_reg,
2821 "SDVOC/VGA DDC BUS"); 2603 "SDVOC/VGA DDC BUS");
2822 dev_priv->hotplug_supported_mask |= SDVOC_HOTPLUG_INT_STATUS; 2604 dev_priv->hotplug_supported_mask |= SDVOC_HOTPLUG_INT_STATUS;
2823 } 2605 }
2824 2606 if (intel_encoder->ddc_bus == NULL || intel_sdvo->analog_ddc_bus == NULL)
2825 if (intel_encoder->ddc_bus == NULL)
2826 goto err_i2c; 2607 goto err_i2c;
2827 2608
2828 /* Wrap with our custom algo which switches to DDC mode */ 2609 /* Wrap with our custom algo which switches to DDC mode */
@@ -2833,53 +2614,56 @@ bool intel_sdvo_init(struct drm_device *dev, int sdvo_reg)
2833 drm_encoder_helper_add(&intel_encoder->enc, &intel_sdvo_helper_funcs); 2614 drm_encoder_helper_add(&intel_encoder->enc, &intel_sdvo_helper_funcs);
2834 2615
2835 /* In default case sdvo lvds is false */ 2616 /* In default case sdvo lvds is false */
2836 intel_sdvo_get_capabilities(intel_encoder, &sdvo_priv->caps); 2617 if (!intel_sdvo_get_capabilities(intel_sdvo, &intel_sdvo->caps))
2618 goto err_enc;
2837 2619
2838 if (intel_sdvo_output_setup(intel_encoder, 2620 if (intel_sdvo_output_setup(intel_sdvo,
2839 sdvo_priv->caps.output_flags) != true) { 2621 intel_sdvo->caps.output_flags) != true) {
2840 DRM_DEBUG_KMS("SDVO output failed to setup on SDVO%c\n", 2622 DRM_DEBUG_KMS("SDVO output failed to setup on SDVO%c\n",
2841 IS_SDVOB(sdvo_reg) ? 'B' : 'C'); 2623 IS_SDVOB(sdvo_reg) ? 'B' : 'C');
2842 goto err_i2c; 2624 goto err_enc;
2843 } 2625 }
2844 2626
2845 intel_sdvo_select_ddc_bus(dev_priv, sdvo_priv, sdvo_reg); 2627 intel_sdvo_select_ddc_bus(dev_priv, intel_sdvo, sdvo_reg);
2846 2628
2847 /* Set the input timing to the screen. Assume always input 0. */ 2629 /* Set the input timing to the screen. Assume always input 0. */
2848 intel_sdvo_set_target_input(intel_encoder, true, false); 2630 if (!intel_sdvo_set_target_input(intel_sdvo))
2849 2631 goto err_enc;
2850 intel_sdvo_get_input_pixel_clock_range(intel_encoder,
2851 &sdvo_priv->pixel_clock_min,
2852 &sdvo_priv->pixel_clock_max);
2853 2632
2633 if (!intel_sdvo_get_input_pixel_clock_range(intel_sdvo,
2634 &intel_sdvo->pixel_clock_min,
2635 &intel_sdvo->pixel_clock_max))
2636 goto err_enc;
2854 2637
2855 DRM_DEBUG_KMS("%s device VID/DID: %02X:%02X.%02X, " 2638 DRM_DEBUG_KMS("%s device VID/DID: %02X:%02X.%02X, "
2856 "clock range %dMHz - %dMHz, " 2639 "clock range %dMHz - %dMHz, "
2857 "input 1: %c, input 2: %c, " 2640 "input 1: %c, input 2: %c, "
2858 "output 1: %c, output 2: %c\n", 2641 "output 1: %c, output 2: %c\n",
2859 SDVO_NAME(sdvo_priv), 2642 SDVO_NAME(intel_sdvo),
2860 sdvo_priv->caps.vendor_id, sdvo_priv->caps.device_id, 2643 intel_sdvo->caps.vendor_id, intel_sdvo->caps.device_id,
2861 sdvo_priv->caps.device_rev_id, 2644 intel_sdvo->caps.device_rev_id,
2862 sdvo_priv->pixel_clock_min / 1000, 2645 intel_sdvo->pixel_clock_min / 1000,
2863 sdvo_priv->pixel_clock_max / 1000, 2646 intel_sdvo->pixel_clock_max / 1000,
2864 (sdvo_priv->caps.sdvo_inputs_mask & 0x1) ? 'Y' : 'N', 2647 (intel_sdvo->caps.sdvo_inputs_mask & 0x1) ? 'Y' : 'N',
2865 (sdvo_priv->caps.sdvo_inputs_mask & 0x2) ? 'Y' : 'N', 2648 (intel_sdvo->caps.sdvo_inputs_mask & 0x2) ? 'Y' : 'N',
2866 /* check currently supported outputs */ 2649 /* check currently supported outputs */
2867 sdvo_priv->caps.output_flags & 2650 intel_sdvo->caps.output_flags &
2868 (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_RGB0) ? 'Y' : 'N', 2651 (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_RGB0) ? 'Y' : 'N',
2869 sdvo_priv->caps.output_flags & 2652 intel_sdvo->caps.output_flags &
2870 (SDVO_OUTPUT_TMDS1 | SDVO_OUTPUT_RGB1) ? 'Y' : 'N'); 2653 (SDVO_OUTPUT_TMDS1 | SDVO_OUTPUT_RGB1) ? 'Y' : 'N');
2871
2872 return true; 2654 return true;
2873 2655
2656err_enc:
2657 drm_encoder_cleanup(&intel_encoder->enc);
2874err_i2c: 2658err_i2c:
2875 if (sdvo_priv->analog_ddc_bus != NULL) 2659 if (intel_sdvo->analog_ddc_bus != NULL)
2876 intel_i2c_destroy(sdvo_priv->analog_ddc_bus); 2660 intel_i2c_destroy(intel_sdvo->analog_ddc_bus);
2877 if (intel_encoder->ddc_bus != NULL) 2661 if (intel_encoder->ddc_bus != NULL)
2878 intel_i2c_destroy(intel_encoder->ddc_bus); 2662 intel_i2c_destroy(intel_encoder->ddc_bus);
2879 if (intel_encoder->i2c_bus != NULL) 2663 if (intel_encoder->i2c_bus != NULL)
2880 intel_i2c_destroy(intel_encoder->i2c_bus); 2664 intel_i2c_destroy(intel_encoder->i2c_bus);
2881err_inteloutput: 2665err_inteloutput:
2882 kfree(intel_encoder); 2666 kfree(intel_sdvo);
2883 2667
2884 return false; 2668 return false;
2885} 2669}
diff --git a/drivers/gpu/drm/i915/intel_sdvo_regs.h b/drivers/gpu/drm/i915/intel_sdvo_regs.h
index ba5cdf8ae40b..a386b022e538 100644
--- a/drivers/gpu/drm/i915/intel_sdvo_regs.h
+++ b/drivers/gpu/drm/i915/intel_sdvo_regs.h
@@ -312,7 +312,7 @@ struct intel_sdvo_set_target_input_args {
312# define SDVO_CLOCK_RATE_MULT_4X (1 << 3) 312# define SDVO_CLOCK_RATE_MULT_4X (1 << 3)
313 313
314#define SDVO_CMD_GET_SUPPORTED_TV_FORMATS 0x27 314#define SDVO_CMD_GET_SUPPORTED_TV_FORMATS 0x27
315/** 5 bytes of bit flags for TV formats shared by all TV format functions */ 315/** 6 bytes of bit flags for TV formats shared by all TV format functions */
316struct intel_sdvo_tv_format { 316struct intel_sdvo_tv_format {
317 unsigned int ntsc_m:1; 317 unsigned int ntsc_m:1;
318 unsigned int ntsc_j:1; 318 unsigned int ntsc_j:1;
@@ -596,32 +596,32 @@ struct intel_sdvo_enhancements_reply {
596 unsigned int overscan_h:1; 596 unsigned int overscan_h:1;
597 597
598 unsigned int overscan_v:1; 598 unsigned int overscan_v:1;
599 unsigned int position_h:1; 599 unsigned int hpos:1;
600 unsigned int position_v:1; 600 unsigned int vpos:1;
601 unsigned int sharpness:1; 601 unsigned int sharpness:1;
602 unsigned int dot_crawl:1; 602 unsigned int dot_crawl:1;
603 unsigned int dither:1; 603 unsigned int dither:1;
604 unsigned int max_tv_chroma_filter:1; 604 unsigned int tv_chroma_filter:1;
605 unsigned int max_tv_luma_filter:1; 605 unsigned int tv_luma_filter:1;
606} __attribute__((packed)); 606} __attribute__((packed));
607 607
608/* Picture enhancement limits below are dependent on the current TV format, 608/* Picture enhancement limits below are dependent on the current TV format,
609 * and thus need to be queried and set after it. 609 * and thus need to be queried and set after it.
610 */ 610 */
611#define SDVO_CMD_GET_MAX_FLICKER_FITER 0x4d 611#define SDVO_CMD_GET_MAX_FLICKER_FILTER 0x4d
612#define SDVO_CMD_GET_MAX_ADAPTIVE_FLICKER_FITER 0x7b 612#define SDVO_CMD_GET_MAX_FLICKER_FILTER_ADAPTIVE 0x7b
613#define SDVO_CMD_GET_MAX_2D_FLICKER_FITER 0x52 613#define SDVO_CMD_GET_MAX_FLICKER_FILTER_2D 0x52
614#define SDVO_CMD_GET_MAX_SATURATION 0x55 614#define SDVO_CMD_GET_MAX_SATURATION 0x55
615#define SDVO_CMD_GET_MAX_HUE 0x58 615#define SDVO_CMD_GET_MAX_HUE 0x58
616#define SDVO_CMD_GET_MAX_BRIGHTNESS 0x5b 616#define SDVO_CMD_GET_MAX_BRIGHTNESS 0x5b
617#define SDVO_CMD_GET_MAX_CONTRAST 0x5e 617#define SDVO_CMD_GET_MAX_CONTRAST 0x5e
618#define SDVO_CMD_GET_MAX_OVERSCAN_H 0x61 618#define SDVO_CMD_GET_MAX_OVERSCAN_H 0x61
619#define SDVO_CMD_GET_MAX_OVERSCAN_V 0x64 619#define SDVO_CMD_GET_MAX_OVERSCAN_V 0x64
620#define SDVO_CMD_GET_MAX_POSITION_H 0x67 620#define SDVO_CMD_GET_MAX_HPOS 0x67
621#define SDVO_CMD_GET_MAX_POSITION_V 0x6a 621#define SDVO_CMD_GET_MAX_VPOS 0x6a
622#define SDVO_CMD_GET_MAX_SHARPNESS_V 0x6d 622#define SDVO_CMD_GET_MAX_SHARPNESS 0x6d
623#define SDVO_CMD_GET_MAX_TV_CHROMA 0x74 623#define SDVO_CMD_GET_MAX_TV_CHROMA_FILTER 0x74
624#define SDVO_CMD_GET_MAX_TV_LUMA 0x77 624#define SDVO_CMD_GET_MAX_TV_LUMA_FILTER 0x77
625struct intel_sdvo_enhancement_limits_reply { 625struct intel_sdvo_enhancement_limits_reply {
626 u16 max_value; 626 u16 max_value;
627 u16 default_value; 627 u16 default_value;
@@ -638,10 +638,10 @@ struct intel_sdvo_enhancement_limits_reply {
638 638
639#define SDVO_CMD_GET_FLICKER_FILTER 0x4e 639#define SDVO_CMD_GET_FLICKER_FILTER 0x4e
640#define SDVO_CMD_SET_FLICKER_FILTER 0x4f 640#define SDVO_CMD_SET_FLICKER_FILTER 0x4f
641#define SDVO_CMD_GET_ADAPTIVE_FLICKER_FITER 0x50 641#define SDVO_CMD_GET_FLICKER_FILTER_ADAPTIVE 0x50
642#define SDVO_CMD_SET_ADAPTIVE_FLICKER_FITER 0x51 642#define SDVO_CMD_SET_FLICKER_FILTER_ADAPTIVE 0x51
643#define SDVO_CMD_GET_2D_FLICKER_FITER 0x53 643#define SDVO_CMD_GET_FLICKER_FILTER_2D 0x53
644#define SDVO_CMD_SET_2D_FLICKER_FITER 0x54 644#define SDVO_CMD_SET_FLICKER_FILTER_2D 0x54
645#define SDVO_CMD_GET_SATURATION 0x56 645#define SDVO_CMD_GET_SATURATION 0x56
646#define SDVO_CMD_SET_SATURATION 0x57 646#define SDVO_CMD_SET_SATURATION 0x57
647#define SDVO_CMD_GET_HUE 0x59 647#define SDVO_CMD_GET_HUE 0x59
@@ -654,16 +654,16 @@ struct intel_sdvo_enhancement_limits_reply {
654#define SDVO_CMD_SET_OVERSCAN_H 0x63 654#define SDVO_CMD_SET_OVERSCAN_H 0x63
655#define SDVO_CMD_GET_OVERSCAN_V 0x65 655#define SDVO_CMD_GET_OVERSCAN_V 0x65
656#define SDVO_CMD_SET_OVERSCAN_V 0x66 656#define SDVO_CMD_SET_OVERSCAN_V 0x66
657#define SDVO_CMD_GET_POSITION_H 0x68 657#define SDVO_CMD_GET_HPOS 0x68
658#define SDVO_CMD_SET_POSITION_H 0x69 658#define SDVO_CMD_SET_HPOS 0x69
659#define SDVO_CMD_GET_POSITION_V 0x6b 659#define SDVO_CMD_GET_VPOS 0x6b
660#define SDVO_CMD_SET_POSITION_V 0x6c 660#define SDVO_CMD_SET_VPOS 0x6c
661#define SDVO_CMD_GET_SHARPNESS 0x6e 661#define SDVO_CMD_GET_SHARPNESS 0x6e
662#define SDVO_CMD_SET_SHARPNESS 0x6f 662#define SDVO_CMD_SET_SHARPNESS 0x6f
663#define SDVO_CMD_GET_TV_CHROMA 0x75 663#define SDVO_CMD_GET_TV_CHROMA_FILTER 0x75
664#define SDVO_CMD_SET_TV_CHROMA 0x76 664#define SDVO_CMD_SET_TV_CHROMA_FILTER 0x76
665#define SDVO_CMD_GET_TV_LUMA 0x78 665#define SDVO_CMD_GET_TV_LUMA_FILTER 0x78
666#define SDVO_CMD_SET_TV_LUMA 0x79 666#define SDVO_CMD_SET_TV_LUMA_FILTER 0x79
667struct intel_sdvo_enhancements_arg { 667struct intel_sdvo_enhancements_arg {
668 u16 value; 668 u16 value;
669}__attribute__((packed)); 669}__attribute__((packed));
diff --git a/drivers/gpu/drm/i915/intel_tv.c b/drivers/gpu/drm/i915/intel_tv.c
index cc3726a4a1cb..c671f60ce80b 100644
--- a/drivers/gpu/drm/i915/intel_tv.c
+++ b/drivers/gpu/drm/i915/intel_tv.c
@@ -44,7 +44,9 @@ enum tv_margin {
44}; 44};
45 45
46/** Private structure for the integrated TV support */ 46/** Private structure for the integrated TV support */
47struct intel_tv_priv { 47struct intel_tv {
48 struct intel_encoder base;
49
48 int type; 50 int type;
49 char *tv_format; 51 char *tv_format;
50 int margin[4]; 52 int margin[4];
@@ -896,6 +898,11 @@ static const struct tv_mode tv_modes[] = {
896 }, 898 },
897}; 899};
898 900
901static struct intel_tv *enc_to_intel_tv(struct drm_encoder *encoder)
902{
903 return container_of(enc_to_intel_encoder(encoder), struct intel_tv, base);
904}
905
899static void 906static void
900intel_tv_dpms(struct drm_encoder *encoder, int mode) 907intel_tv_dpms(struct drm_encoder *encoder, int mode)
901{ 908{
@@ -929,19 +936,17 @@ intel_tv_mode_lookup (char *tv_format)
929} 936}
930 937
931static const struct tv_mode * 938static const struct tv_mode *
932intel_tv_mode_find (struct intel_encoder *intel_encoder) 939intel_tv_mode_find (struct intel_tv *intel_tv)
933{ 940{
934 struct intel_tv_priv *tv_priv = intel_encoder->dev_priv; 941 return intel_tv_mode_lookup(intel_tv->tv_format);
935
936 return intel_tv_mode_lookup(tv_priv->tv_format);
937} 942}
938 943
939static enum drm_mode_status 944static enum drm_mode_status
940intel_tv_mode_valid(struct drm_connector *connector, struct drm_display_mode *mode) 945intel_tv_mode_valid(struct drm_connector *connector, struct drm_display_mode *mode)
941{ 946{
942 struct drm_encoder *encoder = intel_attached_encoder(connector); 947 struct drm_encoder *encoder = intel_attached_encoder(connector);
943 struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder); 948 struct intel_tv *intel_tv = enc_to_intel_tv(encoder);
944 const struct tv_mode *tv_mode = intel_tv_mode_find(intel_encoder); 949 const struct tv_mode *tv_mode = intel_tv_mode_find(intel_tv);
945 950
946 /* Ensure TV refresh is close to desired refresh */ 951 /* Ensure TV refresh is close to desired refresh */
947 if (tv_mode && abs(tv_mode->refresh - drm_mode_vrefresh(mode) * 1000) 952 if (tv_mode && abs(tv_mode->refresh - drm_mode_vrefresh(mode) * 1000)
@@ -957,8 +962,8 @@ intel_tv_mode_fixup(struct drm_encoder *encoder, struct drm_display_mode *mode,
957{ 962{
958 struct drm_device *dev = encoder->dev; 963 struct drm_device *dev = encoder->dev;
959 struct drm_mode_config *drm_config = &dev->mode_config; 964 struct drm_mode_config *drm_config = &dev->mode_config;
960 struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder); 965 struct intel_tv *intel_tv = enc_to_intel_tv(encoder);
961 const struct tv_mode *tv_mode = intel_tv_mode_find (intel_encoder); 966 const struct tv_mode *tv_mode = intel_tv_mode_find(intel_tv);
962 struct drm_encoder *other_encoder; 967 struct drm_encoder *other_encoder;
963 968
964 if (!tv_mode) 969 if (!tv_mode)
@@ -983,9 +988,8 @@ intel_tv_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
983 struct drm_i915_private *dev_priv = dev->dev_private; 988 struct drm_i915_private *dev_priv = dev->dev_private;
984 struct drm_crtc *crtc = encoder->crtc; 989 struct drm_crtc *crtc = encoder->crtc;
985 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 990 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
986 struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder); 991 struct intel_tv *intel_tv = enc_to_intel_tv(encoder);
987 struct intel_tv_priv *tv_priv = intel_encoder->dev_priv; 992 const struct tv_mode *tv_mode = intel_tv_mode_find(intel_tv);
988 const struct tv_mode *tv_mode = intel_tv_mode_find(intel_encoder);
989 u32 tv_ctl; 993 u32 tv_ctl;
990 u32 hctl1, hctl2, hctl3; 994 u32 hctl1, hctl2, hctl3;
991 u32 vctl1, vctl2, vctl3, vctl4, vctl5, vctl6, vctl7; 995 u32 vctl1, vctl2, vctl3, vctl4, vctl5, vctl6, vctl7;
@@ -1001,7 +1005,7 @@ intel_tv_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
1001 tv_ctl = I915_READ(TV_CTL); 1005 tv_ctl = I915_READ(TV_CTL);
1002 tv_ctl &= TV_CTL_SAVE; 1006 tv_ctl &= TV_CTL_SAVE;
1003 1007
1004 switch (tv_priv->type) { 1008 switch (intel_tv->type) {
1005 default: 1009 default:
1006 case DRM_MODE_CONNECTOR_Unknown: 1010 case DRM_MODE_CONNECTOR_Unknown:
1007 case DRM_MODE_CONNECTOR_Composite: 1011 case DRM_MODE_CONNECTOR_Composite:
@@ -1154,11 +1158,11 @@ intel_tv_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
1154 1158
1155 /* Wait for vblank for the disable to take effect */ 1159 /* Wait for vblank for the disable to take effect */
1156 if (!IS_I9XX(dev)) 1160 if (!IS_I9XX(dev))
1157 intel_wait_for_vblank(dev); 1161 intel_wait_for_vblank(dev, intel_crtc->pipe);
1158 1162
1159 I915_WRITE(pipeconf_reg, pipeconf & ~PIPEACONF_ENABLE); 1163 I915_WRITE(pipeconf_reg, pipeconf & ~PIPEACONF_ENABLE);
1160 /* Wait for vblank for the disable to take effect. */ 1164 /* Wait for vblank for the disable to take effect. */
1161 intel_wait_for_vblank(dev); 1165 intel_wait_for_vblank(dev, intel_crtc->pipe);
1162 1166
1163 /* Filter ctl must be set before TV_WIN_SIZE */ 1167 /* Filter ctl must be set before TV_WIN_SIZE */
1164 I915_WRITE(TV_FILTER_CTL_1, TV_AUTO_SCALE); 1168 I915_WRITE(TV_FILTER_CTL_1, TV_AUTO_SCALE);
@@ -1168,12 +1172,12 @@ intel_tv_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
1168 else 1172 else
1169 ysize = 2*tv_mode->nbr_end + 1; 1173 ysize = 2*tv_mode->nbr_end + 1;
1170 1174
1171 xpos += tv_priv->margin[TV_MARGIN_LEFT]; 1175 xpos += intel_tv->margin[TV_MARGIN_LEFT];
1172 ypos += tv_priv->margin[TV_MARGIN_TOP]; 1176 ypos += intel_tv->margin[TV_MARGIN_TOP];
1173 xsize -= (tv_priv->margin[TV_MARGIN_LEFT] + 1177 xsize -= (intel_tv->margin[TV_MARGIN_LEFT] +
1174 tv_priv->margin[TV_MARGIN_RIGHT]); 1178 intel_tv->margin[TV_MARGIN_RIGHT]);
1175 ysize -= (tv_priv->margin[TV_MARGIN_TOP] + 1179 ysize -= (intel_tv->margin[TV_MARGIN_TOP] +
1176 tv_priv->margin[TV_MARGIN_BOTTOM]); 1180 intel_tv->margin[TV_MARGIN_BOTTOM]);
1177 I915_WRITE(TV_WIN_POS, (xpos<<16)|ypos); 1181 I915_WRITE(TV_WIN_POS, (xpos<<16)|ypos);
1178 I915_WRITE(TV_WIN_SIZE, (xsize<<16)|ysize); 1182 I915_WRITE(TV_WIN_SIZE, (xsize<<16)|ysize);
1179 1183
@@ -1222,9 +1226,9 @@ static const struct drm_display_mode reported_modes[] = {
1222 * \return false if TV is disconnected. 1226 * \return false if TV is disconnected.
1223 */ 1227 */
1224static int 1228static int
1225intel_tv_detect_type (struct drm_crtc *crtc, struct intel_encoder *intel_encoder) 1229intel_tv_detect_type (struct intel_tv *intel_tv)
1226{ 1230{
1227 struct drm_encoder *encoder = &intel_encoder->enc; 1231 struct drm_encoder *encoder = &intel_tv->base.enc;
1228 struct drm_device *dev = encoder->dev; 1232 struct drm_device *dev = encoder->dev;
1229 struct drm_i915_private *dev_priv = dev->dev_private; 1233 struct drm_i915_private *dev_priv = dev->dev_private;
1230 unsigned long irqflags; 1234 unsigned long irqflags;
@@ -1263,11 +1267,15 @@ intel_tv_detect_type (struct drm_crtc *crtc, struct intel_encoder *intel_encoder
1263 DAC_C_0_7_V); 1267 DAC_C_0_7_V);
1264 I915_WRITE(TV_CTL, tv_ctl); 1268 I915_WRITE(TV_CTL, tv_ctl);
1265 I915_WRITE(TV_DAC, tv_dac); 1269 I915_WRITE(TV_DAC, tv_dac);
1266 intel_wait_for_vblank(dev); 1270 POSTING_READ(TV_DAC);
1271 msleep(20);
1272
1267 tv_dac = I915_READ(TV_DAC); 1273 tv_dac = I915_READ(TV_DAC);
1268 I915_WRITE(TV_DAC, save_tv_dac); 1274 I915_WRITE(TV_DAC, save_tv_dac);
1269 I915_WRITE(TV_CTL, save_tv_ctl); 1275 I915_WRITE(TV_CTL, save_tv_ctl);
1270 intel_wait_for_vblank(dev); 1276 POSTING_READ(TV_CTL);
1277 msleep(20);
1278
1271 /* 1279 /*
1272 * A B C 1280 * A B C
1273 * 0 1 1 Composite 1281 * 0 1 1 Composite
@@ -1304,12 +1312,11 @@ intel_tv_detect_type (struct drm_crtc *crtc, struct intel_encoder *intel_encoder
1304static void intel_tv_find_better_format(struct drm_connector *connector) 1312static void intel_tv_find_better_format(struct drm_connector *connector)
1305{ 1313{
1306 struct drm_encoder *encoder = intel_attached_encoder(connector); 1314 struct drm_encoder *encoder = intel_attached_encoder(connector);
1307 struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder); 1315 struct intel_tv *intel_tv = enc_to_intel_tv(encoder);
1308 struct intel_tv_priv *tv_priv = intel_encoder->dev_priv; 1316 const struct tv_mode *tv_mode = intel_tv_mode_find(intel_tv);
1309 const struct tv_mode *tv_mode = intel_tv_mode_find(intel_encoder);
1310 int i; 1317 int i;
1311 1318
1312 if ((tv_priv->type == DRM_MODE_CONNECTOR_Component) == 1319 if ((intel_tv->type == DRM_MODE_CONNECTOR_Component) ==
1313 tv_mode->component_only) 1320 tv_mode->component_only)
1314 return; 1321 return;
1315 1322
@@ -1317,12 +1324,12 @@ static void intel_tv_find_better_format(struct drm_connector *connector)
1317 for (i = 0; i < sizeof(tv_modes) / sizeof(*tv_modes); i++) { 1324 for (i = 0; i < sizeof(tv_modes) / sizeof(*tv_modes); i++) {
1318 tv_mode = tv_modes + i; 1325 tv_mode = tv_modes + i;
1319 1326
1320 if ((tv_priv->type == DRM_MODE_CONNECTOR_Component) == 1327 if ((intel_tv->type == DRM_MODE_CONNECTOR_Component) ==
1321 tv_mode->component_only) 1328 tv_mode->component_only)
1322 break; 1329 break;
1323 } 1330 }
1324 1331
1325 tv_priv->tv_format = tv_mode->name; 1332 intel_tv->tv_format = tv_mode->name;
1326 drm_connector_property_set_value(connector, 1333 drm_connector_property_set_value(connector,
1327 connector->dev->mode_config.tv_mode_property, i); 1334 connector->dev->mode_config.tv_mode_property, i);
1328} 1335}
@@ -1336,31 +1343,31 @@ static void intel_tv_find_better_format(struct drm_connector *connector)
1336static enum drm_connector_status 1343static enum drm_connector_status
1337intel_tv_detect(struct drm_connector *connector) 1344intel_tv_detect(struct drm_connector *connector)
1338{ 1345{
1339 struct drm_crtc *crtc;
1340 struct drm_display_mode mode; 1346 struct drm_display_mode mode;
1341 struct drm_encoder *encoder = intel_attached_encoder(connector); 1347 struct drm_encoder *encoder = intel_attached_encoder(connector);
1342 struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder); 1348 struct intel_tv *intel_tv = enc_to_intel_tv(encoder);
1343 struct intel_tv_priv *tv_priv = intel_encoder->dev_priv; 1349 int type;
1344 int dpms_mode;
1345 int type = tv_priv->type;
1346 1350
1347 mode = reported_modes[0]; 1351 mode = reported_modes[0];
1348 drm_mode_set_crtcinfo(&mode, CRTC_INTERLACE_HALVE_V); 1352 drm_mode_set_crtcinfo(&mode, CRTC_INTERLACE_HALVE_V);
1349 1353
1350 if (encoder->crtc && encoder->crtc->enabled) { 1354 if (encoder->crtc && encoder->crtc->enabled) {
1351 type = intel_tv_detect_type(encoder->crtc, intel_encoder); 1355 type = intel_tv_detect_type(intel_tv);
1352 } else { 1356 } else {
1353 crtc = intel_get_load_detect_pipe(intel_encoder, connector, 1357 struct drm_crtc *crtc;
1358 int dpms_mode;
1359
1360 crtc = intel_get_load_detect_pipe(&intel_tv->base, connector,
1354 &mode, &dpms_mode); 1361 &mode, &dpms_mode);
1355 if (crtc) { 1362 if (crtc) {
1356 type = intel_tv_detect_type(crtc, intel_encoder); 1363 type = intel_tv_detect_type(intel_tv);
1357 intel_release_load_detect_pipe(intel_encoder, connector, 1364 intel_release_load_detect_pipe(&intel_tv->base, connector,
1358 dpms_mode); 1365 dpms_mode);
1359 } else 1366 } else
1360 type = -1; 1367 type = -1;
1361 } 1368 }
1362 1369
1363 tv_priv->type = type; 1370 intel_tv->type = type;
1364 1371
1365 if (type < 0) 1372 if (type < 0)
1366 return connector_status_disconnected; 1373 return connector_status_disconnected;
@@ -1391,8 +1398,8 @@ intel_tv_chose_preferred_modes(struct drm_connector *connector,
1391 struct drm_display_mode *mode_ptr) 1398 struct drm_display_mode *mode_ptr)
1392{ 1399{
1393 struct drm_encoder *encoder = intel_attached_encoder(connector); 1400 struct drm_encoder *encoder = intel_attached_encoder(connector);
1394 struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder); 1401 struct intel_tv *intel_tv = enc_to_intel_tv(encoder);
1395 const struct tv_mode *tv_mode = intel_tv_mode_find(intel_encoder); 1402 const struct tv_mode *tv_mode = intel_tv_mode_find(intel_tv);
1396 1403
1397 if (tv_mode->nbr_end < 480 && mode_ptr->vdisplay == 480) 1404 if (tv_mode->nbr_end < 480 && mode_ptr->vdisplay == 480)
1398 mode_ptr->type |= DRM_MODE_TYPE_PREFERRED; 1405 mode_ptr->type |= DRM_MODE_TYPE_PREFERRED;
@@ -1417,8 +1424,8 @@ intel_tv_get_modes(struct drm_connector *connector)
1417{ 1424{
1418 struct drm_display_mode *mode_ptr; 1425 struct drm_display_mode *mode_ptr;
1419 struct drm_encoder *encoder = intel_attached_encoder(connector); 1426 struct drm_encoder *encoder = intel_attached_encoder(connector);
1420 struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder); 1427 struct intel_tv *intel_tv = enc_to_intel_tv(encoder);
1421 const struct tv_mode *tv_mode = intel_tv_mode_find(intel_encoder); 1428 const struct tv_mode *tv_mode = intel_tv_mode_find(intel_tv);
1422 int j, count = 0; 1429 int j, count = 0;
1423 u64 tmp; 1430 u64 tmp;
1424 1431
@@ -1483,8 +1490,7 @@ intel_tv_set_property(struct drm_connector *connector, struct drm_property *prop
1483{ 1490{
1484 struct drm_device *dev = connector->dev; 1491 struct drm_device *dev = connector->dev;
1485 struct drm_encoder *encoder = intel_attached_encoder(connector); 1492 struct drm_encoder *encoder = intel_attached_encoder(connector);
1486 struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder); 1493 struct intel_tv *intel_tv = enc_to_intel_tv(encoder);
1487 struct intel_tv_priv *tv_priv = intel_encoder->dev_priv;
1488 struct drm_crtc *crtc = encoder->crtc; 1494 struct drm_crtc *crtc = encoder->crtc;
1489 int ret = 0; 1495 int ret = 0;
1490 bool changed = false; 1496 bool changed = false;
@@ -1494,30 +1500,30 @@ intel_tv_set_property(struct drm_connector *connector, struct drm_property *prop
1494 goto out; 1500 goto out;
1495 1501
1496 if (property == dev->mode_config.tv_left_margin_property && 1502 if (property == dev->mode_config.tv_left_margin_property &&
1497 tv_priv->margin[TV_MARGIN_LEFT] != val) { 1503 intel_tv->margin[TV_MARGIN_LEFT] != val) {
1498 tv_priv->margin[TV_MARGIN_LEFT] = val; 1504 intel_tv->margin[TV_MARGIN_LEFT] = val;
1499 changed = true; 1505 changed = true;
1500 } else if (property == dev->mode_config.tv_right_margin_property && 1506 } else if (property == dev->mode_config.tv_right_margin_property &&
1501 tv_priv->margin[TV_MARGIN_RIGHT] != val) { 1507 intel_tv->margin[TV_MARGIN_RIGHT] != val) {
1502 tv_priv->margin[TV_MARGIN_RIGHT] = val; 1508 intel_tv->margin[TV_MARGIN_RIGHT] = val;
1503 changed = true; 1509 changed = true;
1504 } else if (property == dev->mode_config.tv_top_margin_property && 1510 } else if (property == dev->mode_config.tv_top_margin_property &&
1505 tv_priv->margin[TV_MARGIN_TOP] != val) { 1511 intel_tv->margin[TV_MARGIN_TOP] != val) {
1506 tv_priv->margin[TV_MARGIN_TOP] = val; 1512 intel_tv->margin[TV_MARGIN_TOP] = val;
1507 changed = true; 1513 changed = true;
1508 } else if (property == dev->mode_config.tv_bottom_margin_property && 1514 } else if (property == dev->mode_config.tv_bottom_margin_property &&
1509 tv_priv->margin[TV_MARGIN_BOTTOM] != val) { 1515 intel_tv->margin[TV_MARGIN_BOTTOM] != val) {
1510 tv_priv->margin[TV_MARGIN_BOTTOM] = val; 1516 intel_tv->margin[TV_MARGIN_BOTTOM] = val;
1511 changed = true; 1517 changed = true;
1512 } else if (property == dev->mode_config.tv_mode_property) { 1518 } else if (property == dev->mode_config.tv_mode_property) {
1513 if (val >= ARRAY_SIZE(tv_modes)) { 1519 if (val >= ARRAY_SIZE(tv_modes)) {
1514 ret = -EINVAL; 1520 ret = -EINVAL;
1515 goto out; 1521 goto out;
1516 } 1522 }
1517 if (!strcmp(tv_priv->tv_format, tv_modes[val].name)) 1523 if (!strcmp(intel_tv->tv_format, tv_modes[val].name))
1518 goto out; 1524 goto out;
1519 1525
1520 tv_priv->tv_format = tv_modes[val].name; 1526 intel_tv->tv_format = tv_modes[val].name;
1521 changed = true; 1527 changed = true;
1522 } else { 1528 } else {
1523 ret = -EINVAL; 1529 ret = -EINVAL;
@@ -1553,16 +1559,8 @@ static const struct drm_connector_helper_funcs intel_tv_connector_helper_funcs =
1553 .best_encoder = intel_attached_encoder, 1559 .best_encoder = intel_attached_encoder,
1554}; 1560};
1555 1561
1556static void intel_tv_enc_destroy(struct drm_encoder *encoder)
1557{
1558 struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
1559
1560 drm_encoder_cleanup(encoder);
1561 kfree(intel_encoder);
1562}
1563
1564static const struct drm_encoder_funcs intel_tv_enc_funcs = { 1562static const struct drm_encoder_funcs intel_tv_enc_funcs = {
1565 .destroy = intel_tv_enc_destroy, 1563 .destroy = intel_encoder_destroy,
1566}; 1564};
1567 1565
1568/* 1566/*
@@ -1606,9 +1604,9 @@ intel_tv_init(struct drm_device *dev)
1606{ 1604{
1607 struct drm_i915_private *dev_priv = dev->dev_private; 1605 struct drm_i915_private *dev_priv = dev->dev_private;
1608 struct drm_connector *connector; 1606 struct drm_connector *connector;
1607 struct intel_tv *intel_tv;
1609 struct intel_encoder *intel_encoder; 1608 struct intel_encoder *intel_encoder;
1610 struct intel_connector *intel_connector; 1609 struct intel_connector *intel_connector;
1611 struct intel_tv_priv *tv_priv;
1612 u32 tv_dac_on, tv_dac_off, save_tv_dac; 1610 u32 tv_dac_on, tv_dac_off, save_tv_dac;
1613 char **tv_format_names; 1611 char **tv_format_names;
1614 int i, initial_mode = 0; 1612 int i, initial_mode = 0;
@@ -1647,18 +1645,18 @@ intel_tv_init(struct drm_device *dev)
1647 (tv_dac_off & TVDAC_STATE_CHG_EN) != 0) 1645 (tv_dac_off & TVDAC_STATE_CHG_EN) != 0)
1648 return; 1646 return;
1649 1647
1650 intel_encoder = kzalloc(sizeof(struct intel_encoder) + 1648 intel_tv = kzalloc(sizeof(struct intel_tv), GFP_KERNEL);
1651 sizeof(struct intel_tv_priv), GFP_KERNEL); 1649 if (!intel_tv) {
1652 if (!intel_encoder) {
1653 return; 1650 return;
1654 } 1651 }
1655 1652
1656 intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL); 1653 intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
1657 if (!intel_connector) { 1654 if (!intel_connector) {
1658 kfree(intel_encoder); 1655 kfree(intel_tv);
1659 return; 1656 return;
1660 } 1657 }
1661 1658
1659 intel_encoder = &intel_tv->base;
1662 connector = &intel_connector->base; 1660 connector = &intel_connector->base;
1663 1661
1664 drm_connector_init(dev, connector, &intel_tv_connector_funcs, 1662 drm_connector_init(dev, connector, &intel_tv_connector_funcs,
@@ -1668,22 +1666,20 @@ intel_tv_init(struct drm_device *dev)
1668 DRM_MODE_ENCODER_TVDAC); 1666 DRM_MODE_ENCODER_TVDAC);
1669 1667
1670 drm_mode_connector_attach_encoder(&intel_connector->base, &intel_encoder->enc); 1668 drm_mode_connector_attach_encoder(&intel_connector->base, &intel_encoder->enc);
1671 tv_priv = (struct intel_tv_priv *)(intel_encoder + 1);
1672 intel_encoder->type = INTEL_OUTPUT_TVOUT; 1669 intel_encoder->type = INTEL_OUTPUT_TVOUT;
1673 intel_encoder->crtc_mask = (1 << 0) | (1 << 1); 1670 intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
1674 intel_encoder->clone_mask = (1 << INTEL_TV_CLONE_BIT); 1671 intel_encoder->clone_mask = (1 << INTEL_TV_CLONE_BIT);
1675 intel_encoder->enc.possible_crtcs = ((1 << 0) | (1 << 1)); 1672 intel_encoder->enc.possible_crtcs = ((1 << 0) | (1 << 1));
1676 intel_encoder->enc.possible_clones = (1 << INTEL_OUTPUT_TVOUT); 1673 intel_encoder->enc.possible_clones = (1 << INTEL_OUTPUT_TVOUT);
1677 intel_encoder->dev_priv = tv_priv; 1674 intel_tv->type = DRM_MODE_CONNECTOR_Unknown;
1678 tv_priv->type = DRM_MODE_CONNECTOR_Unknown;
1679 1675
1680 /* BIOS margin values */ 1676 /* BIOS margin values */
1681 tv_priv->margin[TV_MARGIN_LEFT] = 54; 1677 intel_tv->margin[TV_MARGIN_LEFT] = 54;
1682 tv_priv->margin[TV_MARGIN_TOP] = 36; 1678 intel_tv->margin[TV_MARGIN_TOP] = 36;
1683 tv_priv->margin[TV_MARGIN_RIGHT] = 46; 1679 intel_tv->margin[TV_MARGIN_RIGHT] = 46;
1684 tv_priv->margin[TV_MARGIN_BOTTOM] = 37; 1680 intel_tv->margin[TV_MARGIN_BOTTOM] = 37;
1685 1681
1686 tv_priv->tv_format = kstrdup(tv_modes[initial_mode].name, GFP_KERNEL); 1682 intel_tv->tv_format = kstrdup(tv_modes[initial_mode].name, GFP_KERNEL);
1687 1683
1688 drm_encoder_helper_add(&intel_encoder->enc, &intel_tv_helper_funcs); 1684 drm_encoder_helper_add(&intel_encoder->enc, &intel_tv_helper_funcs);
1689 drm_connector_helper_add(connector, &intel_tv_connector_helper_funcs); 1685 drm_connector_helper_add(connector, &intel_tv_connector_helper_funcs);
@@ -1703,16 +1699,16 @@ intel_tv_init(struct drm_device *dev)
1703 initial_mode); 1699 initial_mode);
1704 drm_connector_attach_property(connector, 1700 drm_connector_attach_property(connector,
1705 dev->mode_config.tv_left_margin_property, 1701 dev->mode_config.tv_left_margin_property,
1706 tv_priv->margin[TV_MARGIN_LEFT]); 1702 intel_tv->margin[TV_MARGIN_LEFT]);
1707 drm_connector_attach_property(connector, 1703 drm_connector_attach_property(connector,
1708 dev->mode_config.tv_top_margin_property, 1704 dev->mode_config.tv_top_margin_property,
1709 tv_priv->margin[TV_MARGIN_TOP]); 1705 intel_tv->margin[TV_MARGIN_TOP]);
1710 drm_connector_attach_property(connector, 1706 drm_connector_attach_property(connector,
1711 dev->mode_config.tv_right_margin_property, 1707 dev->mode_config.tv_right_margin_property,
1712 tv_priv->margin[TV_MARGIN_RIGHT]); 1708 intel_tv->margin[TV_MARGIN_RIGHT]);
1713 drm_connector_attach_property(connector, 1709 drm_connector_attach_property(connector,
1714 dev->mode_config.tv_bottom_margin_property, 1710 dev->mode_config.tv_bottom_margin_property,
1715 tv_priv->margin[TV_MARGIN_BOTTOM]); 1711 intel_tv->margin[TV_MARGIN_BOTTOM]);
1716out: 1712out:
1717 drm_sysfs_connector_add(connector); 1713 drm_sysfs_connector_add(connector);
1718} 1714}
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-26 12:56:52 -0500