2 files changed, 10 insertions, 0 deletions

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 5a22887a5381..88292893b255 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2784,6 +2784,9 @@
 #define  FDI_RX_PHASE_SYNC_POINTER_ENABLE       (1)
 #define FDI_RX_CHICKEN(pipe) _PIPE(pipe, FDI_RXA_CHICKEN, FDI_RXB_CHICKEN)
 
+#define SOUTH_DSPCLK_GATE_D     0xc2020
+#define  PCH_DPLSUNIT_CLOCK_GATE_DISABLE (1<<29)
+
 /* CPU: FDI_TX */
 #define FDI_TXA_CTL             0x60100
 #define FDI_TXB_CTL             0x61100
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 89cfe4684147..8e98d708f970 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5746,6 +5746,13 @@ void intel_init_clock_gating(struct drm_device *dev)
                 I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
 
                 /*
+                 * On Ibex Peak and Cougar Point, we need to disable clock
+                 * gating for the panel power sequencer or it will fail to
+                 * start up when no ports are active.
+                 */
+                I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
+
+                /*
                  * According to the spec the following bits should be set in
                  * order to enable memory self-refresh
                  * The bit 22/21 of 0x42004