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-rw-r--r--drivers/gpu/drm/i915/Makefile1
-rw-r--r--drivers/gpu/drm/i915/i915_drv.c1
-rw-r--r--drivers/gpu/drm/i915/intel_display.c2
-rw-r--r--drivers/gpu/drm/i915/intel_dp.c72
-rw-r--r--drivers/gpu/drm/i915/intel_dp.h144
-rw-r--r--drivers/gpu/drm/i915/intel_dp_i2c.c273
6 files changed, 68 insertions, 425 deletions
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index fa7b9be096bc..e3d049229cdd 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -15,7 +15,6 @@ i915-y := i915_drv.o i915_dma.o i915_irq.o i915_mem.o \
15 intel_lvds.o \ 15 intel_lvds.o \
16 intel_bios.o \ 16 intel_bios.o \
17 intel_dp.o \ 17 intel_dp.o \
18 intel_dp_i2c.o \
19 intel_hdmi.o \ 18 intel_hdmi.o \
20 intel_sdvo.o \ 19 intel_sdvo.o \
21 intel_modes.o \ 20 intel_modes.o \
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 7f436ec075f6..2fa217862058 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -333,6 +333,7 @@ static struct drm_driver driver = {
333 .mmap = drm_gem_mmap, 333 .mmap = drm_gem_mmap,
334 .poll = drm_poll, 334 .poll = drm_poll,
335 .fasync = drm_fasync, 335 .fasync = drm_fasync,
336 .read = drm_read,
336#ifdef CONFIG_COMPAT 337#ifdef CONFIG_COMPAT
337 .compat_ioctl = i915_compat_ioctl, 338 .compat_ioctl = i915_compat_ioctl,
338#endif 339#endif
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 099f420de57a..897230832c8c 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -32,7 +32,7 @@
32#include "intel_drv.h" 32#include "intel_drv.h"
33#include "i915_drm.h" 33#include "i915_drm.h"
34#include "i915_drv.h" 34#include "i915_drv.h"
35#include "intel_dp.h" 35#include "drm_dp_helper.h"
36 36
37#include "drm_crtc_helper.h" 37#include "drm_crtc_helper.h"
38 38
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index d83447557f9b..63424d5db9c6 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -33,7 +33,7 @@
33#include "intel_drv.h" 33#include "intel_drv.h"
34#include "i915_drm.h" 34#include "i915_drm.h"
35#include "i915_drv.h" 35#include "i915_drv.h"
36#include "intel_dp.h" 36#include "drm_dp_helper.h"
37 37
38#define DP_LINK_STATUS_SIZE 6 38#define DP_LINK_STATUS_SIZE 6
39#define DP_LINK_CHECK_TIMEOUT (10 * 1000) 39#define DP_LINK_CHECK_TIMEOUT (10 * 1000)
@@ -382,17 +382,77 @@ intel_dp_aux_native_read(struct intel_output *intel_output,
382} 382}
383 383
384static int 384static int
385intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, 385intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
386 uint8_t *send, int send_bytes, 386 uint8_t write_byte, uint8_t *read_byte)
387 uint8_t *recv, int recv_bytes)
388{ 387{
388 struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
389 struct intel_dp_priv *dp_priv = container_of(adapter, 389 struct intel_dp_priv *dp_priv = container_of(adapter,
390 struct intel_dp_priv, 390 struct intel_dp_priv,
391 adapter); 391 adapter);
392 struct intel_output *intel_output = dp_priv->intel_output; 392 struct intel_output *intel_output = dp_priv->intel_output;
393 uint16_t address = algo_data->address;
394 uint8_t msg[5];
395 uint8_t reply[2];
396 int msg_bytes;
397 int reply_bytes;
398 int ret;
399
400 /* Set up the command byte */
401 if (mode & MODE_I2C_READ)
402 msg[0] = AUX_I2C_READ << 4;
403 else
404 msg[0] = AUX_I2C_WRITE << 4;
405
406 if (!(mode & MODE_I2C_STOP))
407 msg[0] |= AUX_I2C_MOT << 4;
408
409 msg[1] = address >> 8;
410 msg[2] = address;
411
412 switch (mode) {
413 case MODE_I2C_WRITE:
414 msg[3] = 0;
415 msg[4] = write_byte;
416 msg_bytes = 5;
417 reply_bytes = 1;
418 break;
419 case MODE_I2C_READ:
420 msg[3] = 0;
421 msg_bytes = 4;
422 reply_bytes = 2;
423 break;
424 default:
425 msg_bytes = 3;
426 reply_bytes = 1;
427 break;
428 }
393 429
394 return intel_dp_aux_ch(intel_output, 430 for (;;) {
395 send, send_bytes, recv, recv_bytes); 431 ret = intel_dp_aux_ch(intel_output,
432 msg, msg_bytes,
433 reply, reply_bytes);
434 if (ret < 0) {
435 DRM_DEBUG("aux_ch failed %d\n", ret);
436 return ret;
437 }
438 switch (reply[0] & AUX_I2C_REPLY_MASK) {
439 case AUX_I2C_REPLY_ACK:
440 if (mode == MODE_I2C_READ) {
441 *read_byte = reply[1];
442 }
443 return reply_bytes - 1;
444 case AUX_I2C_REPLY_NACK:
445 DRM_DEBUG("aux_ch nack\n");
446 return -EREMOTEIO;
447 case AUX_I2C_REPLY_DEFER:
448 DRM_DEBUG("aux_ch defer\n");
449 udelay(100);
450 break;
451 default:
452 DRM_ERROR("aux_ch invalid reply 0x%02x\n", reply[0]);
453 return -EREMOTEIO;
454 }
455 }
396} 456}
397 457
398static int 458static int
diff --git a/drivers/gpu/drm/i915/intel_dp.h b/drivers/gpu/drm/i915/intel_dp.h
deleted file mode 100644
index 2b38054d3b6d..000000000000
--- a/drivers/gpu/drm/i915/intel_dp.h
+++ /dev/null
@@ -1,144 +0,0 @@
1/*
2 * Copyright © 2008 Keith Packard
3 *
4 * Permission to use, copy, modify, distribute, and sell this software and its
5 * documentation for any purpose is hereby granted without fee, provided that
6 * the above copyright notice appear in all copies and that both that copyright
7 * notice and this permission notice appear in supporting documentation, and
8 * that the name of the copyright holders not be used in advertising or
9 * publicity pertaining to distribution of the software without specific,
10 * written prior permission. The copyright holders make no representations
11 * about the suitability of this software for any purpose. It is provided "as
12 * is" without express or implied warranty.
13 *
14 * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
15 * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
16 * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
17 * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE,
18 * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
19 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE
20 * OF THIS SOFTWARE.
21 */
22
23#ifndef _INTEL_DP_H_
24#define _INTEL_DP_H_
25
26/* From the VESA DisplayPort spec */
27
28#define AUX_NATIVE_WRITE 0x8
29#define AUX_NATIVE_READ 0x9
30#define AUX_I2C_WRITE 0x0
31#define AUX_I2C_READ 0x1
32#define AUX_I2C_STATUS 0x2
33#define AUX_I2C_MOT 0x4
34
35#define AUX_NATIVE_REPLY_ACK (0x0 << 4)
36#define AUX_NATIVE_REPLY_NACK (0x1 << 4)
37#define AUX_NATIVE_REPLY_DEFER (0x2 << 4)
38#define AUX_NATIVE_REPLY_MASK (0x3 << 4)
39
40#define AUX_I2C_REPLY_ACK (0x0 << 6)
41#define AUX_I2C_REPLY_NACK (0x1 << 6)
42#define AUX_I2C_REPLY_DEFER (0x2 << 6)
43#define AUX_I2C_REPLY_MASK (0x3 << 6)
44
45/* AUX CH addresses */
46#define DP_LINK_BW_SET 0x100
47# define DP_LINK_BW_1_62 0x06
48# define DP_LINK_BW_2_7 0x0a
49
50#define DP_LANE_COUNT_SET 0x101
51# define DP_LANE_COUNT_MASK 0x0f
52# define DP_LANE_COUNT_ENHANCED_FRAME_EN (1 << 7)
53
54#define DP_TRAINING_PATTERN_SET 0x102
55
56# define DP_TRAINING_PATTERN_DISABLE 0
57# define DP_TRAINING_PATTERN_1 1
58# define DP_TRAINING_PATTERN_2 2
59# define DP_TRAINING_PATTERN_MASK 0x3
60
61# define DP_LINK_QUAL_PATTERN_DISABLE (0 << 2)
62# define DP_LINK_QUAL_PATTERN_D10_2 (1 << 2)
63# define DP_LINK_QUAL_PATTERN_ERROR_RATE (2 << 2)
64# define DP_LINK_QUAL_PATTERN_PRBS7 (3 << 2)
65# define DP_LINK_QUAL_PATTERN_MASK (3 << 2)
66
67# define DP_RECOVERED_CLOCK_OUT_EN (1 << 4)
68# define DP_LINK_SCRAMBLING_DISABLE (1 << 5)
69
70# define DP_SYMBOL_ERROR_COUNT_BOTH (0 << 6)
71# define DP_SYMBOL_ERROR_COUNT_DISPARITY (1 << 6)
72# define DP_SYMBOL_ERROR_COUNT_SYMBOL (2 << 6)
73# define DP_SYMBOL_ERROR_COUNT_MASK (3 << 6)
74
75#define DP_TRAINING_LANE0_SET 0x103
76#define DP_TRAINING_LANE1_SET 0x104
77#define DP_TRAINING_LANE2_SET 0x105
78#define DP_TRAINING_LANE3_SET 0x106
79
80# define DP_TRAIN_VOLTAGE_SWING_MASK 0x3
81# define DP_TRAIN_VOLTAGE_SWING_SHIFT 0
82# define DP_TRAIN_MAX_SWING_REACHED (1 << 2)
83# define DP_TRAIN_VOLTAGE_SWING_400 (0 << 0)
84# define DP_TRAIN_VOLTAGE_SWING_600 (1 << 0)
85# define DP_TRAIN_VOLTAGE_SWING_800 (2 << 0)
86# define DP_TRAIN_VOLTAGE_SWING_1200 (3 << 0)
87
88# define DP_TRAIN_PRE_EMPHASIS_MASK (3 << 3)
89# define DP_TRAIN_PRE_EMPHASIS_0 (0 << 3)
90# define DP_TRAIN_PRE_EMPHASIS_3_5 (1 << 3)
91# define DP_TRAIN_PRE_EMPHASIS_6 (2 << 3)
92# define DP_TRAIN_PRE_EMPHASIS_9_5 (3 << 3)
93
94# define DP_TRAIN_PRE_EMPHASIS_SHIFT 3
95# define DP_TRAIN_MAX_PRE_EMPHASIS_REACHED (1 << 5)
96
97#define DP_DOWNSPREAD_CTRL 0x107
98# define DP_SPREAD_AMP_0_5 (1 << 4)
99
100#define DP_MAIN_LINK_CHANNEL_CODING_SET 0x108
101# define DP_SET_ANSI_8B10B (1 << 0)
102
103#define DP_LANE0_1_STATUS 0x202
104#define DP_LANE2_3_STATUS 0x203
105
106# define DP_LANE_CR_DONE (1 << 0)
107# define DP_LANE_CHANNEL_EQ_DONE (1 << 1)
108# define DP_LANE_SYMBOL_LOCKED (1 << 2)
109
110#define DP_LANE_ALIGN_STATUS_UPDATED 0x204
111
112#define DP_INTERLANE_ALIGN_DONE (1 << 0)
113#define DP_DOWNSTREAM_PORT_STATUS_CHANGED (1 << 6)
114#define DP_LINK_STATUS_UPDATED (1 << 7)
115
116#define DP_SINK_STATUS 0x205
117
118#define DP_RECEIVE_PORT_0_STATUS (1 << 0)
119#define DP_RECEIVE_PORT_1_STATUS (1 << 1)
120
121#define DP_ADJUST_REQUEST_LANE0_1 0x206
122#define DP_ADJUST_REQUEST_LANE2_3 0x207
123
124#define DP_ADJUST_VOLTAGE_SWING_LANE0_MASK 0x03
125#define DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT 0
126#define DP_ADJUST_PRE_EMPHASIS_LANE0_MASK 0x0c
127#define DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT 2
128#define DP_ADJUST_VOLTAGE_SWING_LANE1_MASK 0x30
129#define DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT 4
130#define DP_ADJUST_PRE_EMPHASIS_LANE1_MASK 0xc0
131#define DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT 6
132
133struct i2c_algo_dp_aux_data {
134 bool running;
135 u16 address;
136 int (*aux_ch) (struct i2c_adapter *adapter,
137 uint8_t *send, int send_bytes,
138 uint8_t *recv, int recv_bytes);
139};
140
141int
142i2c_dp_aux_add_bus(struct i2c_adapter *adapter);
143
144#endif /* _INTEL_DP_H_ */
diff --git a/drivers/gpu/drm/i915/intel_dp_i2c.c b/drivers/gpu/drm/i915/intel_dp_i2c.c
deleted file mode 100644
index a63b6f57d2d4..000000000000
--- a/drivers/gpu/drm/i915/intel_dp_i2c.c
+++ /dev/null
@@ -1,273 +0,0 @@
1/*
2 * Copyright © 2009 Keith Packard
3 *
4 * Permission to use, copy, modify, distribute, and sell this software and its
5 * documentation for any purpose is hereby granted without fee, provided that
6 * the above copyright notice appear in all copies and that both that copyright
7 * notice and this permission notice appear in supporting documentation, and
8 * that the name of the copyright holders not be used in advertising or
9 * publicity pertaining to distribution of the software without specific,
10 * written prior permission. The copyright holders make no representations
11 * about the suitability of this software for any purpose. It is provided "as
12 * is" without express or implied warranty.
13 *
14 * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
15 * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
16 * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
17 * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE,
18 * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
19 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE
20 * OF THIS SOFTWARE.
21 */
22
23#include <linux/kernel.h>
24#include <linux/module.h>
25#include <linux/delay.h>
26#include <linux/slab.h>
27#include <linux/init.h>
28#include <linux/errno.h>
29#include <linux/sched.h>
30#include <linux/i2c.h>
31#include "intel_dp.h"
32#include "drmP.h"
33
34/* Run a single AUX_CH I2C transaction, writing/reading data as necessary */
35
36#define MODE_I2C_START 1
37#define MODE_I2C_WRITE 2
38#define MODE_I2C_READ 4
39#define MODE_I2C_STOP 8
40
41static int
42i2c_algo_dp_aux_transaction(struct i2c_adapter *adapter, int mode,
43 uint8_t write_byte, uint8_t *read_byte)
44{
45 struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
46 uint16_t address = algo_data->address;
47 uint8_t msg[5];
48 uint8_t reply[2];
49 int msg_bytes;
50 int reply_bytes;
51 int ret;
52
53 /* Set up the command byte */
54 if (mode & MODE_I2C_READ)
55 msg[0] = AUX_I2C_READ << 4;
56 else
57 msg[0] = AUX_I2C_WRITE << 4;
58
59 if (!(mode & MODE_I2C_STOP))
60 msg[0] |= AUX_I2C_MOT << 4;
61
62 msg[1] = address >> 8;
63 msg[2] = address;
64
65 switch (mode) {
66 case MODE_I2C_WRITE:
67 msg[3] = 0;
68 msg[4] = write_byte;
69 msg_bytes = 5;
70 reply_bytes = 1;
71 break;
72 case MODE_I2C_READ:
73 msg[3] = 0;
74 msg_bytes = 4;
75 reply_bytes = 2;
76 break;
77 default:
78 msg_bytes = 3;
79 reply_bytes = 1;
80 break;
81 }
82
83 for (;;) {
84 ret = (*algo_data->aux_ch)(adapter,
85 msg, msg_bytes,
86 reply, reply_bytes);
87 if (ret < 0) {
88 DRM_DEBUG("aux_ch failed %d\n", ret);
89 return ret;
90 }
91 switch (reply[0] & AUX_I2C_REPLY_MASK) {
92 case AUX_I2C_REPLY_ACK:
93 if (mode == MODE_I2C_READ) {
94 *read_byte = reply[1];
95 }
96 return reply_bytes - 1;
97 case AUX_I2C_REPLY_NACK:
98 DRM_DEBUG("aux_ch nack\n");
99 return -EREMOTEIO;
100 case AUX_I2C_REPLY_DEFER:
101 DRM_DEBUG("aux_ch defer\n");
102 udelay(100);
103 break;
104 default:
105 DRM_ERROR("aux_ch invalid reply 0x%02x\n", reply[0]);
106 return -EREMOTEIO;
107 }
108 }
109}
110
111/*
112 * I2C over AUX CH
113 */
114
115/*
116 * Send the address. If the I2C link is running, this 'restarts'
117 * the connection with the new address, this is used for doing
118 * a write followed by a read (as needed for DDC)
119 */
120static int
121i2c_algo_dp_aux_address(struct i2c_adapter *adapter, u16 address, bool reading)
122{
123 struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
124 int mode = MODE_I2C_START;
125 int ret;
126
127 if (reading)
128 mode |= MODE_I2C_READ;
129 else
130 mode |= MODE_I2C_WRITE;
131 algo_data->address = address;
132 algo_data->running = true;
133 ret = i2c_algo_dp_aux_transaction(adapter, mode, 0, NULL);
134 return ret;
135}
136
137/*
138 * Stop the I2C transaction. This closes out the link, sending
139 * a bare address packet with the MOT bit turned off
140 */
141static void
142i2c_algo_dp_aux_stop(struct i2c_adapter *adapter, bool reading)
143{
144 struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
145 int mode = MODE_I2C_STOP;
146
147 if (reading)
148 mode |= MODE_I2C_READ;
149 else
150 mode |= MODE_I2C_WRITE;
151 if (algo_data->running) {
152 (void) i2c_algo_dp_aux_transaction(adapter, mode, 0, NULL);
153 algo_data->running = false;
154 }
155}
156
157/*
158 * Write a single byte to the current I2C address, the
159 * the I2C link must be running or this returns -EIO
160 */
161static int
162i2c_algo_dp_aux_put_byte(struct i2c_adapter *adapter, u8 byte)
163{
164 struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
165 int ret;
166
167 if (!algo_data->running)
168 return -EIO;
169
170 ret = i2c_algo_dp_aux_transaction(adapter, MODE_I2C_WRITE, byte, NULL);
171 return ret;
172}
173
174/*
175 * Read a single byte from the current I2C address, the
176 * I2C link must be running or this returns -EIO
177 */
178static int
179i2c_algo_dp_aux_get_byte(struct i2c_adapter *adapter, u8 *byte_ret)
180{
181 struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
182 int ret;
183
184 if (!algo_data->running)
185 return -EIO;
186
187 ret = i2c_algo_dp_aux_transaction(adapter, MODE_I2C_READ, 0, byte_ret);
188 return ret;
189}
190
191static int
192i2c_algo_dp_aux_xfer(struct i2c_adapter *adapter,
193 struct i2c_msg *msgs,
194 int num)
195{
196 int ret = 0;
197 bool reading = false;
198 int m;
199 int b;
200
201 for (m = 0; m < num; m++) {
202 u16 len = msgs[m].len;
203 u8 *buf = msgs[m].buf;
204 reading = (msgs[m].flags & I2C_M_RD) != 0;
205 ret = i2c_algo_dp_aux_address(adapter, msgs[m].addr, reading);
206 if (ret < 0)
207 break;
208 if (reading) {
209 for (b = 0; b < len; b++) {
210 ret = i2c_algo_dp_aux_get_byte(adapter, &buf[b]);
211 if (ret < 0)
212 break;
213 }
214 } else {
215 for (b = 0; b < len; b++) {
216 ret = i2c_algo_dp_aux_put_byte(adapter, buf[b]);
217 if (ret < 0)
218 break;
219 }
220 }
221 if (ret < 0)
222 break;
223 }
224 if (ret >= 0)
225 ret = num;
226 i2c_algo_dp_aux_stop(adapter, reading);
227 DRM_DEBUG("dp_aux_xfer return %d\n", ret);
228 return ret;
229}
230
231static u32
232i2c_algo_dp_aux_functionality(struct i2c_adapter *adapter)
233{
234 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL |
235 I2C_FUNC_SMBUS_READ_BLOCK_DATA |
236 I2C_FUNC_SMBUS_BLOCK_PROC_CALL |
237 I2C_FUNC_10BIT_ADDR;
238}
239
240static const struct i2c_algorithm i2c_dp_aux_algo = {
241 .master_xfer = i2c_algo_dp_aux_xfer,
242 .functionality = i2c_algo_dp_aux_functionality,
243};
244
245static void
246i2c_dp_aux_reset_bus(struct i2c_adapter *adapter)
247{
248 (void) i2c_algo_dp_aux_address(adapter, 0, false);
249 (void) i2c_algo_dp_aux_stop(adapter, false);
250
251}
252
253static int
254i2c_dp_aux_prepare_bus(struct i2c_adapter *adapter)
255{
256 adapter->algo = &i2c_dp_aux_algo;
257 adapter->retries = 3;
258 i2c_dp_aux_reset_bus(adapter);
259 return 0;
260}
261
262int
263i2c_dp_aux_add_bus(struct i2c_adapter *adapter)
264{
265 int error;
266
267 error = i2c_dp_aux_prepare_bus(adapter);
268 if (error)
269 return error;
270 error = i2c_add_adapter(adapter);
271 return error;
272}
273EXPORT_SYMBOL(i2c_dp_aux_add_bus);
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