17 files changed, 193 insertions, 103 deletions

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index ed22612bc847..a24ffbe97c01 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -346,11 +346,40 @@ static const struct pci_device_id pciidlist[] = {		/* aka */
         INTEL_VGA_DEVICE(0x016a, &intel_ivybridge_d_info), /* GT2 server */
         INTEL_VGA_DEVICE(0x0402, &intel_haswell_d_info), /* GT1 desktop */
         INTEL_VGA_DEVICE(0x0412, &intel_haswell_d_info), /* GT2 desktop */
+        INTEL_VGA_DEVICE(0x0422, &intel_haswell_d_info), /* GT2 desktop */
         INTEL_VGA_DEVICE(0x040a, &intel_haswell_d_info), /* GT1 server */
         INTEL_VGA_DEVICE(0x041a, &intel_haswell_d_info), /* GT2 server */
+        INTEL_VGA_DEVICE(0x042a, &intel_haswell_d_info), /* GT2 server */
         INTEL_VGA_DEVICE(0x0406, &intel_haswell_m_info), /* GT1 mobile */
         INTEL_VGA_DEVICE(0x0416, &intel_haswell_m_info), /* GT2 mobile */
-        INTEL_VGA_DEVICE(0x0c16, &intel_haswell_d_info), /* SDV */
+        INTEL_VGA_DEVICE(0x0426, &intel_haswell_m_info), /* GT2 mobile */
+        INTEL_VGA_DEVICE(0x0C02, &intel_haswell_d_info), /* SDV GT1 desktop */
+        INTEL_VGA_DEVICE(0x0C12, &intel_haswell_d_info), /* SDV GT2 desktop */
+        INTEL_VGA_DEVICE(0x0C22, &intel_haswell_d_info), /* SDV GT2 desktop */
+        INTEL_VGA_DEVICE(0x0C0A, &intel_haswell_d_info), /* SDV GT1 server */
+        INTEL_VGA_DEVICE(0x0C1A, &intel_haswell_d_info), /* SDV GT2 server */
+        INTEL_VGA_DEVICE(0x0C2A, &intel_haswell_d_info), /* SDV GT2 server */
+        INTEL_VGA_DEVICE(0x0C06, &intel_haswell_m_info), /* SDV GT1 mobile */
+        INTEL_VGA_DEVICE(0x0C16, &intel_haswell_m_info), /* SDV GT2 mobile */
+        INTEL_VGA_DEVICE(0x0C26, &intel_haswell_m_info), /* SDV GT2 mobile */
+        INTEL_VGA_DEVICE(0x0A02, &intel_haswell_d_info), /* ULT GT1 desktop */
+        INTEL_VGA_DEVICE(0x0A12, &intel_haswell_d_info), /* ULT GT2 desktop */
+        INTEL_VGA_DEVICE(0x0A22, &intel_haswell_d_info), /* ULT GT2 desktop */
+        INTEL_VGA_DEVICE(0x0A0A, &intel_haswell_d_info), /* ULT GT1 server */
+        INTEL_VGA_DEVICE(0x0A1A, &intel_haswell_d_info), /* ULT GT2 server */
+        INTEL_VGA_DEVICE(0x0A2A, &intel_haswell_d_info), /* ULT GT2 server */
+        INTEL_VGA_DEVICE(0x0A06, &intel_haswell_m_info), /* ULT GT1 mobile */
+        INTEL_VGA_DEVICE(0x0A16, &intel_haswell_m_info), /* ULT GT2 mobile */
+        INTEL_VGA_DEVICE(0x0A26, &intel_haswell_m_info), /* ULT GT2 mobile */
+        INTEL_VGA_DEVICE(0x0D12, &intel_haswell_d_info), /* CRW GT1 desktop */
+        INTEL_VGA_DEVICE(0x0D22, &intel_haswell_d_info), /* CRW GT2 desktop */
+        INTEL_VGA_DEVICE(0x0D32, &intel_haswell_d_info), /* CRW GT2 desktop */
+        INTEL_VGA_DEVICE(0x0D1A, &intel_haswell_d_info), /* CRW GT1 server */
+        INTEL_VGA_DEVICE(0x0D2A, &intel_haswell_d_info), /* CRW GT2 server */
+        INTEL_VGA_DEVICE(0x0D3A, &intel_haswell_d_info), /* CRW GT2 server */
+        INTEL_VGA_DEVICE(0x0D16, &intel_haswell_m_info), /* CRW GT1 mobile */
+        INTEL_VGA_DEVICE(0x0D26, &intel_haswell_m_info), /* CRW GT2 mobile */
+        INTEL_VGA_DEVICE(0x0D36, &intel_haswell_m_info), /* CRW GT2 mobile */
         INTEL_VGA_DEVICE(0x0f30, &intel_valleyview_m_info),
         INTEL_VGA_DEVICE(0x0157, &intel_valleyview_m_info),
         INTEL_VGA_DEVICE(0x0155, &intel_valleyview_d_info),
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 5c4657a54f97..489e2b162b27 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -2365,6 +2365,10 @@ int i915_gpu_idle(struct drm_device *dev)
 
         /* Flush everything onto the inactive list. */
         for_each_ring(ring, dev_priv, i) {
+                ret = i915_switch_context(ring, NULL, DEFAULT_CONTEXT_ID);
+                if (ret)
+                        return ret;
+
                 ret = i915_ring_idle(ring);
                 if (ret)
                         return ret;
@@ -2372,10 +2376,6 @@ int i915_gpu_idle(struct drm_device *dev)
                 /* Is the device fubar? */
                 if (WARN_ON(!list_empty(&ring->gpu_write_list)))
                         return -EBUSY;
-
-                ret = i915_switch_context(ring, NULL, DEFAULT_CONTEXT_ID);
-                if (ret)
-                        return ret;
         }
 
         return 0;
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c
index da8b01fb1bf8..a9d58d72bb4d 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -451,7 +451,6 @@ int i915_switch_context(struct intel_ring_buffer *ring,
         struct drm_i915_file_private *file_priv = NULL;
         struct i915_hw_context *to;
         struct drm_i915_gem_object *from_obj = ring->last_context_obj;
-        int ret;
 
         if (dev_priv->hw_contexts_disabled)
                 return 0;
diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
index 5af631e788c8..ff2819ea0813 100644
--- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
@@ -291,6 +291,16 @@ i915_gem_execbuffer_relocate_entry(struct drm_i915_gem_object *obj,
         target_i915_obj = to_intel_bo(target_obj);
         target_offset = target_i915_obj->gtt_offset;
 
+        /* Sandybridge PPGTT errata: We need a global gtt mapping for MI and
+         * pipe_control writes because the gpu doesn't properly redirect them
+         * through the ppgtt for non_secure batchbuffers. */
+        if (unlikely(IS_GEN6(dev) &&
+            reloc->write_domain == I915_GEM_DOMAIN_INSTRUCTION &&
+            !target_i915_obj->has_global_gtt_mapping)) {
+                i915_gem_gtt_bind_object(target_i915_obj,
+                                         target_i915_obj->cache_level);
+        }
+
         /* The target buffer should have appeared before us in the
          * exec_object list, so it should have a GTT space bound by now.
          */
@@ -399,16 +409,6 @@ i915_gem_execbuffer_relocate_entry(struct drm_i915_gem_object *obj,
                 io_mapping_unmap_atomic(reloc_page);
         }
 
-        /* Sandybridge PPGTT errata: We need a global gtt mapping for MI and
-         * pipe_control writes because the gpu doesn't properly redirect them
-         * through the ppgtt for non_secure batchbuffers. */
-        if (unlikely(IS_GEN6(dev) &&
-            reloc->write_domain == I915_GEM_DOMAIN_INSTRUCTION &&
-            !target_i915_obj->has_global_gtt_mapping)) {
-                i915_gem_gtt_bind_object(target_i915_obj,
-                                         target_i915_obj->cache_level);
-        }
-
         /* and update the user's relocation entry */
         reloc->presumed_offset = target_offset;
 
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 9fd25a435536..d9a5372ec56f 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -261,7 +261,10 @@ void i915_ppgtt_bind_object(struct i915_hw_ppgtt *ppgtt,
                 pte_flags |= GEN6_PTE_CACHE_LLC;
                 break;
         case I915_CACHE_NONE:
-                pte_flags |= GEN6_PTE_UNCACHED;
+                if (IS_HASWELL(dev))
+                        pte_flags |= HSW_PTE_UNCACHED;
+                else
+                        pte_flags |= GEN6_PTE_UNCACHED;
                 break;
         default:
                 BUG();
@@ -361,7 +364,8 @@ int i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj)
         struct drm_device *dev = obj->base.dev;
         struct drm_i915_private *dev_priv = dev->dev_private;
 
-        if (dev_priv->mm.gtt->needs_dmar)
+        /* don't map imported dma buf objects */
+        if (dev_priv->mm.gtt->needs_dmar && !obj->sg_table)
                 return intel_gtt_map_memory(obj->pages,
                                             obj->base.size >> PAGE_SHIFT,
                                             &obj->sg_list,
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index acc99b21e0b6..28725ce5b82c 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -115,6 +115,7 @@
 
 #define GEN6_PTE_VALID                  (1 << 0)
 #define GEN6_PTE_UNCACHED               (1 << 1)
+#define HSW_PTE_UNCACHED                (0)
 #define GEN6_PTE_CACHE_LLC              (2 << 1)
 #define GEN6_PTE_CACHE_LLC_MLC          (3 << 1)
 #define GEN6_PTE_CACHE_BITS             (3 << 1)
diff --git a/drivers/gpu/drm/i915/i915_sysfs.c b/drivers/gpu/drm/i915/i915_sysfs.c
index 2f5388af8df9..7631807a2788 100644
--- a/drivers/gpu/drm/i915/i915_sysfs.c
+++ b/drivers/gpu/drm/i915/i915_sysfs.c
@@ -32,6 +32,7 @@
 #include "intel_drv.h"
 #include "i915_drv.h"
 
+#ifdef CONFIG_PM
 static u32 calc_residency(struct drm_device *dev, const u32 reg)
 {
         struct drm_i915_private *dev_priv = dev->dev_private;
@@ -224,3 +225,14 @@ void i915_teardown_sysfs(struct drm_device *dev)
         device_remove_bin_file(&dev->primary->kdev,  &dpf_attrs);
         sysfs_unmerge_group(&dev->primary->kdev.kobj, &rc6_attr_group);
 }
+#else
+void i915_setup_sysfs(struct drm_device *dev)
+{
+        return;
+}
+
+void i915_teardown_sysfs(struct drm_device *dev)
+{
+        return;
+}
+#endif /* CONFIG_PM */
diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c
index 7ed4a41c3965..23bdc8cd1458 100644
--- a/drivers/gpu/drm/i915/intel_crt.c
+++ b/drivers/gpu/drm/i915/intel_crt.c
@@ -326,6 +326,36 @@ static bool intel_crt_detect_hotplug(struct drm_connector *connector)
         return ret;
 }
 
+static struct edid *intel_crt_get_edid(struct drm_connector *connector,
+                                struct i2c_adapter *i2c)
+{
+        struct edid *edid;
+
+        edid = drm_get_edid(connector, i2c);
+
+        if (!edid && !intel_gmbus_is_forced_bit(i2c)) {
+                DRM_DEBUG_KMS("CRT GMBUS EDID read failed, retry using GPIO bit-banging\n");
+                intel_gmbus_force_bit(i2c, true);
+                edid = drm_get_edid(connector, i2c);
+                intel_gmbus_force_bit(i2c, false);
+        }
+
+        return edid;
+}
+
+/* local version of intel_ddc_get_modes() to use intel_crt_get_edid() */
+static int intel_crt_ddc_get_modes(struct drm_connector *connector,
+                                struct i2c_adapter *adapter)
+{
+        struct edid *edid;
+
+        edid = intel_crt_get_edid(connector, adapter);
+        if (!edid)
+                return 0;
+
+        return intel_connector_update_modes(connector, edid);
+}
+
 static bool intel_crt_detect_ddc(struct drm_connector *connector)
 {
         struct intel_crt *crt = intel_attached_crt(connector);
@@ -336,7 +366,7 @@ static bool intel_crt_detect_ddc(struct drm_connector *connector)
         BUG_ON(crt->base.type != INTEL_OUTPUT_ANALOG);
 
         i2c = intel_gmbus_get_adapter(dev_priv, dev_priv->crt_ddc_pin);
-        edid = drm_get_edid(connector, i2c);
+        edid = intel_crt_get_edid(connector, i2c);
 
         if (edid) {
                 bool is_digital = edid->input & DRM_EDID_INPUT_DIGITAL;
@@ -544,13 +574,13 @@ static int intel_crt_get_modes(struct drm_connector *connector)
         struct i2c_adapter *i2c;
 
         i2c = intel_gmbus_get_adapter(dev_priv, dev_priv->crt_ddc_pin);
-        ret = intel_ddc_get_modes(connector, i2c);
+        ret = intel_crt_ddc_get_modes(connector, i2c);
         if (ret || !IS_G4X(dev))
                 return ret;
 
         /* Try to probe digital port for output in DVI-I -> VGA mode. */
         i2c = intel_gmbus_get_adapter(dev_priv, GMBUS_PORT_DPB);
-        return intel_ddc_get_modes(connector, i2c);
+        return intel_crt_ddc_get_modes(connector, i2c);
 }
 
 static int intel_crt_set_property(struct drm_connector *connector,
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index f6159765f1eb..a69a3d0d3acf 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -869,6 +869,7 @@ intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
         unsigned long bestppm, ppm, absppm;
         int dotclk, flag;
 
+        flag = 0;
         dotclk = target * 1000;
         bestppm = 1000000;
         ppm = absppm = 0;
@@ -3753,17 +3754,6 @@ static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc,
                         continue;
                 }
 
-                if (intel_encoder->type == INTEL_OUTPUT_EDP) {
-                        /* Use VBT settings if we have an eDP panel */
-                        unsigned int edp_bpc = dev_priv->edp.bpp / 3;
-
-                        if (edp_bpc < display_bpc) {
-                                DRM_DEBUG_KMS("clamping display bpc (was %d) to eDP (%d)\n", display_bpc, edp_bpc);
-                                display_bpc = edp_bpc;
-                        }
-                        continue;
-                }
-
                 /* Not one of the known troublemakers, check the EDID */
                 list_for_each_entry(connector, &dev->mode_config.connector_list,
                                     head) {
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 0a56b9ab0f58..a6c426afaa7a 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1174,10 +1174,14 @@ static void ironlake_edp_panel_off(struct intel_dp *intel_dp)
         WARN(!intel_dp->want_panel_vdd, "Need VDD to turn off panel\n");
 
         pp = ironlake_get_pp_control(dev_priv);
-        pp &= ~(POWER_TARGET_ON | PANEL_POWER_RESET | EDP_BLC_ENABLE);
+        /* We need to switch off panel power _and_ force vdd, for otherwise some
+         * panels get very unhappy and cease to work. */
+        pp &= ~(POWER_TARGET_ON | EDP_FORCE_VDD | PANEL_POWER_RESET | EDP_BLC_ENABLE);
         I915_WRITE(PCH_PP_CONTROL, pp);
         POSTING_READ(PCH_PP_CONTROL);
 
+        intel_dp->want_panel_vdd = false;
+
         ironlake_wait_panel_off(intel_dp);
 }
 
@@ -1287,11 +1291,9 @@ static void intel_dp_prepare(struct drm_encoder *encoder)
          * ensure that we have vdd while we switch off the panel. */
         ironlake_edp_panel_vdd_on(intel_dp);
         ironlake_edp_backlight_off(intel_dp);
-        ironlake_edp_panel_off(intel_dp);
-
         intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
+        ironlake_edp_panel_off(intel_dp);
         intel_dp_link_down(intel_dp);
-        ironlake_edp_panel_vdd_off(intel_dp, false);
 }
 
 static void intel_dp_commit(struct drm_encoder *encoder)
@@ -1326,11 +1328,9 @@ intel_dp_dpms(struct drm_encoder *encoder, int mode)
                 /* Switching the panel off requires vdd. */
                 ironlake_edp_panel_vdd_on(intel_dp);
                 ironlake_edp_backlight_off(intel_dp);
-                ironlake_edp_panel_off(intel_dp);
-
                 intel_dp_sink_dpms(intel_dp, mode);
+                ironlake_edp_panel_off(intel_dp);
                 intel_dp_link_down(intel_dp);
-                ironlake_edp_panel_vdd_off(intel_dp, false);
 
                 if (is_cpu_edp(intel_dp))
                         ironlake_edp_pll_off(encoder);
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 84353559441c..cd54cf88a28f 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -46,15 +46,16 @@
 })
 
 #define wait_for_atomic_us(COND, US) ({ \
-        int i, ret__ = -ETIMEDOUT;      \
-        for (i = 0; i < (US); i++) {    \
-                if ((COND)) {           \
-                        ret__ = 0;      \
-                        break;          \
-                }                       \
-                udelay(1);              \
-        }                               \
-        ret__;                          \
+        unsigned long timeout__ = jiffies + usecs_to_jiffies(US);       \
+        int ret__ = 0;                                                  \
+        while (!(COND)) {                                               \
+                if (time_after(jiffies, timeout__)) {                   \
+                        ret__ = -ETIMEDOUT;                             \
+                        break;                                          \
+                }                                                       \
+                cpu_relax();                                            \
+        }                                                               \
+        ret__;                                                          \
 })
 
 #define wait_for(COND, MS) _wait_for(COND, MS, 1)
@@ -341,6 +342,8 @@ struct intel_fbc_work {
         int interval;
 };
 
+int intel_connector_update_modes(struct drm_connector *connector,
+                                struct edid *edid);
 int intel_ddc_get_modes(struct drm_connector *c, struct i2c_adapter *adapter);
 
 extern void intel_attach_force_audio_property(struct drm_connector *connector);
@@ -380,7 +383,6 @@ extern void intel_pch_panel_fitting(struct drm_device *dev,
                                     const struct drm_display_mode *mode,
                                     struct drm_display_mode *adjusted_mode);
 extern u32 intel_panel_get_max_backlight(struct drm_device *dev);
-extern u32 intel_panel_get_backlight(struct drm_device *dev);
 extern void intel_panel_set_backlight(struct drm_device *dev, u32 level);
 extern int intel_panel_setup_backlight(struct drm_device *dev);
 extern void intel_panel_enable_backlight(struct drm_device *dev,
diff --git a/drivers/gpu/drm/i915/intel_i2c.c b/drivers/gpu/drm/i915/intel_i2c.c
index 1991a4408cf9..b9755f6378d8 100644
--- a/drivers/gpu/drm/i915/intel_i2c.c
+++ b/drivers/gpu/drm/i915/intel_i2c.c
@@ -486,9 +486,6 @@ int intel_setup_gmbus(struct drm_device *dev)
                 bus->dev_priv = dev_priv;
 
                 bus->adapter.algo = &gmbus_algorithm;
-                ret = i2c_add_adapter(&bus->adapter);
-                if (ret)
-                        goto err;
 
                 /* By default use a conservative clock rate */
                 bus->reg0 = port | GMBUS_RATE_100KHZ;
@@ -498,6 +495,10 @@ int intel_setup_gmbus(struct drm_device *dev)
                         bus->force_bit = true;
 
                 intel_gpio_setup(bus, port);
+
+                ret = i2c_add_adapter(&bus->adapter);
+                if (ret)
+                        goto err;
         }
 
         intel_i2c_reset(dev_priv->dev);
@@ -540,9 +541,6 @@ void intel_teardown_gmbus(struct drm_device *dev)
         struct drm_i915_private *dev_priv = dev->dev_private;
         int i;
 
-        if (dev_priv->gmbus == NULL)
-                return;
-
         for (i = 0; i < GMBUS_NUM_PORTS; i++) {
                 struct intel_gmbus *bus = &dev_priv->gmbus[i];
                 i2c_del_adapter(&bus->adapter);
diff --git a/drivers/gpu/drm/i915/intel_modes.c b/drivers/gpu/drm/i915/intel_modes.c
index 45848b9b670b..29b72593fbb2 100644
--- a/drivers/gpu/drm/i915/intel_modes.c
+++ b/drivers/gpu/drm/i915/intel_modes.c
@@ -33,6 +33,25 @@
 #include "i915_drv.h"
 
 /**
+ * intel_connector_update_modes - update connector from edid
+ * @connector: DRM connector device to use
+ * @edid: previously read EDID information
+ */
+int intel_connector_update_modes(struct drm_connector *connector,
+                                struct edid *edid)
+{
+        int ret;
+
+        drm_mode_connector_update_edid_property(connector, edid);
+        ret = drm_add_edid_modes(connector, edid);
+        drm_edid_to_eld(connector, edid);
+        connector->display_info.raw_edid = NULL;
+        kfree(edid);
+
+        return ret;
+}
+
+/**
  * intel_ddc_get_modes - get modelist from monitor
  * @connector: DRM connector device to use
  * @adapter: i2c adapter
@@ -43,18 +62,12 @@ int intel_ddc_get_modes(struct drm_connector *connector,
                         struct i2c_adapter *adapter)
 {
         struct edid *edid;
-        int ret = 0;
 
         edid = drm_get_edid(connector, adapter);
-        if (edid) {
-                drm_mode_connector_update_edid_property(connector, edid);
-                ret = drm_add_edid_modes(connector, edid);
-                drm_edid_to_eld(connector, edid);
-                connector->display_info.raw_edid = NULL;
-                kfree(edid);
-        }
+        if (!edid)
+                return 0;
 
-        return ret;
+        return intel_connector_update_modes(connector, edid);
 }
 
 static const struct drm_prop_enum_list force_audio_names[] = {
diff --git a/drivers/gpu/drm/i915/intel_panel.c b/drivers/gpu/drm/i915/intel_panel.c
index 10c7d39034e1..3df4f5fa892a 100644
--- a/drivers/gpu/drm/i915/intel_panel.c
+++ b/drivers/gpu/drm/i915/intel_panel.c
@@ -213,7 +213,7 @@ static u32 intel_panel_compute_brightness(struct drm_device *dev, u32 val)
         return val;
 }
 
-u32 intel_panel_get_backlight(struct drm_device *dev)
+static u32 intel_panel_get_backlight(struct drm_device *dev)
 {
         struct drm_i915_private *dev_priv = dev->dev_private;
         u32 val;
@@ -311,9 +311,6 @@ void intel_panel_enable_backlight(struct drm_device *dev,
         if (dev_priv->backlight_level == 0)
                 dev_priv->backlight_level = intel_panel_get_max_backlight(dev);
 
-        dev_priv->backlight_enabled = true;
-        intel_panel_actually_set_backlight(dev, dev_priv->backlight_level);
-
         if (INTEL_INFO(dev)->gen >= 4) {
                 uint32_t reg, tmp;
 
@@ -326,7 +323,7 @@ void intel_panel_enable_backlight(struct drm_device *dev,
                  * we don't track the backlight dpms state, hence check whether
                  * we have to do anything first. */
                 if (tmp & BLM_PWM_ENABLE)
-                        return;
+                        goto set_level;
 
                 if (dev_priv->num_pipe == 3)
                         tmp &= ~BLM_PIPE_SELECT_IVB;
@@ -347,6 +344,14 @@ void intel_panel_enable_backlight(struct drm_device *dev,
                         I915_WRITE(BLC_PWM_PCH_CTL1, tmp);
                 }
         }
+
+set_level:
+        /* Call below after setting BLC_PWM_CPU_CTL2 and BLC_PWM_PCH_CTL1.
+         * BLC_PWM_CPU_CTL may be cleared to zero automatically when these
+         * registers are set.
+         */
+        dev_priv->backlight_enabled = true;
+        intel_panel_actually_set_backlight(dev, dev_priv->backlight_level);
 }
 
 static void intel_panel_init_backlight(struct drm_device *dev)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 94aabcaa3a67..1881c8c83f0e 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -2441,17 +2441,10 @@ static void gen6_enable_rps(struct drm_device *dev)
                    dev_priv->max_delay << 24 |
                    dev_priv->min_delay << 16);
 
-        if (IS_HASWELL(dev)) {
-                I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
-                I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
-                I915_WRITE(GEN6_RP_UP_EI, 66000);
-                I915_WRITE(GEN6_RP_DOWN_EI, 350000);
-        } else {
-                I915_WRITE(GEN6_RP_UP_THRESHOLD, 10000);
-                I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 1000000);
-                I915_WRITE(GEN6_RP_UP_EI, 100000);
-                I915_WRITE(GEN6_RP_DOWN_EI, 5000000);
-        }
+        I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
+        I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
+        I915_WRITE(GEN6_RP_UP_EI, 66000);
+        I915_WRITE(GEN6_RP_DOWN_EI, 350000);
 
         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
         I915_WRITE(GEN6_RP_CONTROL,
@@ -3963,6 +3956,7 @@ static void __gen6_gt_force_wake_get(struct drm_i915_private *dev_priv)
                 DRM_ERROR("Force wake wait timed out\n");
 
         I915_WRITE_NOTRACE(FORCEWAKE, 1);
+        POSTING_READ(FORCEWAKE);
 
         if (wait_for_atomic_us((I915_READ_NOTRACE(forcewake_ack) & 1), 500))
                 DRM_ERROR("Force wake wait timed out\n");
@@ -3983,6 +3977,7 @@ static void __gen6_gt_force_wake_mt_get(struct drm_i915_private *dev_priv)
                 DRM_ERROR("Force wake wait timed out\n");
 
         I915_WRITE_NOTRACE(FORCEWAKE_MT, _MASKED_BIT_ENABLE(1));
+        POSTING_READ(FORCEWAKE_MT);
 
         if (wait_for_atomic_us((I915_READ_NOTRACE(forcewake_ack) & 1), 500))
                 DRM_ERROR("Force wake wait timed out\n");
@@ -4018,14 +4013,14 @@ void gen6_gt_check_fifodbg(struct drm_i915_private *dev_priv)
 static void __gen6_gt_force_wake_put(struct drm_i915_private *dev_priv)
 {
         I915_WRITE_NOTRACE(FORCEWAKE, 0);
-        /* The below doubles as a POSTING_READ */
+        POSTING_READ(FORCEWAKE);
         gen6_gt_check_fifodbg(dev_priv);
 }
 
 static void __gen6_gt_force_wake_mt_put(struct drm_i915_private *dev_priv)
 {
         I915_WRITE_NOTRACE(FORCEWAKE_MT, _MASKED_BIT_DISABLE(1));
-        /* The below doubles as a POSTING_READ */
+        POSTING_READ(FORCEWAKE_MT);
         gen6_gt_check_fifodbg(dev_priv);
 }
 
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index bf0195a96d53..e2a73b38abe9 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -227,31 +227,36 @@ gen6_render_ring_flush(struct intel_ring_buffer *ring,
          * number of bits based on the write domains has little performance
          * impact.
          */
-        flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
-        flags |= PIPE_CONTROL_TLB_INVALIDATE;
-        flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
-        flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
-        flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
-        flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
-        flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
-        flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
-        /*
-         * Ensure that any following seqno writes only happen when the render
-         * cache is indeed flushed (but only if the caller actually wants that).
-         */
-        if (flush_domains)
+        if (flush_domains) {
+                flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
+                flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
+                /*
+                 * Ensure that any following seqno writes only happen
+                 * when the render cache is indeed flushed.
+                 */
                 flags |= PIPE_CONTROL_CS_STALL;
+        }
+        if (invalidate_domains) {
+                flags |= PIPE_CONTROL_TLB_INVALIDATE;
+                flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
+                flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
+                flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
+                flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
+                flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
+                /*
+                 * TLB invalidate requires a post-sync write.
+                 */
+                flags |= PIPE_CONTROL_QW_WRITE;
+        }
 
-        ret = intel_ring_begin(ring, 6);
+        ret = intel_ring_begin(ring, 4);
         if (ret)
                 return ret;
 
-        intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
+        intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
         intel_ring_emit(ring, flags);
         intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT);
-        intel_ring_emit(ring, 0); /* lower dword */
-        intel_ring_emit(ring, 0); /* uppwer dword */
-        intel_ring_emit(ring, MI_NOOP);
+        intel_ring_emit(ring, 0);
         intel_ring_advance(ring);
 
         return 0;
@@ -289,8 +294,6 @@ static int init_ring_common(struct intel_ring_buffer *ring)
         I915_WRITE_HEAD(ring, 0);
         ring->write_tail(ring, 0);
 
-        /* Initialize the ring. */
-        I915_WRITE_START(ring, obj->gtt_offset);
         head = I915_READ_HEAD(ring) & HEAD_ADDR;
 
         /* G45 ring initialization fails to reset head to zero */
@@ -316,6 +319,11 @@ static int init_ring_common(struct intel_ring_buffer *ring)
                 }
         }
 
+        /* Initialize the ring. This must happen _after_ we've cleared the ring
+         * registers with the above sequence (the readback of the HEAD registers
+         * also enforces ordering), otherwise the hw might lose the new ring
+         * register values. */
+        I915_WRITE_START(ring, obj->gtt_offset);
         I915_WRITE_CTL(ring,
                         ((ring->size - PAGE_SIZE) & RING_NR_PAGES)
                         | RING_VALID);
diff --git a/drivers/gpu/drm/i915/intel_sdvo.c b/drivers/gpu/drm/i915/intel_sdvo.c
index 26a6a4d0d078..d81bb0bf2885 100644
--- a/drivers/gpu/drm/i915/intel_sdvo.c
+++ b/drivers/gpu/drm/i915/intel_sdvo.c
@@ -444,13 +444,16 @@ static bool intel_sdvo_write_cmd(struct intel_sdvo *intel_sdvo, u8 cmd,
         struct i2c_msg *msgs;
         int i, ret = true;
 
+        /* Would be simpler to allocate both in one go ? */        
         buf = (u8 *)kzalloc(args_len * 2 + 2, GFP_KERNEL);
         if (!buf)
                 return false;
 
         msgs = kcalloc(args_len + 3, sizeof(*msgs), GFP_KERNEL);
-        if (!msgs)
+        if (!msgs) {
+                kfree(buf);
                 return false;
+        }
 
         intel_sdvo_debug_write(intel_sdvo, cmd, args, args_len);
 
@@ -1689,6 +1692,7 @@ static bool intel_sdvo_detect_hdmi_audio(struct drm_connector *connector)
         edid = intel_sdvo_get_edid(connector);
         if (edid != NULL && edid->input & DRM_EDID_INPUT_DIGITAL)
                 has_audio = drm_detect_monitor_audio(edid);
+        kfree(edid);
 
         return has_audio;
 }