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-rw-r--r--drivers/gpu/drm/i915/i915_debugfs.c131
-rw-r--r--drivers/gpu/drm/i915/i915_dma.c60
-rw-r--r--drivers/gpu/drm/i915/i915_drv.c68
-rw-r--r--drivers/gpu/drm/i915/i915_drv.h113
-rw-r--r--drivers/gpu/drm/i915/i915_gem.c36
-rw-r--r--drivers/gpu/drm/i915/i915_gem_gtt.c35
-rw-r--r--drivers/gpu/drm/i915/i915_gem_tiling.c2
-rw-r--r--drivers/gpu/drm/i915/i915_irq.c311
-rw-r--r--drivers/gpu/drm/i915/i915_reg.h35
-rw-r--r--drivers/gpu/drm/i915/i915_suspend.c3
-rw-r--r--drivers/gpu/drm/i915/intel_bios.c6
-rw-r--r--drivers/gpu/drm/i915/intel_crt.c24
-rw-r--r--drivers/gpu/drm/i915/intel_display.c2303
-rw-r--r--drivers/gpu/drm/i915/intel_drv.h19
-rw-r--r--drivers/gpu/drm/i915/intel_ringbuffer.c88
-rw-r--r--drivers/gpu/drm/i915/intel_ringbuffer.h35
-rw-r--r--drivers/gpu/drm/i915/intel_sdvo.c10
-rw-r--r--drivers/gpu/drm/i915/intel_tv.c13
18 files changed, 2111 insertions, 1181 deletions
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 87c8e29465e3..51c2257b11e6 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -106,11 +106,12 @@ static const char *get_tiling_flag(struct drm_i915_gem_object *obj)
106 } 106 }
107} 107}
108 108
109static const char *agp_type_str(int type) 109static const char *cache_level_str(int type)
110{ 110{
111 switch (type) { 111 switch (type) {
112 case 0: return " uncached"; 112 case I915_CACHE_NONE: return " uncached";
113 case 1: return " snooped"; 113 case I915_CACHE_LLC: return " snooped (LLC)";
114 case I915_CACHE_LLC_MLC: return " snooped (LLC+MLC)";
114 default: return ""; 115 default: return "";
115 } 116 }
116} 117}
@@ -127,7 +128,7 @@ describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj)
127 obj->base.write_domain, 128 obj->base.write_domain,
128 obj->last_rendering_seqno, 129 obj->last_rendering_seqno,
129 obj->last_fenced_seqno, 130 obj->last_fenced_seqno,
130 agp_type_str(obj->agp_type == AGP_USER_CACHED_MEMORY), 131 cache_level_str(obj->cache_level),
131 obj->dirty ? " dirty" : "", 132 obj->dirty ? " dirty" : "",
132 obj->madv == I915_MADV_DONTNEED ? " purgeable" : ""); 133 obj->madv == I915_MADV_DONTNEED ? " purgeable" : "");
133 if (obj->base.name) 134 if (obj->base.name)
@@ -714,7 +715,7 @@ static void print_error_buffers(struct seq_file *m,
714 dirty_flag(err->dirty), 715 dirty_flag(err->dirty),
715 purgeable_flag(err->purgeable), 716 purgeable_flag(err->purgeable),
716 ring_str(err->ring), 717 ring_str(err->ring),
717 agp_type_str(err->agp_type)); 718 cache_level_str(err->cache_level));
718 719
719 if (err->name) 720 if (err->name)
720 seq_printf(m, " (name: %d)", err->name); 721 seq_printf(m, " (name: %d)", err->name);
@@ -852,6 +853,7 @@ static int i915_cur_delayinfo(struct seq_file *m, void *unused)
852 struct drm_info_node *node = (struct drm_info_node *) m->private; 853 struct drm_info_node *node = (struct drm_info_node *) m->private;
853 struct drm_device *dev = node->minor->dev; 854 struct drm_device *dev = node->minor->dev;
854 drm_i915_private_t *dev_priv = dev->dev_private; 855 drm_i915_private_t *dev_priv = dev->dev_private;
856 int ret;
855 857
856 if (IS_GEN5(dev)) { 858 if (IS_GEN5(dev)) {
857 u16 rgvswctl = I915_READ16(MEMSWCTL); 859 u16 rgvswctl = I915_READ16(MEMSWCTL);
@@ -873,7 +875,11 @@ static int i915_cur_delayinfo(struct seq_file *m, void *unused)
873 int max_freq; 875 int max_freq;
874 876
875 /* RPSTAT1 is in the GT power well */ 877 /* RPSTAT1 is in the GT power well */
876 __gen6_gt_force_wake_get(dev_priv); 878 ret = mutex_lock_interruptible(&dev->struct_mutex);
879 if (ret)
880 return ret;
881
882 gen6_gt_force_wake_get(dev_priv);
877 883
878 rpstat = I915_READ(GEN6_RPSTAT1); 884 rpstat = I915_READ(GEN6_RPSTAT1);
879 rpupei = I915_READ(GEN6_RP_CUR_UP_EI); 885 rpupei = I915_READ(GEN6_RP_CUR_UP_EI);
@@ -883,6 +889,9 @@ static int i915_cur_delayinfo(struct seq_file *m, void *unused)
883 rpcurdown = I915_READ(GEN6_RP_CUR_DOWN); 889 rpcurdown = I915_READ(GEN6_RP_CUR_DOWN);
884 rpprevdown = I915_READ(GEN6_RP_PREV_DOWN); 890 rpprevdown = I915_READ(GEN6_RP_PREV_DOWN);
885 891
892 gen6_gt_force_wake_put(dev_priv);
893 mutex_unlock(&dev->struct_mutex);
894
886 seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status); 895 seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);
887 seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat); 896 seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat);
888 seq_printf(m, "Render p-state ratio: %d\n", 897 seq_printf(m, "Render p-state ratio: %d\n",
@@ -917,8 +926,6 @@ static int i915_cur_delayinfo(struct seq_file *m, void *unused)
917 max_freq = rp_state_cap & 0xff; 926 max_freq = rp_state_cap & 0xff;
918 seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n", 927 seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n",
919 max_freq * 50); 928 max_freq * 50);
920
921 __gen6_gt_force_wake_put(dev_priv);
922 } else { 929 } else {
923 seq_printf(m, "no P-state info available\n"); 930 seq_printf(m, "no P-state info available\n");
924 } 931 }
@@ -1058,6 +1065,9 @@ static int i915_fbc_status(struct seq_file *m, void *unused)
1058 case FBC_MULTIPLE_PIPES: 1065 case FBC_MULTIPLE_PIPES:
1059 seq_printf(m, "multiple pipes are enabled"); 1066 seq_printf(m, "multiple pipes are enabled");
1060 break; 1067 break;
1068 case FBC_MODULE_PARAM:
1069 seq_printf(m, "disabled per module param (default off)");
1070 break;
1061 default: 1071 default:
1062 seq_printf(m, "unknown reason"); 1072 seq_printf(m, "unknown reason");
1063 } 1073 }
@@ -1186,6 +1196,42 @@ static int i915_gem_framebuffer_info(struct seq_file *m, void *data)
1186 return 0; 1196 return 0;
1187} 1197}
1188 1198
1199static int i915_context_status(struct seq_file *m, void *unused)
1200{
1201 struct drm_info_node *node = (struct drm_info_node *) m->private;
1202 struct drm_device *dev = node->minor->dev;
1203 drm_i915_private_t *dev_priv = dev->dev_private;
1204 int ret;
1205
1206 ret = mutex_lock_interruptible(&dev->mode_config.mutex);
1207 if (ret)
1208 return ret;
1209
1210 seq_printf(m, "power context ");
1211 describe_obj(m, dev_priv->pwrctx);
1212 seq_printf(m, "\n");
1213
1214 seq_printf(m, "render context ");
1215 describe_obj(m, dev_priv->renderctx);
1216 seq_printf(m, "\n");
1217
1218 mutex_unlock(&dev->mode_config.mutex);
1219
1220 return 0;
1221}
1222
1223static int i915_gen6_forcewake_count_info(struct seq_file *m, void *data)
1224{
1225 struct drm_info_node *node = (struct drm_info_node *) m->private;
1226 struct drm_device *dev = node->minor->dev;
1227 struct drm_i915_private *dev_priv = dev->dev_private;
1228
1229 seq_printf(m, "forcewake count = %d\n",
1230 atomic_read(&dev_priv->forcewake_count));
1231
1232 return 0;
1233}
1234
1189static int 1235static int
1190i915_wedged_open(struct inode *inode, 1236i915_wedged_open(struct inode *inode,
1191 struct file *filp) 1237 struct file *filp)
@@ -1288,6 +1334,67 @@ static int i915_wedged_create(struct dentry *root, struct drm_minor *minor)
1288 return drm_add_fake_info_node(minor, ent, &i915_wedged_fops); 1334 return drm_add_fake_info_node(minor, ent, &i915_wedged_fops);
1289} 1335}
1290 1336
1337static int i915_forcewake_open(struct inode *inode, struct file *file)
1338{
1339 struct drm_device *dev = inode->i_private;
1340 struct drm_i915_private *dev_priv = dev->dev_private;
1341 int ret;
1342
1343 if (!IS_GEN6(dev))
1344 return 0;
1345
1346 ret = mutex_lock_interruptible(&dev->struct_mutex);
1347 if (ret)
1348 return ret;
1349 gen6_gt_force_wake_get(dev_priv);
1350 mutex_unlock(&dev->struct_mutex);
1351
1352 return 0;
1353}
1354
1355int i915_forcewake_release(struct inode *inode, struct file *file)
1356{
1357 struct drm_device *dev = inode->i_private;
1358 struct drm_i915_private *dev_priv = dev->dev_private;
1359
1360 if (!IS_GEN6(dev))
1361 return 0;
1362
1363 /*
1364 * It's bad that we can potentially hang userspace if struct_mutex gets
1365 * forever stuck. However, if we cannot acquire this lock it means that
1366 * almost certainly the driver has hung, is not unload-able. Therefore
1367 * hanging here is probably a minor inconvenience not to be seen my
1368 * almost every user.
1369 */
1370 mutex_lock(&dev->struct_mutex);
1371 gen6_gt_force_wake_put(dev_priv);
1372 mutex_unlock(&dev->struct_mutex);
1373
1374 return 0;
1375}
1376
1377static const struct file_operations i915_forcewake_fops = {
1378 .owner = THIS_MODULE,
1379 .open = i915_forcewake_open,
1380 .release = i915_forcewake_release,
1381};
1382
1383static int i915_forcewake_create(struct dentry *root, struct drm_minor *minor)
1384{
1385 struct drm_device *dev = minor->dev;
1386 struct dentry *ent;
1387
1388 ent = debugfs_create_file("i915_forcewake_user",
1389 S_IRUSR,
1390 root, dev,
1391 &i915_forcewake_fops);
1392 if (IS_ERR(ent))
1393 return PTR_ERR(ent);
1394
1395 return drm_add_fake_info_node(minor, ent, &i915_forcewake_fops);
1396}
1397
1291static struct drm_info_list i915_debugfs_list[] = { 1398static struct drm_info_list i915_debugfs_list[] = {
1292 {"i915_capabilities", i915_capabilities, 0}, 1399 {"i915_capabilities", i915_capabilities, 0},
1293 {"i915_gem_objects", i915_gem_object_info, 0}, 1400 {"i915_gem_objects", i915_gem_object_info, 0},
@@ -1324,6 +1431,8 @@ static struct drm_info_list i915_debugfs_list[] = {
1324 {"i915_sr_status", i915_sr_status, 0}, 1431 {"i915_sr_status", i915_sr_status, 0},
1325 {"i915_opregion", i915_opregion, 0}, 1432 {"i915_opregion", i915_opregion, 0},
1326 {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0}, 1433 {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0},
1434 {"i915_context_status", i915_context_status, 0},
1435 {"i915_gen6_forcewake_count", i915_gen6_forcewake_count_info, 0},
1327}; 1436};
1328#define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list) 1437#define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)
1329 1438
@@ -1335,6 +1444,10 @@ int i915_debugfs_init(struct drm_minor *minor)
1335 if (ret) 1444 if (ret)
1336 return ret; 1445 return ret;
1337 1446
1447 ret = i915_forcewake_create(minor->debugfs_root, minor);
1448 if (ret)
1449 return ret;
1450
1338 return drm_debugfs_create_files(i915_debugfs_list, 1451 return drm_debugfs_create_files(i915_debugfs_list,
1339 I915_DEBUGFS_ENTRIES, 1452 I915_DEBUGFS_ENTRIES,
1340 minor->debugfs_root, minor); 1453 minor->debugfs_root, minor);
@@ -1344,6 +1457,8 @@ void i915_debugfs_cleanup(struct drm_minor *minor)
1344{ 1457{
1345 drm_debugfs_remove_files(i915_debugfs_list, 1458 drm_debugfs_remove_files(i915_debugfs_list,
1346 I915_DEBUGFS_ENTRIES, minor); 1459 I915_DEBUGFS_ENTRIES, minor);
1460 drm_debugfs_remove_files((struct drm_info_list *) &i915_forcewake_fops,
1461 1, minor);
1347 drm_debugfs_remove_files((struct drm_info_list *) &i915_wedged_fops, 1462 drm_debugfs_remove_files((struct drm_info_list *) &i915_wedged_fops,
1348 1, minor); 1463 1, minor);
1349} 1464}
diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index 12876f2795d2..0239e9974bf2 100644
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@ -571,7 +571,7 @@ static int i915_quiescent(struct drm_device *dev)
571 struct intel_ring_buffer *ring = LP_RING(dev->dev_private); 571 struct intel_ring_buffer *ring = LP_RING(dev->dev_private);
572 572
573 i915_kernel_lost_context(dev); 573 i915_kernel_lost_context(dev);
574 return intel_wait_ring_buffer(ring, ring->size - 8); 574 return intel_wait_ring_idle(ring);
575} 575}
576 576
577static int i915_flush_ioctl(struct drm_device *dev, void *data, 577static int i915_flush_ioctl(struct drm_device *dev, void *data,
@@ -1176,11 +1176,11 @@ static bool i915_switcheroo_can_switch(struct pci_dev *pdev)
1176 return can_switch; 1176 return can_switch;
1177} 1177}
1178 1178
1179static int i915_load_modeset_init(struct drm_device *dev) 1179static int i915_load_gem_init(struct drm_device *dev)
1180{ 1180{
1181 struct drm_i915_private *dev_priv = dev->dev_private; 1181 struct drm_i915_private *dev_priv = dev->dev_private;
1182 unsigned long prealloc_size, gtt_size, mappable_size; 1182 unsigned long prealloc_size, gtt_size, mappable_size;
1183 int ret = 0; 1183 int ret;
1184 1184
1185 prealloc_size = dev_priv->mm.gtt->stolen_size; 1185 prealloc_size = dev_priv->mm.gtt->stolen_size;
1186 gtt_size = dev_priv->mm.gtt->gtt_total_entries << PAGE_SHIFT; 1186 gtt_size = dev_priv->mm.gtt->gtt_total_entries << PAGE_SHIFT;
@@ -1204,7 +1204,7 @@ static int i915_load_modeset_init(struct drm_device *dev)
1204 ret = i915_gem_init_ringbuffer(dev); 1204 ret = i915_gem_init_ringbuffer(dev);
1205 mutex_unlock(&dev->struct_mutex); 1205 mutex_unlock(&dev->struct_mutex);
1206 if (ret) 1206 if (ret)
1207 goto out; 1207 return ret;
1208 1208
1209 /* Try to set up FBC with a reasonable compressed buffer size */ 1209 /* Try to set up FBC with a reasonable compressed buffer size */
1210 if (I915_HAS_FBC(dev) && i915_powersave) { 1210 if (I915_HAS_FBC(dev) && i915_powersave) {
@@ -1222,6 +1222,13 @@ static int i915_load_modeset_init(struct drm_device *dev)
1222 1222
1223 /* Allow hardware batchbuffers unless told otherwise. */ 1223 /* Allow hardware batchbuffers unless told otherwise. */
1224 dev_priv->allow_batchbuffer = 1; 1224 dev_priv->allow_batchbuffer = 1;
1225 return 0;
1226}
1227
1228static int i915_load_modeset_init(struct drm_device *dev)
1229{
1230 struct drm_i915_private *dev_priv = dev->dev_private;
1231 int ret;
1225 1232
1226 ret = intel_parse_bios(dev); 1233 ret = intel_parse_bios(dev);
1227 if (ret) 1234 if (ret)
@@ -1236,7 +1243,7 @@ static int i915_load_modeset_init(struct drm_device *dev)
1236 */ 1243 */
1237 ret = vga_client_register(dev->pdev, dev, NULL, i915_vga_set_decode); 1244 ret = vga_client_register(dev->pdev, dev, NULL, i915_vga_set_decode);
1238 if (ret && ret != -ENODEV) 1245 if (ret && ret != -ENODEV)
1239 goto cleanup_ringbuffer; 1246 goto out;
1240 1247
1241 intel_register_dsm_handler(); 1248 intel_register_dsm_handler();
1242 1249
@@ -1253,10 +1260,40 @@ static int i915_load_modeset_init(struct drm_device *dev)
1253 1260
1254 intel_modeset_init(dev); 1261 intel_modeset_init(dev);
1255 1262
1256 ret = drm_irq_install(dev); 1263 ret = i915_load_gem_init(dev);
1257 if (ret) 1264 if (ret)
1258 goto cleanup_vga_switcheroo; 1265 goto cleanup_vga_switcheroo;
1259 1266
1267 intel_modeset_gem_init(dev);
1268
1269 if (IS_IVYBRIDGE(dev)) {
1270 /* Share pre & uninstall handlers with ILK/SNB */
1271 dev->driver->irq_handler = ivybridge_irq_handler;
1272 dev->driver->irq_preinstall = ironlake_irq_preinstall;
1273 dev->driver->irq_postinstall = ivybridge_irq_postinstall;
1274 dev->driver->irq_uninstall = ironlake_irq_uninstall;
1275 dev->driver->enable_vblank = ivybridge_enable_vblank;
1276 dev->driver->disable_vblank = ivybridge_disable_vblank;
1277 } else if (HAS_PCH_SPLIT(dev)) {
1278 dev->driver->irq_handler = ironlake_irq_handler;
1279 dev->driver->irq_preinstall = ironlake_irq_preinstall;
1280 dev->driver->irq_postinstall = ironlake_irq_postinstall;
1281 dev->driver->irq_uninstall = ironlake_irq_uninstall;
1282 dev->driver->enable_vblank = ironlake_enable_vblank;
1283 dev->driver->disable_vblank = ironlake_disable_vblank;
1284 } else {
1285 dev->driver->irq_preinstall = i915_driver_irq_preinstall;
1286 dev->driver->irq_postinstall = i915_driver_irq_postinstall;
1287 dev->driver->irq_uninstall = i915_driver_irq_uninstall;
1288 dev->driver->irq_handler = i915_driver_irq_handler;
1289 dev->driver->enable_vblank = i915_enable_vblank;
1290 dev->driver->disable_vblank = i915_disable_vblank;
1291 }
1292
1293 ret = drm_irq_install(dev);
1294 if (ret)
1295 goto cleanup_gem;
1296
1260 /* Always safe in the mode setting case. */ 1297 /* Always safe in the mode setting case. */
1261 /* FIXME: do pre/post-mode set stuff in core KMS code */ 1298 /* FIXME: do pre/post-mode set stuff in core KMS code */
1262 dev->vblank_disable_allowed = 1; 1299 dev->vblank_disable_allowed = 1;
@@ -1274,14 +1311,14 @@ static int i915_load_modeset_init(struct drm_device *dev)
1274 1311
1275cleanup_irq: 1312cleanup_irq:
1276 drm_irq_uninstall(dev); 1313 drm_irq_uninstall(dev);
1314cleanup_gem:
1315 mutex_lock(&dev->struct_mutex);
1316 i915_gem_cleanup_ringbuffer(dev);
1317 mutex_unlock(&dev->struct_mutex);
1277cleanup_vga_switcheroo: 1318cleanup_vga_switcheroo:
1278 vga_switcheroo_unregister_client(dev->pdev); 1319 vga_switcheroo_unregister_client(dev->pdev);
1279cleanup_vga_client: 1320cleanup_vga_client:
1280 vga_client_register(dev->pdev, NULL, NULL, NULL); 1321 vga_client_register(dev->pdev, NULL, NULL, NULL);
1281cleanup_ringbuffer:
1282 mutex_lock(&dev->struct_mutex);
1283 i915_gem_cleanup_ringbuffer(dev);
1284 mutex_unlock(&dev->struct_mutex);
1285out: 1322out:
1286 return ret; 1323 return ret;
1287} 1324}
@@ -1982,7 +2019,7 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
1982 2019
1983 dev->driver->get_vblank_counter = i915_get_vblank_counter; 2020 dev->driver->get_vblank_counter = i915_get_vblank_counter;
1984 dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */ 2021 dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
1985 if (IS_G4X(dev) || IS_GEN5(dev) || IS_GEN6(dev)) { 2022 if (IS_G4X(dev) || IS_GEN5(dev) || IS_GEN6(dev) || IS_IVYBRIDGE(dev)) {
1986 dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */ 2023 dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
1987 dev->driver->get_vblank_counter = gm45_get_vblank_counter; 2024 dev->driver->get_vblank_counter = gm45_get_vblank_counter;
1988 } 2025 }
@@ -2025,6 +2062,7 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
2025 2062
2026 spin_lock_init(&dev_priv->irq_lock); 2063 spin_lock_init(&dev_priv->irq_lock);
2027 spin_lock_init(&dev_priv->error_lock); 2064 spin_lock_init(&dev_priv->error_lock);
2065 spin_lock_init(&dev_priv->rps_lock);
2028 2066
2029 if (IS_MOBILE(dev) || !IS_GEN2(dev)) 2067 if (IS_MOBILE(dev) || !IS_GEN2(dev))
2030 dev_priv->num_pipe = 2; 2068 dev_priv->num_pipe = 2;
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 32d1b3e829c8..0defd4270594 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -52,9 +52,12 @@ module_param_named(powersave, i915_powersave, int, 0600);
52unsigned int i915_semaphores = 0; 52unsigned int i915_semaphores = 0;
53module_param_named(semaphores, i915_semaphores, int, 0600); 53module_param_named(semaphores, i915_semaphores, int, 0600);
54 54
55unsigned int i915_enable_rc6 = 0; 55unsigned int i915_enable_rc6 = 1;
56module_param_named(i915_enable_rc6, i915_enable_rc6, int, 0600); 56module_param_named(i915_enable_rc6, i915_enable_rc6, int, 0600);
57 57
58unsigned int i915_enable_fbc = 0;
59module_param_named(i915_enable_fbc, i915_enable_fbc, int, 0600);
60
58unsigned int i915_lvds_downclock = 0; 61unsigned int i915_lvds_downclock = 0;
59module_param_named(lvds_downclock, i915_lvds_downclock, int, 0400); 62module_param_named(lvds_downclock, i915_lvds_downclock, int, 0400);
60 63
@@ -169,7 +172,7 @@ static const struct intel_device_info intel_ironlake_d_info = {
169static const struct intel_device_info intel_ironlake_m_info = { 172static const struct intel_device_info intel_ironlake_m_info = {
170 .gen = 5, .is_mobile = 1, 173 .gen = 5, .is_mobile = 1,
171 .need_gfx_hws = 1, .has_hotplug = 1, 174 .need_gfx_hws = 1, .has_hotplug = 1,
172 .has_fbc = 0, /* disabled due to buggy hardware */ 175 .has_fbc = 1,
173 .has_bsd_ring = 1, 176 .has_bsd_ring = 1,
174}; 177};
175 178
@@ -188,6 +191,21 @@ static const struct intel_device_info intel_sandybridge_m_info = {
188 .has_blt_ring = 1, 191 .has_blt_ring = 1,
189}; 192};
190 193
194static const struct intel_device_info intel_ivybridge_d_info = {
195 .is_ivybridge = 1, .gen = 7,
196 .need_gfx_hws = 1, .has_hotplug = 1,
197 .has_bsd_ring = 1,
198 .has_blt_ring = 1,
199};
200
201static const struct intel_device_info intel_ivybridge_m_info = {
202 .is_ivybridge = 1, .gen = 7, .is_mobile = 1,
203 .need_gfx_hws = 1, .has_hotplug = 1,
204 .has_fbc = 0, /* FBC is not enabled on Ivybridge mobile yet */
205 .has_bsd_ring = 1,
206 .has_blt_ring = 1,
207};
208
191static const struct pci_device_id pciidlist[] = { /* aka */ 209static const struct pci_device_id pciidlist[] = { /* aka */
192 INTEL_VGA_DEVICE(0x3577, &intel_i830_info), /* I830_M */ 210 INTEL_VGA_DEVICE(0x3577, &intel_i830_info), /* I830_M */
193 INTEL_VGA_DEVICE(0x2562, &intel_845g_info), /* 845_G */ 211 INTEL_VGA_DEVICE(0x2562, &intel_845g_info), /* 845_G */
@@ -227,6 +245,11 @@ static const struct pci_device_id pciidlist[] = { /* aka */
227 INTEL_VGA_DEVICE(0x0116, &intel_sandybridge_m_info), 245 INTEL_VGA_DEVICE(0x0116, &intel_sandybridge_m_info),
228 INTEL_VGA_DEVICE(0x0126, &intel_sandybridge_m_info), 246 INTEL_VGA_DEVICE(0x0126, &intel_sandybridge_m_info),
229 INTEL_VGA_DEVICE(0x010A, &intel_sandybridge_d_info), 247 INTEL_VGA_DEVICE(0x010A, &intel_sandybridge_d_info),
248 INTEL_VGA_DEVICE(0x0156, &intel_ivybridge_m_info), /* GT1 mobile */
249 INTEL_VGA_DEVICE(0x0166, &intel_ivybridge_m_info), /* GT2 mobile */
250 INTEL_VGA_DEVICE(0x0152, &intel_ivybridge_d_info), /* GT1 desktop */
251 INTEL_VGA_DEVICE(0x0162, &intel_ivybridge_d_info), /* GT2 desktop */
252 INTEL_VGA_DEVICE(0x015a, &intel_ivybridge_d_info), /* GT1 server */
230 {0, 0, 0} 253 {0, 0, 0}
231}; 254};
232 255
@@ -235,7 +258,9 @@ MODULE_DEVICE_TABLE(pci, pciidlist);
235#endif 258#endif
236 259
237#define INTEL_PCH_DEVICE_ID_MASK 0xff00 260#define INTEL_PCH_DEVICE_ID_MASK 0xff00
261#define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00
238#define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00 262#define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00
263#define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00
239 264
240void intel_detect_pch (struct drm_device *dev) 265void intel_detect_pch (struct drm_device *dev)
241{ 266{
@@ -254,16 +279,23 @@ void intel_detect_pch (struct drm_device *dev)
254 int id; 279 int id;
255 id = pch->device & INTEL_PCH_DEVICE_ID_MASK; 280 id = pch->device & INTEL_PCH_DEVICE_ID_MASK;
256 281
257 if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) { 282 if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) {
283 dev_priv->pch_type = PCH_IBX;
284 DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
285 } else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) {
258 dev_priv->pch_type = PCH_CPT; 286 dev_priv->pch_type = PCH_CPT;
259 DRM_DEBUG_KMS("Found CougarPoint PCH\n"); 287 DRM_DEBUG_KMS("Found CougarPoint PCH\n");
288 } else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) {
289 /* PantherPoint is CPT compatible */
290 dev_priv->pch_type = PCH_CPT;
291 DRM_DEBUG_KMS("Found PatherPoint PCH\n");
260 } 292 }
261 } 293 }
262 pci_dev_put(pch); 294 pci_dev_put(pch);
263 } 295 }
264} 296}
265 297
266void __gen6_gt_force_wake_get(struct drm_i915_private *dev_priv) 298static void __gen6_gt_force_wake_get(struct drm_i915_private *dev_priv)
267{ 299{
268 int count; 300 int count;
269 301
@@ -279,12 +311,38 @@ void __gen6_gt_force_wake_get(struct drm_i915_private *dev_priv)
279 udelay(10); 311 udelay(10);
280} 312}
281 313
282void __gen6_gt_force_wake_put(struct drm_i915_private *dev_priv) 314/*
315 * Generally this is called implicitly by the register read function. However,
316 * if some sequence requires the GT to not power down then this function should
317 * be called at the beginning of the sequence followed by a call to
318 * gen6_gt_force_wake_put() at the end of the sequence.
319 */
320void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv)
321{
322 WARN_ON(!mutex_is_locked(&dev_priv->dev->struct_mutex));
323
324 /* Forcewake is atomic in case we get in here without the lock */
325 if (atomic_add_return(1, &dev_priv->forcewake_count) == 1)
326 __gen6_gt_force_wake_get(dev_priv);
327}
328
329static void __gen6_gt_force_wake_put(struct drm_i915_private *dev_priv)
283{ 330{
284 I915_WRITE_NOTRACE(FORCEWAKE, 0); 331 I915_WRITE_NOTRACE(FORCEWAKE, 0);
285 POSTING_READ(FORCEWAKE); 332 POSTING_READ(FORCEWAKE);
286} 333}
287 334
335/*
336 * see gen6_gt_force_wake_get()
337 */
338void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv)
339{
340 WARN_ON(!mutex_is_locked(&dev_priv->dev->struct_mutex));
341
342 if (atomic_dec_and_test(&dev_priv->forcewake_count))
343 __gen6_gt_force_wake_put(dev_priv);
344}
345
288void __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv) 346void __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv)
289{ 347{
290 int loop = 500; 348 int loop = 500;
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 1c1b27c97e5c..ee660355ae68 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -188,7 +188,7 @@ struct drm_i915_error_state {
188 u32 dirty:1; 188 u32 dirty:1;
189 u32 purgeable:1; 189 u32 purgeable:1;
190 u32 ring:4; 190 u32 ring:4;
191 u32 agp_type:1; 191 u32 cache_level:2;
192 } *active_bo, *pinned_bo; 192 } *active_bo, *pinned_bo;
193 u32 active_bo_count, pinned_bo_count; 193 u32 active_bo_count, pinned_bo_count;
194 struct intel_overlay_error_state *overlay; 194 struct intel_overlay_error_state *overlay;
@@ -203,12 +203,19 @@ struct drm_i915_display_funcs {
203 int (*get_display_clock_speed)(struct drm_device *dev); 203 int (*get_display_clock_speed)(struct drm_device *dev);
204 int (*get_fifo_size)(struct drm_device *dev, int plane); 204 int (*get_fifo_size)(struct drm_device *dev, int plane);
205 void (*update_wm)(struct drm_device *dev); 205 void (*update_wm)(struct drm_device *dev);
206 int (*crtc_mode_set)(struct drm_crtc *crtc,
207 struct drm_display_mode *mode,
208 struct drm_display_mode *adjusted_mode,
209 int x, int y,
210 struct drm_framebuffer *old_fb);
211 void (*fdi_link_train)(struct drm_crtc *crtc);
212 void (*init_clock_gating)(struct drm_device *dev);
213 void (*init_pch_clock_gating)(struct drm_device *dev);
206 /* clock updates for mode set */ 214 /* clock updates for mode set */
207 /* cursor updates */ 215 /* cursor updates */
208 /* render clock increase/decrease */ 216 /* render clock increase/decrease */
209 /* display clock increase/decrease */ 217 /* display clock increase/decrease */
210 /* pll clock increase/decrease */ 218 /* pll clock increase/decrease */
211 /* clock gating init */
212}; 219};
213 220
214struct intel_device_info { 221struct intel_device_info {
@@ -223,6 +230,7 @@ struct intel_device_info {
223 u8 is_pineview : 1; 230 u8 is_pineview : 1;
224 u8 is_broadwater : 1; 231 u8 is_broadwater : 1;
225 u8 is_crestline : 1; 232 u8 is_crestline : 1;
233 u8 is_ivybridge : 1;
226 u8 has_fbc : 1; 234 u8 has_fbc : 1;
227 u8 has_pipe_cxsr : 1; 235 u8 has_pipe_cxsr : 1;
228 u8 has_hotplug : 1; 236 u8 has_hotplug : 1;
@@ -242,6 +250,7 @@ enum no_fbc_reason {
242 FBC_BAD_PLANE, /* fbc not supported on plane */ 250 FBC_BAD_PLANE, /* fbc not supported on plane */
243 FBC_NOT_TILED, /* buffer not tiled */ 251 FBC_NOT_TILED, /* buffer not tiled */
244 FBC_MULTIPLE_PIPES, /* more than one pipe active */ 252 FBC_MULTIPLE_PIPES, /* more than one pipe active */
253 FBC_MODULE_PARAM,
245}; 254};
246 255
247enum intel_pch { 256enum intel_pch {
@@ -676,6 +685,10 @@ typedef struct drm_i915_private {
676 685
677 bool mchbar_need_disable; 686 bool mchbar_need_disable;
678 687
688 struct work_struct rps_work;
689 spinlock_t rps_lock;
690 u32 pm_iir;
691
679 u8 cur_delay; 692 u8 cur_delay;
680 u8 min_delay; 693 u8 min_delay;
681 u8 max_delay; 694 u8 max_delay;
@@ -703,8 +716,16 @@ typedef struct drm_i915_private {
703 struct intel_fbdev *fbdev; 716 struct intel_fbdev *fbdev;
704 717
705 struct drm_property *broadcast_rgb_property; 718 struct drm_property *broadcast_rgb_property;
719
720 atomic_t forcewake_count;
706} drm_i915_private_t; 721} drm_i915_private_t;
707 722
723enum i915_cache_level {
724 I915_CACHE_NONE,
725 I915_CACHE_LLC,
726 I915_CACHE_LLC_MLC, /* gen6+ */
727};
728
708struct drm_i915_gem_object { 729struct drm_i915_gem_object {
709 struct drm_gem_object base; 730 struct drm_gem_object base;
710 731
@@ -791,6 +812,8 @@ struct drm_i915_gem_object {
791 unsigned int pending_fenced_gpu_access:1; 812 unsigned int pending_fenced_gpu_access:1;
792 unsigned int fenced_gpu_access:1; 813 unsigned int fenced_gpu_access:1;
793 814
815 unsigned int cache_level:2;
816
794 struct page **pages; 817 struct page **pages;
795 818
796 /** 819 /**
@@ -827,8 +850,6 @@ struct drm_i915_gem_object {
827 /** Record of address bit 17 of each page at last unbind. */ 850 /** Record of address bit 17 of each page at last unbind. */
828 unsigned long *bit_17; 851 unsigned long *bit_17;
829 852
830 /** AGP mapping type (AGP_USER_MEMORY or AGP_USER_CACHED_MEMORY */
831 uint32_t agp_type;
832 853
833 /** 854 /**
834 * If present, while GEM_DOMAIN_CPU is in the read domain this array 855 * If present, while GEM_DOMAIN_CPU is in the read domain this array
@@ -915,13 +936,21 @@ enum intel_chip_family {
915#define IS_G33(dev) (INTEL_INFO(dev)->is_g33) 936#define IS_G33(dev) (INTEL_INFO(dev)->is_g33)
916#define IS_IRONLAKE_D(dev) ((dev)->pci_device == 0x0042) 937#define IS_IRONLAKE_D(dev) ((dev)->pci_device == 0x0042)
917#define IS_IRONLAKE_M(dev) ((dev)->pci_device == 0x0046) 938#define IS_IRONLAKE_M(dev) ((dev)->pci_device == 0x0046)
939#define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge)
918#define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile) 940#define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile)
919 941
942/*
943 * The genX designation typically refers to the render engine, so render
944 * capability related checks should use IS_GEN, while display and other checks
945 * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
946 * chips, etc.).
947 */
920#define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2) 948#define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2)
921#define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3) 949#define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3)
922#define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4) 950#define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4)
923#define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5) 951#define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5)
924#define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6) 952#define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6)
953#define IS_GEN7(dev) (INTEL_INFO(dev)->gen == 7)
925 954
926#define HAS_BSD(dev) (INTEL_INFO(dev)->has_bsd_ring) 955#define HAS_BSD(dev) (INTEL_INFO(dev)->has_bsd_ring)
927#define HAS_BLT(dev) (INTEL_INFO(dev)->has_blt_ring) 956#define HAS_BLT(dev) (INTEL_INFO(dev)->has_blt_ring)
@@ -948,8 +977,8 @@ enum intel_chip_family {
948#define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr) 977#define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
949#define I915_HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc) 978#define I915_HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
950 979
951#define HAS_PCH_SPLIT(dev) (IS_GEN5(dev) || IS_GEN6(dev)) 980#define HAS_PCH_SPLIT(dev) (IS_GEN5(dev) || IS_GEN6(dev) || IS_IVYBRIDGE(dev))
952#define HAS_PIPE_CONTROL(dev) (IS_GEN5(dev) || IS_GEN6(dev)) 981#define HAS_PIPE_CONTROL(dev) (INTEL_INFO(dev)->gen >= 5)
953 982
954#define INTEL_PCH_TYPE(dev) (((struct drm_i915_private *)(dev)->dev_private)->pch_type) 983#define INTEL_PCH_TYPE(dev) (((struct drm_i915_private *)(dev)->dev_private)->pch_type)
955#define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT) 984#define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
@@ -967,6 +996,7 @@ extern unsigned int i915_lvds_downclock;
967extern unsigned int i915_panel_use_ssc; 996extern unsigned int i915_panel_use_ssc;
968extern int i915_vbt_sdvo_panel_type; 997extern int i915_vbt_sdvo_panel_type;
969extern unsigned int i915_enable_rc6; 998extern unsigned int i915_enable_rc6;
999extern unsigned int i915_enable_fbc;
970 1000
971extern int i915_suspend(struct drm_device *dev, pm_message_t state); 1001extern int i915_suspend(struct drm_device *dev, pm_message_t state);
972extern int i915_resume(struct drm_device *dev); 1002extern int i915_resume(struct drm_device *dev);
@@ -1010,12 +1040,27 @@ extern irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS);
1010extern void i915_driver_irq_preinstall(struct drm_device * dev); 1040extern void i915_driver_irq_preinstall(struct drm_device * dev);
1011extern int i915_driver_irq_postinstall(struct drm_device *dev); 1041extern int i915_driver_irq_postinstall(struct drm_device *dev);
1012extern void i915_driver_irq_uninstall(struct drm_device * dev); 1042extern void i915_driver_irq_uninstall(struct drm_device * dev);
1043
1044extern irqreturn_t ironlake_irq_handler(DRM_IRQ_ARGS);
1045extern void ironlake_irq_preinstall(struct drm_device *dev);
1046extern int ironlake_irq_postinstall(struct drm_device *dev);
1047extern void ironlake_irq_uninstall(struct drm_device *dev);
1048
1049extern irqreturn_t ivybridge_irq_handler(DRM_IRQ_ARGS);
1050extern void ivybridge_irq_preinstall(struct drm_device *dev);
1051extern int ivybridge_irq_postinstall(struct drm_device *dev);
1052extern void ivybridge_irq_uninstall(struct drm_device *dev);
1053
1013extern int i915_vblank_pipe_set(struct drm_device *dev, void *data, 1054extern int i915_vblank_pipe_set(struct drm_device *dev, void *data,
1014 struct drm_file *file_priv); 1055 struct drm_file *file_priv);
1015extern int i915_vblank_pipe_get(struct drm_device *dev, void *data, 1056extern int i915_vblank_pipe_get(struct drm_device *dev, void *data,
1016 struct drm_file *file_priv); 1057 struct drm_file *file_priv);
1017extern int i915_enable_vblank(struct drm_device *dev, int crtc); 1058extern int i915_enable_vblank(struct drm_device *dev, int crtc);
1018extern void i915_disable_vblank(struct drm_device *dev, int crtc); 1059extern void i915_disable_vblank(struct drm_device *dev, int crtc);
1060extern int ironlake_enable_vblank(struct drm_device *dev, int crtc);
1061extern void ironlake_disable_vblank(struct drm_device *dev, int crtc);
1062extern int ivybridge_enable_vblank(struct drm_device *dev, int crtc);
1063extern void ivybridge_disable_vblank(struct drm_device *dev, int crtc);
1019extern u32 i915_get_vblank_counter(struct drm_device *dev, int crtc); 1064extern u32 i915_get_vblank_counter(struct drm_device *dev, int crtc);
1020extern u32 gm45_get_vblank_counter(struct drm_device *dev, int crtc); 1065extern u32 gm45_get_vblank_counter(struct drm_device *dev, int crtc);
1021extern int i915_vblank_swap(struct drm_device *dev, void *data, 1066extern int i915_vblank_swap(struct drm_device *dev, void *data,
@@ -1265,6 +1310,7 @@ static inline void intel_unregister_dsm_handler(void) { return; }
1265 1310
1266/* modesetting */ 1311/* modesetting */
1267extern void intel_modeset_init(struct drm_device *dev); 1312extern void intel_modeset_init(struct drm_device *dev);
1313extern void intel_modeset_gem_init(struct drm_device *dev);
1268extern void intel_modeset_cleanup(struct drm_device *dev); 1314extern void intel_modeset_cleanup(struct drm_device *dev);
1269extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state); 1315extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state);
1270extern void i8xx_disable_fbc(struct drm_device *dev); 1316extern void i8xx_disable_fbc(struct drm_device *dev);
@@ -1312,13 +1358,34 @@ extern void intel_display_print_error_state(struct seq_file *m,
1312 LOCK_TEST_WITH_RETURN(dev, file); \ 1358 LOCK_TEST_WITH_RETURN(dev, file); \
1313} while (0) 1359} while (0)
1314 1360
1361/* On SNB platform, before reading ring registers forcewake bit
1362 * must be set to prevent GT core from power down and stale values being
1363 * returned.
1364 */
1365void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv);
1366void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv);
1367void __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv);
1368
1369/* We give fast paths for the really cool registers */
1370#define NEEDS_FORCE_WAKE(dev_priv, reg) \
1371 (((dev_priv)->info->gen >= 6) && \
1372 ((reg) < 0x40000) && \
1373 ((reg) != FORCEWAKE))
1315 1374
1316#define __i915_read(x, y) \ 1375#define __i915_read(x, y) \
1317static inline u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg) { \ 1376static inline u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg) { \
1318 u##x val = read##y(dev_priv->regs + reg); \ 1377 u##x val = 0; \
1378 if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
1379 gen6_gt_force_wake_get(dev_priv); \
1380 val = read##y(dev_priv->regs + reg); \
1381 gen6_gt_force_wake_put(dev_priv); \
1382 } else { \
1383 val = read##y(dev_priv->regs + reg); \
1384 } \
1319 trace_i915_reg_rw(false, reg, val, sizeof(val)); \ 1385 trace_i915_reg_rw(false, reg, val, sizeof(val)); \
1320 return val; \ 1386 return val; \
1321} 1387}
1388
1322__i915_read(8, b) 1389__i915_read(8, b)
1323__i915_read(16, w) 1390__i915_read(16, w)
1324__i915_read(32, l) 1391__i915_read(32, l)
@@ -1328,6 +1395,9 @@ __i915_read(64, q)
1328#define __i915_write(x, y) \ 1395#define __i915_write(x, y) \
1329static inline void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val) { \ 1396static inline void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val) { \
1330 trace_i915_reg_rw(true, reg, val, sizeof(val)); \ 1397 trace_i915_reg_rw(true, reg, val, sizeof(val)); \
1398 if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
1399 __gen6_gt_wait_for_fifo(dev_priv); \
1400 } \
1331 write##y(val, dev_priv->regs + reg); \ 1401 write##y(val, dev_priv->regs + reg); \
1332} 1402}
1333__i915_write(8, b) 1403__i915_write(8, b)
@@ -1356,33 +1426,4 @@ __i915_write(64, q)
1356#define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg) 1426#define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg)
1357 1427
1358 1428
1359/* On SNB platform, before reading ring registers forcewake bit
1360 * must be set to prevent GT core from power down and stale values being
1361 * returned.
1362 */
1363void __gen6_gt_force_wake_get(struct drm_i915_private *dev_priv);
1364void __gen6_gt_force_wake_put(struct drm_i915_private *dev_priv);
1365void __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv);
1366
1367static inline u32 i915_gt_read(struct drm_i915_private *dev_priv, u32 reg)
1368{
1369 u32 val;
1370
1371 if (dev_priv->info->gen >= 6) {
1372 __gen6_gt_force_wake_get(dev_priv);
1373 val = I915_READ(reg);
1374 __gen6_gt_force_wake_put(dev_priv);
1375 } else
1376 val = I915_READ(reg);
1377
1378 return val;
1379}
1380
1381static inline void i915_gt_write(struct drm_i915_private *dev_priv,
1382 u32 reg, u32 val)
1383{
1384 if (dev_priv->info->gen >= 6)
1385 __gen6_gt_wait_for_fifo(dev_priv);
1386 I915_WRITE(reg, val);
1387}
1388#endif 1429#endif
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 7ce3f353af33..c6289034e29a 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -2673,6 +2673,7 @@ i915_gem_object_get_fence(struct drm_i915_gem_object *obj,
2673update: 2673update:
2674 obj->tiling_changed = false; 2674 obj->tiling_changed = false;
2675 switch (INTEL_INFO(dev)->gen) { 2675 switch (INTEL_INFO(dev)->gen) {
2676 case 7:
2676 case 6: 2677 case 6:
2677 ret = sandybridge_write_fence_reg(obj, pipelined); 2678 ret = sandybridge_write_fence_reg(obj, pipelined);
2678 break; 2679 break;
@@ -2706,6 +2707,7 @@ i915_gem_clear_fence_reg(struct drm_device *dev,
2706 uint32_t fence_reg = reg - dev_priv->fence_regs; 2707 uint32_t fence_reg = reg - dev_priv->fence_regs;
2707 2708
2708 switch (INTEL_INFO(dev)->gen) { 2709 switch (INTEL_INFO(dev)->gen) {
2710 case 7:
2709 case 6: 2711 case 6:
2710 I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + fence_reg*8, 0); 2712 I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + fence_reg*8, 0);
2711 break; 2713 break;
@@ -2878,6 +2880,17 @@ i915_gem_clflush_object(struct drm_i915_gem_object *obj)
2878 if (obj->pages == NULL) 2880 if (obj->pages == NULL)
2879 return; 2881 return;
2880 2882
2883 /* If the GPU is snooping the contents of the CPU cache,
2884 * we do not need to manually clear the CPU cache lines. However,
2885 * the caches are only snooped when the render cache is
2886 * flushed/invalidated. As we always have to emit invalidations
2887 * and flushes when moving into and out of the RENDER domain, correct
2888 * snooping behaviour occurs naturally as the result of our domain
2889 * tracking.
2890 */
2891 if (obj->cache_level != I915_CACHE_NONE)
2892 return;
2893
2881 trace_i915_gem_object_clflush(obj); 2894 trace_i915_gem_object_clflush(obj);
2882 2895
2883 drm_clflush_pages(obj->pages, obj->base.size / PAGE_SIZE); 2896 drm_clflush_pages(obj->pages, obj->base.size / PAGE_SIZE);
@@ -3569,7 +3582,7 @@ struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
3569 obj->base.write_domain = I915_GEM_DOMAIN_CPU; 3582 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
3570 obj->base.read_domains = I915_GEM_DOMAIN_CPU; 3583 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
3571 3584
3572 obj->agp_type = AGP_USER_MEMORY; 3585 obj->cache_level = I915_CACHE_NONE;
3573 obj->base.driver_private = NULL; 3586 obj->base.driver_private = NULL;
3574 obj->fence_reg = I915_FENCE_REG_NONE; 3587 obj->fence_reg = I915_FENCE_REG_NONE;
3575 INIT_LIST_HEAD(&obj->mm_list); 3588 INIT_LIST_HEAD(&obj->mm_list);
@@ -3845,25 +3858,10 @@ i915_gem_load(struct drm_device *dev)
3845 dev_priv->num_fence_regs = 8; 3858 dev_priv->num_fence_regs = 8;
3846 3859
3847 /* Initialize fence registers to zero */ 3860 /* Initialize fence registers to zero */
3848 switch (INTEL_INFO(dev)->gen) { 3861 for (i = 0; i < dev_priv->num_fence_regs; i++) {
3849 case 6: 3862 i915_gem_clear_fence_reg(dev, &dev_priv->fence_regs[i]);
3850 for (i = 0; i < 16; i++)
3851 I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + (i * 8), 0);
3852 break;
3853 case 5:
3854 case 4:
3855 for (i = 0; i < 16; i++)
3856 I915_WRITE64(FENCE_REG_965_0 + (i * 8), 0);
3857 break;
3858 case 3:
3859 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
3860 for (i = 0; i < 8; i++)
3861 I915_WRITE(FENCE_REG_945_8 + (i * 4), 0);
3862 case 2:
3863 for (i = 0; i < 8; i++)
3864 I915_WRITE(FENCE_REG_830_0 + (i * 4), 0);
3865 break;
3866 } 3863 }
3864
3867 i915_gem_detect_bit_6_swizzle(dev); 3865 i915_gem_detect_bit_6_swizzle(dev);
3868 init_waitqueue_head(&dev_priv->pending_flip_queue); 3866 init_waitqueue_head(&dev_priv->pending_flip_queue);
3869 3867
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index b0abdc64aa9f..e46b645773cf 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -29,6 +29,26 @@
29#include "i915_trace.h" 29#include "i915_trace.h"
30#include "intel_drv.h" 30#include "intel_drv.h"
31 31
32/* XXX kill agp_type! */
33static unsigned int cache_level_to_agp_type(struct drm_device *dev,
34 enum i915_cache_level cache_level)
35{
36 switch (cache_level) {
37 case I915_CACHE_LLC_MLC:
38 if (INTEL_INFO(dev)->gen >= 6)
39 return AGP_USER_CACHED_MEMORY_LLC_MLC;
40 /* Older chipsets do not have this extra level of CPU
41 * cacheing, so fallthrough and request the PTE simply
42 * as cached.
43 */
44 case I915_CACHE_LLC:
45 return AGP_USER_CACHED_MEMORY;
46 default:
47 case I915_CACHE_NONE:
48 return AGP_USER_MEMORY;
49 }
50}
51
32void i915_gem_restore_gtt_mappings(struct drm_device *dev) 52void i915_gem_restore_gtt_mappings(struct drm_device *dev)
33{ 53{
34 struct drm_i915_private *dev_priv = dev->dev_private; 54 struct drm_i915_private *dev_priv = dev->dev_private;
@@ -39,6 +59,9 @@ void i915_gem_restore_gtt_mappings(struct drm_device *dev)
39 (dev_priv->mm.gtt_end - dev_priv->mm.gtt_start) / PAGE_SIZE); 59 (dev_priv->mm.gtt_end - dev_priv->mm.gtt_start) / PAGE_SIZE);
40 60
41 list_for_each_entry(obj, &dev_priv->mm.gtt_list, gtt_list) { 61 list_for_each_entry(obj, &dev_priv->mm.gtt_list, gtt_list) {
62 unsigned int agp_type =
63 cache_level_to_agp_type(dev, obj->cache_level);
64
42 i915_gem_clflush_object(obj); 65 i915_gem_clflush_object(obj);
43 66
44 if (dev_priv->mm.gtt->needs_dmar) { 67 if (dev_priv->mm.gtt->needs_dmar) {
@@ -46,15 +69,14 @@ void i915_gem_restore_gtt_mappings(struct drm_device *dev)
46 69
47 intel_gtt_insert_sg_entries(obj->sg_list, 70 intel_gtt_insert_sg_entries(obj->sg_list,
48 obj->num_sg, 71 obj->num_sg,
49 obj->gtt_space->start 72 obj->gtt_space->start >> PAGE_SHIFT,
50 >> PAGE_SHIFT, 73 agp_type);
51 obj->agp_type);
52 } else 74 } else
53 intel_gtt_insert_pages(obj->gtt_space->start 75 intel_gtt_insert_pages(obj->gtt_space->start
54 >> PAGE_SHIFT, 76 >> PAGE_SHIFT,
55 obj->base.size >> PAGE_SHIFT, 77 obj->base.size >> PAGE_SHIFT,
56 obj->pages, 78 obj->pages,
57 obj->agp_type); 79 agp_type);
58 } 80 }
59 81
60 intel_gtt_chipset_flush(); 82 intel_gtt_chipset_flush();
@@ -64,6 +86,7 @@ int i915_gem_gtt_bind_object(struct drm_i915_gem_object *obj)
64{ 86{
65 struct drm_device *dev = obj->base.dev; 87 struct drm_device *dev = obj->base.dev;
66 struct drm_i915_private *dev_priv = dev->dev_private; 88 struct drm_i915_private *dev_priv = dev->dev_private;
89 unsigned int agp_type = cache_level_to_agp_type(dev, obj->cache_level);
67 int ret; 90 int ret;
68 91
69 if (dev_priv->mm.gtt->needs_dmar) { 92 if (dev_priv->mm.gtt->needs_dmar) {
@@ -77,12 +100,12 @@ int i915_gem_gtt_bind_object(struct drm_i915_gem_object *obj)
77 intel_gtt_insert_sg_entries(obj->sg_list, 100 intel_gtt_insert_sg_entries(obj->sg_list,
78 obj->num_sg, 101 obj->num_sg,
79 obj->gtt_space->start >> PAGE_SHIFT, 102 obj->gtt_space->start >> PAGE_SHIFT,
80 obj->agp_type); 103 agp_type);
81 } else 104 } else
82 intel_gtt_insert_pages(obj->gtt_space->start >> PAGE_SHIFT, 105 intel_gtt_insert_pages(obj->gtt_space->start >> PAGE_SHIFT,
83 obj->base.size >> PAGE_SHIFT, 106 obj->base.size >> PAGE_SHIFT,
84 obj->pages, 107 obj->pages,
85 obj->agp_type); 108 agp_type);
86 109
87 return 0; 110 return 0;
88} 111}
diff --git a/drivers/gpu/drm/i915/i915_gem_tiling.c b/drivers/gpu/drm/i915/i915_gem_tiling.c
index 281ad3d6115d..82d70fd9e933 100644
--- a/drivers/gpu/drm/i915/i915_gem_tiling.c
+++ b/drivers/gpu/drm/i915/i915_gem_tiling.c
@@ -92,7 +92,7 @@ i915_gem_detect_bit_6_swizzle(struct drm_device *dev)
92 uint32_t swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN; 92 uint32_t swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN;
93 uint32_t swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN; 93 uint32_t swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN;
94 94
95 if (IS_GEN5(dev) || IS_GEN6(dev)) { 95 if (INTEL_INFO(dev)->gen >= 5) {
96 /* On Ironlake whatever DRAM config, GPU always do 96 /* On Ironlake whatever DRAM config, GPU always do
97 * same swizzling setup. 97 * same swizzling setup.
98 */ 98 */
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 188b497e5076..b79619a7b788 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -367,22 +367,30 @@ static void notify_ring(struct drm_device *dev,
367 jiffies + msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)); 367 jiffies + msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD));
368} 368}
369 369
370static void gen6_pm_irq_handler(struct drm_device *dev) 370static void gen6_pm_rps_work(struct work_struct *work)
371{ 371{
372 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 372 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
373 rps_work);
373 u8 new_delay = dev_priv->cur_delay; 374 u8 new_delay = dev_priv->cur_delay;
374 u32 pm_iir; 375 u32 pm_iir, pm_imr;
376
377 spin_lock_irq(&dev_priv->rps_lock);
378 pm_iir = dev_priv->pm_iir;
379 dev_priv->pm_iir = 0;
380 pm_imr = I915_READ(GEN6_PMIMR);
381 spin_unlock_irq(&dev_priv->rps_lock);
375 382
376 pm_iir = I915_READ(GEN6_PMIIR);
377 if (!pm_iir) 383 if (!pm_iir)
378 return; 384 return;
379 385
386 mutex_lock(&dev_priv->dev->struct_mutex);
380 if (pm_iir & GEN6_PM_RP_UP_THRESHOLD) { 387 if (pm_iir & GEN6_PM_RP_UP_THRESHOLD) {
381 if (dev_priv->cur_delay != dev_priv->max_delay) 388 if (dev_priv->cur_delay != dev_priv->max_delay)
382 new_delay = dev_priv->cur_delay + 1; 389 new_delay = dev_priv->cur_delay + 1;
383 if (new_delay > dev_priv->max_delay) 390 if (new_delay > dev_priv->max_delay)
384 new_delay = dev_priv->max_delay; 391 new_delay = dev_priv->max_delay;
385 } else if (pm_iir & (GEN6_PM_RP_DOWN_THRESHOLD | GEN6_PM_RP_DOWN_TIMEOUT)) { 392 } else if (pm_iir & (GEN6_PM_RP_DOWN_THRESHOLD | GEN6_PM_RP_DOWN_TIMEOUT)) {
393 gen6_gt_force_wake_get(dev_priv);
386 if (dev_priv->cur_delay != dev_priv->min_delay) 394 if (dev_priv->cur_delay != dev_priv->min_delay)
387 new_delay = dev_priv->cur_delay - 1; 395 new_delay = dev_priv->cur_delay - 1;
388 if (new_delay < dev_priv->min_delay) { 396 if (new_delay < dev_priv->min_delay) {
@@ -396,13 +404,19 @@ static void gen6_pm_irq_handler(struct drm_device *dev)
396 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, 404 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
397 I915_READ(GEN6_RP_INTERRUPT_LIMITS) & ~0x3f0000); 405 I915_READ(GEN6_RP_INTERRUPT_LIMITS) & ~0x3f0000);
398 } 406 }
399 407 gen6_gt_force_wake_put(dev_priv);
400 } 408 }
401 409
402 gen6_set_rps(dev, new_delay); 410 gen6_set_rps(dev_priv->dev, new_delay);
403 dev_priv->cur_delay = new_delay; 411 dev_priv->cur_delay = new_delay;
404 412
405 I915_WRITE(GEN6_PMIIR, pm_iir); 413 /*
414 * rps_lock not held here because clearing is non-destructive. There is
415 * an *extremely* unlikely race with gen6_rps_enable() that is prevented
416 * by holding struct_mutex for the duration of the write.
417 */
418 I915_WRITE(GEN6_PMIMR, pm_imr & ~pm_iir);
419 mutex_unlock(&dev_priv->dev->struct_mutex);
406} 420}
407 421
408static void pch_irq_handler(struct drm_device *dev) 422static void pch_irq_handler(struct drm_device *dev)
@@ -448,8 +462,97 @@ static void pch_irq_handler(struct drm_device *dev)
448 DRM_DEBUG_DRIVER("PCH transcoder A underrun interrupt\n"); 462 DRM_DEBUG_DRIVER("PCH transcoder A underrun interrupt\n");
449} 463}
450 464
451static irqreturn_t ironlake_irq_handler(struct drm_device *dev) 465irqreturn_t ivybridge_irq_handler(DRM_IRQ_ARGS)
466{
467 struct drm_device *dev = (struct drm_device *) arg;
468 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
469 int ret = IRQ_NONE;
470 u32 de_iir, gt_iir, de_ier, pch_iir, pm_iir;
471 struct drm_i915_master_private *master_priv;
472
473 atomic_inc(&dev_priv->irq_received);
474
475 /* disable master interrupt before clearing iir */
476 de_ier = I915_READ(DEIER);
477 I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
478 POSTING_READ(DEIER);
479
480 de_iir = I915_READ(DEIIR);
481 gt_iir = I915_READ(GTIIR);
482 pch_iir = I915_READ(SDEIIR);
483 pm_iir = I915_READ(GEN6_PMIIR);
484
485 if (de_iir == 0 && gt_iir == 0 && pch_iir == 0 && pm_iir == 0)
486 goto done;
487
488 ret = IRQ_HANDLED;
489
490 if (dev->primary->master) {
491 master_priv = dev->primary->master->driver_priv;
492 if (master_priv->sarea_priv)
493 master_priv->sarea_priv->last_dispatch =
494 READ_BREADCRUMB(dev_priv);
495 }
496
497 if (gt_iir & (GT_USER_INTERRUPT | GT_PIPE_NOTIFY))
498 notify_ring(dev, &dev_priv->ring[RCS]);
499 if (gt_iir & GT_GEN6_BSD_USER_INTERRUPT)
500 notify_ring(dev, &dev_priv->ring[VCS]);
501 if (gt_iir & GT_BLT_USER_INTERRUPT)
502 notify_ring(dev, &dev_priv->ring[BCS]);
503
504 if (de_iir & DE_GSE_IVB)
505 intel_opregion_gse_intr(dev);
506
507 if (de_iir & DE_PLANEA_FLIP_DONE_IVB) {
508 intel_prepare_page_flip(dev, 0);
509 intel_finish_page_flip_plane(dev, 0);
510 }
511
512 if (de_iir & DE_PLANEB_FLIP_DONE_IVB) {
513 intel_prepare_page_flip(dev, 1);
514 intel_finish_page_flip_plane(dev, 1);
515 }
516
517 if (de_iir & DE_PIPEA_VBLANK_IVB)
518 drm_handle_vblank(dev, 0);
519
520 if (de_iir & DE_PIPEB_VBLANK_IVB);
521 drm_handle_vblank(dev, 1);
522
523 /* check event from PCH */
524 if (de_iir & DE_PCH_EVENT_IVB) {
525 if (pch_iir & SDE_HOTPLUG_MASK_CPT)
526 queue_work(dev_priv->wq, &dev_priv->hotplug_work);
527 pch_irq_handler(dev);
528 }
529
530 if (pm_iir & GEN6_PM_DEFERRED_EVENTS) {
531 unsigned long flags;
532 spin_lock_irqsave(&dev_priv->rps_lock, flags);
533 WARN(dev_priv->pm_iir & pm_iir, "Missed a PM interrupt\n");
534 I915_WRITE(GEN6_PMIMR, pm_iir);
535 dev_priv->pm_iir |= pm_iir;
536 spin_unlock_irqrestore(&dev_priv->rps_lock, flags);
537 queue_work(dev_priv->wq, &dev_priv->rps_work);
538 }
539
540 /* should clear PCH hotplug event before clear CPU irq */
541 I915_WRITE(SDEIIR, pch_iir);
542 I915_WRITE(GTIIR, gt_iir);
543 I915_WRITE(DEIIR, de_iir);
544 I915_WRITE(GEN6_PMIIR, pm_iir);
545
546done:
547 I915_WRITE(DEIER, de_ier);
548 POSTING_READ(DEIER);
549
550 return ret;
551}
552
553irqreturn_t ironlake_irq_handler(DRM_IRQ_ARGS)
452{ 554{
555 struct drm_device *dev = (struct drm_device *) arg;
453 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 556 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
454 int ret = IRQ_NONE; 557 int ret = IRQ_NONE;
455 u32 de_iir, gt_iir, de_ier, pch_iir, pm_iir; 558 u32 de_iir, gt_iir, de_ier, pch_iir, pm_iir;
@@ -457,6 +560,8 @@ static irqreturn_t ironlake_irq_handler(struct drm_device *dev)
457 struct drm_i915_master_private *master_priv; 560 struct drm_i915_master_private *master_priv;
458 u32 bsd_usr_interrupt = GT_BSD_USER_INTERRUPT; 561 u32 bsd_usr_interrupt = GT_BSD_USER_INTERRUPT;
459 562
563 atomic_inc(&dev_priv->irq_received);
564
460 if (IS_GEN6(dev)) 565 if (IS_GEN6(dev))
461 bsd_usr_interrupt = GT_GEN6_BSD_USER_INTERRUPT; 566 bsd_usr_interrupt = GT_GEN6_BSD_USER_INTERRUPT;
462 567
@@ -526,13 +631,30 @@ static irqreturn_t ironlake_irq_handler(struct drm_device *dev)
526 i915_handle_rps_change(dev); 631 i915_handle_rps_change(dev);
527 } 632 }
528 633
529 if (IS_GEN6(dev)) 634 if (IS_GEN6(dev) && pm_iir & GEN6_PM_DEFERRED_EVENTS) {
530 gen6_pm_irq_handler(dev); 635 /*
636 * IIR bits should never already be set because IMR should
637 * prevent an interrupt from being shown in IIR. The warning
638 * displays a case where we've unsafely cleared
639 * dev_priv->pm_iir. Although missing an interrupt of the same
640 * type is not a problem, it displays a problem in the logic.
641 *
642 * The mask bit in IMR is cleared by rps_work.
643 */
644 unsigned long flags;
645 spin_lock_irqsave(&dev_priv->rps_lock, flags);
646 WARN(dev_priv->pm_iir & pm_iir, "Missed a PM interrupt\n");
647 I915_WRITE(GEN6_PMIMR, pm_iir);
648 dev_priv->pm_iir |= pm_iir;
649 spin_unlock_irqrestore(&dev_priv->rps_lock, flags);
650 queue_work(dev_priv->wq, &dev_priv->rps_work);
651 }
531 652
532 /* should clear PCH hotplug event before clear CPU irq */ 653 /* should clear PCH hotplug event before clear CPU irq */
533 I915_WRITE(SDEIIR, pch_iir); 654 I915_WRITE(SDEIIR, pch_iir);
534 I915_WRITE(GTIIR, gt_iir); 655 I915_WRITE(GTIIR, gt_iir);
535 I915_WRITE(DEIIR, de_iir); 656 I915_WRITE(DEIIR, de_iir);
657 I915_WRITE(GEN6_PMIIR, pm_iir);
536 658
537done: 659done:
538 I915_WRITE(DEIER, de_ier); 660 I915_WRITE(DEIER, de_ier);
@@ -676,7 +798,7 @@ static u32 capture_bo_list(struct drm_i915_error_buffer *err,
676 err->dirty = obj->dirty; 798 err->dirty = obj->dirty;
677 err->purgeable = obj->madv != I915_MADV_WILLNEED; 799 err->purgeable = obj->madv != I915_MADV_WILLNEED;
678 err->ring = obj->ring ? obj->ring->id : 0; 800 err->ring = obj->ring ? obj->ring->id : 0;
679 err->agp_type = obj->agp_type == AGP_USER_CACHED_MEMORY; 801 err->cache_level = obj->cache_level;
680 802
681 if (++i == count) 803 if (++i == count)
682 break; 804 break;
@@ -1103,9 +1225,6 @@ irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS)
1103 1225
1104 atomic_inc(&dev_priv->irq_received); 1226 atomic_inc(&dev_priv->irq_received);
1105 1227
1106 if (HAS_PCH_SPLIT(dev))
1107 return ironlake_irq_handler(dev);
1108
1109 iir = I915_READ(IIR); 1228 iir = I915_READ(IIR);
1110 1229
1111 if (INTEL_INFO(dev)->gen >= 4) 1230 if (INTEL_INFO(dev)->gen >= 4)
@@ -1344,10 +1463,7 @@ int i915_enable_vblank(struct drm_device *dev, int pipe)
1344 return -EINVAL; 1463 return -EINVAL;
1345 1464
1346 spin_lock_irqsave(&dev_priv->irq_lock, irqflags); 1465 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1347 if (HAS_PCH_SPLIT(dev)) 1466 if (INTEL_INFO(dev)->gen >= 4)
1348 ironlake_enable_display_irq(dev_priv, (pipe == 0) ?
1349 DE_PIPEA_VBLANK: DE_PIPEB_VBLANK);
1350 else if (INTEL_INFO(dev)->gen >= 4)
1351 i915_enable_pipestat(dev_priv, pipe, 1467 i915_enable_pipestat(dev_priv, pipe,
1352 PIPE_START_VBLANK_INTERRUPT_ENABLE); 1468 PIPE_START_VBLANK_INTERRUPT_ENABLE);
1353 else 1469 else
@@ -1362,6 +1478,38 @@ int i915_enable_vblank(struct drm_device *dev, int pipe)
1362 return 0; 1478 return 0;
1363} 1479}
1364 1480
1481int ironlake_enable_vblank(struct drm_device *dev, int pipe)
1482{
1483 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1484 unsigned long irqflags;
1485
1486 if (!i915_pipe_enabled(dev, pipe))
1487 return -EINVAL;
1488
1489 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1490 ironlake_enable_display_irq(dev_priv, (pipe == 0) ?
1491 DE_PIPEA_VBLANK: DE_PIPEB_VBLANK);
1492 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1493
1494 return 0;
1495}
1496
1497int ivybridge_enable_vblank(struct drm_device *dev, int pipe)
1498{
1499 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1500 unsigned long irqflags;
1501
1502 if (!i915_pipe_enabled(dev, pipe))
1503 return -EINVAL;
1504
1505 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1506 ironlake_enable_display_irq(dev_priv, (pipe == 0) ?
1507 DE_PIPEA_VBLANK_IVB : DE_PIPEB_VBLANK_IVB);
1508 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1509
1510 return 0;
1511}
1512
1365/* Called from drm generic code, passed 'crtc' which 1513/* Called from drm generic code, passed 'crtc' which
1366 * we use as a pipe index 1514 * we use as a pipe index
1367 */ 1515 */
@@ -1375,13 +1523,31 @@ void i915_disable_vblank(struct drm_device *dev, int pipe)
1375 I915_WRITE(INSTPM, 1523 I915_WRITE(INSTPM,
1376 INSTPM_AGPBUSY_DIS << 16 | INSTPM_AGPBUSY_DIS); 1524 INSTPM_AGPBUSY_DIS << 16 | INSTPM_AGPBUSY_DIS);
1377 1525
1378 if (HAS_PCH_SPLIT(dev)) 1526 i915_disable_pipestat(dev_priv, pipe,
1379 ironlake_disable_display_irq(dev_priv, (pipe == 0) ? 1527 PIPE_VBLANK_INTERRUPT_ENABLE |
1380 DE_PIPEA_VBLANK: DE_PIPEB_VBLANK); 1528 PIPE_START_VBLANK_INTERRUPT_ENABLE);
1381 else 1529 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1382 i915_disable_pipestat(dev_priv, pipe, 1530}
1383 PIPE_VBLANK_INTERRUPT_ENABLE | 1531
1384 PIPE_START_VBLANK_INTERRUPT_ENABLE); 1532void ironlake_disable_vblank(struct drm_device *dev, int pipe)
1533{
1534 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1535 unsigned long irqflags;
1536
1537 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1538 ironlake_disable_display_irq(dev_priv, (pipe == 0) ?
1539 DE_PIPEA_VBLANK: DE_PIPEB_VBLANK);
1540 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1541}
1542
1543void ivybridge_disable_vblank(struct drm_device *dev, int pipe)
1544{
1545 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1546 unsigned long irqflags;
1547
1548 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1549 ironlake_disable_display_irq(dev_priv, (pipe == 0) ?
1550 DE_PIPEA_VBLANK_IVB : DE_PIPEB_VBLANK_IVB);
1385 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); 1551 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1386} 1552}
1387 1553
@@ -1562,10 +1728,17 @@ repeat:
1562 1728
1563/* drm_dma.h hooks 1729/* drm_dma.h hooks
1564*/ 1730*/
1565static void ironlake_irq_preinstall(struct drm_device *dev) 1731void ironlake_irq_preinstall(struct drm_device *dev)
1566{ 1732{
1567 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 1733 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1568 1734
1735 atomic_set(&dev_priv->irq_received, 0);
1736
1737 INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func);
1738 INIT_WORK(&dev_priv->error_work, i915_error_work_func);
1739 if (IS_GEN6(dev) || IS_IVYBRIDGE(dev))
1740 INIT_WORK(&dev_priv->rps_work, gen6_pm_rps_work);
1741
1569 I915_WRITE(HWSTAM, 0xeffe); 1742 I915_WRITE(HWSTAM, 0xeffe);
1570 1743
1571 /* XXX hotplug from PCH */ 1744 /* XXX hotplug from PCH */
@@ -1585,7 +1758,7 @@ static void ironlake_irq_preinstall(struct drm_device *dev)
1585 POSTING_READ(SDEIER); 1758 POSTING_READ(SDEIER);
1586} 1759}
1587 1760
1588static int ironlake_irq_postinstall(struct drm_device *dev) 1761int ironlake_irq_postinstall(struct drm_device *dev)
1589{ 1762{
1590 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 1763 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1591 /* enable kind of interrupts always enabled */ 1764 /* enable kind of interrupts always enabled */
@@ -1594,6 +1767,13 @@ static int ironlake_irq_postinstall(struct drm_device *dev)
1594 u32 render_irqs; 1767 u32 render_irqs;
1595 u32 hotplug_mask; 1768 u32 hotplug_mask;
1596 1769
1770 DRM_INIT_WAITQUEUE(&dev_priv->ring[RCS].irq_queue);
1771 if (HAS_BSD(dev))
1772 DRM_INIT_WAITQUEUE(&dev_priv->ring[VCS].irq_queue);
1773 if (HAS_BLT(dev))
1774 DRM_INIT_WAITQUEUE(&dev_priv->ring[BCS].irq_queue);
1775
1776 dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
1597 dev_priv->irq_mask = ~display_mask; 1777 dev_priv->irq_mask = ~display_mask;
1598 1778
1599 /* should always can generate irq */ 1779 /* should always can generate irq */
@@ -1650,6 +1830,56 @@ static int ironlake_irq_postinstall(struct drm_device *dev)
1650 return 0; 1830 return 0;
1651} 1831}
1652 1832
1833int ivybridge_irq_postinstall(struct drm_device *dev)
1834{
1835 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1836 /* enable kind of interrupts always enabled */
1837 u32 display_mask = DE_MASTER_IRQ_CONTROL | DE_GSE_IVB |
1838 DE_PCH_EVENT_IVB | DE_PLANEA_FLIP_DONE_IVB |
1839 DE_PLANEB_FLIP_DONE_IVB;
1840 u32 render_irqs;
1841 u32 hotplug_mask;
1842
1843 DRM_INIT_WAITQUEUE(&dev_priv->ring[RCS].irq_queue);
1844 if (HAS_BSD(dev))
1845 DRM_INIT_WAITQUEUE(&dev_priv->ring[VCS].irq_queue);
1846 if (HAS_BLT(dev))
1847 DRM_INIT_WAITQUEUE(&dev_priv->ring[BCS].irq_queue);
1848
1849 dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
1850 dev_priv->irq_mask = ~display_mask;
1851
1852 /* should always can generate irq */
1853 I915_WRITE(DEIIR, I915_READ(DEIIR));
1854 I915_WRITE(DEIMR, dev_priv->irq_mask);
1855 I915_WRITE(DEIER, display_mask | DE_PIPEA_VBLANK_IVB |
1856 DE_PIPEB_VBLANK_IVB);
1857 POSTING_READ(DEIER);
1858
1859 dev_priv->gt_irq_mask = ~0;
1860
1861 I915_WRITE(GTIIR, I915_READ(GTIIR));
1862 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
1863
1864 render_irqs = GT_USER_INTERRUPT | GT_GEN6_BSD_USER_INTERRUPT |
1865 GT_BLT_USER_INTERRUPT;
1866 I915_WRITE(GTIER, render_irqs);
1867 POSTING_READ(GTIER);
1868
1869 hotplug_mask = (SDE_CRT_HOTPLUG_CPT |
1870 SDE_PORTB_HOTPLUG_CPT |
1871 SDE_PORTC_HOTPLUG_CPT |
1872 SDE_PORTD_HOTPLUG_CPT);
1873 dev_priv->pch_irq_mask = ~hotplug_mask;
1874
1875 I915_WRITE(SDEIIR, I915_READ(SDEIIR));
1876 I915_WRITE(SDEIMR, dev_priv->pch_irq_mask);
1877 I915_WRITE(SDEIER, hotplug_mask);
1878 POSTING_READ(SDEIER);
1879
1880 return 0;
1881}
1882
1653void i915_driver_irq_preinstall(struct drm_device * dev) 1883void i915_driver_irq_preinstall(struct drm_device * dev)
1654{ 1884{
1655 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 1885 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
@@ -1660,11 +1890,6 @@ void i915_driver_irq_preinstall(struct drm_device * dev)
1660 INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func); 1890 INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func);
1661 INIT_WORK(&dev_priv->error_work, i915_error_work_func); 1891 INIT_WORK(&dev_priv->error_work, i915_error_work_func);
1662 1892
1663 if (HAS_PCH_SPLIT(dev)) {
1664 ironlake_irq_preinstall(dev);
1665 return;
1666 }
1667
1668 if (I915_HAS_HOTPLUG(dev)) { 1893 if (I915_HAS_HOTPLUG(dev)) {
1669 I915_WRITE(PORT_HOTPLUG_EN, 0); 1894 I915_WRITE(PORT_HOTPLUG_EN, 0);
1670 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); 1895 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
@@ -1688,17 +1913,8 @@ int i915_driver_irq_postinstall(struct drm_device *dev)
1688 u32 enable_mask = I915_INTERRUPT_ENABLE_FIX | I915_INTERRUPT_ENABLE_VAR; 1913 u32 enable_mask = I915_INTERRUPT_ENABLE_FIX | I915_INTERRUPT_ENABLE_VAR;
1689 u32 error_mask; 1914 u32 error_mask;
1690 1915
1691 DRM_INIT_WAITQUEUE(&dev_priv->ring[RCS].irq_queue);
1692 if (HAS_BSD(dev))
1693 DRM_INIT_WAITQUEUE(&dev_priv->ring[VCS].irq_queue);
1694 if (HAS_BLT(dev))
1695 DRM_INIT_WAITQUEUE(&dev_priv->ring[BCS].irq_queue);
1696
1697 dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B; 1916 dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
1698 1917
1699 if (HAS_PCH_SPLIT(dev))
1700 return ironlake_irq_postinstall(dev);
1701
1702 /* Unmask the interrupts that we always want on. */ 1918 /* Unmask the interrupts that we always want on. */
1703 dev_priv->irq_mask = ~I915_INTERRUPT_ENABLE_FIX; 1919 dev_priv->irq_mask = ~I915_INTERRUPT_ENABLE_FIX;
1704 1920
@@ -1767,9 +1983,15 @@ int i915_driver_irq_postinstall(struct drm_device *dev)
1767 return 0; 1983 return 0;
1768} 1984}
1769 1985
1770static void ironlake_irq_uninstall(struct drm_device *dev) 1986void ironlake_irq_uninstall(struct drm_device *dev)
1771{ 1987{
1772 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 1988 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1989
1990 if (!dev_priv)
1991 return;
1992
1993 dev_priv->vblank_pipe = 0;
1994
1773 I915_WRITE(HWSTAM, 0xffffffff); 1995 I915_WRITE(HWSTAM, 0xffffffff);
1774 1996
1775 I915_WRITE(DEIMR, 0xffffffff); 1997 I915_WRITE(DEIMR, 0xffffffff);
@@ -1791,11 +2013,6 @@ void i915_driver_irq_uninstall(struct drm_device * dev)
1791 2013
1792 dev_priv->vblank_pipe = 0; 2014 dev_priv->vblank_pipe = 0;
1793 2015
1794 if (HAS_PCH_SPLIT(dev)) {
1795 ironlake_irq_uninstall(dev);
1796 return;
1797 }
1798
1799 if (I915_HAS_HOTPLUG(dev)) { 2016 if (I915_HAS_HOTPLUG(dev)) {
1800 I915_WRITE(PORT_HOTPLUG_EN, 0); 2017 I915_WRITE(PORT_HOTPLUG_EN, 0);
1801 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); 2018 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index f39ac3a0fa93..2f967af8e62e 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -291,6 +291,9 @@
291#define RING_MAX_IDLE(base) ((base)+0x54) 291#define RING_MAX_IDLE(base) ((base)+0x54)
292#define RING_HWS_PGA(base) ((base)+0x80) 292#define RING_HWS_PGA(base) ((base)+0x80)
293#define RING_HWS_PGA_GEN6(base) ((base)+0x2080) 293#define RING_HWS_PGA_GEN6(base) ((base)+0x2080)
294#define RENDER_HWS_PGA_GEN7 (0x04080)
295#define BSD_HWS_PGA_GEN7 (0x04180)
296#define BLT_HWS_PGA_GEN7 (0x04280)
294#define RING_ACTHD(base) ((base)+0x74) 297#define RING_ACTHD(base) ((base)+0x74)
295#define RING_NOPID(base) ((base)+0x94) 298#define RING_NOPID(base) ((base)+0x94)
296#define RING_IMR(base) ((base)+0xa8) 299#define RING_IMR(base) ((base)+0xa8)
@@ -2778,6 +2781,19 @@
2778#define DE_PIPEA_VSYNC (1 << 3) 2781#define DE_PIPEA_VSYNC (1 << 3)
2779#define DE_PIPEA_FIFO_UNDERRUN (1 << 0) 2782#define DE_PIPEA_FIFO_UNDERRUN (1 << 0)
2780 2783
2784/* More Ivybridge lolz */
2785#define DE_ERR_DEBUG_IVB (1<<30)
2786#define DE_GSE_IVB (1<<29)
2787#define DE_PCH_EVENT_IVB (1<<28)
2788#define DE_DP_A_HOTPLUG_IVB (1<<27)
2789#define DE_AUX_CHANNEL_A_IVB (1<<26)
2790#define DE_SPRITEB_FLIP_DONE_IVB (1<<9)
2791#define DE_SPRITEA_FLIP_DONE_IVB (1<<4)
2792#define DE_PLANEB_FLIP_DONE_IVB (1<<8)
2793#define DE_PLANEA_FLIP_DONE_IVB (1<<3)
2794#define DE_PIPEB_VBLANK_IVB (1<<5)
2795#define DE_PIPEA_VBLANK_IVB (1<<0)
2796
2781#define DEISR 0x44000 2797#define DEISR 0x44000
2782#define DEIMR 0x44004 2798#define DEIMR 0x44004
2783#define DEIIR 0x44008 2799#define DEIIR 0x44008
@@ -2809,6 +2825,7 @@
2809#define ILK_eDP_A_DISABLE (1<<24) 2825#define ILK_eDP_A_DISABLE (1<<24)
2810#define ILK_DESKTOP (1<<23) 2826#define ILK_DESKTOP (1<<23)
2811#define ILK_DSPCLK_GATE 0x42020 2827#define ILK_DSPCLK_GATE 0x42020
2828#define IVB_VRHUNIT_CLK_GATE (1<<28)
2812#define ILK_DPARB_CLK_GATE (1<<5) 2829#define ILK_DPARB_CLK_GATE (1<<5)
2813#define ILK_DPFD_CLK_GATE (1<<7) 2830#define ILK_DPFD_CLK_GATE (1<<7)
2814 2831
@@ -3057,6 +3074,9 @@
3057#define TRANS_6BPC (2<<5) 3074#define TRANS_6BPC (2<<5)
3058#define TRANS_12BPC (3<<5) 3075#define TRANS_12BPC (3<<5)
3059 3076
3077#define SOUTH_CHICKEN2 0xc2004
3078#define DPLS_EDP_PPS_FIX_DIS (1<<0)
3079
3060#define _FDI_RXA_CHICKEN 0xc200c 3080#define _FDI_RXA_CHICKEN 0xc200c
3061#define _FDI_RXB_CHICKEN 0xc2010 3081#define _FDI_RXB_CHICKEN 0xc2010
3062#define FDI_RX_PHASE_SYNC_POINTER_OVR (1<<1) 3082#define FDI_RX_PHASE_SYNC_POINTER_OVR (1<<1)
@@ -3104,7 +3124,15 @@
3104#define FDI_TX_ENHANCE_FRAME_ENABLE (1<<18) 3124#define FDI_TX_ENHANCE_FRAME_ENABLE (1<<18)
3105/* Ironlake: hardwired to 1 */ 3125/* Ironlake: hardwired to 1 */
3106#define FDI_TX_PLL_ENABLE (1<<14) 3126#define FDI_TX_PLL_ENABLE (1<<14)
3127
3128/* Ivybridge has different bits for lolz */
3129#define FDI_LINK_TRAIN_PATTERN_1_IVB (0<<8)
3130#define FDI_LINK_TRAIN_PATTERN_2_IVB (1<<8)
3131#define FDI_LINK_TRAIN_PATTERN_IDLE_IVB (2<<8)
3132#define FDI_LINK_TRAIN_NONE_IVB (3<<8)
3133
3107/* both Tx and Rx */ 3134/* both Tx and Rx */
3135#define FDI_LINK_TRAIN_AUTO (1<<10)
3108#define FDI_SCRAMBLING_ENABLE (0<<7) 3136#define FDI_SCRAMBLING_ENABLE (0<<7)
3109#define FDI_SCRAMBLING_DISABLE (1<<7) 3137#define FDI_SCRAMBLING_DISABLE (1<<7)
3110 3138
@@ -3114,6 +3142,8 @@
3114#define FDI_RX_CTL(pipe) _PIPE(pipe, _FDI_RXA_CTL, _FDI_RXB_CTL) 3142#define FDI_RX_CTL(pipe) _PIPE(pipe, _FDI_RXA_CTL, _FDI_RXB_CTL)
3115#define FDI_RX_ENABLE (1<<31) 3143#define FDI_RX_ENABLE (1<<31)
3116/* train, dp width same as FDI_TX */ 3144/* train, dp width same as FDI_TX */
3145#define FDI_FS_ERRC_ENABLE (1<<27)
3146#define FDI_FE_ERRC_ENABLE (1<<26)
3117#define FDI_DP_PORT_WIDTH_X8 (7<<19) 3147#define FDI_DP_PORT_WIDTH_X8 (7<<19)
3118#define FDI_8BPC (0<<16) 3148#define FDI_8BPC (0<<16)
3119#define FDI_10BPC (1<<16) 3149#define FDI_10BPC (1<<16)
@@ -3386,7 +3416,7 @@
3386#define GEN6_PMINTRMSK 0xA168 3416#define GEN6_PMINTRMSK 0xA168
3387 3417
3388#define GEN6_PMISR 0x44020 3418#define GEN6_PMISR 0x44020
3389#define GEN6_PMIMR 0x44024 3419#define GEN6_PMIMR 0x44024 /* rps_lock */
3390#define GEN6_PMIIR 0x44028 3420#define GEN6_PMIIR 0x44028
3391#define GEN6_PMIER 0x4402C 3421#define GEN6_PMIER 0x4402C
3392#define GEN6_PM_MBOX_EVENT (1<<25) 3422#define GEN6_PM_MBOX_EVENT (1<<25)
@@ -3396,6 +3426,9 @@
3396#define GEN6_PM_RP_DOWN_THRESHOLD (1<<4) 3426#define GEN6_PM_RP_DOWN_THRESHOLD (1<<4)
3397#define GEN6_PM_RP_UP_EI_EXPIRED (1<<2) 3427#define GEN6_PM_RP_UP_EI_EXPIRED (1<<2)
3398#define GEN6_PM_RP_DOWN_EI_EXPIRED (1<<1) 3428#define GEN6_PM_RP_DOWN_EI_EXPIRED (1<<1)
3429#define GEN6_PM_DEFERRED_EVENTS (GEN6_PM_RP_UP_THRESHOLD | \
3430 GEN6_PM_RP_DOWN_THRESHOLD | \
3431 GEN6_PM_RP_DOWN_TIMEOUT)
3399 3432
3400#define GEN6_PCODE_MAILBOX 0x138124 3433#define GEN6_PCODE_MAILBOX 0x138124
3401#define GEN6_PCODE_READY (1<<31) 3434#define GEN6_PCODE_READY (1<<31)
diff --git a/drivers/gpu/drm/i915/i915_suspend.c b/drivers/gpu/drm/i915/i915_suspend.c
index da474153a0a2..60a94d2b5264 100644
--- a/drivers/gpu/drm/i915/i915_suspend.c
+++ b/drivers/gpu/drm/i915/i915_suspend.c
@@ -863,8 +863,7 @@ int i915_restore_state(struct drm_device *dev)
863 I915_WRITE(IMR, dev_priv->saveIMR); 863 I915_WRITE(IMR, dev_priv->saveIMR);
864 } 864 }
865 865
866 /* Clock gating state */ 866 intel_init_clock_gating(dev);
867 intel_enable_clock_gating(dev);
868 867
869 if (IS_IRONLAKE_M(dev)) { 868 if (IS_IRONLAKE_M(dev)) {
870 ironlake_enable_drps(dev); 869 ironlake_enable_drps(dev);
diff --git a/drivers/gpu/drm/i915/intel_bios.c b/drivers/gpu/drm/i915/intel_bios.c
index fb5b4d426ae0..927442a11925 100644
--- a/drivers/gpu/drm/i915/intel_bios.c
+++ b/drivers/gpu/drm/i915/intel_bios.c
@@ -214,9 +214,9 @@ parse_lfp_panel_data(struct drm_i915_private *dev_priv,
214 i915_lvds_downclock) { 214 i915_lvds_downclock) {
215 dev_priv->lvds_downclock_avail = 1; 215 dev_priv->lvds_downclock_avail = 1;
216 dev_priv->lvds_downclock = temp_downclock; 216 dev_priv->lvds_downclock = temp_downclock;
217 DRM_DEBUG_KMS("LVDS downclock is found in VBT. ", 217 DRM_DEBUG_KMS("LVDS downclock is found in VBT. "
218 "Normal Clock %dKHz, downclock %dKHz\n", 218 "Normal Clock %dKHz, downclock %dKHz\n",
219 temp_downclock, panel_fixed_mode->clock); 219 temp_downclock, panel_fixed_mode->clock);
220 } 220 }
221 return; 221 return;
222} 222}
diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c
index d03fc05b39c0..e93f93cc7e78 100644
--- a/drivers/gpu/drm/i915/intel_crt.c
+++ b/drivers/gpu/drm/i915/intel_crt.c
@@ -305,13 +305,11 @@ static bool intel_crt_detect_ddc(struct drm_connector *connector)
305} 305}
306 306
307static enum drm_connector_status 307static enum drm_connector_status
308intel_crt_load_detect(struct drm_crtc *crtc, struct intel_crt *crt) 308intel_crt_load_detect(struct intel_crt *crt)
309{ 309{
310 struct drm_encoder *encoder = &crt->base.base; 310 struct drm_device *dev = crt->base.base.dev;
311 struct drm_device *dev = encoder->dev;
312 struct drm_i915_private *dev_priv = dev->dev_private; 311 struct drm_i915_private *dev_priv = dev->dev_private;
313 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 312 uint32_t pipe = to_intel_crtc(crt->base.base.crtc)->pipe;
314 uint32_t pipe = intel_crtc->pipe;
315 uint32_t save_bclrpat; 313 uint32_t save_bclrpat;
316 uint32_t save_vtotal; 314 uint32_t save_vtotal;
317 uint32_t vtotal, vactive; 315 uint32_t vtotal, vactive;
@@ -432,7 +430,6 @@ intel_crt_detect(struct drm_connector *connector, bool force)
432 struct drm_device *dev = connector->dev; 430 struct drm_device *dev = connector->dev;
433 struct intel_crt *crt = intel_attached_crt(connector); 431 struct intel_crt *crt = intel_attached_crt(connector);
434 struct drm_crtc *crtc; 432 struct drm_crtc *crtc;
435 int dpms_mode;
436 enum drm_connector_status status; 433 enum drm_connector_status status;
437 434
438 if (I915_HAS_HOTPLUG(dev)) { 435 if (I915_HAS_HOTPLUG(dev)) {
@@ -454,17 +451,18 @@ intel_crt_detect(struct drm_connector *connector, bool force)
454 /* for pre-945g platforms use load detect */ 451 /* for pre-945g platforms use load detect */
455 crtc = crt->base.base.crtc; 452 crtc = crt->base.base.crtc;
456 if (crtc && crtc->enabled) { 453 if (crtc && crtc->enabled) {
457 status = intel_crt_load_detect(crtc, crt); 454 status = intel_crt_load_detect(crt);
458 } else { 455 } else {
459 crtc = intel_get_load_detect_pipe(&crt->base, connector, 456 struct intel_load_detect_pipe tmp;
460 NULL, &dpms_mode); 457
461 if (crtc) { 458 if (intel_get_load_detect_pipe(&crt->base, connector, NULL,
459 &tmp)) {
462 if (intel_crt_detect_ddc(connector)) 460 if (intel_crt_detect_ddc(connector))
463 status = connector_status_connected; 461 status = connector_status_connected;
464 else 462 else
465 status = intel_crt_load_detect(crtc, crt); 463 status = intel_crt_load_detect(crt);
466 intel_release_load_detect_pipe(&crt->base, 464 intel_release_load_detect_pipe(&crt->base, connector,
467 connector, dpms_mode); 465 &tmp);
468 } else 466 } else
469 status = connector_status_unknown; 467 status = connector_status_unknown;
470 } 468 }
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 2166ee071ddb..f553ddfdc168 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -76,255 +76,6 @@ struct intel_limit {
76 int, int, intel_clock_t *); 76 int, int, intel_clock_t *);
77}; 77};
78 78
79#define I8XX_DOT_MIN 25000
80#define I8XX_DOT_MAX 350000
81#define I8XX_VCO_MIN 930000
82#define I8XX_VCO_MAX 1400000
83#define I8XX_N_MIN 3
84#define I8XX_N_MAX 16
85#define I8XX_M_MIN 96
86#define I8XX_M_MAX 140
87#define I8XX_M1_MIN 18
88#define I8XX_M1_MAX 26
89#define I8XX_M2_MIN 6
90#define I8XX_M2_MAX 16
91#define I8XX_P_MIN 4
92#define I8XX_P_MAX 128
93#define I8XX_P1_MIN 2
94#define I8XX_P1_MAX 33
95#define I8XX_P1_LVDS_MIN 1
96#define I8XX_P1_LVDS_MAX 6
97#define I8XX_P2_SLOW 4
98#define I8XX_P2_FAST 2
99#define I8XX_P2_LVDS_SLOW 14
100#define I8XX_P2_LVDS_FAST 7
101#define I8XX_P2_SLOW_LIMIT 165000
102
103#define I9XX_DOT_MIN 20000
104#define I9XX_DOT_MAX 400000
105#define I9XX_VCO_MIN 1400000
106#define I9XX_VCO_MAX 2800000
107#define PINEVIEW_VCO_MIN 1700000
108#define PINEVIEW_VCO_MAX 3500000
109#define I9XX_N_MIN 1
110#define I9XX_N_MAX 6
111/* Pineview's Ncounter is a ring counter */
112#define PINEVIEW_N_MIN 3
113#define PINEVIEW_N_MAX 6
114#define I9XX_M_MIN 70
115#define I9XX_M_MAX 120
116#define PINEVIEW_M_MIN 2
117#define PINEVIEW_M_MAX 256
118#define I9XX_M1_MIN 10
119#define I9XX_M1_MAX 22
120#define I9XX_M2_MIN 5
121#define I9XX_M2_MAX 9
122/* Pineview M1 is reserved, and must be 0 */
123#define PINEVIEW_M1_MIN 0
124#define PINEVIEW_M1_MAX 0
125#define PINEVIEW_M2_MIN 0
126#define PINEVIEW_M2_MAX 254
127#define I9XX_P_SDVO_DAC_MIN 5
128#define I9XX_P_SDVO_DAC_MAX 80
129#define I9XX_P_LVDS_MIN 7
130#define I9XX_P_LVDS_MAX 98
131#define PINEVIEW_P_LVDS_MIN 7
132#define PINEVIEW_P_LVDS_MAX 112
133#define I9XX_P1_MIN 1
134#define I9XX_P1_MAX 8
135#define I9XX_P2_SDVO_DAC_SLOW 10
136#define I9XX_P2_SDVO_DAC_FAST 5
137#define I9XX_P2_SDVO_DAC_SLOW_LIMIT 200000
138#define I9XX_P2_LVDS_SLOW 14
139#define I9XX_P2_LVDS_FAST 7
140#define I9XX_P2_LVDS_SLOW_LIMIT 112000
141
142/*The parameter is for SDVO on G4x platform*/
143#define G4X_DOT_SDVO_MIN 25000
144#define G4X_DOT_SDVO_MAX 270000
145#define G4X_VCO_MIN 1750000
146#define G4X_VCO_MAX 3500000
147#define G4X_N_SDVO_MIN 1
148#define G4X_N_SDVO_MAX 4
149#define G4X_M_SDVO_MIN 104
150#define G4X_M_SDVO_MAX 138
151#define G4X_M1_SDVO_MIN 17
152#define G4X_M1_SDVO_MAX 23
153#define G4X_M2_SDVO_MIN 5
154#define G4X_M2_SDVO_MAX 11
155#define G4X_P_SDVO_MIN 10
156#define G4X_P_SDVO_MAX 30
157#define G4X_P1_SDVO_MIN 1
158#define G4X_P1_SDVO_MAX 3
159#define G4X_P2_SDVO_SLOW 10
160#define G4X_P2_SDVO_FAST 10
161#define G4X_P2_SDVO_LIMIT 270000
162
163/*The parameter is for HDMI_DAC on G4x platform*/
164#define G4X_DOT_HDMI_DAC_MIN 22000
165#define G4X_DOT_HDMI_DAC_MAX 400000
166#define G4X_N_HDMI_DAC_MIN 1
167#define G4X_N_HDMI_DAC_MAX 4
168#define G4X_M_HDMI_DAC_MIN 104
169#define G4X_M_HDMI_DAC_MAX 138
170#define G4X_M1_HDMI_DAC_MIN 16
171#define G4X_M1_HDMI_DAC_MAX 23
172#define G4X_M2_HDMI_DAC_MIN 5
173#define G4X_M2_HDMI_DAC_MAX 11
174#define G4X_P_HDMI_DAC_MIN 5
175#define G4X_P_HDMI_DAC_MAX 80
176#define G4X_P1_HDMI_DAC_MIN 1
177#define G4X_P1_HDMI_DAC_MAX 8
178#define G4X_P2_HDMI_DAC_SLOW 10
179#define G4X_P2_HDMI_DAC_FAST 5
180#define G4X_P2_HDMI_DAC_LIMIT 165000
181
182/*The parameter is for SINGLE_CHANNEL_LVDS on G4x platform*/
183#define G4X_DOT_SINGLE_CHANNEL_LVDS_MIN 20000
184#define G4X_DOT_SINGLE_CHANNEL_LVDS_MAX 115000
185#define G4X_N_SINGLE_CHANNEL_LVDS_MIN 1
186#define G4X_N_SINGLE_CHANNEL_LVDS_MAX 3
187#define G4X_M_SINGLE_CHANNEL_LVDS_MIN 104
188#define G4X_M_SINGLE_CHANNEL_LVDS_MAX 138
189#define G4X_M1_SINGLE_CHANNEL_LVDS_MIN 17
190#define G4X_M1_SINGLE_CHANNEL_LVDS_MAX 23
191#define G4X_M2_SINGLE_CHANNEL_LVDS_MIN 5
192#define G4X_M2_SINGLE_CHANNEL_LVDS_MAX 11
193#define G4X_P_SINGLE_CHANNEL_LVDS_MIN 28
194#define G4X_P_SINGLE_CHANNEL_LVDS_MAX 112
195#define G4X_P1_SINGLE_CHANNEL_LVDS_MIN 2
196#define G4X_P1_SINGLE_CHANNEL_LVDS_MAX 8
197#define G4X_P2_SINGLE_CHANNEL_LVDS_SLOW 14
198#define G4X_P2_SINGLE_CHANNEL_LVDS_FAST 14
199#define G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT 0
200
201/*The parameter is for DUAL_CHANNEL_LVDS on G4x platform*/
202#define G4X_DOT_DUAL_CHANNEL_LVDS_MIN 80000
203#define G4X_DOT_DUAL_CHANNEL_LVDS_MAX 224000
204#define G4X_N_DUAL_CHANNEL_LVDS_MIN 1
205#define G4X_N_DUAL_CHANNEL_LVDS_MAX 3
206#define G4X_M_DUAL_CHANNEL_LVDS_MIN 104
207#define G4X_M_DUAL_CHANNEL_LVDS_MAX 138
208#define G4X_M1_DUAL_CHANNEL_LVDS_MIN 17
209#define G4X_M1_DUAL_CHANNEL_LVDS_MAX 23
210#define G4X_M2_DUAL_CHANNEL_LVDS_MIN 5
211#define G4X_M2_DUAL_CHANNEL_LVDS_MAX 11
212#define G4X_P_DUAL_CHANNEL_LVDS_MIN 14
213#define G4X_P_DUAL_CHANNEL_LVDS_MAX 42
214#define G4X_P1_DUAL_CHANNEL_LVDS_MIN 2
215#define G4X_P1_DUAL_CHANNEL_LVDS_MAX 6
216#define G4X_P2_DUAL_CHANNEL_LVDS_SLOW 7
217#define G4X_P2_DUAL_CHANNEL_LVDS_FAST 7
218#define G4X_P2_DUAL_CHANNEL_LVDS_LIMIT 0
219
220/*The parameter is for DISPLAY PORT on G4x platform*/
221#define G4X_DOT_DISPLAY_PORT_MIN 161670
222#define G4X_DOT_DISPLAY_PORT_MAX 227000
223#define G4X_N_DISPLAY_PORT_MIN 1
224#define G4X_N_DISPLAY_PORT_MAX 2
225#define G4X_M_DISPLAY_PORT_MIN 97
226#define G4X_M_DISPLAY_PORT_MAX 108
227#define G4X_M1_DISPLAY_PORT_MIN 0x10
228#define G4X_M1_DISPLAY_PORT_MAX 0x12
229#define G4X_M2_DISPLAY_PORT_MIN 0x05
230#define G4X_M2_DISPLAY_PORT_MAX 0x06
231#define G4X_P_DISPLAY_PORT_MIN 10
232#define G4X_P_DISPLAY_PORT_MAX 20
233#define G4X_P1_DISPLAY_PORT_MIN 1
234#define G4X_P1_DISPLAY_PORT_MAX 2
235#define G4X_P2_DISPLAY_PORT_SLOW 10
236#define G4X_P2_DISPLAY_PORT_FAST 10
237#define G4X_P2_DISPLAY_PORT_LIMIT 0
238
239/* Ironlake / Sandybridge */
240/* as we calculate clock using (register_value + 2) for
241 N/M1/M2, so here the range value for them is (actual_value-2).
242 */
243#define IRONLAKE_DOT_MIN 25000
244#define IRONLAKE_DOT_MAX 350000
245#define IRONLAKE_VCO_MIN 1760000
246#define IRONLAKE_VCO_MAX 3510000
247#define IRONLAKE_M1_MIN 12
248#define IRONLAKE_M1_MAX 22
249#define IRONLAKE_M2_MIN 5
250#define IRONLAKE_M2_MAX 9
251#define IRONLAKE_P2_DOT_LIMIT 225000 /* 225Mhz */
252
253/* We have parameter ranges for different type of outputs. */
254
255/* DAC & HDMI Refclk 120Mhz */
256#define IRONLAKE_DAC_N_MIN 1
257#define IRONLAKE_DAC_N_MAX 5
258#define IRONLAKE_DAC_M_MIN 79
259#define IRONLAKE_DAC_M_MAX 127
260#define IRONLAKE_DAC_P_MIN 5
261#define IRONLAKE_DAC_P_MAX 80
262#define IRONLAKE_DAC_P1_MIN 1
263#define IRONLAKE_DAC_P1_MAX 8
264#define IRONLAKE_DAC_P2_SLOW 10
265#define IRONLAKE_DAC_P2_FAST 5
266
267/* LVDS single-channel 120Mhz refclk */
268#define IRONLAKE_LVDS_S_N_MIN 1
269#define IRONLAKE_LVDS_S_N_MAX 3
270#define IRONLAKE_LVDS_S_M_MIN 79
271#define IRONLAKE_LVDS_S_M_MAX 118
272#define IRONLAKE_LVDS_S_P_MIN 28
273#define IRONLAKE_LVDS_S_P_MAX 112
274#define IRONLAKE_LVDS_S_P1_MIN 2
275#define IRONLAKE_LVDS_S_P1_MAX 8
276#define IRONLAKE_LVDS_S_P2_SLOW 14
277#define IRONLAKE_LVDS_S_P2_FAST 14
278
279/* LVDS dual-channel 120Mhz refclk */
280#define IRONLAKE_LVDS_D_N_MIN 1
281#define IRONLAKE_LVDS_D_N_MAX 3
282#define IRONLAKE_LVDS_D_M_MIN 79
283#define IRONLAKE_LVDS_D_M_MAX 127
284#define IRONLAKE_LVDS_D_P_MIN 14
285#define IRONLAKE_LVDS_D_P_MAX 56
286#define IRONLAKE_LVDS_D_P1_MIN 2
287#define IRONLAKE_LVDS_D_P1_MAX 8
288#define IRONLAKE_LVDS_D_P2_SLOW 7
289#define IRONLAKE_LVDS_D_P2_FAST 7
290
291/* LVDS single-channel 100Mhz refclk */
292#define IRONLAKE_LVDS_S_SSC_N_MIN 1
293#define IRONLAKE_LVDS_S_SSC_N_MAX 2
294#define IRONLAKE_LVDS_S_SSC_M_MIN 79
295#define IRONLAKE_LVDS_S_SSC_M_MAX 126
296#define IRONLAKE_LVDS_S_SSC_P_MIN 28
297#define IRONLAKE_LVDS_S_SSC_P_MAX 112
298#define IRONLAKE_LVDS_S_SSC_P1_MIN 2
299#define IRONLAKE_LVDS_S_SSC_P1_MAX 8
300#define IRONLAKE_LVDS_S_SSC_P2_SLOW 14
301#define IRONLAKE_LVDS_S_SSC_P2_FAST 14
302
303/* LVDS dual-channel 100Mhz refclk */
304#define IRONLAKE_LVDS_D_SSC_N_MIN 1
305#define IRONLAKE_LVDS_D_SSC_N_MAX 3
306#define IRONLAKE_LVDS_D_SSC_M_MIN 79
307#define IRONLAKE_LVDS_D_SSC_M_MAX 126
308#define IRONLAKE_LVDS_D_SSC_P_MIN 14
309#define IRONLAKE_LVDS_D_SSC_P_MAX 42
310#define IRONLAKE_LVDS_D_SSC_P1_MIN 2
311#define IRONLAKE_LVDS_D_SSC_P1_MAX 6
312#define IRONLAKE_LVDS_D_SSC_P2_SLOW 7
313#define IRONLAKE_LVDS_D_SSC_P2_FAST 7
314
315/* DisplayPort */
316#define IRONLAKE_DP_N_MIN 1
317#define IRONLAKE_DP_N_MAX 2
318#define IRONLAKE_DP_M_MIN 81
319#define IRONLAKE_DP_M_MAX 90
320#define IRONLAKE_DP_P_MIN 10
321#define IRONLAKE_DP_P_MAX 20
322#define IRONLAKE_DP_P2_FAST 10
323#define IRONLAKE_DP_P2_SLOW 10
324#define IRONLAKE_DP_P2_LIMIT 0
325#define IRONLAKE_DP_P1_MIN 1
326#define IRONLAKE_DP_P1_MAX 2
327
328/* FDI */ 79/* FDI */
329#define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */ 80#define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
330 81
@@ -353,292 +104,253 @@ intel_fdi_link_freq(struct drm_device *dev)
353} 104}
354 105
355static const intel_limit_t intel_limits_i8xx_dvo = { 106static const intel_limit_t intel_limits_i8xx_dvo = {
356 .dot = { .min = I8XX_DOT_MIN, .max = I8XX_DOT_MAX }, 107 .dot = { .min = 25000, .max = 350000 },
357 .vco = { .min = I8XX_VCO_MIN, .max = I8XX_VCO_MAX }, 108 .vco = { .min = 930000, .max = 1400000 },
358 .n = { .min = I8XX_N_MIN, .max = I8XX_N_MAX }, 109 .n = { .min = 3, .max = 16 },
359 .m = { .min = I8XX_M_MIN, .max = I8XX_M_MAX }, 110 .m = { .min = 96, .max = 140 },
360 .m1 = { .min = I8XX_M1_MIN, .max = I8XX_M1_MAX }, 111 .m1 = { .min = 18, .max = 26 },
361 .m2 = { .min = I8XX_M2_MIN, .max = I8XX_M2_MAX }, 112 .m2 = { .min = 6, .max = 16 },
362 .p = { .min = I8XX_P_MIN, .max = I8XX_P_MAX }, 113 .p = { .min = 4, .max = 128 },
363 .p1 = { .min = I8XX_P1_MIN, .max = I8XX_P1_MAX }, 114 .p1 = { .min = 2, .max = 33 },
364 .p2 = { .dot_limit = I8XX_P2_SLOW_LIMIT, 115 .p2 = { .dot_limit = 165000,
365 .p2_slow = I8XX_P2_SLOW, .p2_fast = I8XX_P2_FAST }, 116 .p2_slow = 4, .p2_fast = 2 },
366 .find_pll = intel_find_best_PLL, 117 .find_pll = intel_find_best_PLL,
367}; 118};
368 119
369static const intel_limit_t intel_limits_i8xx_lvds = { 120static const intel_limit_t intel_limits_i8xx_lvds = {
370 .dot = { .min = I8XX_DOT_MIN, .max = I8XX_DOT_MAX }, 121 .dot = { .min = 25000, .max = 350000 },
371 .vco = { .min = I8XX_VCO_MIN, .max = I8XX_VCO_MAX }, 122 .vco = { .min = 930000, .max = 1400000 },
372 .n = { .min = I8XX_N_MIN, .max = I8XX_N_MAX }, 123 .n = { .min = 3, .max = 16 },
373 .m = { .min = I8XX_M_MIN, .max = I8XX_M_MAX }, 124 .m = { .min = 96, .max = 140 },
374 .m1 = { .min = I8XX_M1_MIN, .max = I8XX_M1_MAX }, 125 .m1 = { .min = 18, .max = 26 },
375 .m2 = { .min = I8XX_M2_MIN, .max = I8XX_M2_MAX }, 126 .m2 = { .min = 6, .max = 16 },
376 .p = { .min = I8XX_P_MIN, .max = I8XX_P_MAX }, 127 .p = { .min = 4, .max = 128 },
377 .p1 = { .min = I8XX_P1_LVDS_MIN, .max = I8XX_P1_LVDS_MAX }, 128 .p1 = { .min = 1, .max = 6 },
378 .p2 = { .dot_limit = I8XX_P2_SLOW_LIMIT, 129 .p2 = { .dot_limit = 165000,
379 .p2_slow = I8XX_P2_LVDS_SLOW, .p2_fast = I8XX_P2_LVDS_FAST }, 130 .p2_slow = 14, .p2_fast = 7 },
380 .find_pll = intel_find_best_PLL, 131 .find_pll = intel_find_best_PLL,
381}; 132};
382 133
383static const intel_limit_t intel_limits_i9xx_sdvo = { 134static const intel_limit_t intel_limits_i9xx_sdvo = {
384 .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX }, 135 .dot = { .min = 20000, .max = 400000 },
385 .vco = { .min = I9XX_VCO_MIN, .max = I9XX_VCO_MAX }, 136 .vco = { .min = 1400000, .max = 2800000 },
386 .n = { .min = I9XX_N_MIN, .max = I9XX_N_MAX }, 137 .n = { .min = 1, .max = 6 },
387 .m = { .min = I9XX_M_MIN, .max = I9XX_M_MAX }, 138 .m = { .min = 70, .max = 120 },
388 .m1 = { .min = I9XX_M1_MIN, .max = I9XX_M1_MAX }, 139 .m1 = { .min = 10, .max = 22 },
389 .m2 = { .min = I9XX_M2_MIN, .max = I9XX_M2_MAX }, 140 .m2 = { .min = 5, .max = 9 },
390 .p = { .min = I9XX_P_SDVO_DAC_MIN, .max = I9XX_P_SDVO_DAC_MAX }, 141 .p = { .min = 5, .max = 80 },
391 .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX }, 142 .p1 = { .min = 1, .max = 8 },
392 .p2 = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT, 143 .p2 = { .dot_limit = 200000,
393 .p2_slow = I9XX_P2_SDVO_DAC_SLOW, .p2_fast = I9XX_P2_SDVO_DAC_FAST }, 144 .p2_slow = 10, .p2_fast = 5 },
394 .find_pll = intel_find_best_PLL, 145 .find_pll = intel_find_best_PLL,
395}; 146};
396 147
397static const intel_limit_t intel_limits_i9xx_lvds = { 148static const intel_limit_t intel_limits_i9xx_lvds = {
398 .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX }, 149 .dot = { .min = 20000, .max = 400000 },
399 .vco = { .min = I9XX_VCO_MIN, .max = I9XX_VCO_MAX }, 150 .vco = { .min = 1400000, .max = 2800000 },
400 .n = { .min = I9XX_N_MIN, .max = I9XX_N_MAX }, 151 .n = { .min = 1, .max = 6 },
401 .m = { .min = I9XX_M_MIN, .max = I9XX_M_MAX }, 152 .m = { .min = 70, .max = 120 },
402 .m1 = { .min = I9XX_M1_MIN, .max = I9XX_M1_MAX }, 153 .m1 = { .min = 10, .max = 22 },
403 .m2 = { .min = I9XX_M2_MIN, .max = I9XX_M2_MAX }, 154 .m2 = { .min = 5, .max = 9 },
404 .p = { .min = I9XX_P_LVDS_MIN, .max = I9XX_P_LVDS_MAX }, 155 .p = { .min = 7, .max = 98 },
405 .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX }, 156 .p1 = { .min = 1, .max = 8 },
406 /* The single-channel range is 25-112Mhz, and dual-channel 157 .p2 = { .dot_limit = 112000,
407 * is 80-224Mhz. Prefer single channel as much as possible. 158 .p2_slow = 14, .p2_fast = 7 },
408 */
409 .p2 = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
410 .p2_slow = I9XX_P2_LVDS_SLOW, .p2_fast = I9XX_P2_LVDS_FAST },
411 .find_pll = intel_find_best_PLL, 159 .find_pll = intel_find_best_PLL,
412}; 160};
413 161
414 /* below parameter and function is for G4X Chipset Family*/ 162
415static const intel_limit_t intel_limits_g4x_sdvo = { 163static const intel_limit_t intel_limits_g4x_sdvo = {
416 .dot = { .min = G4X_DOT_SDVO_MIN, .max = G4X_DOT_SDVO_MAX }, 164 .dot = { .min = 25000, .max = 270000 },
417 .vco = { .min = G4X_VCO_MIN, .max = G4X_VCO_MAX}, 165 .vco = { .min = 1750000, .max = 3500000},
418 .n = { .min = G4X_N_SDVO_MIN, .max = G4X_N_SDVO_MAX }, 166 .n = { .min = 1, .max = 4 },
419 .m = { .min = G4X_M_SDVO_MIN, .max = G4X_M_SDVO_MAX }, 167 .m = { .min = 104, .max = 138 },
420 .m1 = { .min = G4X_M1_SDVO_MIN, .max = G4X_M1_SDVO_MAX }, 168 .m1 = { .min = 17, .max = 23 },
421 .m2 = { .min = G4X_M2_SDVO_MIN, .max = G4X_M2_SDVO_MAX }, 169 .m2 = { .min = 5, .max = 11 },
422 .p = { .min = G4X_P_SDVO_MIN, .max = G4X_P_SDVO_MAX }, 170 .p = { .min = 10, .max = 30 },
423 .p1 = { .min = G4X_P1_SDVO_MIN, .max = G4X_P1_SDVO_MAX}, 171 .p1 = { .min = 1, .max = 3},
424 .p2 = { .dot_limit = G4X_P2_SDVO_LIMIT, 172 .p2 = { .dot_limit = 270000,
425 .p2_slow = G4X_P2_SDVO_SLOW, 173 .p2_slow = 10,
426 .p2_fast = G4X_P2_SDVO_FAST 174 .p2_fast = 10
427 }, 175 },
428 .find_pll = intel_g4x_find_best_PLL, 176 .find_pll = intel_g4x_find_best_PLL,
429}; 177};
430 178
431static const intel_limit_t intel_limits_g4x_hdmi = { 179static const intel_limit_t intel_limits_g4x_hdmi = {
432 .dot = { .min = G4X_DOT_HDMI_DAC_MIN, .max = G4X_DOT_HDMI_DAC_MAX }, 180 .dot = { .min = 22000, .max = 400000 },
433 .vco = { .min = G4X_VCO_MIN, .max = G4X_VCO_MAX}, 181 .vco = { .min = 1750000, .max = 3500000},
434 .n = { .min = G4X_N_HDMI_DAC_MIN, .max = G4X_N_HDMI_DAC_MAX }, 182 .n = { .min = 1, .max = 4 },
435 .m = { .min = G4X_M_HDMI_DAC_MIN, .max = G4X_M_HDMI_DAC_MAX }, 183 .m = { .min = 104, .max = 138 },
436 .m1 = { .min = G4X_M1_HDMI_DAC_MIN, .max = G4X_M1_HDMI_DAC_MAX }, 184 .m1 = { .min = 16, .max = 23 },
437 .m2 = { .min = G4X_M2_HDMI_DAC_MIN, .max = G4X_M2_HDMI_DAC_MAX }, 185 .m2 = { .min = 5, .max = 11 },
438 .p = { .min = G4X_P_HDMI_DAC_MIN, .max = G4X_P_HDMI_DAC_MAX }, 186 .p = { .min = 5, .max = 80 },
439 .p1 = { .min = G4X_P1_HDMI_DAC_MIN, .max = G4X_P1_HDMI_DAC_MAX}, 187 .p1 = { .min = 1, .max = 8},
440 .p2 = { .dot_limit = G4X_P2_HDMI_DAC_LIMIT, 188 .p2 = { .dot_limit = 165000,
441 .p2_slow = G4X_P2_HDMI_DAC_SLOW, 189 .p2_slow = 10, .p2_fast = 5 },
442 .p2_fast = G4X_P2_HDMI_DAC_FAST
443 },
444 .find_pll = intel_g4x_find_best_PLL, 190 .find_pll = intel_g4x_find_best_PLL,
445}; 191};
446 192
447static const intel_limit_t intel_limits_g4x_single_channel_lvds = { 193static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
448 .dot = { .min = G4X_DOT_SINGLE_CHANNEL_LVDS_MIN, 194 .dot = { .min = 20000, .max = 115000 },
449 .max = G4X_DOT_SINGLE_CHANNEL_LVDS_MAX }, 195 .vco = { .min = 1750000, .max = 3500000 },
450 .vco = { .min = G4X_VCO_MIN, 196 .n = { .min = 1, .max = 3 },
451 .max = G4X_VCO_MAX }, 197 .m = { .min = 104, .max = 138 },
452 .n = { .min = G4X_N_SINGLE_CHANNEL_LVDS_MIN, 198 .m1 = { .min = 17, .max = 23 },
453 .max = G4X_N_SINGLE_CHANNEL_LVDS_MAX }, 199 .m2 = { .min = 5, .max = 11 },
454 .m = { .min = G4X_M_SINGLE_CHANNEL_LVDS_MIN, 200 .p = { .min = 28, .max = 112 },
455 .max = G4X_M_SINGLE_CHANNEL_LVDS_MAX }, 201 .p1 = { .min = 2, .max = 8 },
456 .m1 = { .min = G4X_M1_SINGLE_CHANNEL_LVDS_MIN, 202 .p2 = { .dot_limit = 0,
457 .max = G4X_M1_SINGLE_CHANNEL_LVDS_MAX }, 203 .p2_slow = 14, .p2_fast = 14
458 .m2 = { .min = G4X_M2_SINGLE_CHANNEL_LVDS_MIN,
459 .max = G4X_M2_SINGLE_CHANNEL_LVDS_MAX },
460 .p = { .min = G4X_P_SINGLE_CHANNEL_LVDS_MIN,
461 .max = G4X_P_SINGLE_CHANNEL_LVDS_MAX },
462 .p1 = { .min = G4X_P1_SINGLE_CHANNEL_LVDS_MIN,
463 .max = G4X_P1_SINGLE_CHANNEL_LVDS_MAX },
464 .p2 = { .dot_limit = G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT,
465 .p2_slow = G4X_P2_SINGLE_CHANNEL_LVDS_SLOW,
466 .p2_fast = G4X_P2_SINGLE_CHANNEL_LVDS_FAST
467 }, 204 },
468 .find_pll = intel_g4x_find_best_PLL, 205 .find_pll = intel_g4x_find_best_PLL,
469}; 206};
470 207
471static const intel_limit_t intel_limits_g4x_dual_channel_lvds = { 208static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
472 .dot = { .min = G4X_DOT_DUAL_CHANNEL_LVDS_MIN, 209 .dot = { .min = 80000, .max = 224000 },
473 .max = G4X_DOT_DUAL_CHANNEL_LVDS_MAX }, 210 .vco = { .min = 1750000, .max = 3500000 },
474 .vco = { .min = G4X_VCO_MIN, 211 .n = { .min = 1, .max = 3 },
475 .max = G4X_VCO_MAX }, 212 .m = { .min = 104, .max = 138 },
476 .n = { .min = G4X_N_DUAL_CHANNEL_LVDS_MIN, 213 .m1 = { .min = 17, .max = 23 },
477 .max = G4X_N_DUAL_CHANNEL_LVDS_MAX }, 214 .m2 = { .min = 5, .max = 11 },
478 .m = { .min = G4X_M_DUAL_CHANNEL_LVDS_MIN, 215 .p = { .min = 14, .max = 42 },
479 .max = G4X_M_DUAL_CHANNEL_LVDS_MAX }, 216 .p1 = { .min = 2, .max = 6 },
480 .m1 = { .min = G4X_M1_DUAL_CHANNEL_LVDS_MIN, 217 .p2 = { .dot_limit = 0,
481 .max = G4X_M1_DUAL_CHANNEL_LVDS_MAX }, 218 .p2_slow = 7, .p2_fast = 7
482 .m2 = { .min = G4X_M2_DUAL_CHANNEL_LVDS_MIN,
483 .max = G4X_M2_DUAL_CHANNEL_LVDS_MAX },
484 .p = { .min = G4X_P_DUAL_CHANNEL_LVDS_MIN,
485 .max = G4X_P_DUAL_CHANNEL_LVDS_MAX },
486 .p1 = { .min = G4X_P1_DUAL_CHANNEL_LVDS_MIN,
487 .max = G4X_P1_DUAL_CHANNEL_LVDS_MAX },
488 .p2 = { .dot_limit = G4X_P2_DUAL_CHANNEL_LVDS_LIMIT,
489 .p2_slow = G4X_P2_DUAL_CHANNEL_LVDS_SLOW,
490 .p2_fast = G4X_P2_DUAL_CHANNEL_LVDS_FAST
491 }, 219 },
492 .find_pll = intel_g4x_find_best_PLL, 220 .find_pll = intel_g4x_find_best_PLL,
493}; 221};
494 222
495static const intel_limit_t intel_limits_g4x_display_port = { 223static const intel_limit_t intel_limits_g4x_display_port = {
496 .dot = { .min = G4X_DOT_DISPLAY_PORT_MIN, 224 .dot = { .min = 161670, .max = 227000 },
497 .max = G4X_DOT_DISPLAY_PORT_MAX }, 225 .vco = { .min = 1750000, .max = 3500000},
498 .vco = { .min = G4X_VCO_MIN, 226 .n = { .min = 1, .max = 2 },
499 .max = G4X_VCO_MAX}, 227 .m = { .min = 97, .max = 108 },
500 .n = { .min = G4X_N_DISPLAY_PORT_MIN, 228 .m1 = { .min = 0x10, .max = 0x12 },
501 .max = G4X_N_DISPLAY_PORT_MAX }, 229 .m2 = { .min = 0x05, .max = 0x06 },
502 .m = { .min = G4X_M_DISPLAY_PORT_MIN, 230 .p = { .min = 10, .max = 20 },
503 .max = G4X_M_DISPLAY_PORT_MAX }, 231 .p1 = { .min = 1, .max = 2},
504 .m1 = { .min = G4X_M1_DISPLAY_PORT_MIN, 232 .p2 = { .dot_limit = 0,
505 .max = G4X_M1_DISPLAY_PORT_MAX }, 233 .p2_slow = 10, .p2_fast = 10 },
506 .m2 = { .min = G4X_M2_DISPLAY_PORT_MIN,
507 .max = G4X_M2_DISPLAY_PORT_MAX },
508 .p = { .min = G4X_P_DISPLAY_PORT_MIN,
509 .max = G4X_P_DISPLAY_PORT_MAX },
510 .p1 = { .min = G4X_P1_DISPLAY_PORT_MIN,
511 .max = G4X_P1_DISPLAY_PORT_MAX},
512 .p2 = { .dot_limit = G4X_P2_DISPLAY_PORT_LIMIT,
513 .p2_slow = G4X_P2_DISPLAY_PORT_SLOW,
514 .p2_fast = G4X_P2_DISPLAY_PORT_FAST },
515 .find_pll = intel_find_pll_g4x_dp, 234 .find_pll = intel_find_pll_g4x_dp,
516}; 235};
517 236
518static const intel_limit_t intel_limits_pineview_sdvo = { 237static const intel_limit_t intel_limits_pineview_sdvo = {
519 .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX}, 238 .dot = { .min = 20000, .max = 400000},
520 .vco = { .min = PINEVIEW_VCO_MIN, .max = PINEVIEW_VCO_MAX }, 239 .vco = { .min = 1700000, .max = 3500000 },
521 .n = { .min = PINEVIEW_N_MIN, .max = PINEVIEW_N_MAX }, 240 /* Pineview's Ncounter is a ring counter */
522 .m = { .min = PINEVIEW_M_MIN, .max = PINEVIEW_M_MAX }, 241 .n = { .min = 3, .max = 6 },
523 .m1 = { .min = PINEVIEW_M1_MIN, .max = PINEVIEW_M1_MAX }, 242 .m = { .min = 2, .max = 256 },
524 .m2 = { .min = PINEVIEW_M2_MIN, .max = PINEVIEW_M2_MAX }, 243 /* Pineview only has one combined m divider, which we treat as m2. */
525 .p = { .min = I9XX_P_SDVO_DAC_MIN, .max = I9XX_P_SDVO_DAC_MAX }, 244 .m1 = { .min = 0, .max = 0 },
526 .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX }, 245 .m2 = { .min = 0, .max = 254 },
527 .p2 = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT, 246 .p = { .min = 5, .max = 80 },
528 .p2_slow = I9XX_P2_SDVO_DAC_SLOW, .p2_fast = I9XX_P2_SDVO_DAC_FAST }, 247 .p1 = { .min = 1, .max = 8 },
248 .p2 = { .dot_limit = 200000,
249 .p2_slow = 10, .p2_fast = 5 },
529 .find_pll = intel_find_best_PLL, 250 .find_pll = intel_find_best_PLL,
530}; 251};
531 252
532static const intel_limit_t intel_limits_pineview_lvds = { 253static const intel_limit_t intel_limits_pineview_lvds = {
533 .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX }, 254 .dot = { .min = 20000, .max = 400000 },
534 .vco = { .min = PINEVIEW_VCO_MIN, .max = PINEVIEW_VCO_MAX }, 255 .vco = { .min = 1700000, .max = 3500000 },
535 .n = { .min = PINEVIEW_N_MIN, .max = PINEVIEW_N_MAX }, 256 .n = { .min = 3, .max = 6 },
536 .m = { .min = PINEVIEW_M_MIN, .max = PINEVIEW_M_MAX }, 257 .m = { .min = 2, .max = 256 },
537 .m1 = { .min = PINEVIEW_M1_MIN, .max = PINEVIEW_M1_MAX }, 258 .m1 = { .min = 0, .max = 0 },
538 .m2 = { .min = PINEVIEW_M2_MIN, .max = PINEVIEW_M2_MAX }, 259 .m2 = { .min = 0, .max = 254 },
539 .p = { .min = PINEVIEW_P_LVDS_MIN, .max = PINEVIEW_P_LVDS_MAX }, 260 .p = { .min = 7, .max = 112 },
540 .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX }, 261 .p1 = { .min = 1, .max = 8 },
541 /* Pineview only supports single-channel mode. */ 262 .p2 = { .dot_limit = 112000,
542 .p2 = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT, 263 .p2_slow = 14, .p2_fast = 14 },
543 .p2_slow = I9XX_P2_LVDS_SLOW, .p2_fast = I9XX_P2_LVDS_SLOW },
544 .find_pll = intel_find_best_PLL, 264 .find_pll = intel_find_best_PLL,
545}; 265};
546 266
267/* Ironlake / Sandybridge
268 *
269 * We calculate clock using (register_value + 2) for N/M1/M2, so here
270 * the range value for them is (actual_value - 2).
271 */
547static const intel_limit_t intel_limits_ironlake_dac = { 272static const intel_limit_t intel_limits_ironlake_dac = {
548 .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX }, 273 .dot = { .min = 25000, .max = 350000 },
549 .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX }, 274 .vco = { .min = 1760000, .max = 3510000 },
550 .n = { .min = IRONLAKE_DAC_N_MIN, .max = IRONLAKE_DAC_N_MAX }, 275 .n = { .min = 1, .max = 5 },
551 .m = { .min = IRONLAKE_DAC_M_MIN, .max = IRONLAKE_DAC_M_MAX }, 276 .m = { .min = 79, .max = 127 },
552 .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX }, 277 .m1 = { .min = 12, .max = 22 },
553 .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX }, 278 .m2 = { .min = 5, .max = 9 },
554 .p = { .min = IRONLAKE_DAC_P_MIN, .max = IRONLAKE_DAC_P_MAX }, 279 .p = { .min = 5, .max = 80 },
555 .p1 = { .min = IRONLAKE_DAC_P1_MIN, .max = IRONLAKE_DAC_P1_MAX }, 280 .p1 = { .min = 1, .max = 8 },
556 .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT, 281 .p2 = { .dot_limit = 225000,
557 .p2_slow = IRONLAKE_DAC_P2_SLOW, 282 .p2_slow = 10, .p2_fast = 5 },
558 .p2_fast = IRONLAKE_DAC_P2_FAST },
559 .find_pll = intel_g4x_find_best_PLL, 283 .find_pll = intel_g4x_find_best_PLL,
560}; 284};
561 285
562static const intel_limit_t intel_limits_ironlake_single_lvds = { 286static const intel_limit_t intel_limits_ironlake_single_lvds = {
563 .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX }, 287 .dot = { .min = 25000, .max = 350000 },
564 .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX }, 288 .vco = { .min = 1760000, .max = 3510000 },
565 .n = { .min = IRONLAKE_LVDS_S_N_MIN, .max = IRONLAKE_LVDS_S_N_MAX }, 289 .n = { .min = 1, .max = 3 },
566 .m = { .min = IRONLAKE_LVDS_S_M_MIN, .max = IRONLAKE_LVDS_S_M_MAX }, 290 .m = { .min = 79, .max = 118 },
567 .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX }, 291 .m1 = { .min = 12, .max = 22 },
568 .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX }, 292 .m2 = { .min = 5, .max = 9 },
569 .p = { .min = IRONLAKE_LVDS_S_P_MIN, .max = IRONLAKE_LVDS_S_P_MAX }, 293 .p = { .min = 28, .max = 112 },
570 .p1 = { .min = IRONLAKE_LVDS_S_P1_MIN, .max = IRONLAKE_LVDS_S_P1_MAX }, 294 .p1 = { .min = 2, .max = 8 },
571 .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT, 295 .p2 = { .dot_limit = 225000,
572 .p2_slow = IRONLAKE_LVDS_S_P2_SLOW, 296 .p2_slow = 14, .p2_fast = 14 },
573 .p2_fast = IRONLAKE_LVDS_S_P2_FAST },
574 .find_pll = intel_g4x_find_best_PLL, 297 .find_pll = intel_g4x_find_best_PLL,
575}; 298};
576 299
577static const intel_limit_t intel_limits_ironlake_dual_lvds = { 300static const intel_limit_t intel_limits_ironlake_dual_lvds = {
578 .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX }, 301 .dot = { .min = 25000, .max = 350000 },
579 .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX }, 302 .vco = { .min = 1760000, .max = 3510000 },
580 .n = { .min = IRONLAKE_LVDS_D_N_MIN, .max = IRONLAKE_LVDS_D_N_MAX }, 303 .n = { .min = 1, .max = 3 },
581 .m = { .min = IRONLAKE_LVDS_D_M_MIN, .max = IRONLAKE_LVDS_D_M_MAX }, 304 .m = { .min = 79, .max = 127 },
582 .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX }, 305 .m1 = { .min = 12, .max = 22 },
583 .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX }, 306 .m2 = { .min = 5, .max = 9 },
584 .p = { .min = IRONLAKE_LVDS_D_P_MIN, .max = IRONLAKE_LVDS_D_P_MAX }, 307 .p = { .min = 14, .max = 56 },
585 .p1 = { .min = IRONLAKE_LVDS_D_P1_MIN, .max = IRONLAKE_LVDS_D_P1_MAX }, 308 .p1 = { .min = 2, .max = 8 },
586 .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT, 309 .p2 = { .dot_limit = 225000,
587 .p2_slow = IRONLAKE_LVDS_D_P2_SLOW, 310 .p2_slow = 7, .p2_fast = 7 },
588 .p2_fast = IRONLAKE_LVDS_D_P2_FAST },
589 .find_pll = intel_g4x_find_best_PLL, 311 .find_pll = intel_g4x_find_best_PLL,
590}; 312};
591 313
314/* LVDS 100mhz refclk limits. */
592static const intel_limit_t intel_limits_ironlake_single_lvds_100m = { 315static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
593 .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX }, 316 .dot = { .min = 25000, .max = 350000 },
594 .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX }, 317 .vco = { .min = 1760000, .max = 3510000 },
595 .n = { .min = IRONLAKE_LVDS_S_SSC_N_MIN, .max = IRONLAKE_LVDS_S_SSC_N_MAX }, 318 .n = { .min = 1, .max = 2 },
596 .m = { .min = IRONLAKE_LVDS_S_SSC_M_MIN, .max = IRONLAKE_LVDS_S_SSC_M_MAX }, 319 .m = { .min = 79, .max = 126 },
597 .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX }, 320 .m1 = { .min = 12, .max = 22 },
598 .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX }, 321 .m2 = { .min = 5, .max = 9 },
599 .p = { .min = IRONLAKE_LVDS_S_SSC_P_MIN, .max = IRONLAKE_LVDS_S_SSC_P_MAX }, 322 .p = { .min = 28, .max = 112 },
600 .p1 = { .min = IRONLAKE_LVDS_S_SSC_P1_MIN,.max = IRONLAKE_LVDS_S_SSC_P1_MAX }, 323 .p1 = { .min = 2,.max = 8 },
601 .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT, 324 .p2 = { .dot_limit = 225000,
602 .p2_slow = IRONLAKE_LVDS_S_SSC_P2_SLOW, 325 .p2_slow = 14, .p2_fast = 14 },
603 .p2_fast = IRONLAKE_LVDS_S_SSC_P2_FAST },
604 .find_pll = intel_g4x_find_best_PLL, 326 .find_pll = intel_g4x_find_best_PLL,
605}; 327};
606 328
607static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = { 329static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
608 .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX }, 330 .dot = { .min = 25000, .max = 350000 },
609 .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX }, 331 .vco = { .min = 1760000, .max = 3510000 },
610 .n = { .min = IRONLAKE_LVDS_D_SSC_N_MIN, .max = IRONLAKE_LVDS_D_SSC_N_MAX }, 332 .n = { .min = 1, .max = 3 },
611 .m = { .min = IRONLAKE_LVDS_D_SSC_M_MIN, .max = IRONLAKE_LVDS_D_SSC_M_MAX }, 333 .m = { .min = 79, .max = 126 },
612 .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX }, 334 .m1 = { .min = 12, .max = 22 },
613 .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX }, 335 .m2 = { .min = 5, .max = 9 },
614 .p = { .min = IRONLAKE_LVDS_D_SSC_P_MIN, .max = IRONLAKE_LVDS_D_SSC_P_MAX }, 336 .p = { .min = 14, .max = 42 },
615 .p1 = { .min = IRONLAKE_LVDS_D_SSC_P1_MIN,.max = IRONLAKE_LVDS_D_SSC_P1_MAX }, 337 .p1 = { .min = 2,.max = 6 },
616 .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT, 338 .p2 = { .dot_limit = 225000,
617 .p2_slow = IRONLAKE_LVDS_D_SSC_P2_SLOW, 339 .p2_slow = 7, .p2_fast = 7 },
618 .p2_fast = IRONLAKE_LVDS_D_SSC_P2_FAST },
619 .find_pll = intel_g4x_find_best_PLL, 340 .find_pll = intel_g4x_find_best_PLL,
620}; 341};
621 342
622static const intel_limit_t intel_limits_ironlake_display_port = { 343static const intel_limit_t intel_limits_ironlake_display_port = {
623 .dot = { .min = IRONLAKE_DOT_MIN, 344 .dot = { .min = 25000, .max = 350000 },
624 .max = IRONLAKE_DOT_MAX }, 345 .vco = { .min = 1760000, .max = 3510000},
625 .vco = { .min = IRONLAKE_VCO_MIN, 346 .n = { .min = 1, .max = 2 },
626 .max = IRONLAKE_VCO_MAX}, 347 .m = { .min = 81, .max = 90 },
627 .n = { .min = IRONLAKE_DP_N_MIN, 348 .m1 = { .min = 12, .max = 22 },
628 .max = IRONLAKE_DP_N_MAX }, 349 .m2 = { .min = 5, .max = 9 },
629 .m = { .min = IRONLAKE_DP_M_MIN, 350 .p = { .min = 10, .max = 20 },
630 .max = IRONLAKE_DP_M_MAX }, 351 .p1 = { .min = 1, .max = 2},
631 .m1 = { .min = IRONLAKE_M1_MIN, 352 .p2 = { .dot_limit = 0,
632 .max = IRONLAKE_M1_MAX }, 353 .p2_slow = 10, .p2_fast = 10 },
633 .m2 = { .min = IRONLAKE_M2_MIN,
634 .max = IRONLAKE_M2_MAX },
635 .p = { .min = IRONLAKE_DP_P_MIN,
636 .max = IRONLAKE_DP_P_MAX },
637 .p1 = { .min = IRONLAKE_DP_P1_MIN,
638 .max = IRONLAKE_DP_P1_MAX},
639 .p2 = { .dot_limit = IRONLAKE_DP_P2_LIMIT,
640 .p2_slow = IRONLAKE_DP_P2_SLOW,
641 .p2_fast = IRONLAKE_DP_P2_FAST },
642 .find_pll = intel_find_pll_ironlake_dp, 354 .find_pll = intel_find_pll_ironlake_dp,
643}; 355};
644 356
@@ -1828,7 +1540,7 @@ static void sandybridge_blit_fbc_update(struct drm_device *dev)
1828 u32 blt_ecoskpd; 1540 u32 blt_ecoskpd;
1829 1541
1830 /* Make sure blitter notifies FBC of writes */ 1542 /* Make sure blitter notifies FBC of writes */
1831 __gen6_gt_force_wake_get(dev_priv); 1543 gen6_gt_force_wake_get(dev_priv);
1832 blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD); 1544 blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD);
1833 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY << 1545 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY <<
1834 GEN6_BLITTER_LOCK_SHIFT; 1546 GEN6_BLITTER_LOCK_SHIFT;
@@ -1839,7 +1551,7 @@ static void sandybridge_blit_fbc_update(struct drm_device *dev)
1839 GEN6_BLITTER_LOCK_SHIFT); 1551 GEN6_BLITTER_LOCK_SHIFT);
1840 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd); 1552 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1841 POSTING_READ(GEN6_BLITTER_ECOSKPD); 1553 POSTING_READ(GEN6_BLITTER_ECOSKPD);
1842 __gen6_gt_force_wake_put(dev_priv); 1554 gen6_gt_force_wake_put(dev_priv);
1843} 1555}
1844 1556
1845static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval) 1557static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
@@ -2019,6 +1731,11 @@ static void intel_update_fbc(struct drm_device *dev)
2019 intel_fb = to_intel_framebuffer(fb); 1731 intel_fb = to_intel_framebuffer(fb);
2020 obj = intel_fb->obj; 1732 obj = intel_fb->obj;
2021 1733
1734 if (!i915_enable_fbc) {
1735 DRM_DEBUG_KMS("fbc disabled per module param (default off)\n");
1736 dev_priv->no_fbc_reason = FBC_MODULE_PARAM;
1737 goto out_disable;
1738 }
2022 if (intel_fb->obj->base.size > dev_priv->cfb_size) { 1739 if (intel_fb->obj->base.size > dev_priv->cfb_size) {
2023 DRM_DEBUG_KMS("framebuffer too large, disabling " 1740 DRM_DEBUG_KMS("framebuffer too large, disabling "
2024 "compression\n"); 1741 "compression\n");
@@ -2339,8 +2056,13 @@ static void intel_fdi_normal_train(struct drm_crtc *crtc)
2339 /* enable normal train */ 2056 /* enable normal train */
2340 reg = FDI_TX_CTL(pipe); 2057 reg = FDI_TX_CTL(pipe);
2341 temp = I915_READ(reg); 2058 temp = I915_READ(reg);
2342 temp &= ~FDI_LINK_TRAIN_NONE; 2059 if (IS_IVYBRIDGE(dev)) {
2343 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE; 2060 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2061 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2062 } else {
2063 temp &= ~FDI_LINK_TRAIN_NONE;
2064 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2065 }
2344 I915_WRITE(reg, temp); 2066 I915_WRITE(reg, temp);
2345 2067
2346 reg = FDI_RX_CTL(pipe); 2068 reg = FDI_RX_CTL(pipe);
@@ -2357,6 +2079,11 @@ static void intel_fdi_normal_train(struct drm_crtc *crtc)
2357 /* wait one idle pattern time */ 2079 /* wait one idle pattern time */
2358 POSTING_READ(reg); 2080 POSTING_READ(reg);
2359 udelay(1000); 2081 udelay(1000);
2082
2083 /* IVB wants error correction enabled */
2084 if (IS_IVYBRIDGE(dev))
2085 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2086 FDI_FE_ERRC_ENABLE);
2360} 2087}
2361 2088
2362/* The FDI link training functions for ILK/Ibexpeak. */ 2089/* The FDI link training functions for ILK/Ibexpeak. */
@@ -2584,7 +2311,116 @@ static void gen6_fdi_link_train(struct drm_crtc *crtc)
2584 DRM_DEBUG_KMS("FDI train done.\n"); 2311 DRM_DEBUG_KMS("FDI train done.\n");
2585} 2312}
2586 2313
2587static void ironlake_fdi_enable(struct drm_crtc *crtc) 2314/* Manual link training for Ivy Bridge A0 parts */
2315static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2316{
2317 struct drm_device *dev = crtc->dev;
2318 struct drm_i915_private *dev_priv = dev->dev_private;
2319 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2320 int pipe = intel_crtc->pipe;
2321 u32 reg, temp, i;
2322
2323 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2324 for train result */
2325 reg = FDI_RX_IMR(pipe);
2326 temp = I915_READ(reg);
2327 temp &= ~FDI_RX_SYMBOL_LOCK;
2328 temp &= ~FDI_RX_BIT_LOCK;
2329 I915_WRITE(reg, temp);
2330
2331 POSTING_READ(reg);
2332 udelay(150);
2333
2334 /* enable CPU FDI TX and PCH FDI RX */
2335 reg = FDI_TX_CTL(pipe);
2336 temp = I915_READ(reg);
2337 temp &= ~(7 << 19);
2338 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2339 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2340 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2341 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2342 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2343 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2344
2345 reg = FDI_RX_CTL(pipe);
2346 temp = I915_READ(reg);
2347 temp &= ~FDI_LINK_TRAIN_AUTO;
2348 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2349 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2350 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2351
2352 POSTING_READ(reg);
2353 udelay(150);
2354
2355 for (i = 0; i < 4; i++ ) {
2356 reg = FDI_TX_CTL(pipe);
2357 temp = I915_READ(reg);
2358 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2359 temp |= snb_b_fdi_train_param[i];
2360 I915_WRITE(reg, temp);
2361
2362 POSTING_READ(reg);
2363 udelay(500);
2364
2365 reg = FDI_RX_IIR(pipe);
2366 temp = I915_READ(reg);
2367 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2368
2369 if (temp & FDI_RX_BIT_LOCK ||
2370 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2371 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2372 DRM_DEBUG_KMS("FDI train 1 done.\n");
2373 break;
2374 }
2375 }
2376 if (i == 4)
2377 DRM_ERROR("FDI train 1 fail!\n");
2378
2379 /* Train 2 */
2380 reg = FDI_TX_CTL(pipe);
2381 temp = I915_READ(reg);
2382 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2383 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2384 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2385 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2386 I915_WRITE(reg, temp);
2387
2388 reg = FDI_RX_CTL(pipe);
2389 temp = I915_READ(reg);
2390 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2391 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2392 I915_WRITE(reg, temp);
2393
2394 POSTING_READ(reg);
2395 udelay(150);
2396
2397 for (i = 0; i < 4; i++ ) {
2398 reg = FDI_TX_CTL(pipe);
2399 temp = I915_READ(reg);
2400 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2401 temp |= snb_b_fdi_train_param[i];
2402 I915_WRITE(reg, temp);
2403
2404 POSTING_READ(reg);
2405 udelay(500);
2406
2407 reg = FDI_RX_IIR(pipe);
2408 temp = I915_READ(reg);
2409 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2410
2411 if (temp & FDI_RX_SYMBOL_LOCK) {
2412 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2413 DRM_DEBUG_KMS("FDI train 2 done.\n");
2414 break;
2415 }
2416 }
2417 if (i == 4)
2418 DRM_ERROR("FDI train 2 fail!\n");
2419
2420 DRM_DEBUG_KMS("FDI train done.\n");
2421}
2422
2423static void ironlake_fdi_pll_enable(struct drm_crtc *crtc)
2588{ 2424{
2589 struct drm_device *dev = crtc->dev; 2425 struct drm_device *dev = crtc->dev;
2590 struct drm_i915_private *dev_priv = dev->dev_private; 2426 struct drm_i915_private *dev_priv = dev->dev_private;
@@ -2757,10 +2593,7 @@ static void ironlake_pch_enable(struct drm_crtc *crtc)
2757 u32 reg, temp; 2593 u32 reg, temp;
2758 2594
2759 /* For PCH output, training FDI link */ 2595 /* For PCH output, training FDI link */
2760 if (IS_GEN6(dev)) 2596 dev_priv->display.fdi_link_train(crtc);
2761 gen6_fdi_link_train(crtc);
2762 else
2763 ironlake_fdi_link_train(crtc);
2764 2597
2765 intel_enable_pch_pll(dev_priv, pipe); 2598 intel_enable_pch_pll(dev_priv, pipe);
2766 2599
@@ -2850,7 +2683,7 @@ static void ironlake_crtc_enable(struct drm_crtc *crtc)
2850 is_pch_port = intel_crtc_driving_pch(crtc); 2683 is_pch_port = intel_crtc_driving_pch(crtc);
2851 2684
2852 if (is_pch_port) 2685 if (is_pch_port)
2853 ironlake_fdi_enable(crtc); 2686 ironlake_fdi_pll_enable(crtc);
2854 else 2687 else
2855 ironlake_fdi_disable(crtc); 2688 ironlake_fdi_disable(crtc);
2856 2689
@@ -2873,7 +2706,11 @@ static void ironlake_crtc_enable(struct drm_crtc *crtc)
2873 ironlake_pch_enable(crtc); 2706 ironlake_pch_enable(crtc);
2874 2707
2875 intel_crtc_load_lut(crtc); 2708 intel_crtc_load_lut(crtc);
2709
2710 mutex_lock(&dev->struct_mutex);
2876 intel_update_fbc(dev); 2711 intel_update_fbc(dev);
2712 mutex_unlock(&dev->struct_mutex);
2713
2877 intel_crtc_update_cursor(crtc, true); 2714 intel_crtc_update_cursor(crtc, true);
2878} 2715}
2879 2716
@@ -2969,8 +2806,11 @@ static void ironlake_crtc_disable(struct drm_crtc *crtc)
2969 2806
2970 intel_crtc->active = false; 2807 intel_crtc->active = false;
2971 intel_update_watermarks(dev); 2808 intel_update_watermarks(dev);
2809
2810 mutex_lock(&dev->struct_mutex);
2972 intel_update_fbc(dev); 2811 intel_update_fbc(dev);
2973 intel_clear_scanline_wait(dev); 2812 intel_clear_scanline_wait(dev);
2813 mutex_unlock(&dev->struct_mutex);
2974} 2814}
2975 2815
2976static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode) 2816static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
@@ -3497,11 +3337,11 @@ static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
3497 1000; 3337 1000;
3498 entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size); 3338 entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
3499 3339
3500 DRM_DEBUG_KMS("FIFO entries required for mode: %d\n", entries_required); 3340 DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
3501 3341
3502 wm_size = fifo_size - (entries_required + wm->guard_size); 3342 wm_size = fifo_size - (entries_required + wm->guard_size);
3503 3343
3504 DRM_DEBUG_KMS("FIFO watermark level: %d\n", wm_size); 3344 DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
3505 3345
3506 /* Don't promote wm_size to unsigned... */ 3346 /* Don't promote wm_size to unsigned... */
3507 if (wm_size > (long)wm->max_wm) 3347 if (wm_size > (long)wm->max_wm)
@@ -3823,13 +3663,13 @@ static bool g4x_check_srwm(struct drm_device *dev,
3823 display_wm, cursor_wm); 3663 display_wm, cursor_wm);
3824 3664
3825 if (display_wm > display->max_wm) { 3665 if (display_wm > display->max_wm) {
3826 DRM_DEBUG_KMS("display watermark is too large(%d), disabling\n", 3666 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
3827 display_wm, display->max_wm); 3667 display_wm, display->max_wm);
3828 return false; 3668 return false;
3829 } 3669 }
3830 3670
3831 if (cursor_wm > cursor->max_wm) { 3671 if (cursor_wm > cursor->max_wm) {
3832 DRM_DEBUG_KMS("cursor watermark is too large(%d), disabling\n", 3672 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
3833 cursor_wm, cursor->max_wm); 3673 cursor_wm, cursor->max_wm);
3834 return false; 3674 return false;
3835 } 3675 }
@@ -4516,34 +4356,28 @@ static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4516 return dev_priv->lvds_use_ssc && i915_panel_use_ssc; 4356 return dev_priv->lvds_use_ssc && i915_panel_use_ssc;
4517} 4357}
4518 4358
4519static int intel_crtc_mode_set(struct drm_crtc *crtc, 4359static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
4520 struct drm_display_mode *mode, 4360 struct drm_display_mode *mode,
4521 struct drm_display_mode *adjusted_mode, 4361 struct drm_display_mode *adjusted_mode,
4522 int x, int y, 4362 int x, int y,
4523 struct drm_framebuffer *old_fb) 4363 struct drm_framebuffer *old_fb)
4524{ 4364{
4525 struct drm_device *dev = crtc->dev; 4365 struct drm_device *dev = crtc->dev;
4526 struct drm_i915_private *dev_priv = dev->dev_private; 4366 struct drm_i915_private *dev_priv = dev->dev_private;
4527 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 4367 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4528 int pipe = intel_crtc->pipe; 4368 int pipe = intel_crtc->pipe;
4529 int plane = intel_crtc->plane; 4369 int plane = intel_crtc->plane;
4530 u32 fp_reg, dpll_reg;
4531 int refclk, num_connectors = 0; 4370 int refclk, num_connectors = 0;
4532 intel_clock_t clock, reduced_clock; 4371 intel_clock_t clock, reduced_clock;
4533 u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf; 4372 u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf;
4534 bool ok, has_reduced_clock = false, is_sdvo = false, is_dvo = false; 4373 bool ok, has_reduced_clock = false, is_sdvo = false, is_dvo = false;
4535 bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false; 4374 bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
4536 struct intel_encoder *has_edp_encoder = NULL;
4537 struct drm_mode_config *mode_config = &dev->mode_config; 4375 struct drm_mode_config *mode_config = &dev->mode_config;
4538 struct intel_encoder *encoder; 4376 struct intel_encoder *encoder;
4539 const intel_limit_t *limit; 4377 const intel_limit_t *limit;
4540 int ret; 4378 int ret;
4541 struct fdi_m_n m_n = {0}; 4379 u32 temp;
4542 u32 reg, temp;
4543 u32 lvds_sync = 0; 4380 u32 lvds_sync = 0;
4544 int target_clock;
4545
4546 drm_vblank_pre_modeset(dev, pipe);
4547 4381
4548 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) { 4382 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
4549 if (encoder->base.crtc != crtc) 4383 if (encoder->base.crtc != crtc)
@@ -4571,9 +4405,6 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
4571 case INTEL_OUTPUT_DISPLAYPORT: 4405 case INTEL_OUTPUT_DISPLAYPORT:
4572 is_dp = true; 4406 is_dp = true;
4573 break; 4407 break;
4574 case INTEL_OUTPUT_EDP:
4575 has_edp_encoder = encoder;
4576 break;
4577 } 4408 }
4578 4409
4579 num_connectors++; 4410 num_connectors++;
@@ -4585,9 +4416,6 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
4585 refclk / 1000); 4416 refclk / 1000);
4586 } else if (!IS_GEN2(dev)) { 4417 } else if (!IS_GEN2(dev)) {
4587 refclk = 96000; 4418 refclk = 96000;
4588 if (HAS_PCH_SPLIT(dev) &&
4589 (!has_edp_encoder || intel_encoder_is_pch_edp(&has_edp_encoder->base)))
4590 refclk = 120000; /* 120Mhz refclk */
4591 } else { 4419 } else {
4592 refclk = 48000; 4420 refclk = 48000;
4593 } 4421 }
@@ -4601,7 +4429,6 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
4601 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock); 4429 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock);
4602 if (!ok) { 4430 if (!ok) {
4603 DRM_ERROR("Couldn't find PLL settings for mode!\n"); 4431 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4604 drm_vblank_post_modeset(dev, pipe);
4605 return -EINVAL; 4432 return -EINVAL;
4606 } 4433 }
4607 4434
@@ -4645,143 +4472,6 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
4645 } 4472 }
4646 } 4473 }
4647 4474
4648 /* FDI link */
4649 if (HAS_PCH_SPLIT(dev)) {
4650 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4651 int lane = 0, link_bw, bpp;
4652 /* CPU eDP doesn't require FDI link, so just set DP M/N
4653 according to current link config */
4654 if (has_edp_encoder && !intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
4655 target_clock = mode->clock;
4656 intel_edp_link_config(has_edp_encoder,
4657 &lane, &link_bw);
4658 } else {
4659 /* [e]DP over FDI requires target mode clock
4660 instead of link clock */
4661 if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base))
4662 target_clock = mode->clock;
4663 else
4664 target_clock = adjusted_mode->clock;
4665
4666 /* FDI is a binary signal running at ~2.7GHz, encoding
4667 * each output octet as 10 bits. The actual frequency
4668 * is stored as a divider into a 100MHz clock, and the
4669 * mode pixel clock is stored in units of 1KHz.
4670 * Hence the bw of each lane in terms of the mode signal
4671 * is:
4672 */
4673 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
4674 }
4675
4676 /* determine panel color depth */
4677 temp = I915_READ(PIPECONF(pipe));
4678 temp &= ~PIPE_BPC_MASK;
4679 if (is_lvds) {
4680 /* the BPC will be 6 if it is 18-bit LVDS panel */
4681 if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) == LVDS_A3_POWER_UP)
4682 temp |= PIPE_8BPC;
4683 else
4684 temp |= PIPE_6BPC;
4685 } else if (has_edp_encoder) {
4686 switch (dev_priv->edp.bpp/3) {
4687 case 8:
4688 temp |= PIPE_8BPC;
4689 break;
4690 case 10:
4691 temp |= PIPE_10BPC;
4692 break;
4693 case 6:
4694 temp |= PIPE_6BPC;
4695 break;
4696 case 12:
4697 temp |= PIPE_12BPC;
4698 break;
4699 }
4700 } else
4701 temp |= PIPE_8BPC;
4702 I915_WRITE(PIPECONF(pipe), temp);
4703
4704 switch (temp & PIPE_BPC_MASK) {
4705 case PIPE_8BPC:
4706 bpp = 24;
4707 break;
4708 case PIPE_10BPC:
4709 bpp = 30;
4710 break;
4711 case PIPE_6BPC:
4712 bpp = 18;
4713 break;
4714 case PIPE_12BPC:
4715 bpp = 36;
4716 break;
4717 default:
4718 DRM_ERROR("unknown pipe bpc value\n");
4719 bpp = 24;
4720 }
4721
4722 if (!lane) {
4723 /*
4724 * Account for spread spectrum to avoid
4725 * oversubscribing the link. Max center spread
4726 * is 2.5%; use 5% for safety's sake.
4727 */
4728 u32 bps = target_clock * bpp * 21 / 20;
4729 lane = bps / (link_bw * 8) + 1;
4730 }
4731
4732 intel_crtc->fdi_lanes = lane;
4733
4734 if (pixel_multiplier > 1)
4735 link_bw *= pixel_multiplier;
4736 ironlake_compute_m_n(bpp, lane, target_clock, link_bw, &m_n);
4737 }
4738
4739 /* Ironlake: try to setup display ref clock before DPLL
4740 * enabling. This is only under driver's control after
4741 * PCH B stepping, previous chipset stepping should be
4742 * ignoring this setting.
4743 */
4744 if (HAS_PCH_SPLIT(dev)) {
4745 temp = I915_READ(PCH_DREF_CONTROL);
4746 /* Always enable nonspread source */
4747 temp &= ~DREF_NONSPREAD_SOURCE_MASK;
4748 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
4749 temp &= ~DREF_SSC_SOURCE_MASK;
4750 temp |= DREF_SSC_SOURCE_ENABLE;
4751 I915_WRITE(PCH_DREF_CONTROL, temp);
4752
4753 POSTING_READ(PCH_DREF_CONTROL);
4754 udelay(200);
4755
4756 if (has_edp_encoder) {
4757 if (intel_panel_use_ssc(dev_priv)) {
4758 temp |= DREF_SSC1_ENABLE;
4759 I915_WRITE(PCH_DREF_CONTROL, temp);
4760
4761 POSTING_READ(PCH_DREF_CONTROL);
4762 udelay(200);
4763 }
4764 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4765
4766 /* Enable CPU source on CPU attached eDP */
4767 if (!intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
4768 if (intel_panel_use_ssc(dev_priv))
4769 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
4770 else
4771 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
4772 } else {
4773 /* Enable SSC on PCH eDP if needed */
4774 if (intel_panel_use_ssc(dev_priv)) {
4775 DRM_ERROR("enabling SSC on PCH\n");
4776 temp |= DREF_SUPERSPREAD_SOURCE_ENABLE;
4777 }
4778 }
4779 I915_WRITE(PCH_DREF_CONTROL, temp);
4780 POSTING_READ(PCH_DREF_CONTROL);
4781 udelay(200);
4782 }
4783 }
4784
4785 if (IS_PINEVIEW(dev)) { 4475 if (IS_PINEVIEW(dev)) {
4786 fp = (1 << clock.n) << 16 | clock.m1 << 8 | clock.m2; 4476 fp = (1 << clock.n) << 16 | clock.m1 << 8 | clock.m2;
4787 if (has_reduced_clock) 4477 if (has_reduced_clock)
@@ -4794,25 +4484,7 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
4794 reduced_clock.m2; 4484 reduced_clock.m2;
4795 } 4485 }
4796 4486
4797 /* Enable autotuning of the PLL clock (if permissible) */ 4487 dpll = DPLL_VGA_MODE_DIS;
4798 if (HAS_PCH_SPLIT(dev)) {
4799 int factor = 21;
4800
4801 if (is_lvds) {
4802 if ((intel_panel_use_ssc(dev_priv) &&
4803 dev_priv->lvds_ssc_freq == 100) ||
4804 (I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP)
4805 factor = 25;
4806 } else if (is_sdvo && is_tv)
4807 factor = 20;
4808
4809 if (clock.m1 < factor * clock.n)
4810 fp |= FP_CB_TUNE;
4811 }
4812
4813 dpll = 0;
4814 if (!HAS_PCH_SPLIT(dev))
4815 dpll = DPLL_VGA_MODE_DIS;
4816 4488
4817 if (!IS_GEN2(dev)) { 4489 if (!IS_GEN2(dev)) {
4818 if (is_lvds) 4490 if (is_lvds)
@@ -4824,12 +4496,10 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
4824 if (pixel_multiplier > 1) { 4496 if (pixel_multiplier > 1) {
4825 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) 4497 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4826 dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES; 4498 dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
4827 else if (HAS_PCH_SPLIT(dev))
4828 dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
4829 } 4499 }
4830 dpll |= DPLL_DVO_HIGH_SPEED; 4500 dpll |= DPLL_DVO_HIGH_SPEED;
4831 } 4501 }
4832 if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base)) 4502 if (is_dp)
4833 dpll |= DPLL_DVO_HIGH_SPEED; 4503 dpll |= DPLL_DVO_HIGH_SPEED;
4834 4504
4835 /* compute bitmask from p1 value */ 4505 /* compute bitmask from p1 value */
@@ -4837,9 +4507,6 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
4837 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW; 4507 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4838 else { 4508 else {
4839 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; 4509 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4840 /* also FPA1 */
4841 if (HAS_PCH_SPLIT(dev))
4842 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4843 if (IS_G4X(dev) && has_reduced_clock) 4510 if (IS_G4X(dev) && has_reduced_clock)
4844 dpll |= (1 << (reduced_clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; 4511 dpll |= (1 << (reduced_clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4845 } 4512 }
@@ -4857,7 +4524,7 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
4857 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; 4524 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4858 break; 4525 break;
4859 } 4526 }
4860 if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev)) 4527 if (INTEL_INFO(dev)->gen >= 4)
4861 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT); 4528 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4862 } else { 4529 } else {
4863 if (is_lvds) { 4530 if (is_lvds) {
@@ -4891,12 +4558,10 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
4891 4558
4892 /* Ironlake's plane is forced to pipe, bit 24 is to 4559 /* Ironlake's plane is forced to pipe, bit 24 is to
4893 enable color space conversion */ 4560 enable color space conversion */
4894 if (!HAS_PCH_SPLIT(dev)) { 4561 if (pipe == 0)
4895 if (pipe == 0) 4562 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4896 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK; 4563 else
4897 else 4564 dspcntr |= DISPPLANE_SEL_PIPE_B;
4898 dspcntr |= DISPPLANE_SEL_PIPE_B;
4899 }
4900 4565
4901 if (pipe == 0 && INTEL_INFO(dev)->gen < 4) { 4566 if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
4902 /* Enable pixel doubling when the dot clock is > 90% of the (display) 4567 /* Enable pixel doubling when the dot clock is > 90% of the (display)
@@ -4912,27 +4577,506 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
4912 pipeconf &= ~PIPECONF_DOUBLE_WIDE; 4577 pipeconf &= ~PIPECONF_DOUBLE_WIDE;
4913 } 4578 }
4914 4579
4915 if (!HAS_PCH_SPLIT(dev)) 4580 dpll |= DPLL_VCO_ENABLE;
4916 dpll |= DPLL_VCO_ENABLE;
4917 4581
4918 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B'); 4582 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
4919 drm_mode_debug_printmodeline(mode); 4583 drm_mode_debug_printmodeline(mode);
4920 4584
4921 /* assign to Ironlake registers */ 4585 I915_WRITE(FP0(pipe), fp);
4922 if (HAS_PCH_SPLIT(dev)) { 4586 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4923 fp_reg = PCH_FP0(pipe); 4587
4924 dpll_reg = PCH_DPLL(pipe); 4588 POSTING_READ(DPLL(pipe));
4589 udelay(150);
4590
4591 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4592 * This is an exception to the general rule that mode_set doesn't turn
4593 * things on.
4594 */
4595 if (is_lvds) {
4596 temp = I915_READ(LVDS);
4597 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
4598 if (pipe == 1) {
4599 temp |= LVDS_PIPEB_SELECT;
4600 } else {
4601 temp &= ~LVDS_PIPEB_SELECT;
4602 }
4603 /* set the corresponsding LVDS_BORDER bit */
4604 temp |= dev_priv->lvds_border_bits;
4605 /* Set the B0-B3 data pairs corresponding to whether we're going to
4606 * set the DPLLs for dual-channel mode or not.
4607 */
4608 if (clock.p2 == 7)
4609 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
4610 else
4611 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
4612
4613 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
4614 * appropriately here, but we need to look more thoroughly into how
4615 * panels behave in the two modes.
4616 */
4617 /* set the dithering flag on LVDS as needed */
4618 if (INTEL_INFO(dev)->gen >= 4) {
4619 if (dev_priv->lvds_dither)
4620 temp |= LVDS_ENABLE_DITHER;
4621 else
4622 temp &= ~LVDS_ENABLE_DITHER;
4623 }
4624 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
4625 lvds_sync |= LVDS_HSYNC_POLARITY;
4626 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
4627 lvds_sync |= LVDS_VSYNC_POLARITY;
4628 if ((temp & (LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY))
4629 != lvds_sync) {
4630 char flags[2] = "-+";
4631 DRM_INFO("Changing LVDS panel from "
4632 "(%chsync, %cvsync) to (%chsync, %cvsync)\n",
4633 flags[!(temp & LVDS_HSYNC_POLARITY)],
4634 flags[!(temp & LVDS_VSYNC_POLARITY)],
4635 flags[!(lvds_sync & LVDS_HSYNC_POLARITY)],
4636 flags[!(lvds_sync & LVDS_VSYNC_POLARITY)]);
4637 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
4638 temp |= lvds_sync;
4639 }
4640 I915_WRITE(LVDS, temp);
4641 }
4642
4643 if (is_dp) {
4644 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4645 }
4646
4647 I915_WRITE(DPLL(pipe), dpll);
4648
4649 /* Wait for the clocks to stabilize. */
4650 POSTING_READ(DPLL(pipe));
4651 udelay(150);
4652
4653 if (INTEL_INFO(dev)->gen >= 4) {
4654 temp = 0;
4655 if (is_sdvo) {
4656 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
4657 if (temp > 1)
4658 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4659 else
4660 temp = 0;
4661 }
4662 I915_WRITE(DPLL_MD(pipe), temp);
4663 } else {
4664 /* The pixel multiplier can only be updated once the
4665 * DPLL is enabled and the clocks are stable.
4666 *
4667 * So write it again.
4668 */
4669 I915_WRITE(DPLL(pipe), dpll);
4670 }
4671
4672 intel_crtc->lowfreq_avail = false;
4673 if (is_lvds && has_reduced_clock && i915_powersave) {
4674 I915_WRITE(FP1(pipe), fp2);
4675 intel_crtc->lowfreq_avail = true;
4676 if (HAS_PIPE_CXSR(dev)) {
4677 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4678 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4679 }
4680 } else {
4681 I915_WRITE(FP1(pipe), fp);
4682 if (HAS_PIPE_CXSR(dev)) {
4683 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4684 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4685 }
4686 }
4687
4688 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4689 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4690 /* the chip adds 2 halflines automatically */
4691 adjusted_mode->crtc_vdisplay -= 1;
4692 adjusted_mode->crtc_vtotal -= 1;
4693 adjusted_mode->crtc_vblank_start -= 1;
4694 adjusted_mode->crtc_vblank_end -= 1;
4695 adjusted_mode->crtc_vsync_end -= 1;
4696 adjusted_mode->crtc_vsync_start -= 1;
4697 } else
4698 pipeconf &= ~PIPECONF_INTERLACE_W_FIELD_INDICATION; /* progressive */
4699
4700 I915_WRITE(HTOTAL(pipe),
4701 (adjusted_mode->crtc_hdisplay - 1) |
4702 ((adjusted_mode->crtc_htotal - 1) << 16));
4703 I915_WRITE(HBLANK(pipe),
4704 (adjusted_mode->crtc_hblank_start - 1) |
4705 ((adjusted_mode->crtc_hblank_end - 1) << 16));
4706 I915_WRITE(HSYNC(pipe),
4707 (adjusted_mode->crtc_hsync_start - 1) |
4708 ((adjusted_mode->crtc_hsync_end - 1) << 16));
4709
4710 I915_WRITE(VTOTAL(pipe),
4711 (adjusted_mode->crtc_vdisplay - 1) |
4712 ((adjusted_mode->crtc_vtotal - 1) << 16));
4713 I915_WRITE(VBLANK(pipe),
4714 (adjusted_mode->crtc_vblank_start - 1) |
4715 ((adjusted_mode->crtc_vblank_end - 1) << 16));
4716 I915_WRITE(VSYNC(pipe),
4717 (adjusted_mode->crtc_vsync_start - 1) |
4718 ((adjusted_mode->crtc_vsync_end - 1) << 16));
4719
4720 /* pipesrc and dspsize control the size that is scaled from,
4721 * which should always be the user's requested size.
4722 */
4723 I915_WRITE(DSPSIZE(plane),
4724 ((mode->vdisplay - 1) << 16) |
4725 (mode->hdisplay - 1));
4726 I915_WRITE(DSPPOS(plane), 0);
4727 I915_WRITE(PIPESRC(pipe),
4728 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4729
4730 I915_WRITE(PIPECONF(pipe), pipeconf);
4731 POSTING_READ(PIPECONF(pipe));
4732 intel_enable_pipe(dev_priv, pipe, false);
4733
4734 intel_wait_for_vblank(dev, pipe);
4735
4736 I915_WRITE(DSPCNTR(plane), dspcntr);
4737 POSTING_READ(DSPCNTR(plane));
4738
4739 ret = intel_pipe_set_base(crtc, x, y, old_fb);
4740
4741 intel_update_watermarks(dev);
4742
4743 return ret;
4744}
4745
4746static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
4747 struct drm_display_mode *mode,
4748 struct drm_display_mode *adjusted_mode,
4749 int x, int y,
4750 struct drm_framebuffer *old_fb)
4751{
4752 struct drm_device *dev = crtc->dev;
4753 struct drm_i915_private *dev_priv = dev->dev_private;
4754 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4755 int pipe = intel_crtc->pipe;
4756 int plane = intel_crtc->plane;
4757 int refclk, num_connectors = 0;
4758 intel_clock_t clock, reduced_clock;
4759 u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf;
4760 bool ok, has_reduced_clock = false, is_sdvo = false;
4761 bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
4762 struct intel_encoder *has_edp_encoder = NULL;
4763 struct drm_mode_config *mode_config = &dev->mode_config;
4764 struct intel_encoder *encoder;
4765 const intel_limit_t *limit;
4766 int ret;
4767 struct fdi_m_n m_n = {0};
4768 u32 temp;
4769 u32 lvds_sync = 0;
4770 int target_clock, pixel_multiplier, lane, link_bw, bpp, factor;
4771
4772 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
4773 if (encoder->base.crtc != crtc)
4774 continue;
4775
4776 switch (encoder->type) {
4777 case INTEL_OUTPUT_LVDS:
4778 is_lvds = true;
4779 break;
4780 case INTEL_OUTPUT_SDVO:
4781 case INTEL_OUTPUT_HDMI:
4782 is_sdvo = true;
4783 if (encoder->needs_tv_clock)
4784 is_tv = true;
4785 break;
4786 case INTEL_OUTPUT_TVOUT:
4787 is_tv = true;
4788 break;
4789 case INTEL_OUTPUT_ANALOG:
4790 is_crt = true;
4791 break;
4792 case INTEL_OUTPUT_DISPLAYPORT:
4793 is_dp = true;
4794 break;
4795 case INTEL_OUTPUT_EDP:
4796 has_edp_encoder = encoder;
4797 break;
4798 }
4799
4800 num_connectors++;
4801 }
4802
4803 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4804 refclk = dev_priv->lvds_ssc_freq * 1000;
4805 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4806 refclk / 1000);
4807 } else {
4808 refclk = 96000;
4809 if (!has_edp_encoder ||
4810 intel_encoder_is_pch_edp(&has_edp_encoder->base))
4811 refclk = 120000; /* 120Mhz refclk */
4812 }
4813
4814 /*
4815 * Returns a set of divisors for the desired target clock with the given
4816 * refclk, or FALSE. The returned values represent the clock equation:
4817 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4818 */
4819 limit = intel_limit(crtc, refclk);
4820 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock);
4821 if (!ok) {
4822 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4823 return -EINVAL;
4824 }
4825
4826 /* Ensure that the cursor is valid for the new mode before changing... */
4827 intel_crtc_update_cursor(crtc, true);
4828
4829 if (is_lvds && dev_priv->lvds_downclock_avail) {
4830 has_reduced_clock = limit->find_pll(limit, crtc,
4831 dev_priv->lvds_downclock,
4832 refclk,
4833 &reduced_clock);
4834 if (has_reduced_clock && (clock.p != reduced_clock.p)) {
4835 /*
4836 * If the different P is found, it means that we can't
4837 * switch the display clock by using the FP0/FP1.
4838 * In such case we will disable the LVDS downclock
4839 * feature.
4840 */
4841 DRM_DEBUG_KMS("Different P is found for "
4842 "LVDS clock/downclock\n");
4843 has_reduced_clock = 0;
4844 }
4845 }
4846 /* SDVO TV has fixed PLL values depend on its clock range,
4847 this mirrors vbios setting. */
4848 if (is_sdvo && is_tv) {
4849 if (adjusted_mode->clock >= 100000
4850 && adjusted_mode->clock < 140500) {
4851 clock.p1 = 2;
4852 clock.p2 = 10;
4853 clock.n = 3;
4854 clock.m1 = 16;
4855 clock.m2 = 8;
4856 } else if (adjusted_mode->clock >= 140500
4857 && adjusted_mode->clock <= 200000) {
4858 clock.p1 = 1;
4859 clock.p2 = 10;
4860 clock.n = 6;
4861 clock.m1 = 12;
4862 clock.m2 = 8;
4863 }
4864 }
4865
4866 /* FDI link */
4867 pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4868 lane = 0;
4869 /* CPU eDP doesn't require FDI link, so just set DP M/N
4870 according to current link config */
4871 if (has_edp_encoder &&
4872 !intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
4873 target_clock = mode->clock;
4874 intel_edp_link_config(has_edp_encoder,
4875 &lane, &link_bw);
4925 } else { 4876 } else {
4926 fp_reg = FP0(pipe); 4877 /* [e]DP over FDI requires target mode clock
4927 dpll_reg = DPLL(pipe); 4878 instead of link clock */
4879 if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base))
4880 target_clock = mode->clock;
4881 else
4882 target_clock = adjusted_mode->clock;
4883
4884 /* FDI is a binary signal running at ~2.7GHz, encoding
4885 * each output octet as 10 bits. The actual frequency
4886 * is stored as a divider into a 100MHz clock, and the
4887 * mode pixel clock is stored in units of 1KHz.
4888 * Hence the bw of each lane in terms of the mode signal
4889 * is:
4890 */
4891 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
4892 }
4893
4894 /* determine panel color depth */
4895 temp = I915_READ(PIPECONF(pipe));
4896 temp &= ~PIPE_BPC_MASK;
4897 if (is_lvds) {
4898 /* the BPC will be 6 if it is 18-bit LVDS panel */
4899 if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) == LVDS_A3_POWER_UP)
4900 temp |= PIPE_8BPC;
4901 else
4902 temp |= PIPE_6BPC;
4903 } else if (has_edp_encoder) {
4904 switch (dev_priv->edp.bpp/3) {
4905 case 8:
4906 temp |= PIPE_8BPC;
4907 break;
4908 case 10:
4909 temp |= PIPE_10BPC;
4910 break;
4911 case 6:
4912 temp |= PIPE_6BPC;
4913 break;
4914 case 12:
4915 temp |= PIPE_12BPC;
4916 break;
4917 }
4918 } else
4919 temp |= PIPE_8BPC;
4920 I915_WRITE(PIPECONF(pipe), temp);
4921
4922 switch (temp & PIPE_BPC_MASK) {
4923 case PIPE_8BPC:
4924 bpp = 24;
4925 break;
4926 case PIPE_10BPC:
4927 bpp = 30;
4928 break;
4929 case PIPE_6BPC:
4930 bpp = 18;
4931 break;
4932 case PIPE_12BPC:
4933 bpp = 36;
4934 break;
4935 default:
4936 DRM_ERROR("unknown pipe bpc value\n");
4937 bpp = 24;
4938 }
4939
4940 if (!lane) {
4941 /*
4942 * Account for spread spectrum to avoid
4943 * oversubscribing the link. Max center spread
4944 * is 2.5%; use 5% for safety's sake.
4945 */
4946 u32 bps = target_clock * bpp * 21 / 20;
4947 lane = bps / (link_bw * 8) + 1;
4928 } 4948 }
4929 4949
4950 intel_crtc->fdi_lanes = lane;
4951
4952 if (pixel_multiplier > 1)
4953 link_bw *= pixel_multiplier;
4954 ironlake_compute_m_n(bpp, lane, target_clock, link_bw, &m_n);
4955
4956 /* Ironlake: try to setup display ref clock before DPLL
4957 * enabling. This is only under driver's control after
4958 * PCH B stepping, previous chipset stepping should be
4959 * ignoring this setting.
4960 */
4961 temp = I915_READ(PCH_DREF_CONTROL);
4962 /* Always enable nonspread source */
4963 temp &= ~DREF_NONSPREAD_SOURCE_MASK;
4964 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
4965 temp &= ~DREF_SSC_SOURCE_MASK;
4966 temp |= DREF_SSC_SOURCE_ENABLE;
4967 I915_WRITE(PCH_DREF_CONTROL, temp);
4968
4969 POSTING_READ(PCH_DREF_CONTROL);
4970 udelay(200);
4971
4972 if (has_edp_encoder) {
4973 if (intel_panel_use_ssc(dev_priv)) {
4974 temp |= DREF_SSC1_ENABLE;
4975 I915_WRITE(PCH_DREF_CONTROL, temp);
4976
4977 POSTING_READ(PCH_DREF_CONTROL);
4978 udelay(200);
4979 }
4980 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4981
4982 /* Enable CPU source on CPU attached eDP */
4983 if (!intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
4984 if (intel_panel_use_ssc(dev_priv))
4985 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
4986 else
4987 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
4988 } else {
4989 /* Enable SSC on PCH eDP if needed */
4990 if (intel_panel_use_ssc(dev_priv)) {
4991 DRM_ERROR("enabling SSC on PCH\n");
4992 temp |= DREF_SUPERSPREAD_SOURCE_ENABLE;
4993 }
4994 }
4995 I915_WRITE(PCH_DREF_CONTROL, temp);
4996 POSTING_READ(PCH_DREF_CONTROL);
4997 udelay(200);
4998 }
4999
5000 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
5001 if (has_reduced_clock)
5002 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
5003 reduced_clock.m2;
5004
5005 /* Enable autotuning of the PLL clock (if permissible) */
5006 factor = 21;
5007 if (is_lvds) {
5008 if ((intel_panel_use_ssc(dev_priv) &&
5009 dev_priv->lvds_ssc_freq == 100) ||
5010 (I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP)
5011 factor = 25;
5012 } else if (is_sdvo && is_tv)
5013 factor = 20;
5014
5015 if (clock.m1 < factor * clock.n)
5016 fp |= FP_CB_TUNE;
5017
5018 dpll = 0;
5019
5020 if (is_lvds)
5021 dpll |= DPLLB_MODE_LVDS;
5022 else
5023 dpll |= DPLLB_MODE_DAC_SERIAL;
5024 if (is_sdvo) {
5025 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5026 if (pixel_multiplier > 1) {
5027 dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
5028 }
5029 dpll |= DPLL_DVO_HIGH_SPEED;
5030 }
5031 if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base))
5032 dpll |= DPLL_DVO_HIGH_SPEED;
5033
5034 /* compute bitmask from p1 value */
5035 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5036 /* also FPA1 */
5037 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5038
5039 switch (clock.p2) {
5040 case 5:
5041 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5042 break;
5043 case 7:
5044 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5045 break;
5046 case 10:
5047 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5048 break;
5049 case 14:
5050 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5051 break;
5052 }
5053
5054 if (is_sdvo && is_tv)
5055 dpll |= PLL_REF_INPUT_TVCLKINBC;
5056 else if (is_tv)
5057 /* XXX: just matching BIOS for now */
5058 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
5059 dpll |= 3;
5060 else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5061 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5062 else
5063 dpll |= PLL_REF_INPUT_DREFCLK;
5064
5065 /* setup pipeconf */
5066 pipeconf = I915_READ(PIPECONF(pipe));
5067
5068 /* Set up the display plane register */
5069 dspcntr = DISPPLANE_GAMMA_ENABLE;
5070
5071 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
5072 drm_mode_debug_printmodeline(mode);
5073
4930 /* PCH eDP needs FDI, but CPU eDP does not */ 5074 /* PCH eDP needs FDI, but CPU eDP does not */
4931 if (!has_edp_encoder || intel_encoder_is_pch_edp(&has_edp_encoder->base)) { 5075 if (!has_edp_encoder || intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
4932 I915_WRITE(fp_reg, fp); 5076 I915_WRITE(PCH_FP0(pipe), fp);
4933 I915_WRITE(dpll_reg, dpll & ~DPLL_VCO_ENABLE); 5077 I915_WRITE(PCH_DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4934 5078
4935 POSTING_READ(dpll_reg); 5079 POSTING_READ(PCH_DPLL(pipe));
4936 udelay(150); 5080 udelay(150);
4937 } 5081 }
4938 5082
@@ -4964,11 +5108,7 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
4964 * things on. 5108 * things on.
4965 */ 5109 */
4966 if (is_lvds) { 5110 if (is_lvds) {
4967 reg = LVDS; 5111 temp = I915_READ(PCH_LVDS);
4968 if (HAS_PCH_SPLIT(dev))
4969 reg = PCH_LVDS;
4970
4971 temp = I915_READ(reg);
4972 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP; 5112 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
4973 if (pipe == 1) { 5113 if (pipe == 1) {
4974 if (HAS_PCH_CPT(dev)) 5114 if (HAS_PCH_CPT(dev))
@@ -4995,13 +5135,6 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
4995 * appropriately here, but we need to look more thoroughly into how 5135 * appropriately here, but we need to look more thoroughly into how
4996 * panels behave in the two modes. 5136 * panels behave in the two modes.
4997 */ 5137 */
4998 /* set the dithering flag on non-PCH LVDS as needed */
4999 if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev)) {
5000 if (dev_priv->lvds_dither)
5001 temp |= LVDS_ENABLE_DITHER;
5002 else
5003 temp &= ~LVDS_ENABLE_DITHER;
5004 }
5005 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC) 5138 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
5006 lvds_sync |= LVDS_HSYNC_POLARITY; 5139 lvds_sync |= LVDS_HSYNC_POLARITY;
5007 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC) 5140 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
@@ -5018,22 +5151,20 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
5018 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY); 5151 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
5019 temp |= lvds_sync; 5152 temp |= lvds_sync;
5020 } 5153 }
5021 I915_WRITE(reg, temp); 5154 I915_WRITE(PCH_LVDS, temp);
5022 } 5155 }
5023 5156
5024 /* set the dithering flag and clear for anything other than a panel. */ 5157 /* set the dithering flag and clear for anything other than a panel. */
5025 if (HAS_PCH_SPLIT(dev)) { 5158 pipeconf &= ~PIPECONF_DITHER_EN;
5026 pipeconf &= ~PIPECONF_DITHER_EN; 5159 pipeconf &= ~PIPECONF_DITHER_TYPE_MASK;
5027 pipeconf &= ~PIPECONF_DITHER_TYPE_MASK; 5160 if (dev_priv->lvds_dither && (is_lvds || has_edp_encoder)) {
5028 if (dev_priv->lvds_dither && (is_lvds || has_edp_encoder)) { 5161 pipeconf |= PIPECONF_DITHER_EN;
5029 pipeconf |= PIPECONF_DITHER_EN; 5162 pipeconf |= PIPECONF_DITHER_TYPE_ST1;
5030 pipeconf |= PIPECONF_DITHER_TYPE_ST1;
5031 }
5032 } 5163 }
5033 5164
5034 if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base)) { 5165 if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5035 intel_dp_set_m_n(crtc, mode, adjusted_mode); 5166 intel_dp_set_m_n(crtc, mode, adjusted_mode);
5036 } else if (HAS_PCH_SPLIT(dev)) { 5167 } else {
5037 /* For non-DP output, clear any trans DP clock recovery setting.*/ 5168 /* For non-DP output, clear any trans DP clock recovery setting.*/
5038 I915_WRITE(TRANSDATA_M1(pipe), 0); 5169 I915_WRITE(TRANSDATA_M1(pipe), 0);
5039 I915_WRITE(TRANSDATA_N1(pipe), 0); 5170 I915_WRITE(TRANSDATA_N1(pipe), 0);
@@ -5041,43 +5172,32 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
5041 I915_WRITE(TRANSDPLINK_N1(pipe), 0); 5172 I915_WRITE(TRANSDPLINK_N1(pipe), 0);
5042 } 5173 }
5043 5174
5044 if (!has_edp_encoder || intel_encoder_is_pch_edp(&has_edp_encoder->base)) { 5175 if (!has_edp_encoder ||
5045 I915_WRITE(dpll_reg, dpll); 5176 intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5177 I915_WRITE(PCH_DPLL(pipe), dpll);
5046 5178
5047 /* Wait for the clocks to stabilize. */ 5179 /* Wait for the clocks to stabilize. */
5048 POSTING_READ(dpll_reg); 5180 POSTING_READ(PCH_DPLL(pipe));
5049 udelay(150); 5181 udelay(150);
5050 5182
5051 if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev)) { 5183 /* The pixel multiplier can only be updated once the
5052 temp = 0; 5184 * DPLL is enabled and the clocks are stable.
5053 if (is_sdvo) { 5185 *
5054 temp = intel_mode_get_pixel_multiplier(adjusted_mode); 5186 * So write it again.
5055 if (temp > 1) 5187 */
5056 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT; 5188 I915_WRITE(PCH_DPLL(pipe), dpll);
5057 else
5058 temp = 0;
5059 }
5060 I915_WRITE(DPLL_MD(pipe), temp);
5061 } else {
5062 /* The pixel multiplier can only be updated once the
5063 * DPLL is enabled and the clocks are stable.
5064 *
5065 * So write it again.
5066 */
5067 I915_WRITE(dpll_reg, dpll);
5068 }
5069 } 5189 }
5070 5190
5071 intel_crtc->lowfreq_avail = false; 5191 intel_crtc->lowfreq_avail = false;
5072 if (is_lvds && has_reduced_clock && i915_powersave) { 5192 if (is_lvds && has_reduced_clock && i915_powersave) {
5073 I915_WRITE(fp_reg + 4, fp2); 5193 I915_WRITE(PCH_FP1(pipe), fp2);
5074 intel_crtc->lowfreq_avail = true; 5194 intel_crtc->lowfreq_avail = true;
5075 if (HAS_PIPE_CXSR(dev)) { 5195 if (HAS_PIPE_CXSR(dev)) {
5076 DRM_DEBUG_KMS("enabling CxSR downclocking\n"); 5196 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
5077 pipeconf |= PIPECONF_CXSR_DOWNCLOCK; 5197 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
5078 } 5198 }
5079 } else { 5199 } else {
5080 I915_WRITE(fp_reg + 4, fp); 5200 I915_WRITE(PCH_FP1(pipe), fp);
5081 if (HAS_PIPE_CXSR(dev)) { 5201 if (HAS_PIPE_CXSR(dev)) {
5082 DRM_DEBUG_KMS("disabling CxSR downclocking\n"); 5202 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
5083 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK; 5203 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
@@ -5116,33 +5236,24 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
5116 (adjusted_mode->crtc_vsync_start - 1) | 5236 (adjusted_mode->crtc_vsync_start - 1) |
5117 ((adjusted_mode->crtc_vsync_end - 1) << 16)); 5237 ((adjusted_mode->crtc_vsync_end - 1) << 16));
5118 5238
5119 /* pipesrc and dspsize control the size that is scaled from, 5239 /* pipesrc controls the size that is scaled from, which should
5120 * which should always be the user's requested size. 5240 * always be the user's requested size.
5121 */ 5241 */
5122 if (!HAS_PCH_SPLIT(dev)) {
5123 I915_WRITE(DSPSIZE(plane),
5124 ((mode->vdisplay - 1) << 16) |
5125 (mode->hdisplay - 1));
5126 I915_WRITE(DSPPOS(plane), 0);
5127 }
5128 I915_WRITE(PIPESRC(pipe), 5242 I915_WRITE(PIPESRC(pipe),
5129 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1)); 5243 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
5130 5244
5131 if (HAS_PCH_SPLIT(dev)) { 5245 I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
5132 I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m); 5246 I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
5133 I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n); 5247 I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
5134 I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m); 5248 I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
5135 I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
5136 5249
5137 if (has_edp_encoder && !intel_encoder_is_pch_edp(&has_edp_encoder->base)) { 5250 if (has_edp_encoder &&
5138 ironlake_set_pll_edp(crtc, adjusted_mode->clock); 5251 !intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5139 } 5252 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
5140 } 5253 }
5141 5254
5142 I915_WRITE(PIPECONF(pipe), pipeconf); 5255 I915_WRITE(PIPECONF(pipe), pipeconf);
5143 POSTING_READ(PIPECONF(pipe)); 5256 POSTING_READ(PIPECONF(pipe));
5144 if (!HAS_PCH_SPLIT(dev))
5145 intel_enable_pipe(dev_priv, pipe, false);
5146 5257
5147 intel_wait_for_vblank(dev, pipe); 5258 intel_wait_for_vblank(dev, pipe);
5148 5259
@@ -5161,6 +5272,26 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
5161 5272
5162 intel_update_watermarks(dev); 5273 intel_update_watermarks(dev);
5163 5274
5275 return ret;
5276}
5277
5278static int intel_crtc_mode_set(struct drm_crtc *crtc,
5279 struct drm_display_mode *mode,
5280 struct drm_display_mode *adjusted_mode,
5281 int x, int y,
5282 struct drm_framebuffer *old_fb)
5283{
5284 struct drm_device *dev = crtc->dev;
5285 struct drm_i915_private *dev_priv = dev->dev_private;
5286 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5287 int pipe = intel_crtc->pipe;
5288 int ret;
5289
5290 drm_vblank_pre_modeset(dev, pipe);
5291
5292 ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode,
5293 x, y, old_fb);
5294
5164 drm_vblank_post_modeset(dev, pipe); 5295 drm_vblank_post_modeset(dev, pipe);
5165 5296
5166 return ret; 5297 return ret;
@@ -5483,43 +5614,140 @@ static struct drm_display_mode load_detect_mode = {
5483 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 5614 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
5484}; 5615};
5485 5616
5486struct drm_crtc *intel_get_load_detect_pipe(struct intel_encoder *intel_encoder, 5617static struct drm_framebuffer *
5487 struct drm_connector *connector, 5618intel_framebuffer_create(struct drm_device *dev,
5488 struct drm_display_mode *mode, 5619 struct drm_mode_fb_cmd *mode_cmd,
5489 int *dpms_mode) 5620 struct drm_i915_gem_object *obj)
5621{
5622 struct intel_framebuffer *intel_fb;
5623 int ret;
5624
5625 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
5626 if (!intel_fb) {
5627 drm_gem_object_unreference_unlocked(&obj->base);
5628 return ERR_PTR(-ENOMEM);
5629 }
5630
5631 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
5632 if (ret) {
5633 drm_gem_object_unreference_unlocked(&obj->base);
5634 kfree(intel_fb);
5635 return ERR_PTR(ret);
5636 }
5637
5638 return &intel_fb->base;
5639}
5640
5641static u32
5642intel_framebuffer_pitch_for_width(int width, int bpp)
5643{
5644 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
5645 return ALIGN(pitch, 64);
5646}
5647
5648static u32
5649intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
5650{
5651 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
5652 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
5653}
5654
5655static struct drm_framebuffer *
5656intel_framebuffer_create_for_mode(struct drm_device *dev,
5657 struct drm_display_mode *mode,
5658 int depth, int bpp)
5659{
5660 struct drm_i915_gem_object *obj;
5661 struct drm_mode_fb_cmd mode_cmd;
5662
5663 obj = i915_gem_alloc_object(dev,
5664 intel_framebuffer_size_for_mode(mode, bpp));
5665 if (obj == NULL)
5666 return ERR_PTR(-ENOMEM);
5667
5668 mode_cmd.width = mode->hdisplay;
5669 mode_cmd.height = mode->vdisplay;
5670 mode_cmd.depth = depth;
5671 mode_cmd.bpp = bpp;
5672 mode_cmd.pitch = intel_framebuffer_pitch_for_width(mode_cmd.width, bpp);
5673
5674 return intel_framebuffer_create(dev, &mode_cmd, obj);
5675}
5676
5677static struct drm_framebuffer *
5678mode_fits_in_fbdev(struct drm_device *dev,
5679 struct drm_display_mode *mode)
5680{
5681 struct drm_i915_private *dev_priv = dev->dev_private;
5682 struct drm_i915_gem_object *obj;
5683 struct drm_framebuffer *fb;
5684
5685 if (dev_priv->fbdev == NULL)
5686 return NULL;
5687
5688 obj = dev_priv->fbdev->ifb.obj;
5689 if (obj == NULL)
5690 return NULL;
5691
5692 fb = &dev_priv->fbdev->ifb.base;
5693 if (fb->pitch < intel_framebuffer_pitch_for_width(mode->hdisplay,
5694 fb->bits_per_pixel))
5695 return NULL;
5696
5697 if (obj->base.size < mode->vdisplay * fb->pitch)
5698 return NULL;
5699
5700 return fb;
5701}
5702
5703bool intel_get_load_detect_pipe(struct intel_encoder *intel_encoder,
5704 struct drm_connector *connector,
5705 struct drm_display_mode *mode,
5706 struct intel_load_detect_pipe *old)
5490{ 5707{
5491 struct intel_crtc *intel_crtc; 5708 struct intel_crtc *intel_crtc;
5492 struct drm_crtc *possible_crtc; 5709 struct drm_crtc *possible_crtc;
5493 struct drm_crtc *supported_crtc =NULL;
5494 struct drm_encoder *encoder = &intel_encoder->base; 5710 struct drm_encoder *encoder = &intel_encoder->base;
5495 struct drm_crtc *crtc = NULL; 5711 struct drm_crtc *crtc = NULL;
5496 struct drm_device *dev = encoder->dev; 5712 struct drm_device *dev = encoder->dev;
5497 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private; 5713 struct drm_framebuffer *old_fb;
5498 struct drm_crtc_helper_funcs *crtc_funcs;
5499 int i = -1; 5714 int i = -1;
5500 5715
5716 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5717 connector->base.id, drm_get_connector_name(connector),
5718 encoder->base.id, drm_get_encoder_name(encoder));
5719
5501 /* 5720 /*
5502 * Algorithm gets a little messy: 5721 * Algorithm gets a little messy:
5722 *
5503 * - if the connector already has an assigned crtc, use it (but make 5723 * - if the connector already has an assigned crtc, use it (but make
5504 * sure it's on first) 5724 * sure it's on first)
5725 *
5505 * - try to find the first unused crtc that can drive this connector, 5726 * - try to find the first unused crtc that can drive this connector,
5506 * and use that if we find one 5727 * and use that if we find one
5507 * - if there are no unused crtcs available, try to use the first
5508 * one we found that supports the connector
5509 */ 5728 */
5510 5729
5511 /* See if we already have a CRTC for this connector */ 5730 /* See if we already have a CRTC for this connector */
5512 if (encoder->crtc) { 5731 if (encoder->crtc) {
5513 crtc = encoder->crtc; 5732 crtc = encoder->crtc;
5514 /* Make sure the crtc and connector are running */ 5733
5515 intel_crtc = to_intel_crtc(crtc); 5734 intel_crtc = to_intel_crtc(crtc);
5516 *dpms_mode = intel_crtc->dpms_mode; 5735 old->dpms_mode = intel_crtc->dpms_mode;
5736 old->load_detect_temp = false;
5737
5738 /* Make sure the crtc and connector are running */
5517 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) { 5739 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
5740 struct drm_encoder_helper_funcs *encoder_funcs;
5741 struct drm_crtc_helper_funcs *crtc_funcs;
5742
5518 crtc_funcs = crtc->helper_private; 5743 crtc_funcs = crtc->helper_private;
5519 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON); 5744 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
5745
5746 encoder_funcs = encoder->helper_private;
5520 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON); 5747 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
5521 } 5748 }
5522 return crtc; 5749
5750 return true;
5523 } 5751 }
5524 5752
5525 /* Find an unused one (if possible) */ 5753 /* Find an unused one (if possible) */
@@ -5531,46 +5759,66 @@ struct drm_crtc *intel_get_load_detect_pipe(struct intel_encoder *intel_encoder,
5531 crtc = possible_crtc; 5759 crtc = possible_crtc;
5532 break; 5760 break;
5533 } 5761 }
5534 if (!supported_crtc)
5535 supported_crtc = possible_crtc;
5536 } 5762 }
5537 5763
5538 /* 5764 /*
5539 * If we didn't find an unused CRTC, don't use any. 5765 * If we didn't find an unused CRTC, don't use any.
5540 */ 5766 */
5541 if (!crtc) { 5767 if (!crtc) {
5542 return NULL; 5768 DRM_DEBUG_KMS("no pipe available for load-detect\n");
5769 return false;
5543 } 5770 }
5544 5771
5545 encoder->crtc = crtc; 5772 encoder->crtc = crtc;
5546 connector->encoder = encoder; 5773 connector->encoder = encoder;
5547 intel_encoder->load_detect_temp = true;
5548 5774
5549 intel_crtc = to_intel_crtc(crtc); 5775 intel_crtc = to_intel_crtc(crtc);
5550 *dpms_mode = intel_crtc->dpms_mode; 5776 old->dpms_mode = intel_crtc->dpms_mode;
5777 old->load_detect_temp = true;
5778 old->release_fb = NULL;
5551 5779
5552 if (!crtc->enabled) { 5780 if (!mode)
5553 if (!mode) 5781 mode = &load_detect_mode;
5554 mode = &load_detect_mode;
5555 drm_crtc_helper_set_mode(crtc, mode, 0, 0, crtc->fb);
5556 } else {
5557 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
5558 crtc_funcs = crtc->helper_private;
5559 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
5560 }
5561 5782
5562 /* Add this connector to the crtc */ 5783 old_fb = crtc->fb;
5563 encoder_funcs->mode_set(encoder, &crtc->mode, &crtc->mode); 5784
5564 encoder_funcs->commit(encoder); 5785 /* We need a framebuffer large enough to accommodate all accesses
5786 * that the plane may generate whilst we perform load detection.
5787 * We can not rely on the fbcon either being present (we get called
5788 * during its initialisation to detect all boot displays, or it may
5789 * not even exist) or that it is large enough to satisfy the
5790 * requested mode.
5791 */
5792 crtc->fb = mode_fits_in_fbdev(dev, mode);
5793 if (crtc->fb == NULL) {
5794 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
5795 crtc->fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
5796 old->release_fb = crtc->fb;
5797 } else
5798 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
5799 if (IS_ERR(crtc->fb)) {
5800 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
5801 crtc->fb = old_fb;
5802 return false;
5803 }
5804
5805 if (!drm_crtc_helper_set_mode(crtc, mode, 0, 0, old_fb)) {
5806 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
5807 if (old->release_fb)
5808 old->release_fb->funcs->destroy(old->release_fb);
5809 crtc->fb = old_fb;
5810 return false;
5565 } 5811 }
5812
5566 /* let the connector get through one full cycle before testing */ 5813 /* let the connector get through one full cycle before testing */
5567 intel_wait_for_vblank(dev, intel_crtc->pipe); 5814 intel_wait_for_vblank(dev, intel_crtc->pipe);
5568 5815
5569 return crtc; 5816 return true;
5570} 5817}
5571 5818
5572void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder, 5819void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder,
5573 struct drm_connector *connector, int dpms_mode) 5820 struct drm_connector *connector,
5821 struct intel_load_detect_pipe *old)
5574{ 5822{
5575 struct drm_encoder *encoder = &intel_encoder->base; 5823 struct drm_encoder *encoder = &intel_encoder->base;
5576 struct drm_device *dev = encoder->dev; 5824 struct drm_device *dev = encoder->dev;
@@ -5578,19 +5826,24 @@ void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder,
5578 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private; 5826 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
5579 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private; 5827 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
5580 5828
5581 if (intel_encoder->load_detect_temp) { 5829 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5582 encoder->crtc = NULL; 5830 connector->base.id, drm_get_connector_name(connector),
5831 encoder->base.id, drm_get_encoder_name(encoder));
5832
5833 if (old->load_detect_temp) {
5583 connector->encoder = NULL; 5834 connector->encoder = NULL;
5584 intel_encoder->load_detect_temp = false;
5585 crtc->enabled = drm_helper_crtc_in_use(crtc);
5586 drm_helper_disable_unused_functions(dev); 5835 drm_helper_disable_unused_functions(dev);
5836
5837 if (old->release_fb)
5838 old->release_fb->funcs->destroy(old->release_fb);
5839
5840 return;
5587 } 5841 }
5588 5842
5589 /* Switch crtc and encoder back off if necessary */ 5843 /* Switch crtc and encoder back off if necessary */
5590 if (crtc->enabled && dpms_mode != DRM_MODE_DPMS_ON) { 5844 if (old->dpms_mode != DRM_MODE_DPMS_ON) {
5591 if (encoder->crtc == crtc) 5845 encoder_funcs->dpms(encoder, old->dpms_mode);
5592 encoder_funcs->dpms(encoder, dpms_mode); 5846 crtc_funcs->dpms(crtc, old->dpms_mode);
5593 crtc_funcs->dpms(crtc, dpms_mode);
5594 } 5847 }
5595} 5848}
5596 5849
@@ -6185,6 +6438,7 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc,
6185 break; 6438 break;
6186 6439
6187 case 6: 6440 case 6:
6441 case 7:
6188 OUT_RING(MI_DISPLAY_FLIP | 6442 OUT_RING(MI_DISPLAY_FLIP |
6189 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); 6443 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6190 OUT_RING(fb->pitch | obj->tiling_mode); 6444 OUT_RING(fb->pitch | obj->tiling_mode);
@@ -6504,6 +6758,9 @@ static void intel_setup_outputs(struct drm_device *dev)
6504 } 6758 }
6505 6759
6506 intel_panel_setup_backlight(dev); 6760 intel_panel_setup_backlight(dev);
6761
6762 /* disable all the possible outputs/crtcs before entering KMS mode */
6763 drm_helper_disable_unused_functions(dev);
6507} 6764}
6508 6765
6509static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb) 6766static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
@@ -6571,27 +6828,12 @@ intel_user_framebuffer_create(struct drm_device *dev,
6571 struct drm_mode_fb_cmd *mode_cmd) 6828 struct drm_mode_fb_cmd *mode_cmd)
6572{ 6829{
6573 struct drm_i915_gem_object *obj; 6830 struct drm_i915_gem_object *obj;
6574 struct intel_framebuffer *intel_fb;
6575 int ret;
6576 6831
6577 obj = to_intel_bo(drm_gem_object_lookup(dev, filp, mode_cmd->handle)); 6832 obj = to_intel_bo(drm_gem_object_lookup(dev, filp, mode_cmd->handle));
6578 if (&obj->base == NULL) 6833 if (&obj->base == NULL)
6579 return ERR_PTR(-ENOENT); 6834 return ERR_PTR(-ENOENT);
6580 6835
6581 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); 6836 return intel_framebuffer_create(dev, mode_cmd, obj);
6582 if (!intel_fb) {
6583 drm_gem_object_unreference_unlocked(&obj->base);
6584 return ERR_PTR(-ENOMEM);
6585 }
6586
6587 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
6588 if (ret) {
6589 drm_gem_object_unreference_unlocked(&obj->base);
6590 kfree(intel_fb);
6591 return ERR_PTR(ret);
6592 }
6593
6594 return &intel_fb->base;
6595} 6837}
6596 6838
6597static const struct drm_mode_config_funcs intel_mode_funcs = { 6839static const struct drm_mode_config_funcs intel_mode_funcs = {
@@ -6605,13 +6847,14 @@ intel_alloc_context_page(struct drm_device *dev)
6605 struct drm_i915_gem_object *ctx; 6847 struct drm_i915_gem_object *ctx;
6606 int ret; 6848 int ret;
6607 6849
6850 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
6851
6608 ctx = i915_gem_alloc_object(dev, 4096); 6852 ctx = i915_gem_alloc_object(dev, 4096);
6609 if (!ctx) { 6853 if (!ctx) {
6610 DRM_DEBUG("failed to alloc power context, RC6 disabled\n"); 6854 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
6611 return NULL; 6855 return NULL;
6612 } 6856 }
6613 6857
6614 mutex_lock(&dev->struct_mutex);
6615 ret = i915_gem_object_pin(ctx, 4096, true); 6858 ret = i915_gem_object_pin(ctx, 4096, true);
6616 if (ret) { 6859 if (ret) {
6617 DRM_ERROR("failed to pin power context: %d\n", ret); 6860 DRM_ERROR("failed to pin power context: %d\n", ret);
@@ -6623,7 +6866,6 @@ intel_alloc_context_page(struct drm_device *dev)
6623 DRM_ERROR("failed to set-domain on power context: %d\n", ret); 6866 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
6624 goto err_unpin; 6867 goto err_unpin;
6625 } 6868 }
6626 mutex_unlock(&dev->struct_mutex);
6627 6869
6628 return ctx; 6870 return ctx;
6629 6871
@@ -6758,6 +7000,11 @@ void gen6_disable_rps(struct drm_device *dev)
6758 I915_WRITE(GEN6_RPNSWREQ, 1 << 31); 7000 I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
6759 I915_WRITE(GEN6_PMINTRMSK, 0xffffffff); 7001 I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
6760 I915_WRITE(GEN6_PMIER, 0); 7002 I915_WRITE(GEN6_PMIER, 0);
7003
7004 spin_lock_irq(&dev_priv->rps_lock);
7005 dev_priv->pm_iir = 0;
7006 spin_unlock_irq(&dev_priv->rps_lock);
7007
6761 I915_WRITE(GEN6_PMIIR, I915_READ(GEN6_PMIIR)); 7008 I915_WRITE(GEN6_PMIIR, I915_READ(GEN6_PMIIR));
6762} 7009}
6763 7010
@@ -6851,7 +7098,7 @@ void gen6_enable_rps(struct drm_i915_private *dev_priv)
6851{ 7098{
6852 u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP); 7099 u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
6853 u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS); 7100 u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
6854 u32 pcu_mbox; 7101 u32 pcu_mbox, rc6_mask = 0;
6855 int cur_freq, min_freq, max_freq; 7102 int cur_freq, min_freq, max_freq;
6856 int i; 7103 int i;
6857 7104
@@ -6862,7 +7109,8 @@ void gen6_enable_rps(struct drm_i915_private *dev_priv)
6862 * userspace... 7109 * userspace...
6863 */ 7110 */
6864 I915_WRITE(GEN6_RC_STATE, 0); 7111 I915_WRITE(GEN6_RC_STATE, 0);
6865 __gen6_gt_force_wake_get(dev_priv); 7112 mutex_lock(&dev_priv->dev->struct_mutex);
7113 gen6_gt_force_wake_get(dev_priv);
6866 7114
6867 /* disable the counters and set deterministic thresholds */ 7115 /* disable the counters and set deterministic thresholds */
6868 I915_WRITE(GEN6_RC_CONTROL, 0); 7116 I915_WRITE(GEN6_RC_CONTROL, 0);
@@ -6882,9 +7130,12 @@ void gen6_enable_rps(struct drm_i915_private *dev_priv)
6882 I915_WRITE(GEN6_RC6p_THRESHOLD, 100000); 7130 I915_WRITE(GEN6_RC6p_THRESHOLD, 100000);
6883 I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */ 7131 I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
6884 7132
7133 if (i915_enable_rc6)
7134 rc6_mask = GEN6_RC_CTL_RC6p_ENABLE |
7135 GEN6_RC_CTL_RC6_ENABLE;
7136
6885 I915_WRITE(GEN6_RC_CONTROL, 7137 I915_WRITE(GEN6_RC_CONTROL,
6886 GEN6_RC_CTL_RC6p_ENABLE | 7138 rc6_mask |
6887 GEN6_RC_CTL_RC6_ENABLE |
6888 GEN6_RC_CTL_EI_MODE(1) | 7139 GEN6_RC_CTL_EI_MODE(1) |
6889 GEN6_RC_CTL_HW_ENABLE); 7140 GEN6_RC_CTL_HW_ENABLE);
6890 7141
@@ -6956,168 +7207,237 @@ void gen6_enable_rps(struct drm_i915_private *dev_priv)
6956 GEN6_PM_RP_DOWN_THRESHOLD | 7207 GEN6_PM_RP_DOWN_THRESHOLD |
6957 GEN6_PM_RP_UP_EI_EXPIRED | 7208 GEN6_PM_RP_UP_EI_EXPIRED |
6958 GEN6_PM_RP_DOWN_EI_EXPIRED); 7209 GEN6_PM_RP_DOWN_EI_EXPIRED);
7210 spin_lock_irq(&dev_priv->rps_lock);
7211 WARN_ON(dev_priv->pm_iir != 0);
6959 I915_WRITE(GEN6_PMIMR, 0); 7212 I915_WRITE(GEN6_PMIMR, 0);
7213 spin_unlock_irq(&dev_priv->rps_lock);
6960 /* enable all PM interrupts */ 7214 /* enable all PM interrupts */
6961 I915_WRITE(GEN6_PMINTRMSK, 0); 7215 I915_WRITE(GEN6_PMINTRMSK, 0);
6962 7216
6963 __gen6_gt_force_wake_put(dev_priv); 7217 gen6_gt_force_wake_put(dev_priv);
7218 mutex_unlock(&dev_priv->dev->struct_mutex);
6964} 7219}
6965 7220
6966void intel_enable_clock_gating(struct drm_device *dev) 7221static void ironlake_init_clock_gating(struct drm_device *dev)
7222{
7223 struct drm_i915_private *dev_priv = dev->dev_private;
7224 uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
7225
7226 /* Required for FBC */
7227 dspclk_gate |= DPFCUNIT_CLOCK_GATE_DISABLE |
7228 DPFCRUNIT_CLOCK_GATE_DISABLE |
7229 DPFDUNIT_CLOCK_GATE_DISABLE;
7230 /* Required for CxSR */
7231 dspclk_gate |= DPARBUNIT_CLOCK_GATE_DISABLE;
7232
7233 I915_WRITE(PCH_3DCGDIS0,
7234 MARIUNIT_CLOCK_GATE_DISABLE |
7235 SVSMUNIT_CLOCK_GATE_DISABLE);
7236 I915_WRITE(PCH_3DCGDIS1,
7237 VFMUNIT_CLOCK_GATE_DISABLE);
7238
7239 I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
7240
7241 /*
7242 * According to the spec the following bits should be set in
7243 * order to enable memory self-refresh
7244 * The bit 22/21 of 0x42004
7245 * The bit 5 of 0x42020
7246 * The bit 15 of 0x45000
7247 */
7248 I915_WRITE(ILK_DISPLAY_CHICKEN2,
7249 (I915_READ(ILK_DISPLAY_CHICKEN2) |
7250 ILK_DPARB_GATE | ILK_VSDPFD_FULL));
7251 I915_WRITE(ILK_DSPCLK_GATE,
7252 (I915_READ(ILK_DSPCLK_GATE) |
7253 ILK_DPARB_CLK_GATE));
7254 I915_WRITE(DISP_ARB_CTL,
7255 (I915_READ(DISP_ARB_CTL) |
7256 DISP_FBC_WM_DIS));
7257 I915_WRITE(WM3_LP_ILK, 0);
7258 I915_WRITE(WM2_LP_ILK, 0);
7259 I915_WRITE(WM1_LP_ILK, 0);
7260
7261 /*
7262 * Based on the document from hardware guys the following bits
7263 * should be set unconditionally in order to enable FBC.
7264 * The bit 22 of 0x42000
7265 * The bit 22 of 0x42004
7266 * The bit 7,8,9 of 0x42020.
7267 */
7268 if (IS_IRONLAKE_M(dev)) {
7269 I915_WRITE(ILK_DISPLAY_CHICKEN1,
7270 I915_READ(ILK_DISPLAY_CHICKEN1) |
7271 ILK_FBCQ_DIS);
7272 I915_WRITE(ILK_DISPLAY_CHICKEN2,
7273 I915_READ(ILK_DISPLAY_CHICKEN2) |
7274 ILK_DPARB_GATE);
7275 I915_WRITE(ILK_DSPCLK_GATE,
7276 I915_READ(ILK_DSPCLK_GATE) |
7277 ILK_DPFC_DIS1 |
7278 ILK_DPFC_DIS2 |
7279 ILK_CLK_FBC);
7280 }
7281
7282 I915_WRITE(ILK_DISPLAY_CHICKEN2,
7283 I915_READ(ILK_DISPLAY_CHICKEN2) |
7284 ILK_ELPIN_409_SELECT);
7285 I915_WRITE(_3D_CHICKEN2,
7286 _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
7287 _3D_CHICKEN2_WM_READ_PIPELINED);
7288}
7289
7290static void gen6_init_clock_gating(struct drm_device *dev)
6967{ 7291{
6968 struct drm_i915_private *dev_priv = dev->dev_private; 7292 struct drm_i915_private *dev_priv = dev->dev_private;
6969 int pipe; 7293 int pipe;
7294 uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
7295
7296 I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
7297
7298 I915_WRITE(ILK_DISPLAY_CHICKEN2,
7299 I915_READ(ILK_DISPLAY_CHICKEN2) |
7300 ILK_ELPIN_409_SELECT);
7301
7302 I915_WRITE(WM3_LP_ILK, 0);
7303 I915_WRITE(WM2_LP_ILK, 0);
7304 I915_WRITE(WM1_LP_ILK, 0);
6970 7305
6971 /* 7306 /*
6972 * Disable clock gating reported to work incorrectly according to the 7307 * According to the spec the following bits should be
6973 * specs, but enable as much else as we can. 7308 * set in order to enable memory self-refresh and fbc:
7309 * The bit21 and bit22 of 0x42000
7310 * The bit21 and bit22 of 0x42004
7311 * The bit5 and bit7 of 0x42020
7312 * The bit14 of 0x70180
7313 * The bit14 of 0x71180
6974 */ 7314 */
6975 if (HAS_PCH_SPLIT(dev)) { 7315 I915_WRITE(ILK_DISPLAY_CHICKEN1,
6976 uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE; 7316 I915_READ(ILK_DISPLAY_CHICKEN1) |
7317 ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
7318 I915_WRITE(ILK_DISPLAY_CHICKEN2,
7319 I915_READ(ILK_DISPLAY_CHICKEN2) |
7320 ILK_DPARB_GATE | ILK_VSDPFD_FULL);
7321 I915_WRITE(ILK_DSPCLK_GATE,
7322 I915_READ(ILK_DSPCLK_GATE) |
7323 ILK_DPARB_CLK_GATE |
7324 ILK_DPFD_CLK_GATE);
6977 7325
6978 if (IS_GEN5(dev)) { 7326 for_each_pipe(pipe)
6979 /* Required for FBC */ 7327 I915_WRITE(DSPCNTR(pipe),
6980 dspclk_gate |= DPFCUNIT_CLOCK_GATE_DISABLE | 7328 I915_READ(DSPCNTR(pipe)) |
6981 DPFCRUNIT_CLOCK_GATE_DISABLE | 7329 DISPPLANE_TRICKLE_FEED_DISABLE);
6982 DPFDUNIT_CLOCK_GATE_DISABLE; 7330}
6983 /* Required for CxSR */
6984 dspclk_gate |= DPARBUNIT_CLOCK_GATE_DISABLE;
6985
6986 I915_WRITE(PCH_3DCGDIS0,
6987 MARIUNIT_CLOCK_GATE_DISABLE |
6988 SVSMUNIT_CLOCK_GATE_DISABLE);
6989 I915_WRITE(PCH_3DCGDIS1,
6990 VFMUNIT_CLOCK_GATE_DISABLE);
6991 }
6992 7331
6993 I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate); 7332static void ivybridge_init_clock_gating(struct drm_device *dev)
7333{
7334 struct drm_i915_private *dev_priv = dev->dev_private;
7335 int pipe;
7336 uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
6994 7337
6995 /* 7338 I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
6996 * On Ibex Peak and Cougar Point, we need to disable clock
6997 * gating for the panel power sequencer or it will fail to
6998 * start up when no ports are active.
6999 */
7000 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
7001 7339
7002 /* 7340 I915_WRITE(WM3_LP_ILK, 0);
7003 * According to the spec the following bits should be set in 7341 I915_WRITE(WM2_LP_ILK, 0);
7004 * order to enable memory self-refresh 7342 I915_WRITE(WM1_LP_ILK, 0);
7005 * The bit 22/21 of 0x42004
7006 * The bit 5 of 0x42020
7007 * The bit 15 of 0x45000
7008 */
7009 if (IS_GEN5(dev)) {
7010 I915_WRITE(ILK_DISPLAY_CHICKEN2,
7011 (I915_READ(ILK_DISPLAY_CHICKEN2) |
7012 ILK_DPARB_GATE | ILK_VSDPFD_FULL));
7013 I915_WRITE(ILK_DSPCLK_GATE,
7014 (I915_READ(ILK_DSPCLK_GATE) |
7015 ILK_DPARB_CLK_GATE));
7016 I915_WRITE(DISP_ARB_CTL,
7017 (I915_READ(DISP_ARB_CTL) |
7018 DISP_FBC_WM_DIS));
7019 I915_WRITE(WM3_LP_ILK, 0);
7020 I915_WRITE(WM2_LP_ILK, 0);
7021 I915_WRITE(WM1_LP_ILK, 0);
7022 }
7023 /*
7024 * Based on the document from hardware guys the following bits
7025 * should be set unconditionally in order to enable FBC.
7026 * The bit 22 of 0x42000
7027 * The bit 22 of 0x42004
7028 * The bit 7,8,9 of 0x42020.
7029 */
7030 if (IS_IRONLAKE_M(dev)) {
7031 I915_WRITE(ILK_DISPLAY_CHICKEN1,
7032 I915_READ(ILK_DISPLAY_CHICKEN1) |
7033 ILK_FBCQ_DIS);
7034 I915_WRITE(ILK_DISPLAY_CHICKEN2,
7035 I915_READ(ILK_DISPLAY_CHICKEN2) |
7036 ILK_DPARB_GATE);
7037 I915_WRITE(ILK_DSPCLK_GATE,
7038 I915_READ(ILK_DSPCLK_GATE) |
7039 ILK_DPFC_DIS1 |
7040 ILK_DPFC_DIS2 |
7041 ILK_CLK_FBC);
7042 }
7043 7343
7044 I915_WRITE(ILK_DISPLAY_CHICKEN2, 7344 I915_WRITE(ILK_DSPCLK_GATE, IVB_VRHUNIT_CLK_GATE);
7045 I915_READ(ILK_DISPLAY_CHICKEN2) |
7046 ILK_ELPIN_409_SELECT);
7047 7345
7048 if (IS_GEN5(dev)) { 7346 for_each_pipe(pipe)
7049 I915_WRITE(_3D_CHICKEN2, 7347 I915_WRITE(DSPCNTR(pipe),
7050 _3D_CHICKEN2_WM_READ_PIPELINED << 16 | 7348 I915_READ(DSPCNTR(pipe)) |
7051 _3D_CHICKEN2_WM_READ_PIPELINED); 7349 DISPPLANE_TRICKLE_FEED_DISABLE);
7052 } 7350}
7053 7351
7054 if (IS_GEN6(dev)) { 7352static void g4x_init_clock_gating(struct drm_device *dev)
7055 I915_WRITE(WM3_LP_ILK, 0); 7353{
7056 I915_WRITE(WM2_LP_ILK, 0); 7354 struct drm_i915_private *dev_priv = dev->dev_private;
7057 I915_WRITE(WM1_LP_ILK, 0); 7355 uint32_t dspclk_gate;
7058 7356
7059 /* 7357 I915_WRITE(RENCLK_GATE_D1, 0);
7060 * According to the spec the following bits should be 7358 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
7061 * set in order to enable memory self-refresh and fbc: 7359 GS_UNIT_CLOCK_GATE_DISABLE |
7062 * The bit21 and bit22 of 0x42000 7360 CL_UNIT_CLOCK_GATE_DISABLE);
7063 * The bit21 and bit22 of 0x42004 7361 I915_WRITE(RAMCLK_GATE_D, 0);
7064 * The bit5 and bit7 of 0x42020 7362 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
7065 * The bit14 of 0x70180 7363 OVRUNIT_CLOCK_GATE_DISABLE |
7066 * The bit14 of 0x71180 7364 OVCUNIT_CLOCK_GATE_DISABLE;
7067 */ 7365 if (IS_GM45(dev))
7068 I915_WRITE(ILK_DISPLAY_CHICKEN1, 7366 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
7069 I915_READ(ILK_DISPLAY_CHICKEN1) | 7367 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
7070 ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS); 7368}
7071 I915_WRITE(ILK_DISPLAY_CHICKEN2,
7072 I915_READ(ILK_DISPLAY_CHICKEN2) |
7073 ILK_DPARB_GATE | ILK_VSDPFD_FULL);
7074 I915_WRITE(ILK_DSPCLK_GATE,
7075 I915_READ(ILK_DSPCLK_GATE) |
7076 ILK_DPARB_CLK_GATE |
7077 ILK_DPFD_CLK_GATE);
7078
7079 for_each_pipe(pipe)
7080 I915_WRITE(DSPCNTR(pipe),
7081 I915_READ(DSPCNTR(pipe)) |
7082 DISPPLANE_TRICKLE_FEED_DISABLE);
7083 }
7084 } else if (IS_G4X(dev)) {
7085 uint32_t dspclk_gate;
7086 I915_WRITE(RENCLK_GATE_D1, 0);
7087 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
7088 GS_UNIT_CLOCK_GATE_DISABLE |
7089 CL_UNIT_CLOCK_GATE_DISABLE);
7090 I915_WRITE(RAMCLK_GATE_D, 0);
7091 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
7092 OVRUNIT_CLOCK_GATE_DISABLE |
7093 OVCUNIT_CLOCK_GATE_DISABLE;
7094 if (IS_GM45(dev))
7095 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
7096 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
7097 } else if (IS_CRESTLINE(dev)) {
7098 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
7099 I915_WRITE(RENCLK_GATE_D2, 0);
7100 I915_WRITE(DSPCLK_GATE_D, 0);
7101 I915_WRITE(RAMCLK_GATE_D, 0);
7102 I915_WRITE16(DEUC, 0);
7103 } else if (IS_BROADWATER(dev)) {
7104 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
7105 I965_RCC_CLOCK_GATE_DISABLE |
7106 I965_RCPB_CLOCK_GATE_DISABLE |
7107 I965_ISC_CLOCK_GATE_DISABLE |
7108 I965_FBC_CLOCK_GATE_DISABLE);
7109 I915_WRITE(RENCLK_GATE_D2, 0);
7110 } else if (IS_GEN3(dev)) {
7111 u32 dstate = I915_READ(D_STATE);
7112 7369
7113 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING | 7370static void crestline_init_clock_gating(struct drm_device *dev)
7114 DSTATE_DOT_CLOCK_GATING; 7371{
7115 I915_WRITE(D_STATE, dstate); 7372 struct drm_i915_private *dev_priv = dev->dev_private;
7116 } else if (IS_I85X(dev) || IS_I865G(dev)) { 7373
7117 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE); 7374 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
7118 } else if (IS_I830(dev)) { 7375 I915_WRITE(RENCLK_GATE_D2, 0);
7119 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE); 7376 I915_WRITE(DSPCLK_GATE_D, 0);
7120 } 7377 I915_WRITE(RAMCLK_GATE_D, 0);
7378 I915_WRITE16(DEUC, 0);
7379}
7380
7381static void broadwater_init_clock_gating(struct drm_device *dev)
7382{
7383 struct drm_i915_private *dev_priv = dev->dev_private;
7384
7385 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
7386 I965_RCC_CLOCK_GATE_DISABLE |
7387 I965_RCPB_CLOCK_GATE_DISABLE |
7388 I965_ISC_CLOCK_GATE_DISABLE |
7389 I965_FBC_CLOCK_GATE_DISABLE);
7390 I915_WRITE(RENCLK_GATE_D2, 0);
7391}
7392
7393static void gen3_init_clock_gating(struct drm_device *dev)
7394{
7395 struct drm_i915_private *dev_priv = dev->dev_private;
7396 u32 dstate = I915_READ(D_STATE);
7397
7398 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
7399 DSTATE_DOT_CLOCK_GATING;
7400 I915_WRITE(D_STATE, dstate);
7401}
7402
7403static void i85x_init_clock_gating(struct drm_device *dev)
7404{
7405 struct drm_i915_private *dev_priv = dev->dev_private;
7406
7407 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
7408}
7409
7410static void i830_init_clock_gating(struct drm_device *dev)
7411{
7412 struct drm_i915_private *dev_priv = dev->dev_private;
7413
7414 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
7415}
7416
7417static void ibx_init_clock_gating(struct drm_device *dev)
7418{
7419 struct drm_i915_private *dev_priv = dev->dev_private;
7420
7421 /*
7422 * On Ibex Peak and Cougar Point, we need to disable clock
7423 * gating for the panel power sequencer or it will fail to
7424 * start up when no ports are active.
7425 */
7426 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
7427}
7428
7429static void cpt_init_clock_gating(struct drm_device *dev)
7430{
7431 struct drm_i915_private *dev_priv = dev->dev_private;
7432
7433 /*
7434 * On Ibex Peak and Cougar Point, we need to disable clock
7435 * gating for the panel power sequencer or it will fail to
7436 * start up when no ports are active.
7437 */
7438 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
7439 I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
7440 DPLS_EDP_PPS_FIX_DIS);
7121} 7441}
7122 7442
7123static void ironlake_teardown_rc6(struct drm_device *dev) 7443static void ironlake_teardown_rc6(struct drm_device *dev)
@@ -7187,9 +7507,12 @@ void ironlake_enable_rc6(struct drm_device *dev)
7187 if (!i915_enable_rc6) 7507 if (!i915_enable_rc6)
7188 return; 7508 return;
7189 7509
7510 mutex_lock(&dev->struct_mutex);
7190 ret = ironlake_setup_rc6(dev); 7511 ret = ironlake_setup_rc6(dev);
7191 if (ret) 7512 if (ret) {
7513 mutex_unlock(&dev->struct_mutex);
7192 return; 7514 return;
7515 }
7193 7516
7194 /* 7517 /*
7195 * GPU can automatically power down the render unit if given a page 7518 * GPU can automatically power down the render unit if given a page
@@ -7198,6 +7521,7 @@ void ironlake_enable_rc6(struct drm_device *dev)
7198 ret = BEGIN_LP_RING(6); 7521 ret = BEGIN_LP_RING(6);
7199 if (ret) { 7522 if (ret) {
7200 ironlake_teardown_rc6(dev); 7523 ironlake_teardown_rc6(dev);
7524 mutex_unlock(&dev->struct_mutex);
7201 return; 7525 return;
7202 } 7526 }
7203 7527
@@ -7213,10 +7537,33 @@ void ironlake_enable_rc6(struct drm_device *dev)
7213 OUT_RING(MI_FLUSH); 7537 OUT_RING(MI_FLUSH);
7214 ADVANCE_LP_RING(); 7538 ADVANCE_LP_RING();
7215 7539
7540 /*
7541 * Wait for the command parser to advance past MI_SET_CONTEXT. The HW
7542 * does an implicit flush, combined with MI_FLUSH above, it should be
7543 * safe to assume that renderctx is valid
7544 */
7545 ret = intel_wait_ring_idle(LP_RING(dev_priv));
7546 if (ret) {
7547 DRM_ERROR("failed to enable ironlake power power savings\n");
7548 ironlake_teardown_rc6(dev);
7549 mutex_unlock(&dev->struct_mutex);
7550 return;
7551 }
7552
7216 I915_WRITE(PWRCTXA, dev_priv->pwrctx->gtt_offset | PWRCTX_EN); 7553 I915_WRITE(PWRCTXA, dev_priv->pwrctx->gtt_offset | PWRCTX_EN);
7217 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT); 7554 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
7555 mutex_unlock(&dev->struct_mutex);
7218} 7556}
7219 7557
7558void intel_init_clock_gating(struct drm_device *dev)
7559{
7560 struct drm_i915_private *dev_priv = dev->dev_private;
7561
7562 dev_priv->display.init_clock_gating(dev);
7563
7564 if (dev_priv->display.init_pch_clock_gating)
7565 dev_priv->display.init_pch_clock_gating(dev);
7566}
7220 7567
7221/* Set up chip specific display functions */ 7568/* Set up chip specific display functions */
7222static void intel_init_display(struct drm_device *dev) 7569static void intel_init_display(struct drm_device *dev)
@@ -7224,10 +7571,13 @@ static void intel_init_display(struct drm_device *dev)
7224 struct drm_i915_private *dev_priv = dev->dev_private; 7571 struct drm_i915_private *dev_priv = dev->dev_private;
7225 7572
7226 /* We always want a DPMS function */ 7573 /* We always want a DPMS function */
7227 if (HAS_PCH_SPLIT(dev)) 7574 if (HAS_PCH_SPLIT(dev)) {
7228 dev_priv->display.dpms = ironlake_crtc_dpms; 7575 dev_priv->display.dpms = ironlake_crtc_dpms;
7229 else 7576 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
7577 } else {
7230 dev_priv->display.dpms = i9xx_crtc_dpms; 7578 dev_priv->display.dpms = i9xx_crtc_dpms;
7579 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
7580 }
7231 7581
7232 if (I915_HAS_FBC(dev)) { 7582 if (I915_HAS_FBC(dev)) {
7233 if (HAS_PCH_SPLIT(dev)) { 7583 if (HAS_PCH_SPLIT(dev)) {
@@ -7271,6 +7621,11 @@ static void intel_init_display(struct drm_device *dev)
7271 7621
7272 /* For FIFO watermark updates */ 7622 /* For FIFO watermark updates */
7273 if (HAS_PCH_SPLIT(dev)) { 7623 if (HAS_PCH_SPLIT(dev)) {
7624 if (HAS_PCH_IBX(dev))
7625 dev_priv->display.init_pch_clock_gating = ibx_init_clock_gating;
7626 else if (HAS_PCH_CPT(dev))
7627 dev_priv->display.init_pch_clock_gating = cpt_init_clock_gating;
7628
7274 if (IS_GEN5(dev)) { 7629 if (IS_GEN5(dev)) {
7275 if (I915_READ(MLTR_ILK) & ILK_SRLT_MASK) 7630 if (I915_READ(MLTR_ILK) & ILK_SRLT_MASK)
7276 dev_priv->display.update_wm = ironlake_update_wm; 7631 dev_priv->display.update_wm = ironlake_update_wm;
@@ -7279,6 +7634,8 @@ static void intel_init_display(struct drm_device *dev)
7279 "Disable CxSR\n"); 7634 "Disable CxSR\n");
7280 dev_priv->display.update_wm = NULL; 7635 dev_priv->display.update_wm = NULL;
7281 } 7636 }
7637 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
7638 dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
7282 } else if (IS_GEN6(dev)) { 7639 } else if (IS_GEN6(dev)) {
7283 if (SNB_READ_WM0_LATENCY()) { 7640 if (SNB_READ_WM0_LATENCY()) {
7284 dev_priv->display.update_wm = sandybridge_update_wm; 7641 dev_priv->display.update_wm = sandybridge_update_wm;
@@ -7287,6 +7644,20 @@ static void intel_init_display(struct drm_device *dev)
7287 "Disable CxSR\n"); 7644 "Disable CxSR\n");
7288 dev_priv->display.update_wm = NULL; 7645 dev_priv->display.update_wm = NULL;
7289 } 7646 }
7647 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
7648 dev_priv->display.init_clock_gating = gen6_init_clock_gating;
7649 } else if (IS_IVYBRIDGE(dev)) {
7650 /* FIXME: detect B0+ stepping and use auto training */
7651 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
7652 if (SNB_READ_WM0_LATENCY()) {
7653 dev_priv->display.update_wm = sandybridge_update_wm;
7654 } else {
7655 DRM_DEBUG_KMS("Failed to read display plane latency. "
7656 "Disable CxSR\n");
7657 dev_priv->display.update_wm = NULL;
7658 }
7659 dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
7660
7290 } else 7661 } else
7291 dev_priv->display.update_wm = NULL; 7662 dev_priv->display.update_wm = NULL;
7292 } else if (IS_PINEVIEW(dev)) { 7663 } else if (IS_PINEVIEW(dev)) {
@@ -7304,18 +7675,30 @@ static void intel_init_display(struct drm_device *dev)
7304 dev_priv->display.update_wm = NULL; 7675 dev_priv->display.update_wm = NULL;
7305 } else 7676 } else
7306 dev_priv->display.update_wm = pineview_update_wm; 7677 dev_priv->display.update_wm = pineview_update_wm;
7307 } else if (IS_G4X(dev)) 7678 } else if (IS_G4X(dev)) {
7308 dev_priv->display.update_wm = g4x_update_wm; 7679 dev_priv->display.update_wm = g4x_update_wm;
7309 else if (IS_GEN4(dev)) 7680 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
7681 } else if (IS_GEN4(dev)) {
7310 dev_priv->display.update_wm = i965_update_wm; 7682 dev_priv->display.update_wm = i965_update_wm;
7311 else if (IS_GEN3(dev)) { 7683 if (IS_CRESTLINE(dev))
7684 dev_priv->display.init_clock_gating = crestline_init_clock_gating;
7685 else if (IS_BROADWATER(dev))
7686 dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
7687 } else if (IS_GEN3(dev)) {
7312 dev_priv->display.update_wm = i9xx_update_wm; 7688 dev_priv->display.update_wm = i9xx_update_wm;
7313 dev_priv->display.get_fifo_size = i9xx_get_fifo_size; 7689 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
7690 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
7691 } else if (IS_I865G(dev)) {
7692 dev_priv->display.update_wm = i830_update_wm;
7693 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
7694 dev_priv->display.get_fifo_size = i830_get_fifo_size;
7314 } else if (IS_I85X(dev)) { 7695 } else if (IS_I85X(dev)) {
7315 dev_priv->display.update_wm = i9xx_update_wm; 7696 dev_priv->display.update_wm = i9xx_update_wm;
7316 dev_priv->display.get_fifo_size = i85x_get_fifo_size; 7697 dev_priv->display.get_fifo_size = i85x_get_fifo_size;
7698 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
7317 } else { 7699 } else {
7318 dev_priv->display.update_wm = i830_update_wm; 7700 dev_priv->display.update_wm = i830_update_wm;
7701 dev_priv->display.init_clock_gating = i830_init_clock_gating;
7319 if (IS_845G(dev)) 7702 if (IS_845G(dev))
7320 dev_priv->display.get_fifo_size = i845_get_fifo_size; 7703 dev_priv->display.get_fifo_size = i845_get_fifo_size;
7321 else 7704 else
@@ -7441,12 +7824,11 @@ void intel_modeset_init(struct drm_device *dev)
7441 intel_crtc_init(dev, i); 7824 intel_crtc_init(dev, i);
7442 } 7825 }
7443 7826
7444 intel_setup_outputs(dev);
7445
7446 intel_enable_clock_gating(dev);
7447
7448 /* Just disable it once at startup */ 7827 /* Just disable it once at startup */
7449 i915_disable_vga(dev); 7828 i915_disable_vga(dev);
7829 intel_setup_outputs(dev);
7830
7831 intel_init_clock_gating(dev);
7450 7832
7451 if (IS_IRONLAKE_M(dev)) { 7833 if (IS_IRONLAKE_M(dev)) {
7452 ironlake_enable_drps(dev); 7834 ironlake_enable_drps(dev);
@@ -7456,12 +7838,15 @@ void intel_modeset_init(struct drm_device *dev)
7456 if (IS_GEN6(dev)) 7838 if (IS_GEN6(dev))
7457 gen6_enable_rps(dev_priv); 7839 gen6_enable_rps(dev_priv);
7458 7840
7459 if (IS_IRONLAKE_M(dev))
7460 ironlake_enable_rc6(dev);
7461
7462 INIT_WORK(&dev_priv->idle_work, intel_idle_update); 7841 INIT_WORK(&dev_priv->idle_work, intel_idle_update);
7463 setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer, 7842 setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer,
7464 (unsigned long)dev); 7843 (unsigned long)dev);
7844}
7845
7846void intel_modeset_gem_init(struct drm_device *dev)
7847{
7848 if (IS_IRONLAKE_M(dev))
7849 ironlake_enable_rc6(dev);
7465 7850
7466 intel_setup_overlay(dev); 7851 intel_setup_overlay(dev);
7467} 7852}
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 1d20712d527f..831d7a4a0d18 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -140,7 +140,6 @@ struct intel_fbdev {
140struct intel_encoder { 140struct intel_encoder {
141 struct drm_encoder base; 141 struct drm_encoder base;
142 int type; 142 int type;
143 bool load_detect_temp;
144 bool needs_tv_clock; 143 bool needs_tv_clock;
145 void (*hot_plug)(struct intel_encoder *); 144 void (*hot_plug)(struct intel_encoder *);
146 int crtc_mask; 145 int crtc_mask;
@@ -291,13 +290,19 @@ int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
291 struct drm_file *file_priv); 290 struct drm_file *file_priv);
292extern void intel_wait_for_vblank(struct drm_device *dev, int pipe); 291extern void intel_wait_for_vblank(struct drm_device *dev, int pipe);
293extern void intel_wait_for_pipe_off(struct drm_device *dev, int pipe); 292extern void intel_wait_for_pipe_off(struct drm_device *dev, int pipe);
294extern struct drm_crtc *intel_get_load_detect_pipe(struct intel_encoder *intel_encoder, 293
295 struct drm_connector *connector, 294struct intel_load_detect_pipe {
296 struct drm_display_mode *mode, 295 struct drm_framebuffer *release_fb;
297 int *dpms_mode); 296 bool load_detect_temp;
297 int dpms_mode;
298};
299extern bool intel_get_load_detect_pipe(struct intel_encoder *intel_encoder,
300 struct drm_connector *connector,
301 struct drm_display_mode *mode,
302 struct intel_load_detect_pipe *old);
298extern void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder, 303extern void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder,
299 struct drm_connector *connector, 304 struct drm_connector *connector,
300 int dpms_mode); 305 struct intel_load_detect_pipe *old);
301 306
302extern struct drm_connector* intel_sdvo_find(struct drm_device *dev, int sdvoB); 307extern struct drm_connector* intel_sdvo_find(struct drm_device *dev, int sdvoB);
303extern int intel_sdvo_supports_hotplug(struct drm_connector *connector); 308extern int intel_sdvo_supports_hotplug(struct drm_connector *connector);
@@ -339,4 +344,6 @@ extern int intel_overlay_attrs(struct drm_device *dev, void *data,
339 344
340extern void intel_fb_output_poll_changed(struct drm_device *dev); 345extern void intel_fb_output_poll_changed(struct drm_device *dev);
341extern void intel_fb_restore_mode(struct drm_device *dev); 346extern void intel_fb_restore_mode(struct drm_device *dev);
347
348extern void intel_init_clock_gating(struct drm_device *dev);
342#endif /* __INTEL_DRV_H__ */ 349#endif /* __INTEL_DRV_H__ */
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index e9e6f71418a4..95c4b1429935 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -236,7 +236,7 @@ init_pipe_control(struct intel_ring_buffer *ring)
236 ret = -ENOMEM; 236 ret = -ENOMEM;
237 goto err; 237 goto err;
238 } 238 }
239 obj->agp_type = AGP_USER_CACHED_MEMORY; 239 obj->cache_level = I915_CACHE_LLC;
240 240
241 ret = i915_gem_object_pin(obj, 4096, true); 241 ret = i915_gem_object_pin(obj, 4096, true);
242 if (ret) 242 if (ret)
@@ -286,7 +286,7 @@ static int init_render_ring(struct intel_ring_buffer *ring)
286 286
287 if (INTEL_INFO(dev)->gen > 3) { 287 if (INTEL_INFO(dev)->gen > 3) {
288 int mode = VS_TIMER_DISPATCH << 16 | VS_TIMER_DISPATCH; 288 int mode = VS_TIMER_DISPATCH << 16 | VS_TIMER_DISPATCH;
289 if (IS_GEN6(dev)) 289 if (IS_GEN6(dev) || IS_GEN7(dev))
290 mode |= MI_FLUSH_ENABLE << 16 | MI_FLUSH_ENABLE; 290 mode |= MI_FLUSH_ENABLE << 16 | MI_FLUSH_ENABLE;
291 I915_WRITE(MI_MODE, mode); 291 I915_WRITE(MI_MODE, mode);
292 } 292 }
@@ -551,10 +551,31 @@ render_ring_put_irq(struct intel_ring_buffer *ring)
551 551
552void intel_ring_setup_status_page(struct intel_ring_buffer *ring) 552void intel_ring_setup_status_page(struct intel_ring_buffer *ring)
553{ 553{
554 struct drm_device *dev = ring->dev;
554 drm_i915_private_t *dev_priv = ring->dev->dev_private; 555 drm_i915_private_t *dev_priv = ring->dev->dev_private;
555 u32 mmio = IS_GEN6(ring->dev) ? 556 u32 mmio = 0;
556 RING_HWS_PGA_GEN6(ring->mmio_base) : 557
557 RING_HWS_PGA(ring->mmio_base); 558 /* The ring status page addresses are no longer next to the rest of
559 * the ring registers as of gen7.
560 */
561 if (IS_GEN7(dev)) {
562 switch (ring->id) {
563 case RING_RENDER:
564 mmio = RENDER_HWS_PGA_GEN7;
565 break;
566 case RING_BLT:
567 mmio = BLT_HWS_PGA_GEN7;
568 break;
569 case RING_BSD:
570 mmio = BSD_HWS_PGA_GEN7;
571 break;
572 }
573 } else if (IS_GEN6(ring->dev)) {
574 mmio = RING_HWS_PGA_GEN6(ring->mmio_base);
575 } else {
576 mmio = RING_HWS_PGA(ring->mmio_base);
577 }
578
558 I915_WRITE(mmio, (u32)ring->status_page.gfx_addr); 579 I915_WRITE(mmio, (u32)ring->status_page.gfx_addr);
559 POSTING_READ(mmio); 580 POSTING_READ(mmio);
560} 581}
@@ -600,7 +621,7 @@ ring_add_request(struct intel_ring_buffer *ring,
600} 621}
601 622
602static bool 623static bool
603ring_get_irq(struct intel_ring_buffer *ring, u32 flag) 624gen6_ring_get_irq(struct intel_ring_buffer *ring, u32 gflag, u32 rflag)
604{ 625{
605 struct drm_device *dev = ring->dev; 626 struct drm_device *dev = ring->dev;
606 drm_i915_private_t *dev_priv = dev->dev_private; 627 drm_i915_private_t *dev_priv = dev->dev_private;
@@ -609,71 +630,67 @@ ring_get_irq(struct intel_ring_buffer *ring, u32 flag)
609 return false; 630 return false;
610 631
611 spin_lock(&ring->irq_lock); 632 spin_lock(&ring->irq_lock);
612 if (ring->irq_refcount++ == 0) 633 if (ring->irq_refcount++ == 0) {
613 ironlake_enable_irq(dev_priv, flag); 634 ring->irq_mask &= ~rflag;
635 I915_WRITE_IMR(ring, ring->irq_mask);
636 ironlake_enable_irq(dev_priv, gflag);
637 }
614 spin_unlock(&ring->irq_lock); 638 spin_unlock(&ring->irq_lock);
615 639
616 return true; 640 return true;
617} 641}
618 642
619static void 643static void
620ring_put_irq(struct intel_ring_buffer *ring, u32 flag) 644gen6_ring_put_irq(struct intel_ring_buffer *ring, u32 gflag, u32 rflag)
621{ 645{
622 struct drm_device *dev = ring->dev; 646 struct drm_device *dev = ring->dev;
623 drm_i915_private_t *dev_priv = dev->dev_private; 647 drm_i915_private_t *dev_priv = dev->dev_private;
624 648
625 spin_lock(&ring->irq_lock); 649 spin_lock(&ring->irq_lock);
626 if (--ring->irq_refcount == 0) 650 if (--ring->irq_refcount == 0) {
627 ironlake_disable_irq(dev_priv, flag); 651 ring->irq_mask |= rflag;
652 I915_WRITE_IMR(ring, ring->irq_mask);
653 ironlake_disable_irq(dev_priv, gflag);
654 }
628 spin_unlock(&ring->irq_lock); 655 spin_unlock(&ring->irq_lock);
629} 656}
630 657
631static bool 658static bool
632gen6_ring_get_irq(struct intel_ring_buffer *ring, u32 gflag, u32 rflag) 659bsd_ring_get_irq(struct intel_ring_buffer *ring)
633{ 660{
634 struct drm_device *dev = ring->dev; 661 struct drm_device *dev = ring->dev;
635 drm_i915_private_t *dev_priv = dev->dev_private; 662 drm_i915_private_t *dev_priv = dev->dev_private;
636 663
637 if (!dev->irq_enabled) 664 if (!dev->irq_enabled)
638 return false; 665 return false;
639 666
640 spin_lock(&ring->irq_lock); 667 spin_lock(&ring->irq_lock);
641 if (ring->irq_refcount++ == 0) { 668 if (ring->irq_refcount++ == 0) {
642 ring->irq_mask &= ~rflag; 669 if (IS_G4X(dev))
643 I915_WRITE_IMR(ring, ring->irq_mask); 670 i915_enable_irq(dev_priv, I915_BSD_USER_INTERRUPT);
644 ironlake_enable_irq(dev_priv, gflag); 671 else
672 ironlake_enable_irq(dev_priv, GT_BSD_USER_INTERRUPT);
645 } 673 }
646 spin_unlock(&ring->irq_lock); 674 spin_unlock(&ring->irq_lock);
647 675
648 return true; 676 return true;
649} 677}
650
651static void 678static void
652gen6_ring_put_irq(struct intel_ring_buffer *ring, u32 gflag, u32 rflag) 679bsd_ring_put_irq(struct intel_ring_buffer *ring)
653{ 680{
654 struct drm_device *dev = ring->dev; 681 struct drm_device *dev = ring->dev;
655 drm_i915_private_t *dev_priv = dev->dev_private; 682 drm_i915_private_t *dev_priv = dev->dev_private;
656 683
657 spin_lock(&ring->irq_lock); 684 spin_lock(&ring->irq_lock);
658 if (--ring->irq_refcount == 0) { 685 if (--ring->irq_refcount == 0) {
659 ring->irq_mask |= rflag; 686 if (IS_G4X(dev))
660 I915_WRITE_IMR(ring, ring->irq_mask); 687 i915_disable_irq(dev_priv, I915_BSD_USER_INTERRUPT);
661 ironlake_disable_irq(dev_priv, gflag); 688 else
689 ironlake_disable_irq(dev_priv, GT_BSD_USER_INTERRUPT);
662 } 690 }
663 spin_unlock(&ring->irq_lock); 691 spin_unlock(&ring->irq_lock);
664} 692}
665 693
666static bool
667bsd_ring_get_irq(struct intel_ring_buffer *ring)
668{
669 return ring_get_irq(ring, GT_BSD_USER_INTERRUPT);
670}
671static void
672bsd_ring_put_irq(struct intel_ring_buffer *ring)
673{
674 ring_put_irq(ring, GT_BSD_USER_INTERRUPT);
675}
676
677static int 694static int
678ring_dispatch_execbuffer(struct intel_ring_buffer *ring, u32 offset, u32 length) 695ring_dispatch_execbuffer(struct intel_ring_buffer *ring, u32 offset, u32 length)
679{ 696{
@@ -759,7 +776,7 @@ static int init_status_page(struct intel_ring_buffer *ring)
759 ret = -ENOMEM; 776 ret = -ENOMEM;
760 goto err; 777 goto err;
761 } 778 }
762 obj->agp_type = AGP_USER_CACHED_MEMORY; 779 obj->cache_level = I915_CACHE_LLC;
763 780
764 ret = i915_gem_object_pin(obj, 4096, true); 781 ret = i915_gem_object_pin(obj, 4096, true);
765 if (ret != 0) { 782 if (ret != 0) {
@@ -800,6 +817,7 @@ int intel_init_ring_buffer(struct drm_device *dev,
800 INIT_LIST_HEAD(&ring->request_list); 817 INIT_LIST_HEAD(&ring->request_list);
801 INIT_LIST_HEAD(&ring->gpu_write_list); 818 INIT_LIST_HEAD(&ring->gpu_write_list);
802 819
820 init_waitqueue_head(&ring->irq_queue);
803 spin_lock_init(&ring->irq_lock); 821 spin_lock_init(&ring->irq_lock);
804 ring->irq_mask = ~0; 822 ring->irq_mask = ~0;
805 823
@@ -872,7 +890,7 @@ void intel_cleanup_ring_buffer(struct intel_ring_buffer *ring)
872 890
873 /* Disable the ring buffer. The ring must be idle at this point */ 891 /* Disable the ring buffer. The ring must be idle at this point */
874 dev_priv = ring->dev->dev_private; 892 dev_priv = ring->dev->dev_private;
875 ret = intel_wait_ring_buffer(ring, ring->size - 8); 893 ret = intel_wait_ring_idle(ring);
876 if (ret) 894 if (ret)
877 DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n", 895 DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n",
878 ring->name, ret); 896 ring->name, ret);
@@ -1333,7 +1351,7 @@ int intel_init_bsd_ring_buffer(struct drm_device *dev)
1333 drm_i915_private_t *dev_priv = dev->dev_private; 1351 drm_i915_private_t *dev_priv = dev->dev_private;
1334 struct intel_ring_buffer *ring = &dev_priv->ring[VCS]; 1352 struct intel_ring_buffer *ring = &dev_priv->ring[VCS];
1335 1353
1336 if (IS_GEN6(dev)) 1354 if (IS_GEN6(dev) || IS_GEN7(dev))
1337 *ring = gen6_bsd_ring; 1355 *ring = gen6_bsd_ring;
1338 else 1356 else
1339 *ring = bsd_ring; 1357 *ring = bsd_ring;
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h
index f23cc5f037a6..c0e0ee63fbf4 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.h
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
@@ -14,27 +14,24 @@ struct intel_hw_status_page {
14 struct drm_i915_gem_object *obj; 14 struct drm_i915_gem_object *obj;
15}; 15};
16 16
17#define I915_RING_READ(reg) i915_gt_read(dev_priv, reg) 17#define I915_READ_TAIL(ring) I915_READ(RING_TAIL((ring)->mmio_base))
18#define I915_RING_WRITE(reg, val) i915_gt_write(dev_priv, reg, val) 18#define I915_WRITE_TAIL(ring, val) I915_WRITE(RING_TAIL((ring)->mmio_base), val)
19 19
20#define I915_READ_TAIL(ring) I915_RING_READ(RING_TAIL((ring)->mmio_base)) 20#define I915_READ_START(ring) I915_READ(RING_START((ring)->mmio_base))
21#define I915_WRITE_TAIL(ring, val) I915_RING_WRITE(RING_TAIL((ring)->mmio_base), val) 21#define I915_WRITE_START(ring, val) I915_WRITE(RING_START((ring)->mmio_base), val)
22 22
23#define I915_READ_START(ring) I915_RING_READ(RING_START((ring)->mmio_base)) 23#define I915_READ_HEAD(ring) I915_READ(RING_HEAD((ring)->mmio_base))
24#define I915_WRITE_START(ring, val) I915_RING_WRITE(RING_START((ring)->mmio_base), val) 24#define I915_WRITE_HEAD(ring, val) I915_WRITE(RING_HEAD((ring)->mmio_base), val)
25 25
26#define I915_READ_HEAD(ring) I915_RING_READ(RING_HEAD((ring)->mmio_base)) 26#define I915_READ_CTL(ring) I915_READ(RING_CTL((ring)->mmio_base))
27#define I915_WRITE_HEAD(ring, val) I915_RING_WRITE(RING_HEAD((ring)->mmio_base), val) 27#define I915_WRITE_CTL(ring, val) I915_WRITE(RING_CTL((ring)->mmio_base), val)
28 28
29#define I915_READ_CTL(ring) I915_RING_READ(RING_CTL((ring)->mmio_base)) 29#define I915_READ_IMR(ring) I915_READ(RING_IMR((ring)->mmio_base))
30#define I915_WRITE_CTL(ring, val) I915_RING_WRITE(RING_CTL((ring)->mmio_base), val) 30#define I915_WRITE_IMR(ring, val) I915_WRITE(RING_IMR((ring)->mmio_base), val)
31 31
32#define I915_READ_IMR(ring) I915_RING_READ(RING_IMR((ring)->mmio_base)) 32#define I915_READ_NOPID(ring) I915_READ(RING_NOPID((ring)->mmio_base))
33#define I915_WRITE_IMR(ring, val) I915_RING_WRITE(RING_IMR((ring)->mmio_base), val) 33#define I915_READ_SYNC_0(ring) I915_READ(RING_SYNC_0((ring)->mmio_base))
34 34#define I915_READ_SYNC_1(ring) I915_READ(RING_SYNC_1((ring)->mmio_base))
35#define I915_READ_NOPID(ring) I915_RING_READ(RING_NOPID((ring)->mmio_base))
36#define I915_READ_SYNC_0(ring) I915_RING_READ(RING_SYNC_0((ring)->mmio_base))
37#define I915_READ_SYNC_1(ring) I915_RING_READ(RING_SYNC_1((ring)->mmio_base))
38 35
39struct intel_ring_buffer { 36struct intel_ring_buffer {
40 const char *name; 37 const char *name;
@@ -164,7 +161,13 @@ intel_read_status_page(struct intel_ring_buffer *ring,
164#define I915_BREADCRUMB_INDEX 0x21 161#define I915_BREADCRUMB_INDEX 0x21
165 162
166void intel_cleanup_ring_buffer(struct intel_ring_buffer *ring); 163void intel_cleanup_ring_buffer(struct intel_ring_buffer *ring);
164
167int __must_check intel_wait_ring_buffer(struct intel_ring_buffer *ring, int n); 165int __must_check intel_wait_ring_buffer(struct intel_ring_buffer *ring, int n);
166static inline int intel_wait_ring_idle(struct intel_ring_buffer *ring)
167{
168 return intel_wait_ring_buffer(ring, ring->space - 8);
169}
170
168int __must_check intel_ring_begin(struct intel_ring_buffer *ring, int n); 171int __must_check intel_ring_begin(struct intel_ring_buffer *ring, int n);
169 172
170static inline void intel_ring_emit(struct intel_ring_buffer *ring, 173static inline void intel_ring_emit(struct intel_ring_buffer *ring,
diff --git a/drivers/gpu/drm/i915/intel_sdvo.c b/drivers/gpu/drm/i915/intel_sdvo.c
index 4324f33212d6..754086f83941 100644
--- a/drivers/gpu/drm/i915/intel_sdvo.c
+++ b/drivers/gpu/drm/i915/intel_sdvo.c
@@ -2544,21 +2544,19 @@ bool intel_sdvo_init(struct drm_device *dev, int sdvo_reg)
2544 if (!intel_sdvo) 2544 if (!intel_sdvo)
2545 return false; 2545 return false;
2546 2546
2547 intel_sdvo->sdvo_reg = sdvo_reg;
2548 intel_sdvo->slave_addr = intel_sdvo_get_slave_addr(dev, sdvo_reg) >> 1;
2549 intel_sdvo_select_i2c_bus(dev_priv, intel_sdvo, sdvo_reg);
2547 if (!intel_sdvo_init_ddc_proxy(intel_sdvo, dev)) { 2550 if (!intel_sdvo_init_ddc_proxy(intel_sdvo, dev)) {
2548 kfree(intel_sdvo); 2551 kfree(intel_sdvo);
2549 return false; 2552 return false;
2550 } 2553 }
2551 2554
2552 intel_sdvo->sdvo_reg = sdvo_reg; 2555 /* encoder type will be decided later */
2553
2554 intel_encoder = &intel_sdvo->base; 2556 intel_encoder = &intel_sdvo->base;
2555 intel_encoder->type = INTEL_OUTPUT_SDVO; 2557 intel_encoder->type = INTEL_OUTPUT_SDVO;
2556 /* encoder type will be decided later */
2557 drm_encoder_init(dev, &intel_encoder->base, &intel_sdvo_enc_funcs, 0); 2558 drm_encoder_init(dev, &intel_encoder->base, &intel_sdvo_enc_funcs, 0);
2558 2559
2559 intel_sdvo->slave_addr = intel_sdvo_get_slave_addr(dev, sdvo_reg) >> 1;
2560 intel_sdvo_select_i2c_bus(dev_priv, intel_sdvo, sdvo_reg);
2561
2562 /* Read the regs to test if we can talk to the device */ 2560 /* Read the regs to test if we can talk to the device */
2563 for (i = 0; i < 0x40; i++) { 2561 for (i = 0; i < 0x40; i++) {
2564 u8 byte; 2562 u8 byte;
diff --git a/drivers/gpu/drm/i915/intel_tv.c b/drivers/gpu/drm/i915/intel_tv.c
index 6b22c1dcc015..113e4e7264cd 100644
--- a/drivers/gpu/drm/i915/intel_tv.c
+++ b/drivers/gpu/drm/i915/intel_tv.c
@@ -1361,15 +1361,14 @@ intel_tv_detect(struct drm_connector *connector, bool force)
1361 if (intel_tv->base.base.crtc && intel_tv->base.base.crtc->enabled) { 1361 if (intel_tv->base.base.crtc && intel_tv->base.base.crtc->enabled) {
1362 type = intel_tv_detect_type(intel_tv, connector); 1362 type = intel_tv_detect_type(intel_tv, connector);
1363 } else if (force) { 1363 } else if (force) {
1364 struct drm_crtc *crtc; 1364 struct intel_load_detect_pipe tmp;
1365 int dpms_mode;
1366 1365
1367 crtc = intel_get_load_detect_pipe(&intel_tv->base, connector, 1366 if (intel_get_load_detect_pipe(&intel_tv->base, connector,
1368 &mode, &dpms_mode); 1367 &mode, &tmp)) {
1369 if (crtc) {
1370 type = intel_tv_detect_type(intel_tv, connector); 1368 type = intel_tv_detect_type(intel_tv, connector);
1371 intel_release_load_detect_pipe(&intel_tv->base, connector, 1369 intel_release_load_detect_pipe(&intel_tv->base,
1372 dpms_mode); 1370 connector,
1371 &tmp);
1373 } else 1372 } else
1374 return connector_status_unknown; 1373 return connector_status_unknown;
1375 } else 1374 } else
generated by cgit v1.2.2 (git 2.25.0) at 2025-03-12 02:50:26 -0400