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path: root/drivers/gpu/drm/i915/intel_sprite.c
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-rw-r--r--drivers/gpu/drm/i915/intel_sprite.c605
1 files changed, 474 insertions, 131 deletions
diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
index 07a74ef589bd..7d9c340f7693 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -37,6 +37,20 @@
37#include <drm/i915_drm.h> 37#include <drm/i915_drm.h>
38#include "i915_drv.h" 38#include "i915_drv.h"
39 39
40static bool
41format_is_yuv(uint32_t format)
42{
43 switch (format) {
44 case DRM_FORMAT_YUYV:
45 case DRM_FORMAT_UYVY:
46 case DRM_FORMAT_VYUY:
47 case DRM_FORMAT_YVYU:
48 return true;
49 default:
50 return false;
51 }
52}
53
40static int usecs_to_scanlines(const struct drm_display_mode *mode, int usecs) 54static int usecs_to_scanlines(const struct drm_display_mode *mode, int usecs)
41{ 55{
42 /* paranoia */ 56 /* paranoia */
@@ -46,7 +60,23 @@ static int usecs_to_scanlines(const struct drm_display_mode *mode, int usecs)
46 return DIV_ROUND_UP(usecs * mode->crtc_clock, 1000 * mode->crtc_htotal); 60 return DIV_ROUND_UP(usecs * mode->crtc_clock, 1000 * mode->crtc_htotal);
47} 61}
48 62
49static bool intel_pipe_update_start(struct intel_crtc *crtc, uint32_t *start_vbl_count) 63/**
64 * intel_pipe_update_start() - start update of a set of display registers
65 * @crtc: the crtc of which the registers are going to be updated
66 * @start_vbl_count: vblank counter return pointer used for error checking
67 *
68 * Mark the start of an update to pipe registers that should be updated
69 * atomically regarding vblank. If the next vblank will happens within
70 * the next 100 us, this function waits until the vblank passes.
71 *
72 * After a successful call to this function, interrupts will be disabled
73 * until a subsequent call to intel_pipe_update_end(). That is done to
74 * avoid random delays. The value written to @start_vbl_count should be
75 * supplied to intel_pipe_update_end() for error checking.
76 *
77 * Return: true if the call was successful
78 */
79bool intel_pipe_update_start(struct intel_crtc *crtc, uint32_t *start_vbl_count)
50{ 80{
51 struct drm_device *dev = crtc->base.dev; 81 struct drm_device *dev = crtc->base.dev;
52 const struct drm_display_mode *mode = &crtc->config.adjusted_mode; 82 const struct drm_display_mode *mode = &crtc->config.adjusted_mode;
@@ -56,8 +86,6 @@ static bool intel_pipe_update_start(struct intel_crtc *crtc, uint32_t *start_vbl
56 wait_queue_head_t *wq = drm_crtc_vblank_waitqueue(&crtc->base); 86 wait_queue_head_t *wq = drm_crtc_vblank_waitqueue(&crtc->base);
57 DEFINE_WAIT(wait); 87 DEFINE_WAIT(wait);
58 88
59 WARN_ON(!drm_modeset_is_locked(&crtc->base.mutex));
60
61 vblank_start = mode->crtc_vblank_start; 89 vblank_start = mode->crtc_vblank_start;
62 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 90 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
63 vblank_start = DIV_ROUND_UP(vblank_start, 2); 91 vblank_start = DIV_ROUND_UP(vblank_start, 2);
@@ -112,7 +140,16 @@ static bool intel_pipe_update_start(struct intel_crtc *crtc, uint32_t *start_vbl
112 return true; 140 return true;
113} 141}
114 142
115static void intel_pipe_update_end(struct intel_crtc *crtc, u32 start_vbl_count) 143/**
144 * intel_pipe_update_end() - end update of a set of display registers
145 * @crtc: the crtc of which the registers were updated
146 * @start_vbl_count: start vblank counter (used for error checking)
147 *
148 * Mark the end of an update started with intel_pipe_update_start(). This
149 * re-enables interrupts and verifies the update was actually completed
150 * before a vblank using the value of @start_vbl_count.
151 */
152void intel_pipe_update_end(struct intel_crtc *crtc, u32 start_vbl_count)
116{ 153{
117 struct drm_device *dev = crtc->base.dev; 154 struct drm_device *dev = crtc->base.dev;
118 enum pipe pipe = crtc->pipe; 155 enum pipe pipe = crtc->pipe;
@@ -139,6 +176,226 @@ static void intel_update_primary_plane(struct intel_crtc *crtc)
139} 176}
140 177
141static void 178static void
179skl_update_plane(struct drm_plane *drm_plane, struct drm_crtc *crtc,
180 struct drm_framebuffer *fb,
181 struct drm_i915_gem_object *obj, int crtc_x, int crtc_y,
182 unsigned int crtc_w, unsigned int crtc_h,
183 uint32_t x, uint32_t y,
184 uint32_t src_w, uint32_t src_h)
185{
186 struct drm_device *dev = drm_plane->dev;
187 struct drm_i915_private *dev_priv = dev->dev_private;
188 struct intel_plane *intel_plane = to_intel_plane(drm_plane);
189 const int pipe = intel_plane->pipe;
190 const int plane = intel_plane->plane + 1;
191 u32 plane_ctl, stride;
192 int pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
193
194 plane_ctl = I915_READ(PLANE_CTL(pipe, plane));
195
196 /* Mask out pixel format bits in case we change it */
197 plane_ctl &= ~PLANE_CTL_FORMAT_MASK;
198 plane_ctl &= ~PLANE_CTL_ORDER_RGBX;
199 plane_ctl &= ~PLANE_CTL_YUV422_ORDER_MASK;
200 plane_ctl &= ~PLANE_CTL_TILED_MASK;
201 plane_ctl &= ~PLANE_CTL_ALPHA_MASK;
202 plane_ctl &= ~PLANE_CTL_ROTATE_MASK;
203
204 /* Trickle feed has to be enabled */
205 plane_ctl &= ~PLANE_CTL_TRICKLE_FEED_DISABLE;
206
207 switch (fb->pixel_format) {
208 case DRM_FORMAT_RGB565:
209 plane_ctl |= PLANE_CTL_FORMAT_RGB_565;
210 break;
211 case DRM_FORMAT_XBGR8888:
212 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
213 break;
214 case DRM_FORMAT_XRGB8888:
215 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888;
216 break;
217 /*
218 * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
219 * to be already pre-multiplied. We need to add a knob (or a different
220 * DRM_FORMAT) for user-space to configure that.
221 */
222 case DRM_FORMAT_ABGR8888:
223 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888 |
224 PLANE_CTL_ORDER_RGBX |
225 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
226 break;
227 case DRM_FORMAT_ARGB8888:
228 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888 |
229 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
230 break;
231 case DRM_FORMAT_YUYV:
232 plane_ctl |= PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
233 break;
234 case DRM_FORMAT_YVYU:
235 plane_ctl |= PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
236 break;
237 case DRM_FORMAT_UYVY:
238 plane_ctl |= PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
239 break;
240 case DRM_FORMAT_VYUY:
241 plane_ctl |= PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
242 break;
243 default:
244 BUG();
245 }
246
247 switch (obj->tiling_mode) {
248 case I915_TILING_NONE:
249 stride = fb->pitches[0] >> 6;
250 break;
251 case I915_TILING_X:
252 plane_ctl |= PLANE_CTL_TILED_X;
253 stride = fb->pitches[0] >> 9;
254 break;
255 default:
256 BUG();
257 }
258 if (intel_plane->rotation == BIT(DRM_ROTATE_180))
259 plane_ctl |= PLANE_CTL_ROTATE_180;
260
261 plane_ctl |= PLANE_CTL_ENABLE;
262 plane_ctl |= PLANE_CTL_PIPE_CSC_ENABLE;
263
264 intel_update_sprite_watermarks(drm_plane, crtc, src_w, src_h,
265 pixel_size, true,
266 src_w != crtc_w || src_h != crtc_h);
267
268 /* Sizes are 0 based */
269 src_w--;
270 src_h--;
271 crtc_w--;
272 crtc_h--;
273
274 I915_WRITE(PLANE_OFFSET(pipe, plane), (y << 16) | x);
275 I915_WRITE(PLANE_STRIDE(pipe, plane), stride);
276 I915_WRITE(PLANE_POS(pipe, plane), (crtc_y << 16) | crtc_x);
277 I915_WRITE(PLANE_SIZE(pipe, plane), (crtc_h << 16) | crtc_w);
278 I915_WRITE(PLANE_CTL(pipe, plane), plane_ctl);
279 I915_WRITE(PLANE_SURF(pipe, plane), i915_gem_obj_ggtt_offset(obj));
280 POSTING_READ(PLANE_SURF(pipe, plane));
281}
282
283static void
284skl_disable_plane(struct drm_plane *drm_plane, struct drm_crtc *crtc)
285{
286 struct drm_device *dev = drm_plane->dev;
287 struct drm_i915_private *dev_priv = dev->dev_private;
288 struct intel_plane *intel_plane = to_intel_plane(drm_plane);
289 const int pipe = intel_plane->pipe;
290 const int plane = intel_plane->plane + 1;
291
292 I915_WRITE(PLANE_CTL(pipe, plane),
293 I915_READ(PLANE_CTL(pipe, plane)) & ~PLANE_CTL_ENABLE);
294
295 /* Activate double buffered register update */
296 I915_WRITE(PLANE_CTL(pipe, plane), 0);
297 POSTING_READ(PLANE_CTL(pipe, plane));
298
299 intel_update_sprite_watermarks(drm_plane, crtc, 0, 0, 0, false, false);
300}
301
302static int
303skl_update_colorkey(struct drm_plane *drm_plane,
304 struct drm_intel_sprite_colorkey *key)
305{
306 struct drm_device *dev = drm_plane->dev;
307 struct drm_i915_private *dev_priv = dev->dev_private;
308 struct intel_plane *intel_plane = to_intel_plane(drm_plane);
309 const int pipe = intel_plane->pipe;
310 const int plane = intel_plane->plane;
311 u32 plane_ctl;
312
313 I915_WRITE(PLANE_KEYVAL(pipe, plane), key->min_value);
314 I915_WRITE(PLANE_KEYMAX(pipe, plane), key->max_value);
315 I915_WRITE(PLANE_KEYMSK(pipe, plane), key->channel_mask);
316
317 plane_ctl = I915_READ(PLANE_CTL(pipe, plane));
318 plane_ctl &= ~PLANE_CTL_KEY_ENABLE_MASK;
319 if (key->flags & I915_SET_COLORKEY_DESTINATION)
320 plane_ctl |= PLANE_CTL_KEY_ENABLE_DESTINATION;
321 else if (key->flags & I915_SET_COLORKEY_SOURCE)
322 plane_ctl |= PLANE_CTL_KEY_ENABLE_SOURCE;
323 I915_WRITE(PLANE_CTL(pipe, plane), plane_ctl);
324
325 POSTING_READ(PLANE_CTL(pipe, plane));
326
327 return 0;
328}
329
330static void
331skl_get_colorkey(struct drm_plane *drm_plane,
332 struct drm_intel_sprite_colorkey *key)
333{
334 struct drm_device *dev = drm_plane->dev;
335 struct drm_i915_private *dev_priv = dev->dev_private;
336 struct intel_plane *intel_plane = to_intel_plane(drm_plane);
337 const int pipe = intel_plane->pipe;
338 const int plane = intel_plane->plane;
339 u32 plane_ctl;
340
341 key->min_value = I915_READ(PLANE_KEYVAL(pipe, plane));
342 key->max_value = I915_READ(PLANE_KEYMAX(pipe, plane));
343 key->channel_mask = I915_READ(PLANE_KEYMSK(pipe, plane));
344
345 plane_ctl = I915_READ(PLANE_CTL(pipe, plane));
346
347 switch (plane_ctl & PLANE_CTL_KEY_ENABLE_MASK) {
348 case PLANE_CTL_KEY_ENABLE_DESTINATION:
349 key->flags = I915_SET_COLORKEY_DESTINATION;
350 break;
351 case PLANE_CTL_KEY_ENABLE_SOURCE:
352 key->flags = I915_SET_COLORKEY_SOURCE;
353 break;
354 default:
355 key->flags = I915_SET_COLORKEY_NONE;
356 }
357}
358
359static void
360chv_update_csc(struct intel_plane *intel_plane, uint32_t format)
361{
362 struct drm_i915_private *dev_priv = intel_plane->base.dev->dev_private;
363 int plane = intel_plane->plane;
364
365 /* Seems RGB data bypasses the CSC always */
366 if (!format_is_yuv(format))
367 return;
368
369 /*
370 * BT.601 limited range YCbCr -> full range RGB
371 *
372 * |r| | 6537 4769 0| |cr |
373 * |g| = |-3330 4769 -1605| x |y-64|
374 * |b| | 0 4769 8263| |cb |
375 *
376 * Cb and Cr apparently come in as signed already, so no
377 * need for any offset. For Y we need to remove the offset.
378 */
379 I915_WRITE(SPCSCYGOFF(plane), SPCSC_OOFF(0) | SPCSC_IOFF(-64));
380 I915_WRITE(SPCSCCBOFF(plane), SPCSC_OOFF(0) | SPCSC_IOFF(0));
381 I915_WRITE(SPCSCCROFF(plane), SPCSC_OOFF(0) | SPCSC_IOFF(0));
382
383 I915_WRITE(SPCSCC01(plane), SPCSC_C1(4769) | SPCSC_C0(6537));
384 I915_WRITE(SPCSCC23(plane), SPCSC_C1(-3330) | SPCSC_C0(0));
385 I915_WRITE(SPCSCC45(plane), SPCSC_C1(-1605) | SPCSC_C0(4769));
386 I915_WRITE(SPCSCC67(plane), SPCSC_C1(4769) | SPCSC_C0(0));
387 I915_WRITE(SPCSCC8(plane), SPCSC_C0(8263));
388
389 I915_WRITE(SPCSCYGICLAMP(plane), SPCSC_IMAX(940) | SPCSC_IMIN(64));
390 I915_WRITE(SPCSCCBICLAMP(plane), SPCSC_IMAX(448) | SPCSC_IMIN(-448));
391 I915_WRITE(SPCSCCRICLAMP(plane), SPCSC_IMAX(448) | SPCSC_IMIN(-448));
392
393 I915_WRITE(SPCSCYGOCLAMP(plane), SPCSC_OMAX(1023) | SPCSC_OMIN(0));
394 I915_WRITE(SPCSCCBOCLAMP(plane), SPCSC_OMAX(1023) | SPCSC_OMIN(0));
395 I915_WRITE(SPCSCCROCLAMP(plane), SPCSC_OMAX(1023) | SPCSC_OMIN(0));
396}
397
398static void
142vlv_update_plane(struct drm_plane *dplane, struct drm_crtc *crtc, 399vlv_update_plane(struct drm_plane *dplane, struct drm_crtc *crtc,
143 struct drm_framebuffer *fb, 400 struct drm_framebuffer *fb,
144 struct drm_i915_gem_object *obj, int crtc_x, int crtc_y, 401 struct drm_i915_gem_object *obj, int crtc_x, int crtc_y,
@@ -249,6 +506,9 @@ vlv_update_plane(struct drm_plane *dplane, struct drm_crtc *crtc,
249 506
250 intel_update_primary_plane(intel_crtc); 507 intel_update_primary_plane(intel_crtc);
251 508
509 if (IS_CHERRYVIEW(dev) && pipe == PIPE_B)
510 chv_update_csc(intel_plane, fb->pixel_format);
511
252 I915_WRITE(SPSTRIDE(pipe, plane), fb->pitches[0]); 512 I915_WRITE(SPSTRIDE(pipe, plane), fb->pitches[0]);
253 I915_WRITE(SPPOS(pipe, plane), (crtc_y << 16) | crtc_x); 513 I915_WRITE(SPPOS(pipe, plane), (crtc_y << 16) | crtc_x);
254 514
@@ -257,6 +517,8 @@ vlv_update_plane(struct drm_plane *dplane, struct drm_crtc *crtc,
257 else 517 else
258 I915_WRITE(SPLINOFF(pipe, plane), linear_offset); 518 I915_WRITE(SPLINOFF(pipe, plane), linear_offset);
259 519
520 I915_WRITE(SPCONSTALPHA(pipe, plane), 0);
521
260 I915_WRITE(SPSIZE(pipe, plane), (crtc_h << 16) | crtc_w); 522 I915_WRITE(SPSIZE(pipe, plane), (crtc_h << 16) | crtc_w);
261 I915_WRITE(SPCNTR(pipe, plane), sprctl); 523 I915_WRITE(SPCNTR(pipe, plane), sprctl);
262 I915_WRITE(SPSURF(pipe, plane), i915_gem_obj_ggtt_offset(obj) + 524 I915_WRITE(SPSURF(pipe, plane), i915_gem_obj_ggtt_offset(obj) +
@@ -821,20 +1083,6 @@ ilk_get_colorkey(struct drm_plane *plane, struct drm_intel_sprite_colorkey *key)
821 key->flags = I915_SET_COLORKEY_NONE; 1083 key->flags = I915_SET_COLORKEY_NONE;
822} 1084}
823 1085
824static bool
825format_is_yuv(uint32_t format)
826{
827 switch (format) {
828 case DRM_FORMAT_YUYV:
829 case DRM_FORMAT_UYVY:
830 case DRM_FORMAT_VYUY:
831 case DRM_FORMAT_YVYU:
832 return true;
833 default:
834 return false;
835 }
836}
837
838static bool colorkey_enabled(struct intel_plane *intel_plane) 1086static bool colorkey_enabled(struct intel_plane *intel_plane)
839{ 1087{
840 struct drm_intel_sprite_colorkey key; 1088 struct drm_intel_sprite_colorkey key;
@@ -845,57 +1093,23 @@ static bool colorkey_enabled(struct intel_plane *intel_plane)
845} 1093}
846 1094
847static int 1095static int
848intel_update_plane(struct drm_plane *plane, struct drm_crtc *crtc, 1096intel_check_sprite_plane(struct drm_plane *plane,
849 struct drm_framebuffer *fb, int crtc_x, int crtc_y, 1097 struct intel_plane_state *state)
850 unsigned int crtc_w, unsigned int crtc_h,
851 uint32_t src_x, uint32_t src_y,
852 uint32_t src_w, uint32_t src_h)
853{ 1098{
854 struct drm_device *dev = plane->dev; 1099 struct intel_crtc *intel_crtc = to_intel_crtc(state->crtc);
855 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
856 struct intel_plane *intel_plane = to_intel_plane(plane); 1100 struct intel_plane *intel_plane = to_intel_plane(plane);
857 enum pipe pipe = intel_crtc->pipe; 1101 struct drm_framebuffer *fb = state->fb;
858 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); 1102 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
859 struct drm_i915_gem_object *obj = intel_fb->obj; 1103 int crtc_x, crtc_y;
860 struct drm_i915_gem_object *old_obj = intel_plane->obj; 1104 unsigned int crtc_w, crtc_h;
861 int ret; 1105 uint32_t src_x, src_y, src_w, src_h;
862 bool primary_enabled; 1106 struct drm_rect *src = &state->src;
863 bool visible; 1107 struct drm_rect *dst = &state->dst;
1108 struct drm_rect *orig_src = &state->orig_src;
1109 const struct drm_rect *clip = &state->clip;
864 int hscale, vscale; 1110 int hscale, vscale;
865 int max_scale, min_scale; 1111 int max_scale, min_scale;
866 int pixel_size = drm_format_plane_cpp(fb->pixel_format, 0); 1112 int pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
867 struct drm_rect src = {
868 /* sample coordinates in 16.16 fixed point */
869 .x1 = src_x,
870 .x2 = src_x + src_w,
871 .y1 = src_y,
872 .y2 = src_y + src_h,
873 };
874 struct drm_rect dst = {
875 /* integer pixels */
876 .x1 = crtc_x,
877 .x2 = crtc_x + crtc_w,
878 .y1 = crtc_y,
879 .y2 = crtc_y + crtc_h,
880 };
881 const struct drm_rect clip = {
882 .x2 = intel_crtc->active ? intel_crtc->config.pipe_src_w : 0,
883 .y2 = intel_crtc->active ? intel_crtc->config.pipe_src_h : 0,
884 };
885 const struct {
886 int crtc_x, crtc_y;
887 unsigned int crtc_w, crtc_h;
888 uint32_t src_x, src_y, src_w, src_h;
889 } orig = {
890 .crtc_x = crtc_x,
891 .crtc_y = crtc_y,
892 .crtc_w = crtc_w,
893 .crtc_h = crtc_h,
894 .src_x = src_x,
895 .src_y = src_y,
896 .src_w = src_w,
897 .src_h = src_h,
898 };
899 1113
900 /* Don't modify another pipe's plane */ 1114 /* Don't modify another pipe's plane */
901 if (intel_plane->pipe != intel_crtc->pipe) { 1115 if (intel_plane->pipe != intel_crtc->pipe) {
@@ -927,55 +1141,55 @@ intel_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
927 max_scale = intel_plane->max_downscale << 16; 1141 max_scale = intel_plane->max_downscale << 16;
928 min_scale = intel_plane->can_scale ? 1 : (1 << 16); 1142 min_scale = intel_plane->can_scale ? 1 : (1 << 16);
929 1143
930 drm_rect_rotate(&src, fb->width << 16, fb->height << 16, 1144 drm_rect_rotate(src, fb->width << 16, fb->height << 16,
931 intel_plane->rotation); 1145 intel_plane->rotation);
932 1146
933 hscale = drm_rect_calc_hscale_relaxed(&src, &dst, min_scale, max_scale); 1147 hscale = drm_rect_calc_hscale_relaxed(src, dst, min_scale, max_scale);
934 BUG_ON(hscale < 0); 1148 BUG_ON(hscale < 0);
935 1149
936 vscale = drm_rect_calc_vscale_relaxed(&src, &dst, min_scale, max_scale); 1150 vscale = drm_rect_calc_vscale_relaxed(src, dst, min_scale, max_scale);
937 BUG_ON(vscale < 0); 1151 BUG_ON(vscale < 0);
938 1152
939 visible = drm_rect_clip_scaled(&src, &dst, &clip, hscale, vscale); 1153 state->visible = drm_rect_clip_scaled(src, dst, clip, hscale, vscale);
940 1154
941 crtc_x = dst.x1; 1155 crtc_x = dst->x1;
942 crtc_y = dst.y1; 1156 crtc_y = dst->y1;
943 crtc_w = drm_rect_width(&dst); 1157 crtc_w = drm_rect_width(dst);
944 crtc_h = drm_rect_height(&dst); 1158 crtc_h = drm_rect_height(dst);
945 1159
946 if (visible) { 1160 if (state->visible) {
947 /* check again in case clipping clamped the results */ 1161 /* check again in case clipping clamped the results */
948 hscale = drm_rect_calc_hscale(&src, &dst, min_scale, max_scale); 1162 hscale = drm_rect_calc_hscale(src, dst, min_scale, max_scale);
949 if (hscale < 0) { 1163 if (hscale < 0) {
950 DRM_DEBUG_KMS("Horizontal scaling factor out of limits\n"); 1164 DRM_DEBUG_KMS("Horizontal scaling factor out of limits\n");
951 drm_rect_debug_print(&src, true); 1165 drm_rect_debug_print(src, true);
952 drm_rect_debug_print(&dst, false); 1166 drm_rect_debug_print(dst, false);
953 1167
954 return hscale; 1168 return hscale;
955 } 1169 }
956 1170
957 vscale = drm_rect_calc_vscale(&src, &dst, min_scale, max_scale); 1171 vscale = drm_rect_calc_vscale(src, dst, min_scale, max_scale);
958 if (vscale < 0) { 1172 if (vscale < 0) {
959 DRM_DEBUG_KMS("Vertical scaling factor out of limits\n"); 1173 DRM_DEBUG_KMS("Vertical scaling factor out of limits\n");
960 drm_rect_debug_print(&src, true); 1174 drm_rect_debug_print(src, true);
961 drm_rect_debug_print(&dst, false); 1175 drm_rect_debug_print(dst, false);
962 1176
963 return vscale; 1177 return vscale;
964 } 1178 }
965 1179
966 /* Make the source viewport size an exact multiple of the scaling factors. */ 1180 /* Make the source viewport size an exact multiple of the scaling factors. */
967 drm_rect_adjust_size(&src, 1181 drm_rect_adjust_size(src,
968 drm_rect_width(&dst) * hscale - drm_rect_width(&src), 1182 drm_rect_width(dst) * hscale - drm_rect_width(src),
969 drm_rect_height(&dst) * vscale - drm_rect_height(&src)); 1183 drm_rect_height(dst) * vscale - drm_rect_height(src));
970 1184
971 drm_rect_rotate_inv(&src, fb->width << 16, fb->height << 16, 1185 drm_rect_rotate_inv(src, fb->width << 16, fb->height << 16,
972 intel_plane->rotation); 1186 intel_plane->rotation);
973 1187
974 /* sanity check to make sure the src viewport wasn't enlarged */ 1188 /* sanity check to make sure the src viewport wasn't enlarged */
975 WARN_ON(src.x1 < (int) src_x || 1189 WARN_ON(src->x1 < (int) orig_src->x1 ||
976 src.y1 < (int) src_y || 1190 src->y1 < (int) orig_src->y1 ||
977 src.x2 > (int) (src_x + src_w) || 1191 src->x2 > (int) orig_src->x2 ||
978 src.y2 > (int) (src_y + src_h)); 1192 src->y2 > (int) orig_src->y2);
979 1193
980 /* 1194 /*
981 * Hardware doesn't handle subpixel coordinates. 1195 * Hardware doesn't handle subpixel coordinates.
@@ -983,10 +1197,10 @@ intel_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
983 * increase the source viewport size, because that could 1197 * increase the source viewport size, because that could
984 * push the downscaling factor out of bounds. 1198 * push the downscaling factor out of bounds.
985 */ 1199 */
986 src_x = src.x1 >> 16; 1200 src_x = src->x1 >> 16;
987 src_w = drm_rect_width(&src) >> 16; 1201 src_w = drm_rect_width(src) >> 16;
988 src_y = src.y1 >> 16; 1202 src_y = src->y1 >> 16;
989 src_h = drm_rect_height(&src) >> 16; 1203 src_h = drm_rect_height(src) >> 16;
990 1204
991 if (format_is_yuv(fb->pixel_format)) { 1205 if (format_is_yuv(fb->pixel_format)) {
992 src_x &= ~1; 1206 src_x &= ~1;
@@ -1000,12 +1214,12 @@ intel_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
1000 crtc_w &= ~1; 1214 crtc_w &= ~1;
1001 1215
1002 if (crtc_w == 0) 1216 if (crtc_w == 0)
1003 visible = false; 1217 state->visible = false;
1004 } 1218 }
1005 } 1219 }
1006 1220
1007 /* Check size restrictions when scaling */ 1221 /* Check size restrictions when scaling */
1008 if (visible && (src_w != crtc_w || src_h != crtc_h)) { 1222 if (state->visible && (src_w != crtc_w || src_h != crtc_h)) {
1009 unsigned int width_bytes; 1223 unsigned int width_bytes;
1010 1224
1011 WARN_ON(!intel_plane->can_scale); 1225 WARN_ON(!intel_plane->can_scale);
@@ -1013,12 +1227,13 @@ intel_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
1013 /* FIXME interlacing min height is 6 */ 1227 /* FIXME interlacing min height is 6 */
1014 1228
1015 if (crtc_w < 3 || crtc_h < 3) 1229 if (crtc_w < 3 || crtc_h < 3)
1016 visible = false; 1230 state->visible = false;
1017 1231
1018 if (src_w < 3 || src_h < 3) 1232 if (src_w < 3 || src_h < 3)
1019 visible = false; 1233 state->visible = false;
1020 1234
1021 width_bytes = ((src_x * pixel_size) & 63) + src_w * pixel_size; 1235 width_bytes = ((src_x * pixel_size) & 63) +
1236 src_w * pixel_size;
1022 1237
1023 if (src_w > 2048 || src_h > 2048 || 1238 if (src_w > 2048 || src_h > 2048 ||
1024 width_bytes > 4096 || fb->pitches[0] > 4096) { 1239 width_bytes > 4096 || fb->pitches[0] > 4096) {
@@ -1027,42 +1242,90 @@ intel_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
1027 } 1242 }
1028 } 1243 }
1029 1244
1030 dst.x1 = crtc_x; 1245 if (state->visible) {
1031 dst.x2 = crtc_x + crtc_w; 1246 src->x1 = src_x;
1032 dst.y1 = crtc_y; 1247 src->x2 = src_x + src_w;
1033 dst.y2 = crtc_y + crtc_h; 1248 src->y1 = src_y;
1249 src->y2 = src_y + src_h;
1250 }
1034 1251
1035 /* 1252 dst->x1 = crtc_x;
1036 * If the sprite is completely covering the primary plane, 1253 dst->x2 = crtc_x + crtc_w;
1037 * we can disable the primary and save power. 1254 dst->y1 = crtc_y;
1038 */ 1255 dst->y2 = crtc_y + crtc_h;
1039 primary_enabled = !drm_rect_equals(&dst, &clip) || colorkey_enabled(intel_plane);
1040 WARN_ON(!primary_enabled && !visible && intel_crtc->active);
1041 1256
1042 mutex_lock(&dev->struct_mutex); 1257 return 0;
1258}
1043 1259
1044 /* Note that this will apply the VT-d workaround for scanouts, 1260static int
1045 * which is more restrictive than required for sprites. (The 1261intel_prepare_sprite_plane(struct drm_plane *plane,
1046 * primary plane requires 256KiB alignment with 64 PTE padding, 1262 struct intel_plane_state *state)
1047 * the sprite planes only require 128KiB alignment and 32 PTE padding. 1263{
1048 */ 1264 struct drm_device *dev = plane->dev;
1049 ret = intel_pin_and_fence_fb_obj(dev, obj, NULL); 1265 struct drm_crtc *crtc = state->crtc;
1266 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1267 struct intel_plane *intel_plane = to_intel_plane(plane);
1268 enum pipe pipe = intel_crtc->pipe;
1269 struct drm_framebuffer *fb = state->fb;
1270 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
1271 struct drm_i915_gem_object *old_obj = intel_plane->obj;
1272 int ret;
1050 1273
1051 i915_gem_track_fb(old_obj, obj, 1274 if (old_obj != obj) {
1052 INTEL_FRONTBUFFER_SPRITE(pipe)); 1275 mutex_lock(&dev->struct_mutex);
1053 mutex_unlock(&dev->struct_mutex);
1054 1276
1055 if (ret) 1277 /* Note that this will apply the VT-d workaround for scanouts,
1056 return ret; 1278 * which is more restrictive than required for sprites. (The
1279 * primary plane requires 256KiB alignment with 64 PTE padding,
1280 * the sprite planes only require 128KiB alignment and 32 PTE
1281 * padding.
1282 */
1283 ret = intel_pin_and_fence_fb_obj(plane, fb, NULL);
1284 if (ret == 0)
1285 i915_gem_track_fb(old_obj, obj,
1286 INTEL_FRONTBUFFER_SPRITE(pipe));
1287 mutex_unlock(&dev->struct_mutex);
1288 if (ret)
1289 return ret;
1290 }
1291
1292 return 0;
1293}
1057 1294
1058 intel_plane->crtc_x = orig.crtc_x; 1295static void
1059 intel_plane->crtc_y = orig.crtc_y; 1296intel_commit_sprite_plane(struct drm_plane *plane,
1060 intel_plane->crtc_w = orig.crtc_w; 1297 struct intel_plane_state *state)
1061 intel_plane->crtc_h = orig.crtc_h; 1298{
1062 intel_plane->src_x = orig.src_x; 1299 struct drm_device *dev = plane->dev;
1063 intel_plane->src_y = orig.src_y; 1300 struct drm_crtc *crtc = state->crtc;
1064 intel_plane->src_w = orig.src_w; 1301 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1065 intel_plane->src_h = orig.src_h; 1302 struct intel_plane *intel_plane = to_intel_plane(plane);
1303 enum pipe pipe = intel_crtc->pipe;
1304 struct drm_framebuffer *fb = state->fb;
1305 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
1306 struct drm_i915_gem_object *old_obj = intel_plane->obj;
1307 int crtc_x, crtc_y;
1308 unsigned int crtc_w, crtc_h;
1309 uint32_t src_x, src_y, src_w, src_h;
1310 struct drm_rect *dst = &state->dst;
1311 const struct drm_rect *clip = &state->clip;
1312 bool primary_enabled;
1313
1314 /*
1315 * If the sprite is completely covering the primary plane,
1316 * we can disable the primary and save power.
1317 */
1318 primary_enabled = !drm_rect_equals(dst, clip) || colorkey_enabled(intel_plane);
1319 WARN_ON(!primary_enabled && !state->visible && intel_crtc->active);
1320
1321 intel_plane->crtc_x = state->orig_dst.x1;
1322 intel_plane->crtc_y = state->orig_dst.y1;
1323 intel_plane->crtc_w = drm_rect_width(&state->orig_dst);
1324 intel_plane->crtc_h = drm_rect_height(&state->orig_dst);
1325 intel_plane->src_x = state->orig_src.x1;
1326 intel_plane->src_y = state->orig_src.y1;
1327 intel_plane->src_w = drm_rect_width(&state->orig_src);
1328 intel_plane->src_h = drm_rect_height(&state->orig_src);
1066 intel_plane->obj = obj; 1329 intel_plane->obj = obj;
1067 1330
1068 if (intel_crtc->active) { 1331 if (intel_crtc->active) {
@@ -1076,12 +1339,22 @@ intel_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
1076 if (primary_was_enabled && !primary_enabled) 1339 if (primary_was_enabled && !primary_enabled)
1077 intel_pre_disable_primary(crtc); 1340 intel_pre_disable_primary(crtc);
1078 1341
1079 if (visible) 1342 if (state->visible) {
1343 crtc_x = state->dst.x1;
1344 crtc_y = state->dst.y1;
1345 crtc_w = drm_rect_width(&state->dst);
1346 crtc_h = drm_rect_height(&state->dst);
1347 src_x = state->src.x1;
1348 src_y = state->src.y1;
1349 src_w = drm_rect_width(&state->src);
1350 src_h = drm_rect_height(&state->src);
1080 intel_plane->update_plane(plane, crtc, fb, obj, 1351 intel_plane->update_plane(plane, crtc, fb, obj,
1081 crtc_x, crtc_y, crtc_w, crtc_h, 1352 crtc_x, crtc_y, crtc_w, crtc_h,
1082 src_x, src_y, src_w, src_h); 1353 src_x, src_y, src_w, src_h);
1083 else 1354 } else {
1084 intel_plane->disable_plane(plane, crtc); 1355 intel_plane->disable_plane(plane, crtc);
1356 }
1357
1085 1358
1086 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_SPRITE(pipe)); 1359 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_SPRITE(pipe));
1087 1360
@@ -1090,21 +1363,65 @@ intel_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
1090 } 1363 }
1091 1364
1092 /* Unpin old obj after new one is active to avoid ugliness */ 1365 /* Unpin old obj after new one is active to avoid ugliness */
1093 if (old_obj) { 1366 if (old_obj && old_obj != obj) {
1367
1094 /* 1368 /*
1095 * It's fairly common to simply update the position of 1369 * It's fairly common to simply update the position of
1096 * an existing object. In that case, we don't need to 1370 * an existing object. In that case, we don't need to
1097 * wait for vblank to avoid ugliness, we only need to 1371 * wait for vblank to avoid ugliness, we only need to
1098 * do the pin & ref bookkeeping. 1372 * do the pin & ref bookkeeping.
1099 */ 1373 */
1100 if (old_obj != obj && intel_crtc->active) 1374 if (intel_crtc->active)
1101 intel_wait_for_vblank(dev, intel_crtc->pipe); 1375 intel_wait_for_vblank(dev, intel_crtc->pipe);
1102 1376
1103 mutex_lock(&dev->struct_mutex); 1377 mutex_lock(&dev->struct_mutex);
1104 intel_unpin_fb_obj(old_obj); 1378 intel_unpin_fb_obj(old_obj);
1105 mutex_unlock(&dev->struct_mutex); 1379 mutex_unlock(&dev->struct_mutex);
1106 } 1380 }
1381}
1382
1383static int
1384intel_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
1385 struct drm_framebuffer *fb, int crtc_x, int crtc_y,
1386 unsigned int crtc_w, unsigned int crtc_h,
1387 uint32_t src_x, uint32_t src_y,
1388 uint32_t src_w, uint32_t src_h)
1389{
1390 struct intel_plane_state state;
1391 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1392 int ret;
1107 1393
1394 state.crtc = crtc;
1395 state.fb = fb;
1396
1397 /* sample coordinates in 16.16 fixed point */
1398 state.src.x1 = src_x;
1399 state.src.x2 = src_x + src_w;
1400 state.src.y1 = src_y;
1401 state.src.y2 = src_y + src_h;
1402
1403 /* integer pixels */
1404 state.dst.x1 = crtc_x;
1405 state.dst.x2 = crtc_x + crtc_w;
1406 state.dst.y1 = crtc_y;
1407 state.dst.y2 = crtc_y + crtc_h;
1408
1409 state.clip.x1 = 0;
1410 state.clip.y1 = 0;
1411 state.clip.x2 = intel_crtc->active ? intel_crtc->config.pipe_src_w : 0;
1412 state.clip.y2 = intel_crtc->active ? intel_crtc->config.pipe_src_h : 0;
1413 state.orig_src = state.src;
1414 state.orig_dst = state.dst;
1415
1416 ret = intel_check_sprite_plane(plane, &state);
1417 if (ret)
1418 return ret;
1419
1420 ret = intel_prepare_sprite_plane(plane, &state);
1421 if (ret)
1422 return ret;
1423
1424 intel_commit_sprite_plane(plane, &state);
1108 return 0; 1425 return 0;
1109} 1426}
1110 1427
@@ -1305,6 +1622,18 @@ static uint32_t vlv_plane_formats[] = {
1305 DRM_FORMAT_VYUY, 1622 DRM_FORMAT_VYUY,
1306}; 1623};
1307 1624
1625static uint32_t skl_plane_formats[] = {
1626 DRM_FORMAT_RGB565,
1627 DRM_FORMAT_ABGR8888,
1628 DRM_FORMAT_ARGB8888,
1629 DRM_FORMAT_XBGR8888,
1630 DRM_FORMAT_XRGB8888,
1631 DRM_FORMAT_YUYV,
1632 DRM_FORMAT_YVYU,
1633 DRM_FORMAT_UYVY,
1634 DRM_FORMAT_VYUY,
1635};
1636
1308int 1637int
1309intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane) 1638intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane)
1310{ 1639{
@@ -1368,7 +1697,21 @@ intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane)
1368 num_plane_formats = ARRAY_SIZE(snb_plane_formats); 1697 num_plane_formats = ARRAY_SIZE(snb_plane_formats);
1369 } 1698 }
1370 break; 1699 break;
1371 1700 case 9:
1701 /*
1702 * FIXME: Skylake planes can be scaled (with some restrictions),
1703 * but this is for another time.
1704 */
1705 intel_plane->can_scale = false;
1706 intel_plane->max_downscale = 1;
1707 intel_plane->update_plane = skl_update_plane;
1708 intel_plane->disable_plane = skl_disable_plane;
1709 intel_plane->update_colorkey = skl_update_colorkey;
1710 intel_plane->get_colorkey = skl_get_colorkey;
1711
1712 plane_formats = skl_plane_formats;
1713 num_plane_formats = ARRAY_SIZE(skl_plane_formats);
1714 break;
1372 default: 1715 default:
1373 kfree(intel_plane); 1716 kfree(intel_plane);
1374 return -ENODEV; 1717 return -ENODEV;