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path: root/drivers/gpu/drm/i915/intel_sprite.c
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Diffstat (limited to 'drivers/gpu/drm/i915/intel_sprite.c')
-rw-r--r--drivers/gpu/drm/i915/intel_sprite.c42
1 files changed, 0 insertions, 42 deletions
diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
index 3e6e95fe46ae..1dfdccbb9ab2 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -412,8 +412,6 @@ vlv_update_plane(struct drm_plane *dplane, struct drm_crtc *crtc,
412 u32 sprctl; 412 u32 sprctl;
413 unsigned long sprsurf_offset, linear_offset; 413 unsigned long sprsurf_offset, linear_offset;
414 int pixel_size = drm_format_plane_cpp(fb->pixel_format, 0); 414 int pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
415 u32 start_vbl_count;
416 bool atomic_update;
417 415
418 sprctl = I915_READ(SPCNTR(pipe, plane)); 416 sprctl = I915_READ(SPCNTR(pipe, plane));
419 417
@@ -502,8 +500,6 @@ vlv_update_plane(struct drm_plane *dplane, struct drm_crtc *crtc,
502 linear_offset += src_h * fb->pitches[0] + src_w * pixel_size; 500 linear_offset += src_h * fb->pitches[0] + src_w * pixel_size;
503 } 501 }
504 502
505 atomic_update = intel_pipe_update_start(intel_crtc, &start_vbl_count);
506
507 intel_update_primary_plane(intel_crtc); 503 intel_update_primary_plane(intel_crtc);
508 504
509 if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) 505 if (IS_CHERRYVIEW(dev) && pipe == PIPE_B)
@@ -525,9 +521,6 @@ vlv_update_plane(struct drm_plane *dplane, struct drm_crtc *crtc,
525 sprsurf_offset); 521 sprsurf_offset);
526 522
527 intel_flush_primary_plane(dev_priv, intel_crtc->plane); 523 intel_flush_primary_plane(dev_priv, intel_crtc->plane);
528
529 if (atomic_update)
530 intel_pipe_update_end(intel_crtc, start_vbl_count);
531} 524}
532 525
533static void 526static void
@@ -539,10 +532,6 @@ vlv_disable_plane(struct drm_plane *dplane, struct drm_crtc *crtc)
539 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 532 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
540 int pipe = intel_plane->pipe; 533 int pipe = intel_plane->pipe;
541 int plane = intel_plane->plane; 534 int plane = intel_plane->plane;
542 u32 start_vbl_count;
543 bool atomic_update;
544
545 atomic_update = intel_pipe_update_start(intel_crtc, &start_vbl_count);
546 535
547 intel_update_primary_plane(intel_crtc); 536 intel_update_primary_plane(intel_crtc);
548 537
@@ -553,9 +542,6 @@ vlv_disable_plane(struct drm_plane *dplane, struct drm_crtc *crtc)
553 542
554 intel_flush_primary_plane(dev_priv, intel_crtc->plane); 543 intel_flush_primary_plane(dev_priv, intel_crtc->plane);
555 544
556 if (atomic_update)
557 intel_pipe_update_end(intel_crtc, start_vbl_count);
558
559 intel_update_sprite_watermarks(dplane, crtc, 0, 0, 0, false, false); 545 intel_update_sprite_watermarks(dplane, crtc, 0, 0, 0, false, false);
560} 546}
561 547
@@ -626,8 +612,6 @@ ivb_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
626 u32 sprctl, sprscale = 0; 612 u32 sprctl, sprscale = 0;
627 unsigned long sprsurf_offset, linear_offset; 613 unsigned long sprsurf_offset, linear_offset;
628 int pixel_size = drm_format_plane_cpp(fb->pixel_format, 0); 614 int pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
629 u32 start_vbl_count;
630 bool atomic_update;
631 615
632 sprctl = I915_READ(SPRCTL(pipe)); 616 sprctl = I915_READ(SPRCTL(pipe));
633 617
@@ -711,8 +695,6 @@ ivb_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
711 } 695 }
712 } 696 }
713 697
714 atomic_update = intel_pipe_update_start(intel_crtc, &start_vbl_count);
715
716 intel_update_primary_plane(intel_crtc); 698 intel_update_primary_plane(intel_crtc);
717 699
718 I915_WRITE(SPRSTRIDE(pipe), fb->pitches[0]); 700 I915_WRITE(SPRSTRIDE(pipe), fb->pitches[0]);
@@ -735,9 +717,6 @@ ivb_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
735 i915_gem_obj_ggtt_offset(obj) + sprsurf_offset); 717 i915_gem_obj_ggtt_offset(obj) + sprsurf_offset);
736 718
737 intel_flush_primary_plane(dev_priv, intel_crtc->plane); 719 intel_flush_primary_plane(dev_priv, intel_crtc->plane);
738
739 if (atomic_update)
740 intel_pipe_update_end(intel_crtc, start_vbl_count);
741} 720}
742 721
743static void 722static void
@@ -748,10 +727,6 @@ ivb_disable_plane(struct drm_plane *plane, struct drm_crtc *crtc)
748 struct intel_plane *intel_plane = to_intel_plane(plane); 727 struct intel_plane *intel_plane = to_intel_plane(plane);
749 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 728 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
750 int pipe = intel_plane->pipe; 729 int pipe = intel_plane->pipe;
751 u32 start_vbl_count;
752 bool atomic_update;
753
754 atomic_update = intel_pipe_update_start(intel_crtc, &start_vbl_count);
755 730
756 intel_update_primary_plane(intel_crtc); 731 intel_update_primary_plane(intel_crtc);
757 732
@@ -764,9 +739,6 @@ ivb_disable_plane(struct drm_plane *plane, struct drm_crtc *crtc)
764 739
765 intel_flush_primary_plane(dev_priv, intel_crtc->plane); 740 intel_flush_primary_plane(dev_priv, intel_crtc->plane);
766 741
767 if (atomic_update)
768 intel_pipe_update_end(intel_crtc, start_vbl_count);
769
770 /* 742 /*
771 * Avoid underruns when disabling the sprite. 743 * Avoid underruns when disabling the sprite.
772 * FIXME remove once watermark updates are done properly. 744 * FIXME remove once watermark updates are done properly.
@@ -845,8 +817,6 @@ ilk_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
845 unsigned long dvssurf_offset, linear_offset; 817 unsigned long dvssurf_offset, linear_offset;
846 u32 dvscntr, dvsscale; 818 u32 dvscntr, dvsscale;
847 int pixel_size = drm_format_plane_cpp(fb->pixel_format, 0); 819 int pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
848 u32 start_vbl_count;
849 bool atomic_update;
850 820
851 dvscntr = I915_READ(DVSCNTR(pipe)); 821 dvscntr = I915_READ(DVSCNTR(pipe));
852 822
@@ -921,8 +891,6 @@ ilk_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
921 linear_offset += src_h * fb->pitches[0] + src_w * pixel_size; 891 linear_offset += src_h * fb->pitches[0] + src_w * pixel_size;
922 } 892 }
923 893
924 atomic_update = intel_pipe_update_start(intel_crtc, &start_vbl_count);
925
926 intel_update_primary_plane(intel_crtc); 894 intel_update_primary_plane(intel_crtc);
927 895
928 I915_WRITE(DVSSTRIDE(pipe), fb->pitches[0]); 896 I915_WRITE(DVSSTRIDE(pipe), fb->pitches[0]);
@@ -940,9 +908,6 @@ ilk_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
940 i915_gem_obj_ggtt_offset(obj) + dvssurf_offset); 908 i915_gem_obj_ggtt_offset(obj) + dvssurf_offset);
941 909
942 intel_flush_primary_plane(dev_priv, intel_crtc->plane); 910 intel_flush_primary_plane(dev_priv, intel_crtc->plane);
943
944 if (atomic_update)
945 intel_pipe_update_end(intel_crtc, start_vbl_count);
946} 911}
947 912
948static void 913static void
@@ -953,10 +918,6 @@ ilk_disable_plane(struct drm_plane *plane, struct drm_crtc *crtc)
953 struct intel_plane *intel_plane = to_intel_plane(plane); 918 struct intel_plane *intel_plane = to_intel_plane(plane);
954 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 919 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
955 int pipe = intel_plane->pipe; 920 int pipe = intel_plane->pipe;
956 u32 start_vbl_count;
957 bool atomic_update;
958
959 atomic_update = intel_pipe_update_start(intel_crtc, &start_vbl_count);
960 921
961 intel_update_primary_plane(intel_crtc); 922 intel_update_primary_plane(intel_crtc);
962 923
@@ -968,9 +929,6 @@ ilk_disable_plane(struct drm_plane *plane, struct drm_crtc *crtc)
968 929
969 intel_flush_primary_plane(dev_priv, intel_crtc->plane); 930 intel_flush_primary_plane(dev_priv, intel_crtc->plane);
970 931
971 if (atomic_update)
972 intel_pipe_update_end(intel_crtc, start_vbl_count);
973
974 /* 932 /*
975 * Avoid underruns when disabling the sprite. 933 * Avoid underruns when disabling the sprite.
976 * FIXME remove once watermark updates are done properly. 934 * FIXME remove once watermark updates are done properly.