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path: root/drivers/gpu/drm/i915/intel_ringbuffer.h
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Diffstat (limited to 'drivers/gpu/drm/i915/intel_ringbuffer.h')
-rw-r--r--drivers/gpu/drm/i915/intel_ringbuffer.h36
1 files changed, 21 insertions, 15 deletions
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h
index 8e2e357ad6ee..be9087e4c9be 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.h
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
@@ -16,21 +16,24 @@ struct intel_hw_status_page {
16 16
17#define I915_RING_READ(reg) i915_safe_read(dev_priv, reg) 17#define I915_RING_READ(reg) i915_safe_read(dev_priv, reg)
18 18
19#define I915_READ_TAIL(ring) I915_RING_READ(RING_TAIL(ring->mmio_base)) 19#define I915_READ_TAIL(ring) I915_RING_READ(RING_TAIL((ring)->mmio_base))
20#define I915_WRITE_TAIL(ring, val) I915_WRITE(RING_TAIL(ring->mmio_base), val) 20#define I915_WRITE_TAIL(ring, val) I915_WRITE(RING_TAIL((ring)->mmio_base), val)
21 21
22#define I915_READ_START(ring) I915_RING_READ(RING_START(ring->mmio_base)) 22#define I915_READ_START(ring) I915_RING_READ(RING_START((ring)->mmio_base))
23#define I915_WRITE_START(ring, val) I915_WRITE(RING_START(ring->mmio_base), val) 23#define I915_WRITE_START(ring, val) I915_WRITE(RING_START((ring)->mmio_base), val)
24 24
25#define I915_READ_HEAD(ring) I915_RING_READ(RING_HEAD(ring->mmio_base)) 25#define I915_READ_HEAD(ring) I915_RING_READ(RING_HEAD((ring)->mmio_base))
26#define I915_WRITE_HEAD(ring, val) I915_WRITE(RING_HEAD(ring->mmio_base), val) 26#define I915_WRITE_HEAD(ring, val) I915_WRITE(RING_HEAD((ring)->mmio_base), val)
27 27
28#define I915_READ_CTL(ring) I915_RING_READ(RING_CTL(ring->mmio_base)) 28#define I915_READ_CTL(ring) I915_RING_READ(RING_CTL((ring)->mmio_base))
29#define I915_WRITE_CTL(ring, val) I915_WRITE(RING_CTL(ring->mmio_base), val) 29#define I915_WRITE_CTL(ring, val) I915_WRITE(RING_CTL((ring)->mmio_base), val)
30 30
31#define I915_READ_NOPID(ring) I915_RING_READ(RING_NOPID(ring->mmio_base)) 31#define I915_WRITE_IMR(ring, val) I915_WRITE(RING_IMR((ring)->mmio_base), val)
32#define I915_READ_SYNC_0(ring) I915_RING_READ(RING_SYNC_0(ring->mmio_base)) 32#define I915_READ_IMR(ring) I915_RING_READ(RING_IMR((ring)->mmio_base))
33#define I915_READ_SYNC_1(ring) I915_RING_READ(RING_SYNC_1(ring->mmio_base)) 33
34#define I915_READ_NOPID(ring) I915_RING_READ(RING_NOPID((ring)->mmio_base))
35#define I915_READ_SYNC_0(ring) I915_RING_READ(RING_SYNC_0((ring)->mmio_base))
36#define I915_READ_SYNC_1(ring) I915_RING_READ(RING_SYNC_1((ring)->mmio_base))
34 37
35struct intel_ring_buffer { 38struct intel_ring_buffer {
36 const char *name; 39 const char *name;
@@ -49,12 +52,15 @@ struct intel_ring_buffer {
49 u32 tail; 52 u32 tail;
50 int space; 53 int space;
51 int size; 54 int size;
55 int effective_size;
52 struct intel_hw_status_page status_page; 56 struct intel_hw_status_page status_page;
53 57
58 spinlock_t irq_lock;
59 u32 irq_refcount;
60 u32 irq_mask;
54 u32 irq_seqno; /* last seq seem at irq time */ 61 u32 irq_seqno; /* last seq seem at irq time */
55 u32 waiting_seqno; 62 u32 waiting_seqno;
56 u32 sync_seqno[I915_NUM_RINGS-1]; 63 u32 sync_seqno[I915_NUM_RINGS-1];
57 atomic_t irq_refcount;
58 bool __must_check (*irq_get)(struct intel_ring_buffer *ring); 64 bool __must_check (*irq_get)(struct intel_ring_buffer *ring);
59 void (*irq_put)(struct intel_ring_buffer *ring); 65 void (*irq_put)(struct intel_ring_buffer *ring);
60 66
@@ -62,9 +68,9 @@ struct intel_ring_buffer {
62 68
63 void (*write_tail)(struct intel_ring_buffer *ring, 69 void (*write_tail)(struct intel_ring_buffer *ring,
64 u32 value); 70 u32 value);
65 void (*flush)(struct intel_ring_buffer *ring, 71 int __must_check (*flush)(struct intel_ring_buffer *ring,
66 u32 invalidate_domains, 72 u32 invalidate_domains,
67 u32 flush_domains); 73 u32 flush_domains);
68 int (*add_request)(struct intel_ring_buffer *ring, 74 int (*add_request)(struct intel_ring_buffer *ring,
69 u32 *seqno); 75 u32 *seqno);
70 u32 (*get_seqno)(struct intel_ring_buffer *ring); 76 u32 (*get_seqno)(struct intel_ring_buffer *ring);