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path: root/drivers/gpu/drm/i915/intel_ringbuffer.c
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Diffstat (limited to 'drivers/gpu/drm/i915/intel_ringbuffer.c')
-rw-r--r--drivers/gpu/drm/i915/intel_ringbuffer.c152
1 files changed, 83 insertions, 69 deletions
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 31b36c5ac894..6bc68bdcf433 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -406,17 +406,24 @@ gen8_render_ring_flush(struct intel_ring_buffer *ring,
406static void ring_write_tail(struct intel_ring_buffer *ring, 406static void ring_write_tail(struct intel_ring_buffer *ring,
407 u32 value) 407 u32 value)
408{ 408{
409 drm_i915_private_t *dev_priv = ring->dev->dev_private; 409 struct drm_i915_private *dev_priv = ring->dev->dev_private;
410 I915_WRITE_TAIL(ring, value); 410 I915_WRITE_TAIL(ring, value);
411} 411}
412 412
413u32 intel_ring_get_active_head(struct intel_ring_buffer *ring) 413u64 intel_ring_get_active_head(struct intel_ring_buffer *ring)
414{ 414{
415 drm_i915_private_t *dev_priv = ring->dev->dev_private; 415 struct drm_i915_private *dev_priv = ring->dev->dev_private;
416 u32 acthd_reg = INTEL_INFO(ring->dev)->gen >= 4 ? 416 u64 acthd;
417 RING_ACTHD(ring->mmio_base) : ACTHD; 417
418 if (INTEL_INFO(ring->dev)->gen >= 8)
419 acthd = I915_READ64_2x32(RING_ACTHD(ring->mmio_base),
420 RING_ACTHD_UDW(ring->mmio_base));
421 else if (INTEL_INFO(ring->dev)->gen >= 4)
422 acthd = I915_READ(RING_ACTHD(ring->mmio_base));
423 else
424 acthd = I915_READ(ACTHD);
418 425
419 return I915_READ(acthd_reg); 426 return acthd;
420} 427}
421 428
422static void ring_setup_phys_status_page(struct intel_ring_buffer *ring) 429static void ring_setup_phys_status_page(struct intel_ring_buffer *ring)
@@ -433,22 +440,24 @@ static void ring_setup_phys_status_page(struct intel_ring_buffer *ring)
433static int init_ring_common(struct intel_ring_buffer *ring) 440static int init_ring_common(struct intel_ring_buffer *ring)
434{ 441{
435 struct drm_device *dev = ring->dev; 442 struct drm_device *dev = ring->dev;
436 drm_i915_private_t *dev_priv = dev->dev_private; 443 struct drm_i915_private *dev_priv = dev->dev_private;
437 struct drm_i915_gem_object *obj = ring->obj; 444 struct drm_i915_gem_object *obj = ring->obj;
438 int ret = 0; 445 int ret = 0;
439 u32 head; 446 u32 head;
440 447
441 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL); 448 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
442 449
443 if (I915_NEED_GFX_HWS(dev))
444 intel_ring_setup_status_page(ring);
445 else
446 ring_setup_phys_status_page(ring);
447
448 /* Stop the ring if it's running. */ 450 /* Stop the ring if it's running. */
449 I915_WRITE_CTL(ring, 0); 451 I915_WRITE_CTL(ring, 0);
450 I915_WRITE_HEAD(ring, 0); 452 I915_WRITE_HEAD(ring, 0);
451 ring->write_tail(ring, 0); 453 ring->write_tail(ring, 0);
454 if (wait_for_atomic((I915_READ_MODE(ring) & MODE_IDLE) != 0, 1000))
455 DRM_ERROR("%s :timed out trying to stop ring\n", ring->name);
456
457 if (I915_NEED_GFX_HWS(dev))
458 intel_ring_setup_status_page(ring);
459 else
460 ring_setup_phys_status_page(ring);
452 461
453 head = I915_READ_HEAD(ring) & HEAD_ADDR; 462 head = I915_READ_HEAD(ring) & HEAD_ADDR;
454 463
@@ -531,9 +540,11 @@ init_pipe_control(struct intel_ring_buffer *ring)
531 goto err; 540 goto err;
532 } 541 }
533 542
534 i915_gem_object_set_cache_level(ring->scratch.obj, I915_CACHE_LLC); 543 ret = i915_gem_object_set_cache_level(ring->scratch.obj, I915_CACHE_LLC);
544 if (ret)
545 goto err_unref;
535 546
536 ret = i915_gem_obj_ggtt_pin(ring->scratch.obj, 4096, true, false); 547 ret = i915_gem_obj_ggtt_pin(ring->scratch.obj, 4096, 0);
537 if (ret) 548 if (ret)
538 goto err_unref; 549 goto err_unref;
539 550
@@ -549,7 +560,7 @@ init_pipe_control(struct intel_ring_buffer *ring)
549 return 0; 560 return 0;
550 561
551err_unpin: 562err_unpin:
552 i915_gem_object_unpin(ring->scratch.obj); 563 i915_gem_object_ggtt_unpin(ring->scratch.obj);
553err_unref: 564err_unref:
554 drm_gem_object_unreference(&ring->scratch.obj->base); 565 drm_gem_object_unreference(&ring->scratch.obj->base);
555err: 566err:
@@ -562,14 +573,15 @@ static int init_render_ring(struct intel_ring_buffer *ring)
562 struct drm_i915_private *dev_priv = dev->dev_private; 573 struct drm_i915_private *dev_priv = dev->dev_private;
563 int ret = init_ring_common(ring); 574 int ret = init_ring_common(ring);
564 575
565 if (INTEL_INFO(dev)->gen > 3) 576 /* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */
577 if (INTEL_INFO(dev)->gen >= 4 && INTEL_INFO(dev)->gen < 7)
566 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH)); 578 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH));
567 579
568 /* We need to disable the AsyncFlip performance optimisations in order 580 /* We need to disable the AsyncFlip performance optimisations in order
569 * to use MI_WAIT_FOR_EVENT within the CS. It should already be 581 * to use MI_WAIT_FOR_EVENT within the CS. It should already be
570 * programmed to '1' on all products. 582 * programmed to '1' on all products.
571 * 583 *
572 * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv 584 * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv,bdw
573 */ 585 */
574 if (INTEL_INFO(dev)->gen >= 6) 586 if (INTEL_INFO(dev)->gen >= 6)
575 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE)); 587 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE));
@@ -625,7 +637,7 @@ static void render_ring_cleanup(struct intel_ring_buffer *ring)
625 637
626 if (INTEL_INFO(dev)->gen >= 5) { 638 if (INTEL_INFO(dev)->gen >= 5) {
627 kunmap(sg_page(ring->scratch.obj->pages->sgl)); 639 kunmap(sg_page(ring->scratch.obj->pages->sgl));
628 i915_gem_object_unpin(ring->scratch.obj); 640 i915_gem_object_ggtt_unpin(ring->scratch.obj);
629 } 641 }
630 642
631 drm_gem_object_unreference(&ring->scratch.obj->base); 643 drm_gem_object_unreference(&ring->scratch.obj->base);
@@ -809,8 +821,11 @@ gen6_ring_get_seqno(struct intel_ring_buffer *ring, bool lazy_coherency)
809 /* Workaround to force correct ordering between irq and seqno writes on 821 /* Workaround to force correct ordering between irq and seqno writes on
810 * ivb (and maybe also on snb) by reading from a CS register (like 822 * ivb (and maybe also on snb) by reading from a CS register (like
811 * ACTHD) before reading the status page. */ 823 * ACTHD) before reading the status page. */
812 if (!lazy_coherency) 824 if (!lazy_coherency) {
813 intel_ring_get_active_head(ring); 825 struct drm_i915_private *dev_priv = ring->dev->dev_private;
826 POSTING_READ(RING_ACTHD(ring->mmio_base));
827 }
828
814 return intel_read_status_page(ring, I915_GEM_HWS_INDEX); 829 return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
815} 830}
816 831
@@ -842,7 +857,7 @@ static bool
842gen5_ring_get_irq(struct intel_ring_buffer *ring) 857gen5_ring_get_irq(struct intel_ring_buffer *ring)
843{ 858{
844 struct drm_device *dev = ring->dev; 859 struct drm_device *dev = ring->dev;
845 drm_i915_private_t *dev_priv = dev->dev_private; 860 struct drm_i915_private *dev_priv = dev->dev_private;
846 unsigned long flags; 861 unsigned long flags;
847 862
848 if (!dev->irq_enabled) 863 if (!dev->irq_enabled)
@@ -860,7 +875,7 @@ static void
860gen5_ring_put_irq(struct intel_ring_buffer *ring) 875gen5_ring_put_irq(struct intel_ring_buffer *ring)
861{ 876{
862 struct drm_device *dev = ring->dev; 877 struct drm_device *dev = ring->dev;
863 drm_i915_private_t *dev_priv = dev->dev_private; 878 struct drm_i915_private *dev_priv = dev->dev_private;
864 unsigned long flags; 879 unsigned long flags;
865 880
866 spin_lock_irqsave(&dev_priv->irq_lock, flags); 881 spin_lock_irqsave(&dev_priv->irq_lock, flags);
@@ -873,7 +888,7 @@ static bool
873i9xx_ring_get_irq(struct intel_ring_buffer *ring) 888i9xx_ring_get_irq(struct intel_ring_buffer *ring)
874{ 889{
875 struct drm_device *dev = ring->dev; 890 struct drm_device *dev = ring->dev;
876 drm_i915_private_t *dev_priv = dev->dev_private; 891 struct drm_i915_private *dev_priv = dev->dev_private;
877 unsigned long flags; 892 unsigned long flags;
878 893
879 if (!dev->irq_enabled) 894 if (!dev->irq_enabled)
@@ -894,7 +909,7 @@ static void
894i9xx_ring_put_irq(struct intel_ring_buffer *ring) 909i9xx_ring_put_irq(struct intel_ring_buffer *ring)
895{ 910{
896 struct drm_device *dev = ring->dev; 911 struct drm_device *dev = ring->dev;
897 drm_i915_private_t *dev_priv = dev->dev_private; 912 struct drm_i915_private *dev_priv = dev->dev_private;
898 unsigned long flags; 913 unsigned long flags;
899 914
900 spin_lock_irqsave(&dev_priv->irq_lock, flags); 915 spin_lock_irqsave(&dev_priv->irq_lock, flags);
@@ -910,7 +925,7 @@ static bool
910i8xx_ring_get_irq(struct intel_ring_buffer *ring) 925i8xx_ring_get_irq(struct intel_ring_buffer *ring)
911{ 926{
912 struct drm_device *dev = ring->dev; 927 struct drm_device *dev = ring->dev;
913 drm_i915_private_t *dev_priv = dev->dev_private; 928 struct drm_i915_private *dev_priv = dev->dev_private;
914 unsigned long flags; 929 unsigned long flags;
915 930
916 if (!dev->irq_enabled) 931 if (!dev->irq_enabled)
@@ -931,7 +946,7 @@ static void
931i8xx_ring_put_irq(struct intel_ring_buffer *ring) 946i8xx_ring_put_irq(struct intel_ring_buffer *ring)
932{ 947{
933 struct drm_device *dev = ring->dev; 948 struct drm_device *dev = ring->dev;
934 drm_i915_private_t *dev_priv = dev->dev_private; 949 struct drm_i915_private *dev_priv = dev->dev_private;
935 unsigned long flags; 950 unsigned long flags;
936 951
937 spin_lock_irqsave(&dev_priv->irq_lock, flags); 952 spin_lock_irqsave(&dev_priv->irq_lock, flags);
@@ -946,7 +961,7 @@ i8xx_ring_put_irq(struct intel_ring_buffer *ring)
946void intel_ring_setup_status_page(struct intel_ring_buffer *ring) 961void intel_ring_setup_status_page(struct intel_ring_buffer *ring)
947{ 962{
948 struct drm_device *dev = ring->dev; 963 struct drm_device *dev = ring->dev;
949 drm_i915_private_t *dev_priv = ring->dev->dev_private; 964 struct drm_i915_private *dev_priv = ring->dev->dev_private;
950 u32 mmio = 0; 965 u32 mmio = 0;
951 966
952 /* The ring status page addresses are no longer next to the rest of 967 /* The ring status page addresses are no longer next to the rest of
@@ -977,9 +992,19 @@ void intel_ring_setup_status_page(struct intel_ring_buffer *ring)
977 I915_WRITE(mmio, (u32)ring->status_page.gfx_addr); 992 I915_WRITE(mmio, (u32)ring->status_page.gfx_addr);
978 POSTING_READ(mmio); 993 POSTING_READ(mmio);
979 994
980 /* Flush the TLB for this page */ 995 /*
981 if (INTEL_INFO(dev)->gen >= 6) { 996 * Flush the TLB for this page
997 *
998 * FIXME: These two bits have disappeared on gen8, so a question
999 * arises: do we still need this and if so how should we go about
1000 * invalidating the TLB?
1001 */
1002 if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 8) {
982 u32 reg = RING_INSTPM(ring->mmio_base); 1003 u32 reg = RING_INSTPM(ring->mmio_base);
1004
1005 /* ring should be idle before issuing a sync flush*/
1006 WARN_ON((I915_READ_MODE(ring) & MODE_IDLE) == 0);
1007
983 I915_WRITE(reg, 1008 I915_WRITE(reg,
984 _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE | 1009 _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE |
985 INSTPM_SYNC_FLUSH)); 1010 INSTPM_SYNC_FLUSH));
@@ -1029,7 +1054,7 @@ static bool
1029gen6_ring_get_irq(struct intel_ring_buffer *ring) 1054gen6_ring_get_irq(struct intel_ring_buffer *ring)
1030{ 1055{
1031 struct drm_device *dev = ring->dev; 1056 struct drm_device *dev = ring->dev;
1032 drm_i915_private_t *dev_priv = dev->dev_private; 1057 struct drm_i915_private *dev_priv = dev->dev_private;
1033 unsigned long flags; 1058 unsigned long flags;
1034 1059
1035 if (!dev->irq_enabled) 1060 if (!dev->irq_enabled)
@@ -1054,7 +1079,7 @@ static void
1054gen6_ring_put_irq(struct intel_ring_buffer *ring) 1079gen6_ring_put_irq(struct intel_ring_buffer *ring)
1055{ 1080{
1056 struct drm_device *dev = ring->dev; 1081 struct drm_device *dev = ring->dev;
1057 drm_i915_private_t *dev_priv = dev->dev_private; 1082 struct drm_i915_private *dev_priv = dev->dev_private;
1058 unsigned long flags; 1083 unsigned long flags;
1059 1084
1060 spin_lock_irqsave(&dev_priv->irq_lock, flags); 1085 spin_lock_irqsave(&dev_priv->irq_lock, flags);
@@ -1253,7 +1278,7 @@ static void cleanup_status_page(struct intel_ring_buffer *ring)
1253 return; 1278 return;
1254 1279
1255 kunmap(sg_page(obj->pages->sgl)); 1280 kunmap(sg_page(obj->pages->sgl));
1256 i915_gem_object_unpin(obj); 1281 i915_gem_object_ggtt_unpin(obj);
1257 drm_gem_object_unreference(&obj->base); 1282 drm_gem_object_unreference(&obj->base);
1258 ring->status_page.obj = NULL; 1283 ring->status_page.obj = NULL;
1259} 1284}
@@ -1271,12 +1296,13 @@ static int init_status_page(struct intel_ring_buffer *ring)
1271 goto err; 1296 goto err;
1272 } 1297 }
1273 1298
1274 i915_gem_object_set_cache_level(obj, I915_CACHE_LLC); 1299 ret = i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
1300 if (ret)
1301 goto err_unref;
1275 1302
1276 ret = i915_gem_obj_ggtt_pin(obj, 4096, true, false); 1303 ret = i915_gem_obj_ggtt_pin(obj, 4096, 0);
1277 if (ret != 0) { 1304 if (ret)
1278 goto err_unref; 1305 goto err_unref;
1279 }
1280 1306
1281 ring->status_page.gfx_addr = i915_gem_obj_ggtt_offset(obj); 1307 ring->status_page.gfx_addr = i915_gem_obj_ggtt_offset(obj);
1282 ring->status_page.page_addr = kmap(sg_page(obj->pages->sgl)); 1308 ring->status_page.page_addr = kmap(sg_page(obj->pages->sgl));
@@ -1293,7 +1319,7 @@ static int init_status_page(struct intel_ring_buffer *ring)
1293 return 0; 1319 return 0;
1294 1320
1295err_unpin: 1321err_unpin:
1296 i915_gem_object_unpin(obj); 1322 i915_gem_object_ggtt_unpin(obj);
1297err_unref: 1323err_unref:
1298 drm_gem_object_unreference(&obj->base); 1324 drm_gem_object_unreference(&obj->base);
1299err: 1325err:
@@ -1356,7 +1382,7 @@ static int intel_init_ring_buffer(struct drm_device *dev,
1356 1382
1357 ring->obj = obj; 1383 ring->obj = obj;
1358 1384
1359 ret = i915_gem_obj_ggtt_pin(obj, PAGE_SIZE, true, false); 1385 ret = i915_gem_obj_ggtt_pin(obj, PAGE_SIZE, PIN_MAPPABLE);
1360 if (ret) 1386 if (ret)
1361 goto err_unref; 1387 goto err_unref;
1362 1388
@@ -1385,12 +1411,14 @@ static int intel_init_ring_buffer(struct drm_device *dev,
1385 if (IS_I830(ring->dev) || IS_845G(ring->dev)) 1411 if (IS_I830(ring->dev) || IS_845G(ring->dev))
1386 ring->effective_size -= 128; 1412 ring->effective_size -= 128;
1387 1413
1414 i915_cmd_parser_init_ring(ring);
1415
1388 return 0; 1416 return 0;
1389 1417
1390err_unmap: 1418err_unmap:
1391 iounmap(ring->virtual_start); 1419 iounmap(ring->virtual_start);
1392err_unpin: 1420err_unpin:
1393 i915_gem_object_unpin(obj); 1421 i915_gem_object_ggtt_unpin(obj);
1394err_unref: 1422err_unref:
1395 drm_gem_object_unreference(&obj->base); 1423 drm_gem_object_unreference(&obj->base);
1396 ring->obj = NULL; 1424 ring->obj = NULL;
@@ -1418,7 +1446,7 @@ void intel_cleanup_ring_buffer(struct intel_ring_buffer *ring)
1418 1446
1419 iounmap(ring->virtual_start); 1447 iounmap(ring->virtual_start);
1420 1448
1421 i915_gem_object_unpin(ring->obj); 1449 i915_gem_object_ggtt_unpin(ring->obj);
1422 drm_gem_object_unreference(&ring->obj->base); 1450 drm_gem_object_unreference(&ring->obj->base);
1423 ring->obj = NULL; 1451 ring->obj = NULL;
1424 ring->preallocated_lazy_request = NULL; 1452 ring->preallocated_lazy_request = NULL;
@@ -1430,28 +1458,16 @@ void intel_cleanup_ring_buffer(struct intel_ring_buffer *ring)
1430 cleanup_status_page(ring); 1458 cleanup_status_page(ring);
1431} 1459}
1432 1460
1433static int intel_ring_wait_seqno(struct intel_ring_buffer *ring, u32 seqno)
1434{
1435 int ret;
1436
1437 ret = i915_wait_seqno(ring, seqno);
1438 if (!ret)
1439 i915_gem_retire_requests_ring(ring);
1440
1441 return ret;
1442}
1443
1444static int intel_ring_wait_request(struct intel_ring_buffer *ring, int n) 1461static int intel_ring_wait_request(struct intel_ring_buffer *ring, int n)
1445{ 1462{
1446 struct drm_i915_gem_request *request; 1463 struct drm_i915_gem_request *request;
1447 u32 seqno = 0; 1464 u32 seqno = 0, tail;
1448 int ret; 1465 int ret;
1449 1466
1450 i915_gem_retire_requests_ring(ring);
1451
1452 if (ring->last_retired_head != -1) { 1467 if (ring->last_retired_head != -1) {
1453 ring->head = ring->last_retired_head; 1468 ring->head = ring->last_retired_head;
1454 ring->last_retired_head = -1; 1469 ring->last_retired_head = -1;
1470
1455 ring->space = ring_space(ring); 1471 ring->space = ring_space(ring);
1456 if (ring->space >= n) 1472 if (ring->space >= n)
1457 return 0; 1473 return 0;
@@ -1468,6 +1484,7 @@ static int intel_ring_wait_request(struct intel_ring_buffer *ring, int n)
1468 space += ring->size; 1484 space += ring->size;
1469 if (space >= n) { 1485 if (space >= n) {
1470 seqno = request->seqno; 1486 seqno = request->seqno;
1487 tail = request->tail;
1471 break; 1488 break;
1472 } 1489 }
1473 1490
@@ -1482,15 +1499,11 @@ static int intel_ring_wait_request(struct intel_ring_buffer *ring, int n)
1482 if (seqno == 0) 1499 if (seqno == 0)
1483 return -ENOSPC; 1500 return -ENOSPC;
1484 1501
1485 ret = intel_ring_wait_seqno(ring, seqno); 1502 ret = i915_wait_seqno(ring, seqno);
1486 if (ret) 1503 if (ret)
1487 return ret; 1504 return ret;
1488 1505
1489 if (WARN_ON(ring->last_retired_head == -1)) 1506 ring->head = tail;
1490 return -ENOSPC;
1491
1492 ring->head = ring->last_retired_head;
1493 ring->last_retired_head = -1;
1494 ring->space = ring_space(ring); 1507 ring->space = ring_space(ring);
1495 if (WARN_ON(ring->space < n)) 1508 if (WARN_ON(ring->space < n))
1496 return -ENOSPC; 1509 return -ENOSPC;
@@ -1528,7 +1541,8 @@ static int ring_wait_for_space(struct intel_ring_buffer *ring, int n)
1528 return 0; 1541 return 0;
1529 } 1542 }
1530 1543
1531 if (dev->primary->master) { 1544 if (!drm_core_check_feature(dev, DRIVER_MODESET) &&
1545 dev->primary->master) {
1532 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv; 1546 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
1533 if (master_priv->sarea_priv) 1547 if (master_priv->sarea_priv)
1534 master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT; 1548 master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
@@ -1632,7 +1646,7 @@ static int __intel_ring_prepare(struct intel_ring_buffer *ring,
1632int intel_ring_begin(struct intel_ring_buffer *ring, 1646int intel_ring_begin(struct intel_ring_buffer *ring,
1633 int num_dwords) 1647 int num_dwords)
1634{ 1648{
1635 drm_i915_private_t *dev_priv = ring->dev->dev_private; 1649 struct drm_i915_private *dev_priv = ring->dev->dev_private;
1636 int ret; 1650 int ret;
1637 1651
1638 ret = i915_gem_check_wedge(&dev_priv->gpu_error, 1652 ret = i915_gem_check_wedge(&dev_priv->gpu_error,
@@ -1694,7 +1708,7 @@ void intel_ring_init_seqno(struct intel_ring_buffer *ring, u32 seqno)
1694static void gen6_bsd_ring_write_tail(struct intel_ring_buffer *ring, 1708static void gen6_bsd_ring_write_tail(struct intel_ring_buffer *ring,
1695 u32 value) 1709 u32 value)
1696{ 1710{
1697 drm_i915_private_t *dev_priv = ring->dev->dev_private; 1711 struct drm_i915_private *dev_priv = ring->dev->dev_private;
1698 1712
1699 /* Every tail move must follow the sequence below */ 1713 /* Every tail move must follow the sequence below */
1700 1714
@@ -1869,7 +1883,7 @@ static int gen6_ring_flush(struct intel_ring_buffer *ring,
1869 1883
1870int intel_init_render_ring_buffer(struct drm_device *dev) 1884int intel_init_render_ring_buffer(struct drm_device *dev)
1871{ 1885{
1872 drm_i915_private_t *dev_priv = dev->dev_private; 1886 struct drm_i915_private *dev_priv = dev->dev_private;
1873 struct intel_ring_buffer *ring = &dev_priv->ring[RCS]; 1887 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
1874 1888
1875 ring->name = "render ring"; 1889 ring->name = "render ring";
@@ -1954,7 +1968,7 @@ int intel_init_render_ring_buffer(struct drm_device *dev)
1954 return -ENOMEM; 1968 return -ENOMEM;
1955 } 1969 }
1956 1970
1957 ret = i915_gem_obj_ggtt_pin(obj, 0, true, false); 1971 ret = i915_gem_obj_ggtt_pin(obj, 0, 0);
1958 if (ret != 0) { 1972 if (ret != 0) {
1959 drm_gem_object_unreference(&obj->base); 1973 drm_gem_object_unreference(&obj->base);
1960 DRM_ERROR("Failed to ping batch bo\n"); 1974 DRM_ERROR("Failed to ping batch bo\n");
@@ -1970,7 +1984,7 @@ int intel_init_render_ring_buffer(struct drm_device *dev)
1970 1984
1971int intel_render_ring_init_dri(struct drm_device *dev, u64 start, u32 size) 1985int intel_render_ring_init_dri(struct drm_device *dev, u64 start, u32 size)
1972{ 1986{
1973 drm_i915_private_t *dev_priv = dev->dev_private; 1987 struct drm_i915_private *dev_priv = dev->dev_private;
1974 struct intel_ring_buffer *ring = &dev_priv->ring[RCS]; 1988 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
1975 int ret; 1989 int ret;
1976 1990
@@ -2038,7 +2052,7 @@ int intel_render_ring_init_dri(struct drm_device *dev, u64 start, u32 size)
2038 2052
2039int intel_init_bsd_ring_buffer(struct drm_device *dev) 2053int intel_init_bsd_ring_buffer(struct drm_device *dev)
2040{ 2054{
2041 drm_i915_private_t *dev_priv = dev->dev_private; 2055 struct drm_i915_private *dev_priv = dev->dev_private;
2042 struct intel_ring_buffer *ring = &dev_priv->ring[VCS]; 2056 struct intel_ring_buffer *ring = &dev_priv->ring[VCS];
2043 2057
2044 ring->name = "bsd ring"; 2058 ring->name = "bsd ring";
@@ -2101,7 +2115,7 @@ int intel_init_bsd_ring_buffer(struct drm_device *dev)
2101 2115
2102int intel_init_blt_ring_buffer(struct drm_device *dev) 2116int intel_init_blt_ring_buffer(struct drm_device *dev)
2103{ 2117{
2104 drm_i915_private_t *dev_priv = dev->dev_private; 2118 struct drm_i915_private *dev_priv = dev->dev_private;
2105 struct intel_ring_buffer *ring = &dev_priv->ring[BCS]; 2119 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
2106 2120
2107 ring->name = "blitter ring"; 2121 ring->name = "blitter ring";
@@ -2141,7 +2155,7 @@ int intel_init_blt_ring_buffer(struct drm_device *dev)
2141 2155
2142int intel_init_vebox_ring_buffer(struct drm_device *dev) 2156int intel_init_vebox_ring_buffer(struct drm_device *dev)
2143{ 2157{
2144 drm_i915_private_t *dev_priv = dev->dev_private; 2158 struct drm_i915_private *dev_priv = dev->dev_private;
2145 struct intel_ring_buffer *ring = &dev_priv->ring[VECS]; 2159 struct intel_ring_buffer *ring = &dev_priv->ring[VECS];
2146 2160
2147 ring->name = "video enhancement ring"; 2161 ring->name = "video enhancement ring";