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path: root/drivers/gpu/drm/i915/intel_ringbuffer.c
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Diffstat (limited to 'drivers/gpu/drm/i915/intel_ringbuffer.c')
-rw-r--r--drivers/gpu/drm/i915/intel_ringbuffer.c39
1 files changed, 22 insertions, 17 deletions
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index ea81b541ce0b..e0c7bf27eafd 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -663,18 +663,28 @@ static void render_ring_cleanup(struct intel_ring_buffer *ring)
663 ring->scratch.obj = NULL; 663 ring->scratch.obj = NULL;
664} 664}
665 665
666static void gen6_signal(struct intel_ring_buffer *signaller) 666static int gen6_signal(struct intel_ring_buffer *signaller,
667 unsigned int num_dwords)
667{ 668{
668 struct drm_i915_private *dev_priv = signaller->dev->dev_private; 669 struct drm_device *dev = signaller->dev;
670 struct drm_i915_private *dev_priv = dev->dev_private;
669 struct intel_ring_buffer *useless; 671 struct intel_ring_buffer *useless;
670 int i; 672 int i, ret;
671 673
672/* NB: In order to be able to do semaphore MBOX updates for varying number 674 /* NB: In order to be able to do semaphore MBOX updates for varying
673 * of rings, it's easiest if we round up each individual update to a 675 * number of rings, it's easiest if we round up each individual update
674 * multiple of 2 (since ring updates must always be a multiple of 2) 676 * to a multiple of 2 (since ring updates must always be a multiple of
675 * even though the actual update only requires 3 dwords. 677 * 2) even though the actual update only requires 3 dwords.
676 */ 678 */
677#define MBOX_UPDATE_DWORDS 4 679#define MBOX_UPDATE_DWORDS 4
680 if (i915_semaphore_is_enabled(dev))
681 num_dwords += ((I915_NUM_RINGS-1) * MBOX_UPDATE_DWORDS);
682
683 ret = intel_ring_begin(signaller, num_dwords);
684 if (ret)
685 return ret;
686#undef MBOX_UPDATE_DWORDS
687
678 for_each_ring(useless, dev_priv, i) { 688 for_each_ring(useless, dev_priv, i) {
679 u32 mbox_reg = signaller->semaphore.mbox.signal[i]; 689 u32 mbox_reg = signaller->semaphore.mbox.signal[i];
680 if (mbox_reg != GEN6_NOSYNC) { 690 if (mbox_reg != GEN6_NOSYNC) {
@@ -689,6 +699,8 @@ static void gen6_signal(struct intel_ring_buffer *signaller)
689 intel_ring_emit(signaller, MI_NOOP); 699 intel_ring_emit(signaller, MI_NOOP);
690 } 700 }
691 } 701 }
702
703 return 0;
692} 704}
693 705
694/** 706/**
@@ -703,19 +715,12 @@ static void gen6_signal(struct intel_ring_buffer *signaller)
703static int 715static int
704gen6_add_request(struct intel_ring_buffer *ring) 716gen6_add_request(struct intel_ring_buffer *ring)
705{ 717{
706 struct drm_device *dev = ring->dev; 718 int ret;
707 int ret, num_dwords = 4;
708
709 if (i915_semaphore_is_enabled(dev))
710 num_dwords += ((I915_NUM_RINGS-1) * MBOX_UPDATE_DWORDS);
711#undef MBOX_UPDATE_DWORDS
712 719
713 ret = intel_ring_begin(ring, num_dwords); 720 ret = ring->semaphore.signal(ring, 4);
714 if (ret) 721 if (ret)
715 return ret; 722 return ret;
716 723
717 ring->semaphore.signal(ring);
718
719 intel_ring_emit(ring, MI_STORE_DWORD_INDEX); 724 intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
720 intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT); 725 intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
721 intel_ring_emit(ring, ring->outstanding_lazy_seqno); 726 intel_ring_emit(ring, ring->outstanding_lazy_seqno);