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path: root/drivers/gpu/drm/i915/intel_pm.c
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Diffstat (limited to 'drivers/gpu/drm/i915/intel_pm.c')
-rw-r--r--drivers/gpu/drm/i915/intel_pm.c23
1 files changed, 10 insertions, 13 deletions
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index d1e53abec1b5..54242e4f6f4c 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -511,8 +511,7 @@ void intel_update_fbc(struct drm_device *dev)
511 obj = intel_fb->obj; 511 obj = intel_fb->obj;
512 adjusted_mode = &intel_crtc->config.adjusted_mode; 512 adjusted_mode = &intel_crtc->config.adjusted_mode;
513 513
514 if (i915.enable_fbc < 0 && 514 if (i915.enable_fbc < 0) {
515 INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) {
516 if (set_no_fbc_reason(dev_priv, FBC_CHIP_DEFAULT)) 515 if (set_no_fbc_reason(dev_priv, FBC_CHIP_DEFAULT))
517 DRM_DEBUG_KMS("disabled per chip default\n"); 516 DRM_DEBUG_KMS("disabled per chip default\n");
518 goto out_disable; 517 goto out_disable;
@@ -3506,15 +3505,11 @@ static void gen8_enable_rps(struct drm_device *dev)
3506 3505
3507 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10); 3506 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
3508 3507
3509 /* WaDisablePwrmtrEvent:chv (pre-production hw) */
3510 I915_WRITE(0xA80C, I915_READ(0xA80C) & 0x00ffffff);
3511 I915_WRITE(0xA810, I915_READ(0xA810) & 0xffffff00);
3512
3513 /* 5: Enable RPS */ 3508 /* 5: Enable RPS */
3514 I915_WRITE(GEN6_RP_CONTROL, 3509 I915_WRITE(GEN6_RP_CONTROL,
3515 GEN6_RP_MEDIA_TURBO | 3510 GEN6_RP_MEDIA_TURBO |
3516 GEN6_RP_MEDIA_HW_NORMAL_MODE | 3511 GEN6_RP_MEDIA_HW_NORMAL_MODE |
3517 GEN6_RP_MEDIA_IS_GFX | /* WaSetMaskForGfxBusyness:chv (pre-production hw ?) */ 3512 GEN6_RP_MEDIA_IS_GFX |
3518 GEN6_RP_ENABLE | 3513 GEN6_RP_ENABLE |
3519 GEN6_RP_UP_BUSY_AVG | 3514 GEN6_RP_UP_BUSY_AVG |
3520 GEN6_RP_DOWN_IDLE_AVG); 3515 GEN6_RP_DOWN_IDLE_AVG);
@@ -6024,30 +6019,32 @@ void intel_display_power_put(struct drm_i915_private *dev_priv,
6024static struct i915_power_domains *hsw_pwr; 6019static struct i915_power_domains *hsw_pwr;
6025 6020
6026/* Display audio driver power well request */ 6021/* Display audio driver power well request */
6027void i915_request_power_well(void) 6022int i915_request_power_well(void)
6028{ 6023{
6029 struct drm_i915_private *dev_priv; 6024 struct drm_i915_private *dev_priv;
6030 6025
6031 if (WARN_ON(!hsw_pwr)) 6026 if (!hsw_pwr)
6032 return; 6027 return -ENODEV;
6033 6028
6034 dev_priv = container_of(hsw_pwr, struct drm_i915_private, 6029 dev_priv = container_of(hsw_pwr, struct drm_i915_private,
6035 power_domains); 6030 power_domains);
6036 intel_display_power_get(dev_priv, POWER_DOMAIN_AUDIO); 6031 intel_display_power_get(dev_priv, POWER_DOMAIN_AUDIO);
6032 return 0;
6037} 6033}
6038EXPORT_SYMBOL_GPL(i915_request_power_well); 6034EXPORT_SYMBOL_GPL(i915_request_power_well);
6039 6035
6040/* Display audio driver power well release */ 6036/* Display audio driver power well release */
6041void i915_release_power_well(void) 6037int i915_release_power_well(void)
6042{ 6038{
6043 struct drm_i915_private *dev_priv; 6039 struct drm_i915_private *dev_priv;
6044 6040
6045 if (WARN_ON(!hsw_pwr)) 6041 if (!hsw_pwr)
6046 return; 6042 return -ENODEV;
6047 6043
6048 dev_priv = container_of(hsw_pwr, struct drm_i915_private, 6044 dev_priv = container_of(hsw_pwr, struct drm_i915_private,
6049 power_domains); 6045 power_domains);
6050 intel_display_power_put(dev_priv, POWER_DOMAIN_AUDIO); 6046 intel_display_power_put(dev_priv, POWER_DOMAIN_AUDIO);
6047 return 0;
6051} 6048}
6052EXPORT_SYMBOL_GPL(i915_release_power_well); 6049EXPORT_SYMBOL_GPL(i915_release_power_well);
6053 6050