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path: root/drivers/gpu/drm/i915/intel_pm.c
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Diffstat (limited to 'drivers/gpu/drm/i915/intel_pm.c')
-rw-r--r--drivers/gpu/drm/i915/intel_pm.c5
1 files changed, 4 insertions, 1 deletions
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 61fee7fcdc2c..adca00783e61 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -2574,7 +2574,7 @@ static void gen6_enable_rps(struct drm_device *dev)
2574 I915_WRITE(GEN6_RC_SLEEP, 0); 2574 I915_WRITE(GEN6_RC_SLEEP, 0);
2575 I915_WRITE(GEN6_RC1e_THRESHOLD, 1000); 2575 I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
2576 I915_WRITE(GEN6_RC6_THRESHOLD, 50000); 2576 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
2577 I915_WRITE(GEN6_RC6p_THRESHOLD, 100000); 2577 I915_WRITE(GEN6_RC6p_THRESHOLD, 150000);
2578 I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */ 2578 I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
2579 2579
2580 /* Check if we are enabling RC6 */ 2580 /* Check if we are enabling RC6 */
@@ -4079,6 +4079,9 @@ void intel_set_power_well(struct drm_device *dev, bool enable)
4079 if (!IS_HASWELL(dev)) 4079 if (!IS_HASWELL(dev))
4080 return; 4080 return;
4081 4081
4082 if (!i915_disable_power_well && !enable)
4083 return;
4084
4082 tmp = I915_READ(HSW_PWR_WELL_DRIVER); 4085 tmp = I915_READ(HSW_PWR_WELL_DRIVER);
4083 is_enabled = tmp & HSW_PWR_WELL_STATE; 4086 is_enabled = tmp & HSW_PWR_WELL_STATE;
4084 enable_requested = tmp & HSW_PWR_WELL_ENABLE; 4087 enable_requested = tmp & HSW_PWR_WELL_ENABLE;