1 files changed, 29 insertions, 0 deletions

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 9ad0c6afc487..ee72807069e4 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3209,6 +3209,14 @@ void gen6_set_rps(struct drm_device *dev, u8 val)
 */
 static void vlv_set_rps_idle(struct drm_i915_private *dev_priv)
 {
+        struct drm_device *dev = dev_priv->dev;
+
+        /* Latest VLV doesn't need to force the gfx clock */
+        if (dev->pdev->revision >= 0xd) {
+                valleyview_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit);
+                return;
+        }
+
         /*
          * When we are idle.  Drop to min voltage state.
          */
@@ -6038,6 +6046,27 @@ int i915_release_power_well(void)
 }
 EXPORT_SYMBOL_GPL(i915_release_power_well);
 
+/*
+ * Private interface for the audio driver to get CDCLK in kHz.
+ *
+ * Caller must request power well using i915_request_power_well() prior to
+ * making the call.
+ */
+int i915_get_cdclk_freq(void)
+{
+        struct drm_i915_private *dev_priv;
+
+        if (!hsw_pwr)
+                return -ENODEV;
+
+        dev_priv = container_of(hsw_pwr, struct drm_i915_private,
+                                power_domains);
+
+        return intel_ddi_get_cdclk_freq(dev_priv);
+}
+EXPORT_SYMBOL_GPL(i915_get_cdclk_freq);
+
+
 #define POWER_DOMAIN_MASK (BIT(POWER_DOMAIN_NUM) - 1)
 
 #define HSW_ALWAYS_ON_POWER_DOMAINS (                   \