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path: root/drivers/gpu/drm/i915/intel_pm.c
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Diffstat (limited to 'drivers/gpu/drm/i915/intel_pm.c')
-rw-r--r--drivers/gpu/drm/i915/intel_pm.c1202
1 files changed, 826 insertions, 376 deletions
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index e1fc35a72656..5874716774a7 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -92,12 +92,12 @@ static void i8xx_enable_fbc(struct drm_crtc *crtc)
92{ 92{
93 struct drm_device *dev = crtc->dev; 93 struct drm_device *dev = crtc->dev;
94 struct drm_i915_private *dev_priv = dev->dev_private; 94 struct drm_i915_private *dev_priv = dev->dev_private;
95 struct drm_framebuffer *fb = crtc->fb; 95 struct drm_framebuffer *fb = crtc->primary->fb;
96 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); 96 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
97 struct drm_i915_gem_object *obj = intel_fb->obj; 97 struct drm_i915_gem_object *obj = intel_fb->obj;
98 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 98 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
99 int cfb_pitch; 99 int cfb_pitch;
100 int plane, i; 100 int i;
101 u32 fbc_ctl; 101 u32 fbc_ctl;
102 102
103 cfb_pitch = dev_priv->fbc.size / FBC_LL_SIZE; 103 cfb_pitch = dev_priv->fbc.size / FBC_LL_SIZE;
@@ -109,7 +109,6 @@ static void i8xx_enable_fbc(struct drm_crtc *crtc)
109 cfb_pitch = (cfb_pitch / 32) - 1; 109 cfb_pitch = (cfb_pitch / 32) - 1;
110 else 110 else
111 cfb_pitch = (cfb_pitch / 64) - 1; 111 cfb_pitch = (cfb_pitch / 64) - 1;
112 plane = intel_crtc->plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
113 112
114 /* Clear old tags */ 113 /* Clear old tags */
115 for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++) 114 for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
@@ -120,7 +119,7 @@ static void i8xx_enable_fbc(struct drm_crtc *crtc)
120 119
121 /* Set it up... */ 120 /* Set it up... */
122 fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE; 121 fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE;
123 fbc_ctl2 |= plane; 122 fbc_ctl2 |= FBC_CTL_PLANE(intel_crtc->plane);
124 I915_WRITE(FBC_CONTROL2, fbc_ctl2); 123 I915_WRITE(FBC_CONTROL2, fbc_ctl2);
125 I915_WRITE(FBC_FENCE_OFF, crtc->y); 124 I915_WRITE(FBC_FENCE_OFF, crtc->y);
126 } 125 }
@@ -135,7 +134,7 @@ static void i8xx_enable_fbc(struct drm_crtc *crtc)
135 fbc_ctl |= obj->fence_reg; 134 fbc_ctl |= obj->fence_reg;
136 I915_WRITE(FBC_CONTROL, fbc_ctl); 135 I915_WRITE(FBC_CONTROL, fbc_ctl);
137 136
138 DRM_DEBUG_KMS("enabled FBC, pitch %d, yoff %d, plane %c, ", 137 DRM_DEBUG_KMS("enabled FBC, pitch %d, yoff %d, plane %c\n",
139 cfb_pitch, crtc->y, plane_name(intel_crtc->plane)); 138 cfb_pitch, crtc->y, plane_name(intel_crtc->plane));
140} 139}
141 140
@@ -150,21 +149,23 @@ static void g4x_enable_fbc(struct drm_crtc *crtc)
150{ 149{
151 struct drm_device *dev = crtc->dev; 150 struct drm_device *dev = crtc->dev;
152 struct drm_i915_private *dev_priv = dev->dev_private; 151 struct drm_i915_private *dev_priv = dev->dev_private;
153 struct drm_framebuffer *fb = crtc->fb; 152 struct drm_framebuffer *fb = crtc->primary->fb;
154 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); 153 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
155 struct drm_i915_gem_object *obj = intel_fb->obj; 154 struct drm_i915_gem_object *obj = intel_fb->obj;
156 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 155 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
157 int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
158 u32 dpfc_ctl; 156 u32 dpfc_ctl;
159 157
160 dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X; 158 dpfc_ctl = DPFC_CTL_PLANE(intel_crtc->plane) | DPFC_SR_EN;
159 if (drm_format_plane_cpp(fb->pixel_format, 0) == 2)
160 dpfc_ctl |= DPFC_CTL_LIMIT_2X;
161 else
162 dpfc_ctl |= DPFC_CTL_LIMIT_1X;
161 dpfc_ctl |= DPFC_CTL_FENCE_EN | obj->fence_reg; 163 dpfc_ctl |= DPFC_CTL_FENCE_EN | obj->fence_reg;
162 I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
163 164
164 I915_WRITE(DPFC_FENCE_YOFF, crtc->y); 165 I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
165 166
166 /* enable it... */ 167 /* enable it... */
167 I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN); 168 I915_WRITE(DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
168 169
169 DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane)); 170 DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane));
170} 171}
@@ -220,22 +221,20 @@ static void ironlake_enable_fbc(struct drm_crtc *crtc)
220{ 221{
221 struct drm_device *dev = crtc->dev; 222 struct drm_device *dev = crtc->dev;
222 struct drm_i915_private *dev_priv = dev->dev_private; 223 struct drm_i915_private *dev_priv = dev->dev_private;
223 struct drm_framebuffer *fb = crtc->fb; 224 struct drm_framebuffer *fb = crtc->primary->fb;
224 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); 225 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
225 struct drm_i915_gem_object *obj = intel_fb->obj; 226 struct drm_i915_gem_object *obj = intel_fb->obj;
226 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 227 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
227 int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
228 u32 dpfc_ctl; 228 u32 dpfc_ctl;
229 229
230 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL); 230 dpfc_ctl = DPFC_CTL_PLANE(intel_crtc->plane);
231 dpfc_ctl &= DPFC_RESERVED; 231 if (drm_format_plane_cpp(fb->pixel_format, 0) == 2)
232 dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X); 232 dpfc_ctl |= DPFC_CTL_LIMIT_2X;
233 /* Set persistent mode for front-buffer rendering, ala X. */ 233 else
234 dpfc_ctl |= DPFC_CTL_PERSISTENT_MODE; 234 dpfc_ctl |= DPFC_CTL_LIMIT_1X;
235 dpfc_ctl |= DPFC_CTL_FENCE_EN; 235 dpfc_ctl |= DPFC_CTL_FENCE_EN;
236 if (IS_GEN5(dev)) 236 if (IS_GEN5(dev))
237 dpfc_ctl |= obj->fence_reg; 237 dpfc_ctl |= obj->fence_reg;
238 I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY);
239 238
240 I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y); 239 I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
241 I915_WRITE(ILK_FBC_RT_BASE, i915_gem_obj_ggtt_offset(obj) | ILK_FBC_RT_VALID); 240 I915_WRITE(ILK_FBC_RT_BASE, i915_gem_obj_ggtt_offset(obj) | ILK_FBC_RT_VALID);
@@ -278,24 +277,31 @@ static void gen7_enable_fbc(struct drm_crtc *crtc)
278{ 277{
279 struct drm_device *dev = crtc->dev; 278 struct drm_device *dev = crtc->dev;
280 struct drm_i915_private *dev_priv = dev->dev_private; 279 struct drm_i915_private *dev_priv = dev->dev_private;
281 struct drm_framebuffer *fb = crtc->fb; 280 struct drm_framebuffer *fb = crtc->primary->fb;
282 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); 281 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
283 struct drm_i915_gem_object *obj = intel_fb->obj; 282 struct drm_i915_gem_object *obj = intel_fb->obj;
284 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 283 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
284 u32 dpfc_ctl;
285 285
286 I915_WRITE(IVB_FBC_RT_BASE, i915_gem_obj_ggtt_offset(obj)); 286 dpfc_ctl = IVB_DPFC_CTL_PLANE(intel_crtc->plane);
287 if (drm_format_plane_cpp(fb->pixel_format, 0) == 2)
288 dpfc_ctl |= DPFC_CTL_LIMIT_2X;
289 else
290 dpfc_ctl |= DPFC_CTL_LIMIT_1X;
291 dpfc_ctl |= IVB_DPFC_CTL_FENCE_EN;
287 292
288 I915_WRITE(ILK_DPFC_CONTROL, DPFC_CTL_EN | DPFC_CTL_LIMIT_1X | 293 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
289 IVB_DPFC_CTL_FENCE_EN |
290 intel_crtc->plane << IVB_DPFC_CTL_PLANE_SHIFT);
291 294
292 if (IS_IVYBRIDGE(dev)) { 295 if (IS_IVYBRIDGE(dev)) {
293 /* WaFbcAsynchFlipDisableFbcQueue:ivb */ 296 /* WaFbcAsynchFlipDisableFbcQueue:ivb */
294 I915_WRITE(ILK_DISPLAY_CHICKEN1, ILK_FBCQ_DIS); 297 I915_WRITE(ILK_DISPLAY_CHICKEN1,
298 I915_READ(ILK_DISPLAY_CHICKEN1) |
299 ILK_FBCQ_DIS);
295 } else { 300 } else {
296 /* WaFbcAsynchFlipDisableFbcQueue:hsw */ 301 /* WaFbcAsynchFlipDisableFbcQueue:hsw,bdw */
297 I915_WRITE(HSW_PIPE_SLICE_CHICKEN_1(intel_crtc->pipe), 302 I915_WRITE(CHICKEN_PIPESL_1(intel_crtc->pipe),
298 HSW_BYPASS_FBC_QUEUE); 303 I915_READ(CHICKEN_PIPESL_1(intel_crtc->pipe)) |
304 HSW_FBCQ_DIS);
299 } 305 }
300 306
301 I915_WRITE(SNB_DPFC_CTL_SA, 307 I915_WRITE(SNB_DPFC_CTL_SA,
@@ -330,11 +336,11 @@ static void intel_fbc_work_fn(struct work_struct *__work)
330 /* Double check that we haven't switched fb without cancelling 336 /* Double check that we haven't switched fb without cancelling
331 * the prior work. 337 * the prior work.
332 */ 338 */
333 if (work->crtc->fb == work->fb) { 339 if (work->crtc->primary->fb == work->fb) {
334 dev_priv->display.enable_fbc(work->crtc); 340 dev_priv->display.enable_fbc(work->crtc);
335 341
336 dev_priv->fbc.plane = to_intel_crtc(work->crtc)->plane; 342 dev_priv->fbc.plane = to_intel_crtc(work->crtc)->plane;
337 dev_priv->fbc.fb_id = work->crtc->fb->base.id; 343 dev_priv->fbc.fb_id = work->crtc->primary->fb->base.id;
338 dev_priv->fbc.y = work->crtc->y; 344 dev_priv->fbc.y = work->crtc->y;
339 } 345 }
340 346
@@ -387,7 +393,7 @@ static void intel_enable_fbc(struct drm_crtc *crtc)
387 } 393 }
388 394
389 work->crtc = crtc; 395 work->crtc = crtc;
390 work->fb = crtc->fb; 396 work->fb = crtc->primary->fb;
391 INIT_DELAYED_WORK(&work->work, intel_fbc_work_fn); 397 INIT_DELAYED_WORK(&work->work, intel_fbc_work_fn);
392 398
393 dev_priv->fbc.fbc_work = work; 399 dev_priv->fbc.fbc_work = work;
@@ -466,7 +472,7 @@ void intel_update_fbc(struct drm_device *dev)
466 return; 472 return;
467 } 473 }
468 474
469 if (!i915_powersave) { 475 if (!i915.powersave) {
470 if (set_no_fbc_reason(dev_priv, FBC_MODULE_PARAM)) 476 if (set_no_fbc_reason(dev_priv, FBC_MODULE_PARAM))
471 DRM_DEBUG_KMS("fbc disabled per module param\n"); 477 DRM_DEBUG_KMS("fbc disabled per module param\n");
472 return; 478 return;
@@ -493,25 +499,25 @@ void intel_update_fbc(struct drm_device *dev)
493 } 499 }
494 } 500 }
495 501
496 if (!crtc || crtc->fb == NULL) { 502 if (!crtc || crtc->primary->fb == NULL) {
497 if (set_no_fbc_reason(dev_priv, FBC_NO_OUTPUT)) 503 if (set_no_fbc_reason(dev_priv, FBC_NO_OUTPUT))
498 DRM_DEBUG_KMS("no output, disabling\n"); 504 DRM_DEBUG_KMS("no output, disabling\n");
499 goto out_disable; 505 goto out_disable;
500 } 506 }
501 507
502 intel_crtc = to_intel_crtc(crtc); 508 intel_crtc = to_intel_crtc(crtc);
503 fb = crtc->fb; 509 fb = crtc->primary->fb;
504 intel_fb = to_intel_framebuffer(fb); 510 intel_fb = to_intel_framebuffer(fb);
505 obj = intel_fb->obj; 511 obj = intel_fb->obj;
506 adjusted_mode = &intel_crtc->config.adjusted_mode; 512 adjusted_mode = &intel_crtc->config.adjusted_mode;
507 513
508 if (i915_enable_fbc < 0 && 514 if (i915.enable_fbc < 0 &&
509 INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) { 515 INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) {
510 if (set_no_fbc_reason(dev_priv, FBC_CHIP_DEFAULT)) 516 if (set_no_fbc_reason(dev_priv, FBC_CHIP_DEFAULT))
511 DRM_DEBUG_KMS("disabled per chip default\n"); 517 DRM_DEBUG_KMS("disabled per chip default\n");
512 goto out_disable; 518 goto out_disable;
513 } 519 }
514 if (!i915_enable_fbc) { 520 if (!i915.enable_fbc) {
515 if (set_no_fbc_reason(dev_priv, FBC_MODULE_PARAM)) 521 if (set_no_fbc_reason(dev_priv, FBC_MODULE_PARAM))
516 DRM_DEBUG_KMS("fbc disabled per module param\n"); 522 DRM_DEBUG_KMS("fbc disabled per module param\n");
517 goto out_disable; 523 goto out_disable;
@@ -537,7 +543,7 @@ void intel_update_fbc(struct drm_device *dev)
537 DRM_DEBUG_KMS("mode too large for compression, disabling\n"); 543 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
538 goto out_disable; 544 goto out_disable;
539 } 545 }
540 if ((INTEL_INFO(dev)->gen < 4 || IS_HASWELL(dev)) && 546 if ((INTEL_INFO(dev)->gen < 4 || HAS_DDI(dev)) &&
541 intel_crtc->plane != PLANE_A) { 547 intel_crtc->plane != PLANE_A) {
542 if (set_no_fbc_reason(dev_priv, FBC_BAD_PLANE)) 548 if (set_no_fbc_reason(dev_priv, FBC_BAD_PLANE))
543 DRM_DEBUG_KMS("plane not A, disabling compression\n"); 549 DRM_DEBUG_KMS("plane not A, disabling compression\n");
@@ -617,7 +623,7 @@ out_disable:
617 623
618static void i915_pineview_get_mem_freq(struct drm_device *dev) 624static void i915_pineview_get_mem_freq(struct drm_device *dev)
619{ 625{
620 drm_i915_private_t *dev_priv = dev->dev_private; 626 struct drm_i915_private *dev_priv = dev->dev_private;
621 u32 tmp; 627 u32 tmp;
622 628
623 tmp = I915_READ(CLKCFG); 629 tmp = I915_READ(CLKCFG);
@@ -656,7 +662,7 @@ static void i915_pineview_get_mem_freq(struct drm_device *dev)
656 662
657static void i915_ironlake_get_mem_freq(struct drm_device *dev) 663static void i915_ironlake_get_mem_freq(struct drm_device *dev)
658{ 664{
659 drm_i915_private_t *dev_priv = dev->dev_private; 665 struct drm_i915_private *dev_priv = dev->dev_private;
660 u16 ddrpll, csipll; 666 u16 ddrpll, csipll;
661 667
662 ddrpll = I915_READ16(DDRMPLL1); 668 ddrpll = I915_READ16(DDRMPLL1);
@@ -1035,7 +1041,7 @@ static void pineview_update_wm(struct drm_crtc *unused_crtc)
1035 crtc = single_enabled_crtc(dev); 1041 crtc = single_enabled_crtc(dev);
1036 if (crtc) { 1042 if (crtc) {
1037 const struct drm_display_mode *adjusted_mode; 1043 const struct drm_display_mode *adjusted_mode;
1038 int pixel_size = crtc->fb->bits_per_pixel / 8; 1044 int pixel_size = crtc->primary->fb->bits_per_pixel / 8;
1039 int clock; 1045 int clock;
1040 1046
1041 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode; 1047 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
@@ -1115,7 +1121,7 @@ static bool g4x_compute_wm0(struct drm_device *dev,
1115 clock = adjusted_mode->crtc_clock; 1121 clock = adjusted_mode->crtc_clock;
1116 htotal = adjusted_mode->crtc_htotal; 1122 htotal = adjusted_mode->crtc_htotal;
1117 hdisplay = to_intel_crtc(crtc)->config.pipe_src_w; 1123 hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
1118 pixel_size = crtc->fb->bits_per_pixel / 8; 1124 pixel_size = crtc->primary->fb->bits_per_pixel / 8;
1119 1125
1120 /* Use the small buffer method to calculate plane watermark */ 1126 /* Use the small buffer method to calculate plane watermark */
1121 entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000; 1127 entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
@@ -1128,9 +1134,9 @@ static bool g4x_compute_wm0(struct drm_device *dev,
1128 *plane_wm = display->max_wm; 1134 *plane_wm = display->max_wm;
1129 1135
1130 /* Use the large buffer method to calculate cursor watermark */ 1136 /* Use the large buffer method to calculate cursor watermark */
1131 line_time_us = ((htotal * 1000) / clock); 1137 line_time_us = max(htotal * 1000 / clock, 1);
1132 line_count = (cursor_latency_ns / line_time_us + 1000) / 1000; 1138 line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
1133 entries = line_count * 64 * pixel_size; 1139 entries = line_count * to_intel_crtc(crtc)->cursor_width * pixel_size;
1134 tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8; 1140 tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
1135 if (tlb_miss > 0) 1141 if (tlb_miss > 0)
1136 entries += tlb_miss; 1142 entries += tlb_miss;
@@ -1202,9 +1208,9 @@ static bool g4x_compute_srwm(struct drm_device *dev,
1202 clock = adjusted_mode->crtc_clock; 1208 clock = adjusted_mode->crtc_clock;
1203 htotal = adjusted_mode->crtc_htotal; 1209 htotal = adjusted_mode->crtc_htotal;
1204 hdisplay = to_intel_crtc(crtc)->config.pipe_src_w; 1210 hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
1205 pixel_size = crtc->fb->bits_per_pixel / 8; 1211 pixel_size = crtc->primary->fb->bits_per_pixel / 8;
1206 1212
1207 line_time_us = (htotal * 1000) / clock; 1213 line_time_us = max(htotal * 1000 / clock, 1);
1208 line_count = (latency_ns / line_time_us + 1000) / 1000; 1214 line_count = (latency_ns / line_time_us + 1000) / 1000;
1209 line_size = hdisplay * pixel_size; 1215 line_size = hdisplay * pixel_size;
1210 1216
@@ -1216,7 +1222,7 @@ static bool g4x_compute_srwm(struct drm_device *dev,
1216 *display_wm = entries + display->guard_size; 1222 *display_wm = entries + display->guard_size;
1217 1223
1218 /* calculate the self-refresh watermark for display cursor */ 1224 /* calculate the self-refresh watermark for display cursor */
1219 entries = line_count * pixel_size * 64; 1225 entries = line_count * pixel_size * to_intel_crtc(crtc)->cursor_width;
1220 entries = DIV_ROUND_UP(entries, cursor->cacheline_size); 1226 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1221 *cursor_wm = entries + cursor->guard_size; 1227 *cursor_wm = entries + cursor->guard_size;
1222 1228
@@ -1241,7 +1247,7 @@ static bool vlv_compute_drain_latency(struct drm_device *dev,
1241 return false; 1247 return false;
1242 1248
1243 clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock; 1249 clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
1244 pixel_size = crtc->fb->bits_per_pixel / 8; /* BPP */ 1250 pixel_size = crtc->primary->fb->bits_per_pixel / 8; /* BPP */
1245 1251
1246 entries = (clock / 1000) * pixel_size; 1252 entries = (clock / 1000) * pixel_size;
1247 *plane_prec_mult = (entries > 256) ? 1253 *plane_prec_mult = (entries > 256) ?
@@ -1433,11 +1439,11 @@ static void i965_update_wm(struct drm_crtc *unused_crtc)
1433 int clock = adjusted_mode->crtc_clock; 1439 int clock = adjusted_mode->crtc_clock;
1434 int htotal = adjusted_mode->crtc_htotal; 1440 int htotal = adjusted_mode->crtc_htotal;
1435 int hdisplay = to_intel_crtc(crtc)->config.pipe_src_w; 1441 int hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
1436 int pixel_size = crtc->fb->bits_per_pixel / 8; 1442 int pixel_size = crtc->primary->fb->bits_per_pixel / 8;
1437 unsigned long line_time_us; 1443 unsigned long line_time_us;
1438 int entries; 1444 int entries;
1439 1445
1440 line_time_us = ((htotal * 1000) / clock); 1446 line_time_us = max(htotal * 1000 / clock, 1);
1441 1447
1442 /* Use ns/us then divide to preserve precision */ 1448 /* Use ns/us then divide to preserve precision */
1443 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) * 1449 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
@@ -1451,7 +1457,7 @@ static void i965_update_wm(struct drm_crtc *unused_crtc)
1451 entries, srwm); 1457 entries, srwm);
1452 1458
1453 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) * 1459 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1454 pixel_size * 64; 1460 pixel_size * to_intel_crtc(crtc)->cursor_width;
1455 entries = DIV_ROUND_UP(entries, 1461 entries = DIV_ROUND_UP(entries,
1456 i965_cursor_wm_info.cacheline_size); 1462 i965_cursor_wm_info.cacheline_size);
1457 cursor_sr = i965_cursor_wm_info.fifo_size - 1463 cursor_sr = i965_cursor_wm_info.fifo_size -
@@ -1506,7 +1512,7 @@ static void i9xx_update_wm(struct drm_crtc *unused_crtc)
1506 crtc = intel_get_crtc_for_plane(dev, 0); 1512 crtc = intel_get_crtc_for_plane(dev, 0);
1507 if (intel_crtc_active(crtc)) { 1513 if (intel_crtc_active(crtc)) {
1508 const struct drm_display_mode *adjusted_mode; 1514 const struct drm_display_mode *adjusted_mode;
1509 int cpp = crtc->fb->bits_per_pixel / 8; 1515 int cpp = crtc->primary->fb->bits_per_pixel / 8;
1510 if (IS_GEN2(dev)) 1516 if (IS_GEN2(dev))
1511 cpp = 4; 1517 cpp = 4;
1512 1518
@@ -1522,7 +1528,7 @@ static void i9xx_update_wm(struct drm_crtc *unused_crtc)
1522 crtc = intel_get_crtc_for_plane(dev, 1); 1528 crtc = intel_get_crtc_for_plane(dev, 1);
1523 if (intel_crtc_active(crtc)) { 1529 if (intel_crtc_active(crtc)) {
1524 const struct drm_display_mode *adjusted_mode; 1530 const struct drm_display_mode *adjusted_mode;
1525 int cpp = crtc->fb->bits_per_pixel / 8; 1531 int cpp = crtc->primary->fb->bits_per_pixel / 8;
1526 if (IS_GEN2(dev)) 1532 if (IS_GEN2(dev))
1527 cpp = 4; 1533 cpp = 4;
1528 1534
@@ -1559,11 +1565,11 @@ static void i9xx_update_wm(struct drm_crtc *unused_crtc)
1559 int clock = adjusted_mode->crtc_clock; 1565 int clock = adjusted_mode->crtc_clock;
1560 int htotal = adjusted_mode->crtc_htotal; 1566 int htotal = adjusted_mode->crtc_htotal;
1561 int hdisplay = to_intel_crtc(enabled)->config.pipe_src_w; 1567 int hdisplay = to_intel_crtc(enabled)->config.pipe_src_w;
1562 int pixel_size = enabled->fb->bits_per_pixel / 8; 1568 int pixel_size = enabled->primary->fb->bits_per_pixel / 8;
1563 unsigned long line_time_us; 1569 unsigned long line_time_us;
1564 int entries; 1570 int entries;
1565 1571
1566 line_time_us = (htotal * 1000) / clock; 1572 line_time_us = max(htotal * 1000 / clock, 1);
1567 1573
1568 /* Use ns/us then divide to preserve precision */ 1574 /* Use ns/us then divide to preserve precision */
1569 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) * 1575 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
@@ -1886,7 +1892,7 @@ static unsigned int ilk_cursor_wm_max(const struct drm_device *dev,
1886} 1892}
1887 1893
1888/* Calculate the maximum FBC watermark */ 1894/* Calculate the maximum FBC watermark */
1889static unsigned int ilk_fbc_wm_max(struct drm_device *dev) 1895static unsigned int ilk_fbc_wm_max(const struct drm_device *dev)
1890{ 1896{
1891 /* max that registers can hold */ 1897 /* max that registers can hold */
1892 if (INTEL_INFO(dev)->gen >= 8) 1898 if (INTEL_INFO(dev)->gen >= 8)
@@ -1895,7 +1901,7 @@ static unsigned int ilk_fbc_wm_max(struct drm_device *dev)
1895 return 15; 1901 return 15;
1896} 1902}
1897 1903
1898static void ilk_compute_wm_maximums(struct drm_device *dev, 1904static void ilk_compute_wm_maximums(const struct drm_device *dev,
1899 int level, 1905 int level,
1900 const struct intel_wm_config *config, 1906 const struct intel_wm_config *config,
1901 enum intel_ddb_partitioning ddb_partitioning, 1907 enum intel_ddb_partitioning ddb_partitioning,
@@ -1948,7 +1954,7 @@ static bool ilk_validate_wm_level(int level,
1948 return ret; 1954 return ret;
1949} 1955}
1950 1956
1951static void ilk_compute_wm_level(struct drm_i915_private *dev_priv, 1957static void ilk_compute_wm_level(const struct drm_i915_private *dev_priv,
1952 int level, 1958 int level,
1953 const struct ilk_pipe_wm_parameters *p, 1959 const struct ilk_pipe_wm_parameters *p,
1954 struct intel_wm_level *result) 1960 struct intel_wm_level *result)
@@ -2079,7 +2085,7 @@ static void intel_print_wm_latency(struct drm_device *dev,
2079 } 2085 }
2080} 2086}
2081 2087
2082static void intel_setup_wm_latency(struct drm_device *dev) 2088static void ilk_setup_wm_latency(struct drm_device *dev)
2083{ 2089{
2084 struct drm_i915_private *dev_priv = dev->dev_private; 2090 struct drm_i915_private *dev_priv = dev->dev_private;
2085 2091
@@ -2111,10 +2117,10 @@ static void ilk_compute_wm_parameters(struct drm_crtc *crtc,
2111 if (p->active) { 2117 if (p->active) {
2112 p->pipe_htotal = intel_crtc->config.adjusted_mode.crtc_htotal; 2118 p->pipe_htotal = intel_crtc->config.adjusted_mode.crtc_htotal;
2113 p->pixel_rate = ilk_pipe_pixel_rate(dev, crtc); 2119 p->pixel_rate = ilk_pipe_pixel_rate(dev, crtc);
2114 p->pri.bytes_per_pixel = crtc->fb->bits_per_pixel / 8; 2120 p->pri.bytes_per_pixel = crtc->primary->fb->bits_per_pixel / 8;
2115 p->cur.bytes_per_pixel = 4; 2121 p->cur.bytes_per_pixel = 4;
2116 p->pri.horiz_pixels = intel_crtc->config.pipe_src_w; 2122 p->pri.horiz_pixels = intel_crtc->config.pipe_src_w;
2117 p->cur.horiz_pixels = 64; 2123 p->cur.horiz_pixels = intel_crtc->cursor_width;
2118 /* TODO: for now, assume primary and cursor planes are always enabled. */ 2124 /* TODO: for now, assume primary and cursor planes are always enabled. */
2119 p->pri.enabled = true; 2125 p->pri.enabled = true;
2120 p->cur.enabled = true; 2126 p->cur.enabled = true;
@@ -2123,7 +2129,7 @@ static void ilk_compute_wm_parameters(struct drm_crtc *crtc,
2123 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) 2129 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
2124 config->num_pipes_active += intel_crtc_active(crtc); 2130 config->num_pipes_active += intel_crtc_active(crtc);
2125 2131
2126 list_for_each_entry(plane, &dev->mode_config.plane_list, head) { 2132 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
2127 struct intel_plane *intel_plane = to_intel_plane(plane); 2133 struct intel_plane *intel_plane = to_intel_plane(plane);
2128 2134
2129 if (intel_plane->pipe == pipe) 2135 if (intel_plane->pipe == pipe)
@@ -2140,7 +2146,7 @@ static bool intel_compute_pipe_wm(struct drm_crtc *crtc,
2140 struct intel_pipe_wm *pipe_wm) 2146 struct intel_pipe_wm *pipe_wm)
2141{ 2147{
2142 struct drm_device *dev = crtc->dev; 2148 struct drm_device *dev = crtc->dev;
2143 struct drm_i915_private *dev_priv = dev->dev_private; 2149 const struct drm_i915_private *dev_priv = dev->dev_private;
2144 int level, max_level = ilk_wm_max_level(dev); 2150 int level, max_level = ilk_wm_max_level(dev);
2145 /* LP0 watermark maximums depend on this pipe alone */ 2151 /* LP0 watermark maximums depend on this pipe alone */
2146 struct intel_wm_config config = { 2152 struct intel_wm_config config = {
@@ -2738,7 +2744,7 @@ intel_alloc_context_page(struct drm_device *dev)
2738 return NULL; 2744 return NULL;
2739 } 2745 }
2740 2746
2741 ret = i915_gem_obj_ggtt_pin(ctx, 4096, true, false); 2747 ret = i915_gem_obj_ggtt_pin(ctx, 4096, 0);
2742 if (ret) { 2748 if (ret) {
2743 DRM_ERROR("failed to pin power context: %d\n", ret); 2749 DRM_ERROR("failed to pin power context: %d\n", ret);
2744 goto err_unref; 2750 goto err_unref;
@@ -2753,7 +2759,7 @@ intel_alloc_context_page(struct drm_device *dev)
2753 return ctx; 2759 return ctx;
2754 2760
2755err_unpin: 2761err_unpin:
2756 i915_gem_object_unpin(ctx); 2762 i915_gem_object_ggtt_unpin(ctx);
2757err_unref: 2763err_unref:
2758 drm_gem_object_unreference(&ctx->base); 2764 drm_gem_object_unreference(&ctx->base);
2759 return NULL; 2765 return NULL;
@@ -2901,9 +2907,9 @@ static u32 gen6_rps_limits(struct drm_i915_private *dev_priv, u8 val)
2901 * the hw runs at the minimal clock before selecting the desired 2907 * the hw runs at the minimal clock before selecting the desired
2902 * frequency, if the down threshold expires in that window we will not 2908 * frequency, if the down threshold expires in that window we will not
2903 * receive a down interrupt. */ 2909 * receive a down interrupt. */
2904 limits = dev_priv->rps.max_delay << 24; 2910 limits = dev_priv->rps.max_freq_softlimit << 24;
2905 if (val <= dev_priv->rps.min_delay) 2911 if (val <= dev_priv->rps.min_freq_softlimit)
2906 limits |= dev_priv->rps.min_delay << 16; 2912 limits |= dev_priv->rps.min_freq_softlimit << 16;
2907 2913
2908 return limits; 2914 return limits;
2909} 2915}
@@ -2915,26 +2921,26 @@ static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val)
2915 new_power = dev_priv->rps.power; 2921 new_power = dev_priv->rps.power;
2916 switch (dev_priv->rps.power) { 2922 switch (dev_priv->rps.power) {
2917 case LOW_POWER: 2923 case LOW_POWER:
2918 if (val > dev_priv->rps.rpe_delay + 1 && val > dev_priv->rps.cur_delay) 2924 if (val > dev_priv->rps.efficient_freq + 1 && val > dev_priv->rps.cur_freq)
2919 new_power = BETWEEN; 2925 new_power = BETWEEN;
2920 break; 2926 break;
2921 2927
2922 case BETWEEN: 2928 case BETWEEN:
2923 if (val <= dev_priv->rps.rpe_delay && val < dev_priv->rps.cur_delay) 2929 if (val <= dev_priv->rps.efficient_freq && val < dev_priv->rps.cur_freq)
2924 new_power = LOW_POWER; 2930 new_power = LOW_POWER;
2925 else if (val >= dev_priv->rps.rp0_delay && val > dev_priv->rps.cur_delay) 2931 else if (val >= dev_priv->rps.rp0_freq && val > dev_priv->rps.cur_freq)
2926 new_power = HIGH_POWER; 2932 new_power = HIGH_POWER;
2927 break; 2933 break;
2928 2934
2929 case HIGH_POWER: 2935 case HIGH_POWER:
2930 if (val < (dev_priv->rps.rp1_delay + dev_priv->rps.rp0_delay) >> 1 && val < dev_priv->rps.cur_delay) 2936 if (val < (dev_priv->rps.rp1_freq + dev_priv->rps.rp0_freq) >> 1 && val < dev_priv->rps.cur_freq)
2931 new_power = BETWEEN; 2937 new_power = BETWEEN;
2932 break; 2938 break;
2933 } 2939 }
2934 /* Max/min bins are special */ 2940 /* Max/min bins are special */
2935 if (val == dev_priv->rps.min_delay) 2941 if (val == dev_priv->rps.min_freq_softlimit)
2936 new_power = LOW_POWER; 2942 new_power = LOW_POWER;
2937 if (val == dev_priv->rps.max_delay) 2943 if (val == dev_priv->rps.max_freq_softlimit)
2938 new_power = HIGH_POWER; 2944 new_power = HIGH_POWER;
2939 if (new_power == dev_priv->rps.power) 2945 if (new_power == dev_priv->rps.power)
2940 return; 2946 return;
@@ -3000,41 +3006,113 @@ static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val)
3000 dev_priv->rps.last_adj = 0; 3006 dev_priv->rps.last_adj = 0;
3001} 3007}
3002 3008
3009static u32 gen6_rps_pm_mask(struct drm_i915_private *dev_priv, u8 val)
3010{
3011 u32 mask = 0;
3012
3013 if (val > dev_priv->rps.min_freq_softlimit)
3014 mask |= GEN6_PM_RP_DOWN_THRESHOLD | GEN6_PM_RP_DOWN_TIMEOUT;
3015 if (val < dev_priv->rps.max_freq_softlimit)
3016 mask |= GEN6_PM_RP_UP_THRESHOLD;
3017
3018 /* IVB and SNB hard hangs on looping batchbuffer
3019 * if GEN6_PM_UP_EI_EXPIRED is masked.
3020 */
3021 if (INTEL_INFO(dev_priv->dev)->gen <= 7 && !IS_HASWELL(dev_priv->dev))
3022 mask |= GEN6_PM_RP_UP_EI_EXPIRED;
3023
3024 return ~mask;
3025}
3026
3027/* gen6_set_rps is called to update the frequency request, but should also be
3028 * called when the range (min_delay and max_delay) is modified so that we can
3029 * update the GEN6_RP_INTERRUPT_LIMITS register accordingly. */
3003void gen6_set_rps(struct drm_device *dev, u8 val) 3030void gen6_set_rps(struct drm_device *dev, u8 val)
3004{ 3031{
3005 struct drm_i915_private *dev_priv = dev->dev_private; 3032 struct drm_i915_private *dev_priv = dev->dev_private;
3006 3033
3007 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); 3034 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3008 WARN_ON(val > dev_priv->rps.max_delay); 3035 WARN_ON(val > dev_priv->rps.max_freq_softlimit);
3009 WARN_ON(val < dev_priv->rps.min_delay); 3036 WARN_ON(val < dev_priv->rps.min_freq_softlimit);
3010
3011 if (val == dev_priv->rps.cur_delay)
3012 return;
3013 3037
3014 gen6_set_rps_thresholds(dev_priv, val); 3038 /* min/max delay may still have been modified so be sure to
3039 * write the limits value.
3040 */
3041 if (val != dev_priv->rps.cur_freq) {
3042 gen6_set_rps_thresholds(dev_priv, val);
3015 3043
3016 if (IS_HASWELL(dev)) 3044 if (IS_HASWELL(dev))
3017 I915_WRITE(GEN6_RPNSWREQ, 3045 I915_WRITE(GEN6_RPNSWREQ,
3018 HSW_FREQUENCY(val)); 3046 HSW_FREQUENCY(val));
3019 else 3047 else
3020 I915_WRITE(GEN6_RPNSWREQ, 3048 I915_WRITE(GEN6_RPNSWREQ,
3021 GEN6_FREQUENCY(val) | 3049 GEN6_FREQUENCY(val) |
3022 GEN6_OFFSET(0) | 3050 GEN6_OFFSET(0) |
3023 GEN6_AGGRESSIVE_TURBO); 3051 GEN6_AGGRESSIVE_TURBO);
3052 }
3024 3053
3025 /* Make sure we continue to get interrupts 3054 /* Make sure we continue to get interrupts
3026 * until we hit the minimum or maximum frequencies. 3055 * until we hit the minimum or maximum frequencies.
3027 */ 3056 */
3028 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, 3057 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, gen6_rps_limits(dev_priv, val));
3029 gen6_rps_limits(dev_priv, val)); 3058 I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
3030 3059
3031 POSTING_READ(GEN6_RPNSWREQ); 3060 POSTING_READ(GEN6_RPNSWREQ);
3032 3061
3033 dev_priv->rps.cur_delay = val; 3062 dev_priv->rps.cur_freq = val;
3034
3035 trace_intel_gpu_freq_change(val * 50); 3063 trace_intel_gpu_freq_change(val * 50);
3036} 3064}
3037 3065
3066/* vlv_set_rps_idle: Set the frequency to Rpn if Gfx clocks are down
3067 *
3068 * * If Gfx is Idle, then
3069 * 1. Mask Turbo interrupts
3070 * 2. Bring up Gfx clock
3071 * 3. Change the freq to Rpn and wait till P-Unit updates freq
3072 * 4. Clear the Force GFX CLK ON bit so that Gfx can down
3073 * 5. Unmask Turbo interrupts
3074*/
3075static void vlv_set_rps_idle(struct drm_i915_private *dev_priv)
3076{
3077 /*
3078 * When we are idle. Drop to min voltage state.
3079 */
3080
3081 if (dev_priv->rps.cur_freq <= dev_priv->rps.min_freq_softlimit)
3082 return;
3083
3084 /* Mask turbo interrupt so that they will not come in between */
3085 I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
3086
3087 /* Bring up the Gfx clock */
3088 I915_WRITE(VLV_GTLC_SURVIVABILITY_REG,
3089 I915_READ(VLV_GTLC_SURVIVABILITY_REG) |
3090 VLV_GFX_CLK_FORCE_ON_BIT);
3091
3092 if (wait_for(((VLV_GFX_CLK_STATUS_BIT &
3093 I915_READ(VLV_GTLC_SURVIVABILITY_REG)) != 0), 5)) {
3094 DRM_ERROR("GFX_CLK_ON request timed out\n");
3095 return;
3096 }
3097
3098 dev_priv->rps.cur_freq = dev_priv->rps.min_freq_softlimit;
3099
3100 vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ,
3101 dev_priv->rps.min_freq_softlimit);
3102
3103 if (wait_for(((vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS))
3104 & GENFREQSTATUS) == 0, 5))
3105 DRM_ERROR("timed out waiting for Punit\n");
3106
3107 /* Release the Gfx clock */
3108 I915_WRITE(VLV_GTLC_SURVIVABILITY_REG,
3109 I915_READ(VLV_GTLC_SURVIVABILITY_REG) &
3110 ~VLV_GFX_CLK_FORCE_ON_BIT);
3111
3112 I915_WRITE(GEN6_PMINTRMSK,
3113 gen6_rps_pm_mask(dev_priv, dev_priv->rps.cur_freq));
3114}
3115
3038void gen6_rps_idle(struct drm_i915_private *dev_priv) 3116void gen6_rps_idle(struct drm_i915_private *dev_priv)
3039{ 3117{
3040 struct drm_device *dev = dev_priv->dev; 3118 struct drm_device *dev = dev_priv->dev;
@@ -3042,9 +3120,9 @@ void gen6_rps_idle(struct drm_i915_private *dev_priv)
3042 mutex_lock(&dev_priv->rps.hw_lock); 3120 mutex_lock(&dev_priv->rps.hw_lock);
3043 if (dev_priv->rps.enabled) { 3121 if (dev_priv->rps.enabled) {
3044 if (IS_VALLEYVIEW(dev)) 3122 if (IS_VALLEYVIEW(dev))
3045 valleyview_set_rps(dev_priv->dev, dev_priv->rps.min_delay); 3123 vlv_set_rps_idle(dev_priv);
3046 else 3124 else
3047 gen6_set_rps(dev_priv->dev, dev_priv->rps.min_delay); 3125 gen6_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit);
3048 dev_priv->rps.last_adj = 0; 3126 dev_priv->rps.last_adj = 0;
3049 } 3127 }
3050 mutex_unlock(&dev_priv->rps.hw_lock); 3128 mutex_unlock(&dev_priv->rps.hw_lock);
@@ -3057,9 +3135,9 @@ void gen6_rps_boost(struct drm_i915_private *dev_priv)
3057 mutex_lock(&dev_priv->rps.hw_lock); 3135 mutex_lock(&dev_priv->rps.hw_lock);
3058 if (dev_priv->rps.enabled) { 3136 if (dev_priv->rps.enabled) {
3059 if (IS_VALLEYVIEW(dev)) 3137 if (IS_VALLEYVIEW(dev))
3060 valleyview_set_rps(dev_priv->dev, dev_priv->rps.max_delay); 3138 valleyview_set_rps(dev_priv->dev, dev_priv->rps.max_freq_softlimit);
3061 else 3139 else
3062 gen6_set_rps(dev_priv->dev, dev_priv->rps.max_delay); 3140 gen6_set_rps(dev_priv->dev, dev_priv->rps.max_freq_softlimit);
3063 dev_priv->rps.last_adj = 0; 3141 dev_priv->rps.last_adj = 0;
3064 } 3142 }
3065 mutex_unlock(&dev_priv->rps.hw_lock); 3143 mutex_unlock(&dev_priv->rps.hw_lock);
@@ -3070,21 +3148,20 @@ void valleyview_set_rps(struct drm_device *dev, u8 val)
3070 struct drm_i915_private *dev_priv = dev->dev_private; 3148 struct drm_i915_private *dev_priv = dev->dev_private;
3071 3149
3072 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); 3150 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3073 WARN_ON(val > dev_priv->rps.max_delay); 3151 WARN_ON(val > dev_priv->rps.max_freq_softlimit);
3074 WARN_ON(val < dev_priv->rps.min_delay); 3152 WARN_ON(val < dev_priv->rps.min_freq_softlimit);
3075 3153
3076 DRM_DEBUG_DRIVER("GPU freq request from %d MHz (%u) to %d MHz (%u)\n", 3154 DRM_DEBUG_DRIVER("GPU freq request from %d MHz (%u) to %d MHz (%u)\n",
3077 vlv_gpu_freq(dev_priv, dev_priv->rps.cur_delay), 3155 vlv_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
3078 dev_priv->rps.cur_delay, 3156 dev_priv->rps.cur_freq,
3079 vlv_gpu_freq(dev_priv, val), val); 3157 vlv_gpu_freq(dev_priv, val), val);
3080 3158
3081 if (val == dev_priv->rps.cur_delay) 3159 if (val != dev_priv->rps.cur_freq)
3082 return; 3160 vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
3083
3084 vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
3085 3161
3086 dev_priv->rps.cur_delay = val; 3162 I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
3087 3163
3164 dev_priv->rps.cur_freq = val;
3088 trace_intel_gpu_freq_change(vlv_gpu_freq(dev_priv, val)); 3165 trace_intel_gpu_freq_change(vlv_gpu_freq(dev_priv, val));
3089} 3166}
3090 3167
@@ -3093,7 +3170,8 @@ static void gen6_disable_rps_interrupts(struct drm_device *dev)
3093 struct drm_i915_private *dev_priv = dev->dev_private; 3170 struct drm_i915_private *dev_priv = dev->dev_private;
3094 3171
3095 I915_WRITE(GEN6_PMINTRMSK, 0xffffffff); 3172 I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
3096 I915_WRITE(GEN6_PMIER, I915_READ(GEN6_PMIER) & ~GEN6_PM_RPS_EVENTS); 3173 I915_WRITE(GEN6_PMIER, I915_READ(GEN6_PMIER) &
3174 ~dev_priv->pm_rps_events);
3097 /* Complete PM interrupt masking here doesn't race with the rps work 3175 /* Complete PM interrupt masking here doesn't race with the rps work
3098 * item again unmasking PM interrupts because that is using a different 3176 * item again unmasking PM interrupts because that is using a different
3099 * register (PMIMR) to mask PM interrupts. The only risk is in leaving 3177 * register (PMIMR) to mask PM interrupts. The only risk is in leaving
@@ -3103,7 +3181,7 @@ static void gen6_disable_rps_interrupts(struct drm_device *dev)
3103 dev_priv->rps.pm_iir = 0; 3181 dev_priv->rps.pm_iir = 0;
3104 spin_unlock_irq(&dev_priv->irq_lock); 3182 spin_unlock_irq(&dev_priv->irq_lock);
3105 3183
3106 I915_WRITE(GEN6_PMIIR, GEN6_PM_RPS_EVENTS); 3184 I915_WRITE(GEN6_PMIIR, dev_priv->pm_rps_events);
3107} 3185}
3108 3186
3109static void gen6_disable_rps(struct drm_device *dev) 3187static void gen6_disable_rps(struct drm_device *dev)
@@ -3123,25 +3201,14 @@ static void valleyview_disable_rps(struct drm_device *dev)
3123 I915_WRITE(GEN6_RC_CONTROL, 0); 3201 I915_WRITE(GEN6_RC_CONTROL, 0);
3124 3202
3125 gen6_disable_rps_interrupts(dev); 3203 gen6_disable_rps_interrupts(dev);
3126
3127 if (dev_priv->vlv_pctx) {
3128 drm_gem_object_unreference(&dev_priv->vlv_pctx->base);
3129 dev_priv->vlv_pctx = NULL;
3130 }
3131} 3204}
3132 3205
3133static void intel_print_rc6_info(struct drm_device *dev, u32 mode) 3206static void intel_print_rc6_info(struct drm_device *dev, u32 mode)
3134{ 3207{
3135 if (IS_GEN6(dev))
3136 DRM_DEBUG_DRIVER("Sandybridge: deep RC6 disabled\n");
3137
3138 if (IS_HASWELL(dev))
3139 DRM_DEBUG_DRIVER("Haswell: only RC6 available\n");
3140
3141 DRM_INFO("Enabling RC6 states: RC6 %s, RC6p %s, RC6pp %s\n", 3208 DRM_INFO("Enabling RC6 states: RC6 %s, RC6p %s, RC6pp %s\n",
3142 (mode & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off", 3209 (mode & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off",
3143 (mode & GEN6_RC_CTL_RC6p_ENABLE) ? "on" : "off", 3210 (mode & GEN6_RC_CTL_RC6p_ENABLE) ? "on" : "off",
3144 (mode & GEN6_RC_CTL_RC6pp_ENABLE) ? "on" : "off"); 3211 (mode & GEN6_RC_CTL_RC6pp_ENABLE) ? "on" : "off");
3145} 3212}
3146 3213
3147int intel_enable_rc6(const struct drm_device *dev) 3214int intel_enable_rc6(const struct drm_device *dev)
@@ -3151,44 +3218,28 @@ int intel_enable_rc6(const struct drm_device *dev)
3151 return 0; 3218 return 0;
3152 3219
3153 /* Respect the kernel parameter if it is set */ 3220 /* Respect the kernel parameter if it is set */
3154 if (i915_enable_rc6 >= 0) 3221 if (i915.enable_rc6 >= 0)
3155 return i915_enable_rc6; 3222 return i915.enable_rc6;
3156 3223
3157 /* Disable RC6 on Ironlake */ 3224 /* Disable RC6 on Ironlake */
3158 if (INTEL_INFO(dev)->gen == 5) 3225 if (INTEL_INFO(dev)->gen == 5)
3159 return 0; 3226 return 0;
3160 3227
3161 if (IS_HASWELL(dev)) 3228 if (IS_IVYBRIDGE(dev))
3162 return INTEL_RC6_ENABLE; 3229 return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE);
3163
3164 /* snb/ivb have more than one rc6 state. */
3165 if (INTEL_INFO(dev)->gen == 6)
3166 return INTEL_RC6_ENABLE;
3167 3230
3168 return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE); 3231 return INTEL_RC6_ENABLE;
3169} 3232}
3170 3233
3171static void gen6_enable_rps_interrupts(struct drm_device *dev) 3234static void gen6_enable_rps_interrupts(struct drm_device *dev)
3172{ 3235{
3173 struct drm_i915_private *dev_priv = dev->dev_private; 3236 struct drm_i915_private *dev_priv = dev->dev_private;
3174 u32 enabled_intrs;
3175 3237
3176 spin_lock_irq(&dev_priv->irq_lock); 3238 spin_lock_irq(&dev_priv->irq_lock);
3177 WARN_ON(dev_priv->rps.pm_iir); 3239 WARN_ON(dev_priv->rps.pm_iir);
3178 snb_enable_pm_irq(dev_priv, GEN6_PM_RPS_EVENTS); 3240 snb_enable_pm_irq(dev_priv, dev_priv->pm_rps_events);
3179 I915_WRITE(GEN6_PMIIR, GEN6_PM_RPS_EVENTS); 3241 I915_WRITE(GEN6_PMIIR, dev_priv->pm_rps_events);
3180 spin_unlock_irq(&dev_priv->irq_lock); 3242 spin_unlock_irq(&dev_priv->irq_lock);
3181
3182 /* only unmask PM interrupts we need. Mask all others. */
3183 enabled_intrs = GEN6_PM_RPS_EVENTS;
3184
3185 /* IVB and SNB hard hangs on looping batchbuffer
3186 * if GEN6_PM_UP_EI_EXPIRED is masked.
3187 */
3188 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
3189 enabled_intrs |= GEN6_PM_RP_UP_EI_EXPIRED;
3190
3191 I915_WRITE(GEN6_PMINTRMSK, ~enabled_intrs);
3192} 3243}
3193 3244
3194static void gen8_enable_rps(struct drm_device *dev) 3245static void gen8_enable_rps(struct drm_device *dev)
@@ -3222,10 +3273,10 @@ static void gen8_enable_rps(struct drm_device *dev)
3222 /* 3: Enable RC6 */ 3273 /* 3: Enable RC6 */
3223 if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE) 3274 if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
3224 rc6_mask = GEN6_RC_CTL_RC6_ENABLE; 3275 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
3225 DRM_INFO("RC6 %s\n", (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off"); 3276 intel_print_rc6_info(dev, rc6_mask);
3226 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE | 3277 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
3227 GEN6_RC_CTL_EI_MODE(1) | 3278 GEN6_RC_CTL_EI_MODE(1) |
3228 rc6_mask); 3279 rc6_mask);
3229 3280
3230 /* 4 Program defaults and thresholds for RPS*/ 3281 /* 4 Program defaults and thresholds for RPS*/
3231 I915_WRITE(GEN6_RPNSWREQ, HSW_FREQUENCY(10)); /* Request 500 MHz */ 3282 I915_WRITE(GEN6_RPNSWREQ, HSW_FREQUENCY(10)); /* Request 500 MHz */
@@ -3235,8 +3286,8 @@ static void gen8_enable_rps(struct drm_device *dev)
3235 3286
3236 /* Docs recommend 900MHz, and 300 MHz respectively */ 3287 /* Docs recommend 900MHz, and 300 MHz respectively */
3237 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, 3288 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
3238 dev_priv->rps.max_delay << 24 | 3289 dev_priv->rps.max_freq_softlimit << 24 |
3239 dev_priv->rps.min_delay << 16); 3290 dev_priv->rps.min_freq_softlimit << 16);
3240 3291
3241 I915_WRITE(GEN6_RP_UP_THRESHOLD, 7600000 / 128); /* 76ms busyness per EI, 90% */ 3292 I915_WRITE(GEN6_RP_UP_THRESHOLD, 7600000 / 128); /* 76ms busyness per EI, 90% */
3242 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 31300000 / 128); /* 313ms busyness per EI, 70%*/ 3293 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 31300000 / 128); /* 313ms busyness per EI, 70%*/
@@ -3269,7 +3320,7 @@ static void gen6_enable_rps(struct drm_device *dev)
3269 struct intel_ring_buffer *ring; 3320 struct intel_ring_buffer *ring;
3270 u32 rp_state_cap; 3321 u32 rp_state_cap;
3271 u32 gt_perf_status; 3322 u32 gt_perf_status;
3272 u32 rc6vids, pcu_mbox, rc6_mask = 0; 3323 u32 rc6vids, pcu_mbox = 0, rc6_mask = 0;
3273 u32 gtfifodbg; 3324 u32 gtfifodbg;
3274 int rc6_mode; 3325 int rc6_mode;
3275 int i, ret; 3326 int i, ret;
@@ -3295,13 +3346,23 @@ static void gen6_enable_rps(struct drm_device *dev)
3295 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP); 3346 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
3296 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS); 3347 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
3297 3348
3298 /* In units of 50MHz */ 3349 /* All of these values are in units of 50MHz */
3299 dev_priv->rps.hw_max = dev_priv->rps.max_delay = rp_state_cap & 0xff; 3350 dev_priv->rps.cur_freq = 0;
3300 dev_priv->rps.min_delay = (rp_state_cap >> 16) & 0xff; 3351 /* static values from HW: RP0 < RPe < RP1 < RPn (min_freq) */
3301 dev_priv->rps.rp1_delay = (rp_state_cap >> 8) & 0xff; 3352 dev_priv->rps.rp1_freq = (rp_state_cap >> 8) & 0xff;
3302 dev_priv->rps.rp0_delay = (rp_state_cap >> 0) & 0xff; 3353 dev_priv->rps.rp0_freq = (rp_state_cap >> 0) & 0xff;
3303 dev_priv->rps.rpe_delay = dev_priv->rps.rp1_delay; 3354 dev_priv->rps.min_freq = (rp_state_cap >> 16) & 0xff;
3304 dev_priv->rps.cur_delay = 0; 3355 /* XXX: only BYT has a special efficient freq */
3356 dev_priv->rps.efficient_freq = dev_priv->rps.rp1_freq;
3357 /* hw_max = RP0 until we check for overclocking */
3358 dev_priv->rps.max_freq = dev_priv->rps.rp0_freq;
3359
3360 /* Preserve min/max settings in case of re-init */
3361 if (dev_priv->rps.max_freq_softlimit == 0)
3362 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
3363
3364 if (dev_priv->rps.min_freq_softlimit == 0)
3365 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
3305 3366
3306 /* disable the counters and set deterministic thresholds */ 3367 /* disable the counters and set deterministic thresholds */
3307 I915_WRITE(GEN6_RC_CONTROL, 0); 3368 I915_WRITE(GEN6_RC_CONTROL, 0);
@@ -3350,21 +3411,19 @@ static void gen6_enable_rps(struct drm_device *dev)
3350 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10); 3411 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
3351 3412
3352 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_MIN_FREQ_TABLE, 0); 3413 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_MIN_FREQ_TABLE, 0);
3353 if (!ret) { 3414 if (ret)
3354 pcu_mbox = 0;
3355 ret = sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &pcu_mbox);
3356 if (!ret && (pcu_mbox & (1<<31))) { /* OC supported */
3357 DRM_DEBUG_DRIVER("Overclocking supported. Max: %dMHz, Overclock max: %dMHz\n",
3358 (dev_priv->rps.max_delay & 0xff) * 50,
3359 (pcu_mbox & 0xff) * 50);
3360 dev_priv->rps.hw_max = pcu_mbox & 0xff;
3361 }
3362 } else {
3363 DRM_DEBUG_DRIVER("Failed to set the min frequency\n"); 3415 DRM_DEBUG_DRIVER("Failed to set the min frequency\n");
3416
3417 ret = sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &pcu_mbox);
3418 if (!ret && (pcu_mbox & (1<<31))) { /* OC supported */
3419 DRM_DEBUG_DRIVER("Overclocking supported. Max: %dMHz, Overclock max: %dMHz\n",
3420 (dev_priv->rps.max_freq_softlimit & 0xff) * 50,
3421 (pcu_mbox & 0xff) * 50);
3422 dev_priv->rps.max_freq = pcu_mbox & 0xff;
3364 } 3423 }
3365 3424
3366 dev_priv->rps.power = HIGH_POWER; /* force a reset */ 3425 dev_priv->rps.power = HIGH_POWER; /* force a reset */
3367 gen6_set_rps(dev_priv->dev, dev_priv->rps.min_delay); 3426 gen6_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit);
3368 3427
3369 gen6_enable_rps_interrupts(dev); 3428 gen6_enable_rps_interrupts(dev);
3370 3429
@@ -3420,9 +3479,9 @@ void gen6_update_ring_freq(struct drm_device *dev)
3420 * to use for memory access. We do this by specifying the IA frequency 3479 * to use for memory access. We do this by specifying the IA frequency
3421 * the PCU should use as a reference to determine the ring frequency. 3480 * the PCU should use as a reference to determine the ring frequency.
3422 */ 3481 */
3423 for (gpu_freq = dev_priv->rps.max_delay; gpu_freq >= dev_priv->rps.min_delay; 3482 for (gpu_freq = dev_priv->rps.max_freq_softlimit; gpu_freq >= dev_priv->rps.min_freq_softlimit;
3424 gpu_freq--) { 3483 gpu_freq--) {
3425 int diff = dev_priv->rps.max_delay - gpu_freq; 3484 int diff = dev_priv->rps.max_freq_softlimit - gpu_freq;
3426 unsigned int ia_freq = 0, ring_freq = 0; 3485 unsigned int ia_freq = 0, ring_freq = 0;
3427 3486
3428 if (INTEL_INFO(dev)->gen >= 8) { 3487 if (INTEL_INFO(dev)->gen >= 8) {
@@ -3485,6 +3544,15 @@ int valleyview_rps_min_freq(struct drm_i915_private *dev_priv)
3485 return vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) & 0xff; 3544 return vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) & 0xff;
3486} 3545}
3487 3546
3547/* Check that the pctx buffer wasn't move under us. */
3548static void valleyview_check_pctx(struct drm_i915_private *dev_priv)
3549{
3550 unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
3551
3552 WARN_ON(pctx_addr != dev_priv->mm.stolen_base +
3553 dev_priv->vlv_pctx->stolen->start);
3554}
3555
3488static void valleyview_setup_pctx(struct drm_device *dev) 3556static void valleyview_setup_pctx(struct drm_device *dev)
3489{ 3557{
3490 struct drm_i915_private *dev_priv = dev->dev_private; 3558 struct drm_i915_private *dev_priv = dev->dev_private;
@@ -3529,6 +3597,17 @@ out:
3529 dev_priv->vlv_pctx = pctx; 3597 dev_priv->vlv_pctx = pctx;
3530} 3598}
3531 3599
3600static void valleyview_cleanup_pctx(struct drm_device *dev)
3601{
3602 struct drm_i915_private *dev_priv = dev->dev_private;
3603
3604 if (WARN_ON(!dev_priv->vlv_pctx))
3605 return;
3606
3607 drm_gem_object_unreference(&dev_priv->vlv_pctx->base);
3608 dev_priv->vlv_pctx = NULL;
3609}
3610
3532static void valleyview_enable_rps(struct drm_device *dev) 3611static void valleyview_enable_rps(struct drm_device *dev)
3533{ 3612{
3534 struct drm_i915_private *dev_priv = dev->dev_private; 3613 struct drm_i915_private *dev_priv = dev->dev_private;
@@ -3538,6 +3617,8 @@ static void valleyview_enable_rps(struct drm_device *dev)
3538 3617
3539 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); 3618 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3540 3619
3620 valleyview_check_pctx(dev_priv);
3621
3541 if ((gtfifodbg = I915_READ(GTFIFODBG))) { 3622 if ((gtfifodbg = I915_READ(GTFIFODBG))) {
3542 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n", 3623 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
3543 gtfifodbg); 3624 gtfifodbg);
@@ -3588,32 +3669,39 @@ static void valleyview_enable_rps(struct drm_device *dev)
3588 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val & 0x10 ? "yes" : "no"); 3669 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val & 0x10 ? "yes" : "no");
3589 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val); 3670 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
3590 3671
3591 dev_priv->rps.cur_delay = (val >> 8) & 0xff; 3672 dev_priv->rps.cur_freq = (val >> 8) & 0xff;
3592 DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n", 3673 DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
3593 vlv_gpu_freq(dev_priv, dev_priv->rps.cur_delay), 3674 vlv_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
3594 dev_priv->rps.cur_delay); 3675 dev_priv->rps.cur_freq);
3595 3676
3596 dev_priv->rps.max_delay = valleyview_rps_max_freq(dev_priv); 3677 dev_priv->rps.max_freq = valleyview_rps_max_freq(dev_priv);
3597 dev_priv->rps.hw_max = dev_priv->rps.max_delay; 3678 dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
3598 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n", 3679 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
3599 vlv_gpu_freq(dev_priv, dev_priv->rps.max_delay), 3680 vlv_gpu_freq(dev_priv, dev_priv->rps.max_freq),
3600 dev_priv->rps.max_delay); 3681 dev_priv->rps.max_freq);
3601 3682
3602 dev_priv->rps.rpe_delay = valleyview_rps_rpe_freq(dev_priv); 3683 dev_priv->rps.efficient_freq = valleyview_rps_rpe_freq(dev_priv);
3603 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n", 3684 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
3604 vlv_gpu_freq(dev_priv, dev_priv->rps.rpe_delay), 3685 vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
3605 dev_priv->rps.rpe_delay); 3686 dev_priv->rps.efficient_freq);
3606 3687
3607 dev_priv->rps.min_delay = valleyview_rps_min_freq(dev_priv); 3688 dev_priv->rps.min_freq = valleyview_rps_min_freq(dev_priv);
3608 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n", 3689 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
3609 vlv_gpu_freq(dev_priv, dev_priv->rps.min_delay), 3690 vlv_gpu_freq(dev_priv, dev_priv->rps.min_freq),
3610 dev_priv->rps.min_delay); 3691 dev_priv->rps.min_freq);
3692
3693 /* Preserve min/max settings in case of re-init */
3694 if (dev_priv->rps.max_freq_softlimit == 0)
3695 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
3696
3697 if (dev_priv->rps.min_freq_softlimit == 0)
3698 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
3611 3699
3612 DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n", 3700 DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
3613 vlv_gpu_freq(dev_priv, dev_priv->rps.rpe_delay), 3701 vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
3614 dev_priv->rps.rpe_delay); 3702 dev_priv->rps.efficient_freq);
3615 3703
3616 valleyview_set_rps(dev_priv->dev, dev_priv->rps.rpe_delay); 3704 valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq);
3617 3705
3618 gen6_enable_rps_interrupts(dev); 3706 gen6_enable_rps_interrupts(dev);
3619 3707
@@ -3625,13 +3713,13 @@ void ironlake_teardown_rc6(struct drm_device *dev)
3625 struct drm_i915_private *dev_priv = dev->dev_private; 3713 struct drm_i915_private *dev_priv = dev->dev_private;
3626 3714
3627 if (dev_priv->ips.renderctx) { 3715 if (dev_priv->ips.renderctx) {
3628 i915_gem_object_unpin(dev_priv->ips.renderctx); 3716 i915_gem_object_ggtt_unpin(dev_priv->ips.renderctx);
3629 drm_gem_object_unreference(&dev_priv->ips.renderctx->base); 3717 drm_gem_object_unreference(&dev_priv->ips.renderctx->base);
3630 dev_priv->ips.renderctx = NULL; 3718 dev_priv->ips.renderctx = NULL;
3631 } 3719 }
3632 3720
3633 if (dev_priv->ips.pwrctx) { 3721 if (dev_priv->ips.pwrctx) {
3634 i915_gem_object_unpin(dev_priv->ips.pwrctx); 3722 i915_gem_object_ggtt_unpin(dev_priv->ips.pwrctx);
3635 drm_gem_object_unreference(&dev_priv->ips.pwrctx->base); 3723 drm_gem_object_unreference(&dev_priv->ips.pwrctx->base);
3636 dev_priv->ips.pwrctx = NULL; 3724 dev_priv->ips.pwrctx = NULL;
3637 } 3725 }
@@ -3823,9 +3911,10 @@ static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv)
3823 3911
3824unsigned long i915_chipset_val(struct drm_i915_private *dev_priv) 3912unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
3825{ 3913{
3914 struct drm_device *dev = dev_priv->dev;
3826 unsigned long val; 3915 unsigned long val;
3827 3916
3828 if (dev_priv->info->gen != 5) 3917 if (INTEL_INFO(dev)->gen != 5)
3829 return 0; 3918 return 0;
3830 3919
3831 spin_lock_irq(&mchdev_lock); 3920 spin_lock_irq(&mchdev_lock);
@@ -3854,6 +3943,7 @@ unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
3854 3943
3855static u16 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid) 3944static u16 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
3856{ 3945{
3946 struct drm_device *dev = dev_priv->dev;
3857 static const struct v_table { 3947 static const struct v_table {
3858 u16 vd; /* in .1 mil */ 3948 u16 vd; /* in .1 mil */
3859 u16 vm; /* in .1 mil */ 3949 u16 vm; /* in .1 mil */
@@ -3987,7 +4077,7 @@ static u16 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
3987 { 16000, 14875, }, 4077 { 16000, 14875, },
3988 { 16125, 15000, }, 4078 { 16125, 15000, },
3989 }; 4079 };
3990 if (dev_priv->info->is_mobile) 4080 if (INTEL_INFO(dev)->is_mobile)
3991 return v_table[pxvid].vm; 4081 return v_table[pxvid].vm;
3992 else 4082 else
3993 return v_table[pxvid].vd; 4083 return v_table[pxvid].vd;
@@ -4030,7 +4120,9 @@ static void __i915_update_gfx_val(struct drm_i915_private *dev_priv)
4030 4120
4031void i915_update_gfx_val(struct drm_i915_private *dev_priv) 4121void i915_update_gfx_val(struct drm_i915_private *dev_priv)
4032{ 4122{
4033 if (dev_priv->info->gen != 5) 4123 struct drm_device *dev = dev_priv->dev;
4124
4125 if (INTEL_INFO(dev)->gen != 5)
4034 return; 4126 return;
4035 4127
4036 spin_lock_irq(&mchdev_lock); 4128 spin_lock_irq(&mchdev_lock);
@@ -4047,7 +4139,7 @@ static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv)
4047 4139
4048 assert_spin_locked(&mchdev_lock); 4140 assert_spin_locked(&mchdev_lock);
4049 4141
4050 pxvid = I915_READ(PXVFREQ_BASE + (dev_priv->rps.cur_delay * 4)); 4142 pxvid = I915_READ(PXVFREQ_BASE + (dev_priv->rps.cur_freq * 4));
4051 pxvid = (pxvid >> 24) & 0x7f; 4143 pxvid = (pxvid >> 24) & 0x7f;
4052 ext_v = pvid_to_extvid(dev_priv, pxvid); 4144 ext_v = pvid_to_extvid(dev_priv, pxvid);
4053 4145
@@ -4079,9 +4171,10 @@ static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv)
4079 4171
4080unsigned long i915_gfx_val(struct drm_i915_private *dev_priv) 4172unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
4081{ 4173{
4174 struct drm_device *dev = dev_priv->dev;
4082 unsigned long val; 4175 unsigned long val;
4083 4176
4084 if (dev_priv->info->gen != 5) 4177 if (INTEL_INFO(dev)->gen != 5)
4085 return 0; 4178 return 0;
4086 4179
4087 spin_lock_irq(&mchdev_lock); 4180 spin_lock_irq(&mchdev_lock);
@@ -4270,6 +4363,7 @@ void intel_gpu_ips_teardown(void)
4270 i915_mch_dev = NULL; 4363 i915_mch_dev = NULL;
4271 spin_unlock_irq(&mchdev_lock); 4364 spin_unlock_irq(&mchdev_lock);
4272} 4365}
4366
4273static void intel_init_emon(struct drm_device *dev) 4367static void intel_init_emon(struct drm_device *dev)
4274{ 4368{
4275 struct drm_i915_private *dev_priv = dev->dev_private; 4369 struct drm_i915_private *dev_priv = dev->dev_private;
@@ -4341,6 +4435,18 @@ static void intel_init_emon(struct drm_device *dev)
4341 dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK); 4435 dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK);
4342} 4436}
4343 4437
4438void intel_init_gt_powersave(struct drm_device *dev)
4439{
4440 if (IS_VALLEYVIEW(dev))
4441 valleyview_setup_pctx(dev);
4442}
4443
4444void intel_cleanup_gt_powersave(struct drm_device *dev)
4445{
4446 if (IS_VALLEYVIEW(dev))
4447 valleyview_cleanup_pctx(dev);
4448}
4449
4344void intel_disable_gt_powersave(struct drm_device *dev) 4450void intel_disable_gt_powersave(struct drm_device *dev)
4345{ 4451{
4346 struct drm_i915_private *dev_priv = dev->dev_private; 4452 struct drm_i915_private *dev_priv = dev->dev_private;
@@ -4395,8 +4501,6 @@ void intel_enable_gt_powersave(struct drm_device *dev)
4395 ironlake_enable_rc6(dev); 4501 ironlake_enable_rc6(dev);
4396 intel_init_emon(dev); 4502 intel_init_emon(dev);
4397 } else if (IS_GEN6(dev) || IS_GEN7(dev)) { 4503 } else if (IS_GEN6(dev) || IS_GEN7(dev)) {
4398 if (IS_VALLEYVIEW(dev))
4399 valleyview_setup_pctx(dev);
4400 /* 4504 /*
4401 * PCU communication is slow and this doesn't need to be 4505 * PCU communication is slow and this doesn't need to be
4402 * done at any specific time, so do this out of our fast path 4506 * done at any specific time, so do this out of our fast path
@@ -4587,6 +4691,17 @@ static void gen6_init_clock_gating(struct drm_device *dev)
4587 I915_WRITE(GEN6_GT_MODE, 4691 I915_WRITE(GEN6_GT_MODE,
4588 _MASKED_BIT_ENABLE(GEN6_TD_FOUR_ROW_DISPATCH_DISABLE)); 4692 _MASKED_BIT_ENABLE(GEN6_TD_FOUR_ROW_DISPATCH_DISABLE));
4589 4693
4694 /*
4695 * BSpec recoomends 8x4 when MSAA is used,
4696 * however in practice 16x4 seems fastest.
4697 *
4698 * Note that PS/WM thread counts depend on the WIZ hashing
4699 * disable bit, which we don't touch here, but it's good
4700 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
4701 */
4702 I915_WRITE(GEN6_GT_MODE,
4703 GEN6_WIZ_HASHING_MASK | GEN6_WIZ_HASHING_16x4);
4704
4590 ilk_init_lp_watermarks(dev); 4705 ilk_init_lp_watermarks(dev);
4591 4706
4592 I915_WRITE(CACHE_MODE_0, 4707 I915_WRITE(CACHE_MODE_0,
@@ -4607,17 +4722,24 @@ static void gen6_init_clock_gating(struct drm_device *dev)
4607 * According to the spec, bit 11 (RCCUNIT) must also be set, 4722 * According to the spec, bit 11 (RCCUNIT) must also be set,
4608 * but we didn't debug actual testcases to find it out. 4723 * but we didn't debug actual testcases to find it out.
4609 * 4724 *
4610 * Also apply WaDisableVDSUnitClockGating:snb and 4725 * WaDisableRCCUnitClockGating:snb
4611 * WaDisableRCPBUnitClockGating:snb. 4726 * WaDisableRCPBUnitClockGating:snb
4612 */ 4727 */
4613 I915_WRITE(GEN6_UCGCTL2, 4728 I915_WRITE(GEN6_UCGCTL2,
4614 GEN7_VDSUNIT_CLOCK_GATE_DISABLE |
4615 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE | 4729 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
4616 GEN6_RCCUNIT_CLOCK_GATE_DISABLE); 4730 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
4617 4731
4618 /* Bspec says we need to always set all mask bits. */ 4732 /* WaStripsFansDisableFastClipPerformanceFix:snb */
4619 I915_WRITE(_3D_CHICKEN3, (0xFFFF << 16) | 4733 I915_WRITE(_3D_CHICKEN3,
4620 _3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL); 4734 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL));
4735
4736 /*
4737 * Bspec says:
4738 * "This bit must be set if 3DSTATE_CLIP clip mode is set to normal and
4739 * 3DSTATE_SF number of SF output attributes is more than 16."
4740 */
4741 I915_WRITE(_3D_CHICKEN3,
4742 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH));
4621 4743
4622 /* 4744 /*
4623 * According to the spec the following bits should be 4745 * According to the spec the following bits should be
@@ -4643,11 +4765,6 @@ static void gen6_init_clock_gating(struct drm_device *dev)
4643 4765
4644 g4x_disable_trickle_feed(dev); 4766 g4x_disable_trickle_feed(dev);
4645 4767
4646 /* The default value should be 0x200 according to docs, but the two
4647 * platforms I checked have a 0 for this. (Maybe BIOS overrides?) */
4648 I915_WRITE(GEN6_GT_MODE, _MASKED_BIT_DISABLE(0xffff));
4649 I915_WRITE(GEN6_GT_MODE, _MASKED_BIT_ENABLE(GEN6_GT_MODE_HI));
4650
4651 cpt_init_clock_gating(dev); 4768 cpt_init_clock_gating(dev);
4652 4769
4653 gen6_check_mch_setup(dev); 4770 gen6_check_mch_setup(dev);
@@ -4657,14 +4774,17 @@ static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
4657{ 4774{
4658 uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE); 4775 uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE);
4659 4776
4777 /*
4778 * WaVSThreadDispatchOverride:ivb,vlv
4779 *
4780 * This actually overrides the dispatch
4781 * mode for all thread types.
4782 */
4660 reg &= ~GEN7_FF_SCHED_MASK; 4783 reg &= ~GEN7_FF_SCHED_MASK;
4661 reg |= GEN7_FF_TS_SCHED_HW; 4784 reg |= GEN7_FF_TS_SCHED_HW;
4662 reg |= GEN7_FF_VS_SCHED_HW; 4785 reg |= GEN7_FF_VS_SCHED_HW;
4663 reg |= GEN7_FF_DS_SCHED_HW; 4786 reg |= GEN7_FF_DS_SCHED_HW;
4664 4787
4665 if (IS_HASWELL(dev_priv->dev))
4666 reg &= ~GEN7_FF_VS_REF_CNT_FFME;
4667
4668 I915_WRITE(GEN7_FF_THREAD_MODE, reg); 4788 I915_WRITE(GEN7_FF_THREAD_MODE, reg);
4669} 4789}
4670 4790
@@ -4702,7 +4822,7 @@ static void lpt_suspend_hw(struct drm_device *dev)
4702static void gen8_init_clock_gating(struct drm_device *dev) 4822static void gen8_init_clock_gating(struct drm_device *dev)
4703{ 4823{
4704 struct drm_i915_private *dev_priv = dev->dev_private; 4824 struct drm_i915_private *dev_priv = dev->dev_private;
4705 enum pipe i; 4825 enum pipe pipe;
4706 4826
4707 I915_WRITE(WM3_LP_ILK, 0); 4827 I915_WRITE(WM3_LP_ILK, 0);
4708 I915_WRITE(WM2_LP_ILK, 0); 4828 I915_WRITE(WM2_LP_ILK, 0);
@@ -4711,8 +4831,19 @@ static void gen8_init_clock_gating(struct drm_device *dev)
4711 /* FIXME(BDW): Check all the w/a, some might only apply to 4831 /* FIXME(BDW): Check all the w/a, some might only apply to
4712 * pre-production hw. */ 4832 * pre-production hw. */
4713 4833
4714 WARN(!i915_preliminary_hw_support, 4834 /* WaDisablePartialInstShootdown:bdw */
4715 "GEN8_CENTROID_PIXEL_OPT_DIS not be needed for production\n"); 4835 I915_WRITE(GEN8_ROW_CHICKEN,
4836 _MASKED_BIT_ENABLE(PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE));
4837
4838 /* WaDisableThreadStallDopClockGating:bdw */
4839 /* FIXME: Unclear whether we really need this on production bdw. */
4840 I915_WRITE(GEN8_ROW_CHICKEN,
4841 _MASKED_BIT_ENABLE(STALL_DOP_GATING_DISABLE));
4842
4843 /*
4844 * This GEN8_CENTROID_PIXEL_OPT_DIS W/A is only needed for
4845 * pre-production hardware
4846 */
4716 I915_WRITE(HALF_SLICE_CHICKEN3, 4847 I915_WRITE(HALF_SLICE_CHICKEN3,
4717 _MASKED_BIT_ENABLE(GEN8_CENTROID_PIXEL_OPT_DIS)); 4848 _MASKED_BIT_ENABLE(GEN8_CENTROID_PIXEL_OPT_DIS));
4718 I915_WRITE(HALF_SLICE_CHICKEN3, 4849 I915_WRITE(HALF_SLICE_CHICKEN3,
@@ -4736,10 +4867,10 @@ static void gen8_init_clock_gating(struct drm_device *dev)
4736 I915_READ(CHICKEN_PAR1_1) | DPA_MASK_VBLANK_SRD); 4867 I915_READ(CHICKEN_PAR1_1) | DPA_MASK_VBLANK_SRD);
4737 4868
4738 /* WaPsrDPRSUnmaskVBlankInSRD:bdw */ 4869 /* WaPsrDPRSUnmaskVBlankInSRD:bdw */
4739 for_each_pipe(i) { 4870 for_each_pipe(pipe) {
4740 I915_WRITE(CHICKEN_PIPESL_1(i), 4871 I915_WRITE(CHICKEN_PIPESL_1(pipe),
4741 I915_READ(CHICKEN_PIPESL_1(i) | 4872 I915_READ(CHICKEN_PIPESL_1(pipe)) |
4742 DPRS_MASK_VBLANK_SRD)); 4873 BDW_DPRS_MASK_VBLANK_SRD);
4743 } 4874 }
4744 4875
4745 /* Use Force Non-Coherent whenever executing a 3D context. This is a 4876 /* Use Force Non-Coherent whenever executing a 3D context. This is a
@@ -4755,6 +4886,28 @@ static void gen8_init_clock_gating(struct drm_device *dev)
4755 I915_WRITE(GEN7_FF_THREAD_MODE, 4886 I915_WRITE(GEN7_FF_THREAD_MODE,
4756 I915_READ(GEN7_FF_THREAD_MODE) & 4887 I915_READ(GEN7_FF_THREAD_MODE) &
4757 ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME)); 4888 ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
4889
4890 /*
4891 * BSpec recommends 8x4 when MSAA is used,
4892 * however in practice 16x4 seems fastest.
4893 *
4894 * Note that PS/WM thread counts depend on the WIZ hashing
4895 * disable bit, which we don't touch here, but it's good
4896 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
4897 */
4898 I915_WRITE(GEN7_GT_MODE,
4899 GEN6_WIZ_HASHING_MASK | GEN6_WIZ_HASHING_16x4);
4900
4901 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
4902 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
4903
4904 /* WaDisableSDEUnitClockGating:bdw */
4905 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
4906 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
4907
4908 /* Wa4x4STCOptimizationDisable:bdw */
4909 I915_WRITE(CACHE_MODE_1,
4910 _MASKED_BIT_ENABLE(GEN8_4x4_STC_OPTIMIZATION_DISABLE));
4758} 4911}
4759 4912
4760static void haswell_init_clock_gating(struct drm_device *dev) 4913static void haswell_init_clock_gating(struct drm_device *dev)
@@ -4763,21 +4916,6 @@ static void haswell_init_clock_gating(struct drm_device *dev)
4763 4916
4764 ilk_init_lp_watermarks(dev); 4917 ilk_init_lp_watermarks(dev);
4765 4918
4766 /* According to the spec, bit 13 (RCZUNIT) must be set on IVB.
4767 * This implements the WaDisableRCZUnitClockGating:hsw workaround.
4768 */
4769 I915_WRITE(GEN6_UCGCTL2, GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
4770
4771 /* Apply the WaDisableRHWOOptimizationForRenderHang:hsw workaround. */
4772 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
4773 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
4774
4775 /* WaApplyL3ControlAndL3ChickenMode:hsw */
4776 I915_WRITE(GEN7_L3CNTLREG1,
4777 GEN7_WA_FOR_GEN7_L3_CONTROL);
4778 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
4779 GEN7_WA_L3_CHICKEN_MODE);
4780
4781 /* L3 caching of data atomics doesn't work -- disable it. */ 4919 /* L3 caching of data atomics doesn't work -- disable it. */
4782 I915_WRITE(HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE); 4920 I915_WRITE(HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE);
4783 I915_WRITE(HSW_ROW_CHICKEN3, 4921 I915_WRITE(HSW_ROW_CHICKEN3,
@@ -4789,12 +4927,28 @@ static void haswell_init_clock_gating(struct drm_device *dev)
4789 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB); 4927 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
4790 4928
4791 /* WaVSRefCountFullforceMissDisable:hsw */ 4929 /* WaVSRefCountFullforceMissDisable:hsw */
4792 gen7_setup_fixed_func_scheduler(dev_priv); 4930 I915_WRITE(GEN7_FF_THREAD_MODE,
4931 I915_READ(GEN7_FF_THREAD_MODE) & ~GEN7_FF_VS_REF_CNT_FFME);
4932
4933 /* enable HiZ Raw Stall Optimization */
4934 I915_WRITE(CACHE_MODE_0_GEN7,
4935 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
4793 4936
4794 /* WaDisable4x2SubspanOptimization:hsw */ 4937 /* WaDisable4x2SubspanOptimization:hsw */
4795 I915_WRITE(CACHE_MODE_1, 4938 I915_WRITE(CACHE_MODE_1,
4796 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE)); 4939 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
4797 4940
4941 /*
4942 * BSpec recommends 8x4 when MSAA is used,
4943 * however in practice 16x4 seems fastest.
4944 *
4945 * Note that PS/WM thread counts depend on the WIZ hashing
4946 * disable bit, which we don't touch here, but it's good
4947 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
4948 */
4949 I915_WRITE(GEN7_GT_MODE,
4950 GEN6_WIZ_HASHING_MASK | GEN6_WIZ_HASHING_16x4);
4951
4798 /* WaSwitchSolVfFArbitrationPriority:hsw */ 4952 /* WaSwitchSolVfFArbitrationPriority:hsw */
4799 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL); 4953 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
4800 4954
@@ -4827,9 +4981,6 @@ static void ivybridge_init_clock_gating(struct drm_device *dev)
4827 if (IS_IVB_GT1(dev)) 4981 if (IS_IVB_GT1(dev))
4828 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1, 4982 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
4829 _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE)); 4983 _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
4830 else
4831 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1_GT2,
4832 _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
4833 4984
4834 /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */ 4985 /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
4835 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1, 4986 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
@@ -4843,31 +4994,24 @@ static void ivybridge_init_clock_gating(struct drm_device *dev)
4843 if (IS_IVB_GT1(dev)) 4994 if (IS_IVB_GT1(dev))
4844 I915_WRITE(GEN7_ROW_CHICKEN2, 4995 I915_WRITE(GEN7_ROW_CHICKEN2,
4845 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE)); 4996 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
4846 else 4997 else {
4998 /* must write both registers */
4999 I915_WRITE(GEN7_ROW_CHICKEN2,
5000 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
4847 I915_WRITE(GEN7_ROW_CHICKEN2_GT2, 5001 I915_WRITE(GEN7_ROW_CHICKEN2_GT2,
4848 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE)); 5002 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
4849 5003 }
4850 5004
4851 /* WaForceL3Serialization:ivb */ 5005 /* WaForceL3Serialization:ivb */
4852 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) & 5006 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
4853 ~L3SQ_URB_READ_CAM_MATCH_DISABLE); 5007 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
4854 5008
4855 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock 5009 /*
4856 * gating disable must be set. Failure to set it results in
4857 * flickering pixels due to Z write ordering failures after
4858 * some amount of runtime in the Mesa "fire" demo, and Unigine
4859 * Sanctuary and Tropics, and apparently anything else with
4860 * alpha test or pixel discard.
4861 *
4862 * According to the spec, bit 11 (RCCUNIT) must also be set,
4863 * but we didn't debug actual testcases to find it out.
4864 *
4865 * According to the spec, bit 13 (RCZUNIT) must be set on IVB. 5010 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
4866 * This implements the WaDisableRCZUnitClockGating:ivb workaround. 5011 * This implements the WaDisableRCZUnitClockGating:ivb workaround.
4867 */ 5012 */
4868 I915_WRITE(GEN6_UCGCTL2, 5013 I915_WRITE(GEN6_UCGCTL2,
4869 GEN6_RCZUNIT_CLOCK_GATE_DISABLE | 5014 GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
4870 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
4871 5015
4872 /* This is required by WaCatErrorRejectionIssue:ivb */ 5016 /* This is required by WaCatErrorRejectionIssue:ivb */
4873 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG, 5017 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
@@ -4876,13 +5020,29 @@ static void ivybridge_init_clock_gating(struct drm_device *dev)
4876 5020
4877 g4x_disable_trickle_feed(dev); 5021 g4x_disable_trickle_feed(dev);
4878 5022
4879 /* WaVSRefCountFullforceMissDisable:ivb */
4880 gen7_setup_fixed_func_scheduler(dev_priv); 5023 gen7_setup_fixed_func_scheduler(dev_priv);
4881 5024
5025 if (0) { /* causes HiZ corruption on ivb:gt1 */
5026 /* enable HiZ Raw Stall Optimization */
5027 I915_WRITE(CACHE_MODE_0_GEN7,
5028 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
5029 }
5030
4882 /* WaDisable4x2SubspanOptimization:ivb */ 5031 /* WaDisable4x2SubspanOptimization:ivb */
4883 I915_WRITE(CACHE_MODE_1, 5032 I915_WRITE(CACHE_MODE_1,
4884 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE)); 5033 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
4885 5034
5035 /*
5036 * BSpec recommends 8x4 when MSAA is used,
5037 * however in practice 16x4 seems fastest.
5038 *
5039 * Note that PS/WM thread counts depend on the WIZ hashing
5040 * disable bit, which we don't touch here, but it's good
5041 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
5042 */
5043 I915_WRITE(GEN7_GT_MODE,
5044 GEN6_WIZ_HASHING_MASK | GEN6_WIZ_HASHING_16x4);
5045
4886 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR); 5046 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
4887 snpcr &= ~GEN6_MBC_SNPCR_MASK; 5047 snpcr &= ~GEN6_MBC_SNPCR_MASK;
4888 snpcr |= GEN6_MBC_SNPCR_MED; 5048 snpcr |= GEN6_MBC_SNPCR_MED;
@@ -4904,13 +5064,11 @@ static void valleyview_init_clock_gating(struct drm_device *dev)
4904 mutex_unlock(&dev_priv->rps.hw_lock); 5064 mutex_unlock(&dev_priv->rps.hw_lock);
4905 switch ((val >> 6) & 3) { 5065 switch ((val >> 6) & 3) {
4906 case 0: 5066 case 0:
4907 dev_priv->mem_freq = 800;
4908 break;
4909 case 1: 5067 case 1:
4910 dev_priv->mem_freq = 1066; 5068 dev_priv->mem_freq = 800;
4911 break; 5069 break;
4912 case 2: 5070 case 2:
4913 dev_priv->mem_freq = 1333; 5071 dev_priv->mem_freq = 1066;
4914 break; 5072 break;
4915 case 3: 5073 case 3:
4916 dev_priv->mem_freq = 1333; 5074 dev_priv->mem_freq = 1333;
@@ -4929,19 +5087,12 @@ static void valleyview_init_clock_gating(struct drm_device *dev)
4929 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE | 5087 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
4930 CHICKEN3_DGMG_DONE_FIX_DISABLE); 5088 CHICKEN3_DGMG_DONE_FIX_DISABLE);
4931 5089
5090 /* WaPsdDispatchEnable:vlv */
4932 /* WaDisablePSDDualDispatchEnable:vlv */ 5091 /* WaDisablePSDDualDispatchEnable:vlv */
4933 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1, 5092 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
4934 _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP | 5093 _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP |
4935 GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE)); 5094 GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
4936 5095
4937 /* Apply the WaDisableRHWOOptimizationForRenderHang:vlv workaround. */
4938 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
4939 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
4940
4941 /* WaApplyL3ControlAndL3ChickenMode:vlv */
4942 I915_WRITE(GEN7_L3CNTLREG1, I915_READ(GEN7_L3CNTLREG1) | GEN7_L3AGDIS);
4943 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER, GEN7_WA_L3_CHICKEN_MODE);
4944
4945 /* WaForceL3Serialization:vlv */ 5096 /* WaForceL3Serialization:vlv */
4946 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) & 5097 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
4947 ~L3SQ_URB_READ_CAM_MATCH_DISABLE); 5098 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
@@ -4955,51 +5106,39 @@ static void valleyview_init_clock_gating(struct drm_device *dev)
4955 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) | 5106 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
4956 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB); 5107 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
4957 5108
4958 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock 5109 gen7_setup_fixed_func_scheduler(dev_priv);
4959 * gating disable must be set. Failure to set it results in 5110
4960 * flickering pixels due to Z write ordering failures after 5111 /*
4961 * some amount of runtime in the Mesa "fire" demo, and Unigine
4962 * Sanctuary and Tropics, and apparently anything else with
4963 * alpha test or pixel discard.
4964 *
4965 * According to the spec, bit 11 (RCCUNIT) must also be set,
4966 * but we didn't debug actual testcases to find it out.
4967 *
4968 * According to the spec, bit 13 (RCZUNIT) must be set on IVB. 5112 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
4969 * This implements the WaDisableRCZUnitClockGating:vlv workaround. 5113 * This implements the WaDisableRCZUnitClockGating:vlv workaround.
4970 *
4971 * Also apply WaDisableVDSUnitClockGating:vlv and
4972 * WaDisableRCPBUnitClockGating:vlv.
4973 */ 5114 */
4974 I915_WRITE(GEN6_UCGCTL2, 5115 I915_WRITE(GEN6_UCGCTL2,
4975 GEN7_VDSUNIT_CLOCK_GATE_DISABLE | 5116 GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
4976 GEN7_TDLUNIT_CLOCK_GATE_DISABLE |
4977 GEN6_RCZUNIT_CLOCK_GATE_DISABLE |
4978 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
4979 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
4980 5117
5118 /* WaDisableL3Bank2xClockGate:vlv */
4981 I915_WRITE(GEN7_UCGCTL4, GEN7_L3BANK2X_CLOCK_GATE_DISABLE); 5119 I915_WRITE(GEN7_UCGCTL4, GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
4982 5120
4983 I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE); 5121 I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);
4984 5122
5123 /*
5124 * BSpec says this must be set, even though
5125 * WaDisable4x2SubspanOptimization isn't listed for VLV.
5126 */
4985 I915_WRITE(CACHE_MODE_1, 5127 I915_WRITE(CACHE_MODE_1,
4986 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE)); 5128 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
4987 5129
4988 /* 5130 /*
5131 * WaIncreaseL3CreditsForVLVB0:vlv
5132 * This is the hardware default actually.
5133 */
5134 I915_WRITE(GEN7_L3SQCREG1, VLV_B0_WA_L3SQCREG1_VALUE);
5135
5136 /*
4989 * WaDisableVLVClockGating_VBIIssue:vlv 5137 * WaDisableVLVClockGating_VBIIssue:vlv
4990 * Disable clock gating on th GCFG unit to prevent a delay 5138 * Disable clock gating on th GCFG unit to prevent a delay
4991 * in the reporting of vblank events. 5139 * in the reporting of vblank events.
4992 */ 5140 */
4993 I915_WRITE(VLV_GUNIT_CLOCK_GATE, 0xffffffff); 5141 I915_WRITE(VLV_GUNIT_CLOCK_GATE, GCFG_DIS);
4994
4995 /* Conservative clock gating settings for now */
4996 I915_WRITE(0x9400, 0xffffffff);
4997 I915_WRITE(0x9404, 0xffffffff);
4998 I915_WRITE(0x9408, 0xffffffff);
4999 I915_WRITE(0x940c, 0xffffffff);
5000 I915_WRITE(0x9410, 0xffffffff);
5001 I915_WRITE(0x9414, 0xffffffff);
5002 I915_WRITE(0x9418, 0xffffffff);
5003} 5142}
5004 5143
5005static void g4x_init_clock_gating(struct drm_device *dev) 5144static void g4x_init_clock_gating(struct drm_device *dev)
@@ -5114,19 +5253,16 @@ void intel_suspend_hw(struct drm_device *dev)
5114 * enable it, so check if it's enabled and also check if we've requested it to 5253 * enable it, so check if it's enabled and also check if we've requested it to
5115 * be enabled. 5254 * be enabled.
5116 */ 5255 */
5117static bool hsw_power_well_enabled(struct drm_device *dev, 5256static bool hsw_power_well_enabled(struct drm_i915_private *dev_priv,
5118 struct i915_power_well *power_well) 5257 struct i915_power_well *power_well)
5119{ 5258{
5120 struct drm_i915_private *dev_priv = dev->dev_private;
5121
5122 return I915_READ(HSW_PWR_WELL_DRIVER) == 5259 return I915_READ(HSW_PWR_WELL_DRIVER) ==
5123 (HSW_PWR_WELL_ENABLE_REQUEST | HSW_PWR_WELL_STATE_ENABLED); 5260 (HSW_PWR_WELL_ENABLE_REQUEST | HSW_PWR_WELL_STATE_ENABLED);
5124} 5261}
5125 5262
5126bool intel_display_power_enabled_sw(struct drm_device *dev, 5263bool intel_display_power_enabled_sw(struct drm_i915_private *dev_priv,
5127 enum intel_display_power_domain domain) 5264 enum intel_display_power_domain domain)
5128{ 5265{
5129 struct drm_i915_private *dev_priv = dev->dev_private;
5130 struct i915_power_domains *power_domains; 5266 struct i915_power_domains *power_domains;
5131 5267
5132 power_domains = &dev_priv->power_domains; 5268 power_domains = &dev_priv->power_domains;
@@ -5134,15 +5270,17 @@ bool intel_display_power_enabled_sw(struct drm_device *dev,
5134 return power_domains->domain_use_count[domain]; 5270 return power_domains->domain_use_count[domain];
5135} 5271}
5136 5272
5137bool intel_display_power_enabled(struct drm_device *dev, 5273bool intel_display_power_enabled(struct drm_i915_private *dev_priv,
5138 enum intel_display_power_domain domain) 5274 enum intel_display_power_domain domain)
5139{ 5275{
5140 struct drm_i915_private *dev_priv = dev->dev_private;
5141 struct i915_power_domains *power_domains; 5276 struct i915_power_domains *power_domains;
5142 struct i915_power_well *power_well; 5277 struct i915_power_well *power_well;
5143 bool is_enabled; 5278 bool is_enabled;
5144 int i; 5279 int i;
5145 5280
5281 if (dev_priv->pm.suspended)
5282 return false;
5283
5146 power_domains = &dev_priv->power_domains; 5284 power_domains = &dev_priv->power_domains;
5147 5285
5148 is_enabled = true; 5286 is_enabled = true;
@@ -5152,7 +5290,7 @@ bool intel_display_power_enabled(struct drm_device *dev,
5152 if (power_well->always_on) 5290 if (power_well->always_on)
5153 continue; 5291 continue;
5154 5292
5155 if (!power_well->is_enabled(dev, power_well)) { 5293 if (!power_well->ops->is_enabled(dev_priv, power_well)) {
5156 is_enabled = false; 5294 is_enabled = false;
5157 break; 5295 break;
5158 } 5296 }
@@ -5162,6 +5300,12 @@ bool intel_display_power_enabled(struct drm_device *dev,
5162 return is_enabled; 5300 return is_enabled;
5163} 5301}
5164 5302
5303/*
5304 * Starting with Haswell, we have a "Power Down Well" that can be turned off
5305 * when not needed anymore. We have 4 registers that can request the power well
5306 * to be enabled, and it will only be disabled if none of the registers is
5307 * requesting it to be enabled.
5308 */
5165static void hsw_power_well_post_enable(struct drm_i915_private *dev_priv) 5309static void hsw_power_well_post_enable(struct drm_i915_private *dev_priv)
5166{ 5310{
5167 struct drm_device *dev = dev_priv->dev; 5311 struct drm_device *dev = dev_priv->dev;
@@ -5198,10 +5342,17 @@ static void hsw_power_well_post_enable(struct drm_i915_private *dev_priv)
5198 } 5342 }
5199} 5343}
5200 5344
5345static void reset_vblank_counter(struct drm_device *dev, enum pipe pipe)
5346{
5347 assert_spin_locked(&dev->vbl_lock);
5348
5349 dev->vblank[pipe].last = 0;
5350}
5351
5201static void hsw_power_well_post_disable(struct drm_i915_private *dev_priv) 5352static void hsw_power_well_post_disable(struct drm_i915_private *dev_priv)
5202{ 5353{
5203 struct drm_device *dev = dev_priv->dev; 5354 struct drm_device *dev = dev_priv->dev;
5204 enum pipe p; 5355 enum pipe pipe;
5205 unsigned long irqflags; 5356 unsigned long irqflags;
5206 5357
5207 /* 5358 /*
@@ -5212,21 +5363,18 @@ static void hsw_power_well_post_disable(struct drm_i915_private *dev_priv)
5212 * FIXME: Should we do this in general in drm_vblank_post_modeset? 5363 * FIXME: Should we do this in general in drm_vblank_post_modeset?
5213 */ 5364 */
5214 spin_lock_irqsave(&dev->vbl_lock, irqflags); 5365 spin_lock_irqsave(&dev->vbl_lock, irqflags);
5215 for_each_pipe(p) 5366 for_each_pipe(pipe)
5216 if (p != PIPE_A) 5367 if (pipe != PIPE_A)
5217 dev->vblank[p].last = 0; 5368 reset_vblank_counter(dev, pipe);
5218 spin_unlock_irqrestore(&dev->vbl_lock, irqflags); 5369 spin_unlock_irqrestore(&dev->vbl_lock, irqflags);
5219} 5370}
5220 5371
5221static void hsw_set_power_well(struct drm_device *dev, 5372static void hsw_set_power_well(struct drm_i915_private *dev_priv,
5222 struct i915_power_well *power_well, bool enable) 5373 struct i915_power_well *power_well, bool enable)
5223{ 5374{
5224 struct drm_i915_private *dev_priv = dev->dev_private;
5225 bool is_enabled, enable_requested; 5375 bool is_enabled, enable_requested;
5226 uint32_t tmp; 5376 uint32_t tmp;
5227 5377
5228 WARN_ON(dev_priv->pc8.enabled);
5229
5230 tmp = I915_READ(HSW_PWR_WELL_DRIVER); 5378 tmp = I915_READ(HSW_PWR_WELL_DRIVER);
5231 is_enabled = tmp & HSW_PWR_WELL_STATE_ENABLED; 5379 is_enabled = tmp & HSW_PWR_WELL_STATE_ENABLED;
5232 enable_requested = tmp & HSW_PWR_WELL_ENABLE_REQUEST; 5380 enable_requested = tmp & HSW_PWR_WELL_ENABLE_REQUEST;
@@ -5255,55 +5403,229 @@ static void hsw_set_power_well(struct drm_device *dev,
5255 } 5403 }
5256} 5404}
5257 5405
5258static void __intel_power_well_get(struct drm_device *dev, 5406static void hsw_power_well_sync_hw(struct drm_i915_private *dev_priv,
5259 struct i915_power_well *power_well) 5407 struct i915_power_well *power_well)
5260{ 5408{
5261 struct drm_i915_private *dev_priv = dev->dev_private; 5409 hsw_set_power_well(dev_priv, power_well, power_well->count > 0);
5262 5410
5263 if (!power_well->count++ && power_well->set) { 5411 /*
5264 hsw_disable_package_c8(dev_priv); 5412 * We're taking over the BIOS, so clear any requests made by it since
5265 power_well->set(dev, power_well, true); 5413 * the driver is in charge now.
5266 } 5414 */
5415 if (I915_READ(HSW_PWR_WELL_BIOS) & HSW_PWR_WELL_ENABLE_REQUEST)
5416 I915_WRITE(HSW_PWR_WELL_BIOS, 0);
5417}
5418
5419static void hsw_power_well_enable(struct drm_i915_private *dev_priv,
5420 struct i915_power_well *power_well)
5421{
5422 hsw_set_power_well(dev_priv, power_well, true);
5267} 5423}
5268 5424
5269static void __intel_power_well_put(struct drm_device *dev, 5425static void hsw_power_well_disable(struct drm_i915_private *dev_priv,
5270 struct i915_power_well *power_well) 5426 struct i915_power_well *power_well)
5271{ 5427{
5272 struct drm_i915_private *dev_priv = dev->dev_private; 5428 hsw_set_power_well(dev_priv, power_well, false);
5429}
5430
5431static void i9xx_always_on_power_well_noop(struct drm_i915_private *dev_priv,
5432 struct i915_power_well *power_well)
5433{
5434}
5435
5436static bool i9xx_always_on_power_well_enabled(struct drm_i915_private *dev_priv,
5437 struct i915_power_well *power_well)
5438{
5439 return true;
5440}
5441
5442static void vlv_set_power_well(struct drm_i915_private *dev_priv,
5443 struct i915_power_well *power_well, bool enable)
5444{
5445 enum punit_power_well power_well_id = power_well->data;
5446 u32 mask;
5447 u32 state;
5448 u32 ctrl;
5449
5450 mask = PUNIT_PWRGT_MASK(power_well_id);
5451 state = enable ? PUNIT_PWRGT_PWR_ON(power_well_id) :
5452 PUNIT_PWRGT_PWR_GATE(power_well_id);
5453
5454 mutex_lock(&dev_priv->rps.hw_lock);
5455
5456#define COND \
5457 ((vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask) == state)
5458
5459 if (COND)
5460 goto out;
5461
5462 ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL);
5463 ctrl &= ~mask;
5464 ctrl |= state;
5465 vlv_punit_write(dev_priv, PUNIT_REG_PWRGT_CTRL, ctrl);
5466
5467 if (wait_for(COND, 100))
5468 DRM_ERROR("timout setting power well state %08x (%08x)\n",
5469 state,
5470 vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL));
5471
5472#undef COND
5473
5474out:
5475 mutex_unlock(&dev_priv->rps.hw_lock);
5476}
5477
5478static void vlv_power_well_sync_hw(struct drm_i915_private *dev_priv,
5479 struct i915_power_well *power_well)
5480{
5481 vlv_set_power_well(dev_priv, power_well, power_well->count > 0);
5482}
5483
5484static void vlv_power_well_enable(struct drm_i915_private *dev_priv,
5485 struct i915_power_well *power_well)
5486{
5487 vlv_set_power_well(dev_priv, power_well, true);
5488}
5489
5490static void vlv_power_well_disable(struct drm_i915_private *dev_priv,
5491 struct i915_power_well *power_well)
5492{
5493 vlv_set_power_well(dev_priv, power_well, false);
5494}
5495
5496static bool vlv_power_well_enabled(struct drm_i915_private *dev_priv,
5497 struct i915_power_well *power_well)
5498{
5499 int power_well_id = power_well->data;
5500 bool enabled = false;
5501 u32 mask;
5502 u32 state;
5503 u32 ctrl;
5504
5505 mask = PUNIT_PWRGT_MASK(power_well_id);
5506 ctrl = PUNIT_PWRGT_PWR_ON(power_well_id);
5507
5508 mutex_lock(&dev_priv->rps.hw_lock);
5509
5510 state = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask;
5511 /*
5512 * We only ever set the power-on and power-gate states, anything
5513 * else is unexpected.
5514 */
5515 WARN_ON(state != PUNIT_PWRGT_PWR_ON(power_well_id) &&
5516 state != PUNIT_PWRGT_PWR_GATE(power_well_id));
5517 if (state == ctrl)
5518 enabled = true;
5519
5520 /*
5521 * A transient state at this point would mean some unexpected party
5522 * is poking at the power controls too.
5523 */
5524 ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL) & mask;
5525 WARN_ON(ctrl != state);
5526
5527 mutex_unlock(&dev_priv->rps.hw_lock);
5528
5529 return enabled;
5530}
5273 5531
5274 WARN_ON(!power_well->count); 5532static void vlv_display_power_well_enable(struct drm_i915_private *dev_priv,
5533 struct i915_power_well *power_well)
5534{
5535 WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DISP2D);
5536
5537 vlv_set_power_well(dev_priv, power_well, true);
5538
5539 spin_lock_irq(&dev_priv->irq_lock);
5540 valleyview_enable_display_irqs(dev_priv);
5541 spin_unlock_irq(&dev_priv->irq_lock);
5542
5543 /*
5544 * During driver initialization we need to defer enabling hotplug
5545 * processing until fbdev is set up.
5546 */
5547 if (dev_priv->enable_hotplug_processing)
5548 intel_hpd_init(dev_priv->dev);
5549
5550 i915_redisable_vga_power_on(dev_priv->dev);
5551}
5552
5553static void vlv_display_power_well_disable(struct drm_i915_private *dev_priv,
5554 struct i915_power_well *power_well)
5555{
5556 struct drm_device *dev = dev_priv->dev;
5557 enum pipe pipe;
5558
5559 WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DISP2D);
5560
5561 spin_lock_irq(&dev_priv->irq_lock);
5562 for_each_pipe(pipe)
5563 __intel_set_cpu_fifo_underrun_reporting(dev, pipe, false);
5564
5565 valleyview_disable_display_irqs(dev_priv);
5566 spin_unlock_irq(&dev_priv->irq_lock);
5567
5568 spin_lock_irq(&dev->vbl_lock);
5569 for_each_pipe(pipe)
5570 reset_vblank_counter(dev, pipe);
5571 spin_unlock_irq(&dev->vbl_lock);
5572
5573 vlv_set_power_well(dev_priv, power_well, false);
5574}
5275 5575
5276 if (!--power_well->count && power_well->set && 5576static void check_power_well_state(struct drm_i915_private *dev_priv,
5277 i915_disable_power_well) { 5577 struct i915_power_well *power_well)
5278 power_well->set(dev, power_well, false); 5578{
5279 hsw_enable_package_c8(dev_priv); 5579 bool enabled = power_well->ops->is_enabled(dev_priv, power_well);
5580
5581 if (power_well->always_on || !i915.disable_power_well) {
5582 if (!enabled)
5583 goto mismatch;
5584
5585 return;
5280 } 5586 }
5587
5588 if (enabled != (power_well->count > 0))
5589 goto mismatch;
5590
5591 return;
5592
5593mismatch:
5594 WARN(1, "state mismatch for '%s' (always_on %d hw state %d use-count %d disable_power_well %d\n",
5595 power_well->name, power_well->always_on, enabled,
5596 power_well->count, i915.disable_power_well);
5281} 5597}
5282 5598
5283void intel_display_power_get(struct drm_device *dev, 5599void intel_display_power_get(struct drm_i915_private *dev_priv,
5284 enum intel_display_power_domain domain) 5600 enum intel_display_power_domain domain)
5285{ 5601{
5286 struct drm_i915_private *dev_priv = dev->dev_private;
5287 struct i915_power_domains *power_domains; 5602 struct i915_power_domains *power_domains;
5288 struct i915_power_well *power_well; 5603 struct i915_power_well *power_well;
5289 int i; 5604 int i;
5290 5605
5606 intel_runtime_pm_get(dev_priv);
5607
5291 power_domains = &dev_priv->power_domains; 5608 power_domains = &dev_priv->power_domains;
5292 5609
5293 mutex_lock(&power_domains->lock); 5610 mutex_lock(&power_domains->lock);
5294 5611
5295 for_each_power_well(i, power_well, BIT(domain), power_domains) 5612 for_each_power_well(i, power_well, BIT(domain), power_domains) {
5296 __intel_power_well_get(dev, power_well); 5613 if (!power_well->count++) {
5614 DRM_DEBUG_KMS("enabling %s\n", power_well->name);
5615 power_well->ops->enable(dev_priv, power_well);
5616 }
5617
5618 check_power_well_state(dev_priv, power_well);
5619 }
5297 5620
5298 power_domains->domain_use_count[domain]++; 5621 power_domains->domain_use_count[domain]++;
5299 5622
5300 mutex_unlock(&power_domains->lock); 5623 mutex_unlock(&power_domains->lock);
5301} 5624}
5302 5625
5303void intel_display_power_put(struct drm_device *dev, 5626void intel_display_power_put(struct drm_i915_private *dev_priv,
5304 enum intel_display_power_domain domain) 5627 enum intel_display_power_domain domain)
5305{ 5628{
5306 struct drm_i915_private *dev_priv = dev->dev_private;
5307 struct i915_power_domains *power_domains; 5629 struct i915_power_domains *power_domains;
5308 struct i915_power_well *power_well; 5630 struct i915_power_well *power_well;
5309 int i; 5631 int i;
@@ -5315,10 +5637,20 @@ void intel_display_power_put(struct drm_device *dev,
5315 WARN_ON(!power_domains->domain_use_count[domain]); 5637 WARN_ON(!power_domains->domain_use_count[domain]);
5316 power_domains->domain_use_count[domain]--; 5638 power_domains->domain_use_count[domain]--;
5317 5639
5318 for_each_power_well_rev(i, power_well, BIT(domain), power_domains) 5640 for_each_power_well_rev(i, power_well, BIT(domain), power_domains) {
5319 __intel_power_well_put(dev, power_well); 5641 WARN_ON(!power_well->count);
5642
5643 if (!--power_well->count && i915.disable_power_well) {
5644 DRM_DEBUG_KMS("disabling %s\n", power_well->name);
5645 power_well->ops->disable(dev_priv, power_well);
5646 }
5647
5648 check_power_well_state(dev_priv, power_well);
5649 }
5320 5650
5321 mutex_unlock(&power_domains->lock); 5651 mutex_unlock(&power_domains->lock);
5652
5653 intel_runtime_pm_put(dev_priv);
5322} 5654}
5323 5655
5324static struct i915_power_domains *hsw_pwr; 5656static struct i915_power_domains *hsw_pwr;
@@ -5333,7 +5665,7 @@ void i915_request_power_well(void)
5333 5665
5334 dev_priv = container_of(hsw_pwr, struct drm_i915_private, 5666 dev_priv = container_of(hsw_pwr, struct drm_i915_private,
5335 power_domains); 5667 power_domains);
5336 intel_display_power_get(dev_priv->dev, POWER_DOMAIN_AUDIO); 5668 intel_display_power_get(dev_priv, POWER_DOMAIN_AUDIO);
5337} 5669}
5338EXPORT_SYMBOL_GPL(i915_request_power_well); 5670EXPORT_SYMBOL_GPL(i915_request_power_well);
5339 5671
@@ -5347,29 +5679,99 @@ void i915_release_power_well(void)
5347 5679
5348 dev_priv = container_of(hsw_pwr, struct drm_i915_private, 5680 dev_priv = container_of(hsw_pwr, struct drm_i915_private,
5349 power_domains); 5681 power_domains);
5350 intel_display_power_put(dev_priv->dev, POWER_DOMAIN_AUDIO); 5682 intel_display_power_put(dev_priv, POWER_DOMAIN_AUDIO);
5351} 5683}
5352EXPORT_SYMBOL_GPL(i915_release_power_well); 5684EXPORT_SYMBOL_GPL(i915_release_power_well);
5353 5685
5686#define POWER_DOMAIN_MASK (BIT(POWER_DOMAIN_NUM) - 1)
5687
5688#define HSW_ALWAYS_ON_POWER_DOMAINS ( \
5689 BIT(POWER_DOMAIN_PIPE_A) | \
5690 BIT(POWER_DOMAIN_TRANSCODER_EDP) | \
5691 BIT(POWER_DOMAIN_PORT_DDI_A_2_LANES) | \
5692 BIT(POWER_DOMAIN_PORT_DDI_A_4_LANES) | \
5693 BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \
5694 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
5695 BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \
5696 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
5697 BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) | \
5698 BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \
5699 BIT(POWER_DOMAIN_PORT_CRT) | \
5700 BIT(POWER_DOMAIN_INIT))
5701#define HSW_DISPLAY_POWER_DOMAINS ( \
5702 (POWER_DOMAIN_MASK & ~HSW_ALWAYS_ON_POWER_DOMAINS) | \
5703 BIT(POWER_DOMAIN_INIT))
5704
5705#define BDW_ALWAYS_ON_POWER_DOMAINS ( \
5706 HSW_ALWAYS_ON_POWER_DOMAINS | \
5707 BIT(POWER_DOMAIN_PIPE_A_PANEL_FITTER))
5708#define BDW_DISPLAY_POWER_DOMAINS ( \
5709 (POWER_DOMAIN_MASK & ~BDW_ALWAYS_ON_POWER_DOMAINS) | \
5710 BIT(POWER_DOMAIN_INIT))
5711
5712#define VLV_ALWAYS_ON_POWER_DOMAINS BIT(POWER_DOMAIN_INIT)
5713#define VLV_DISPLAY_POWER_DOMAINS POWER_DOMAIN_MASK
5714
5715#define VLV_DPIO_CMN_BC_POWER_DOMAINS ( \
5716 BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \
5717 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
5718 BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \
5719 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
5720 BIT(POWER_DOMAIN_PORT_CRT) | \
5721 BIT(POWER_DOMAIN_INIT))
5722
5723#define VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS ( \
5724 BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \
5725 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
5726 BIT(POWER_DOMAIN_INIT))
5727
5728#define VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS ( \
5729 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
5730 BIT(POWER_DOMAIN_INIT))
5731
5732#define VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS ( \
5733 BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \
5734 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
5735 BIT(POWER_DOMAIN_INIT))
5736
5737#define VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS ( \
5738 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
5739 BIT(POWER_DOMAIN_INIT))
5740
5741static const struct i915_power_well_ops i9xx_always_on_power_well_ops = {
5742 .sync_hw = i9xx_always_on_power_well_noop,
5743 .enable = i9xx_always_on_power_well_noop,
5744 .disable = i9xx_always_on_power_well_noop,
5745 .is_enabled = i9xx_always_on_power_well_enabled,
5746};
5747
5354static struct i915_power_well i9xx_always_on_power_well[] = { 5748static struct i915_power_well i9xx_always_on_power_well[] = {
5355 { 5749 {
5356 .name = "always-on", 5750 .name = "always-on",
5357 .always_on = 1, 5751 .always_on = 1,
5358 .domains = POWER_DOMAIN_MASK, 5752 .domains = POWER_DOMAIN_MASK,
5753 .ops = &i9xx_always_on_power_well_ops,
5359 }, 5754 },
5360}; 5755};
5361 5756
5757static const struct i915_power_well_ops hsw_power_well_ops = {
5758 .sync_hw = hsw_power_well_sync_hw,
5759 .enable = hsw_power_well_enable,
5760 .disable = hsw_power_well_disable,
5761 .is_enabled = hsw_power_well_enabled,
5762};
5763
5362static struct i915_power_well hsw_power_wells[] = { 5764static struct i915_power_well hsw_power_wells[] = {
5363 { 5765 {
5364 .name = "always-on", 5766 .name = "always-on",
5365 .always_on = 1, 5767 .always_on = 1,
5366 .domains = HSW_ALWAYS_ON_POWER_DOMAINS, 5768 .domains = HSW_ALWAYS_ON_POWER_DOMAINS,
5769 .ops = &i9xx_always_on_power_well_ops,
5367 }, 5770 },
5368 { 5771 {
5369 .name = "display", 5772 .name = "display",
5370 .domains = POWER_DOMAIN_MASK & ~HSW_ALWAYS_ON_POWER_DOMAINS, 5773 .domains = HSW_DISPLAY_POWER_DOMAINS,
5371 .is_enabled = hsw_power_well_enabled, 5774 .ops = &hsw_power_well_ops,
5372 .set = hsw_set_power_well,
5373 }, 5775 },
5374}; 5776};
5375 5777
@@ -5378,12 +5780,83 @@ static struct i915_power_well bdw_power_wells[] = {
5378 .name = "always-on", 5780 .name = "always-on",
5379 .always_on = 1, 5781 .always_on = 1,
5380 .domains = BDW_ALWAYS_ON_POWER_DOMAINS, 5782 .domains = BDW_ALWAYS_ON_POWER_DOMAINS,
5783 .ops = &i9xx_always_on_power_well_ops,
5381 }, 5784 },
5382 { 5785 {
5383 .name = "display", 5786 .name = "display",
5384 .domains = POWER_DOMAIN_MASK & ~BDW_ALWAYS_ON_POWER_DOMAINS, 5787 .domains = BDW_DISPLAY_POWER_DOMAINS,
5385 .is_enabled = hsw_power_well_enabled, 5788 .ops = &hsw_power_well_ops,
5386 .set = hsw_set_power_well, 5789 },
5790};
5791
5792static const struct i915_power_well_ops vlv_display_power_well_ops = {
5793 .sync_hw = vlv_power_well_sync_hw,
5794 .enable = vlv_display_power_well_enable,
5795 .disable = vlv_display_power_well_disable,
5796 .is_enabled = vlv_power_well_enabled,
5797};
5798
5799static const struct i915_power_well_ops vlv_dpio_power_well_ops = {
5800 .sync_hw = vlv_power_well_sync_hw,
5801 .enable = vlv_power_well_enable,
5802 .disable = vlv_power_well_disable,
5803 .is_enabled = vlv_power_well_enabled,
5804};
5805
5806static struct i915_power_well vlv_power_wells[] = {
5807 {
5808 .name = "always-on",
5809 .always_on = 1,
5810 .domains = VLV_ALWAYS_ON_POWER_DOMAINS,
5811 .ops = &i9xx_always_on_power_well_ops,
5812 },
5813 {
5814 .name = "display",
5815 .domains = VLV_DISPLAY_POWER_DOMAINS,
5816 .data = PUNIT_POWER_WELL_DISP2D,
5817 .ops = &vlv_display_power_well_ops,
5818 },
5819 {
5820 .name = "dpio-common",
5821 .domains = VLV_DPIO_CMN_BC_POWER_DOMAINS,
5822 .data = PUNIT_POWER_WELL_DPIO_CMN_BC,
5823 .ops = &vlv_dpio_power_well_ops,
5824 },
5825 {
5826 .name = "dpio-tx-b-01",
5827 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
5828 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
5829 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
5830 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
5831 .ops = &vlv_dpio_power_well_ops,
5832 .data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_01,
5833 },
5834 {
5835 .name = "dpio-tx-b-23",
5836 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
5837 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
5838 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
5839 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
5840 .ops = &vlv_dpio_power_well_ops,
5841 .data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_23,
5842 },
5843 {
5844 .name = "dpio-tx-c-01",
5845 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
5846 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
5847 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
5848 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
5849 .ops = &vlv_dpio_power_well_ops,
5850 .data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_01,
5851 },
5852 {
5853 .name = "dpio-tx-c-23",
5854 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
5855 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
5856 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
5857 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
5858 .ops = &vlv_dpio_power_well_ops,
5859 .data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_23,
5387 }, 5860 },
5388}; 5861};
5389 5862
@@ -5392,9 +5865,8 @@ static struct i915_power_well bdw_power_wells[] = {
5392 (power_domains)->power_well_count = ARRAY_SIZE(__power_wells); \ 5865 (power_domains)->power_well_count = ARRAY_SIZE(__power_wells); \
5393}) 5866})
5394 5867
5395int intel_power_domains_init(struct drm_device *dev) 5868int intel_power_domains_init(struct drm_i915_private *dev_priv)
5396{ 5869{
5397 struct drm_i915_private *dev_priv = dev->dev_private;
5398 struct i915_power_domains *power_domains = &dev_priv->power_domains; 5870 struct i915_power_domains *power_domains = &dev_priv->power_domains;
5399 5871
5400 mutex_init(&power_domains->lock); 5872 mutex_init(&power_domains->lock);
@@ -5403,12 +5875,14 @@ int intel_power_domains_init(struct drm_device *dev)
5403 * The enabling order will be from lower to higher indexed wells, 5875 * The enabling order will be from lower to higher indexed wells,
5404 * the disabling order is reversed. 5876 * the disabling order is reversed.
5405 */ 5877 */
5406 if (IS_HASWELL(dev)) { 5878 if (IS_HASWELL(dev_priv->dev)) {
5407 set_power_wells(power_domains, hsw_power_wells); 5879 set_power_wells(power_domains, hsw_power_wells);
5408 hsw_pwr = power_domains; 5880 hsw_pwr = power_domains;
5409 } else if (IS_BROADWELL(dev)) { 5881 } else if (IS_BROADWELL(dev_priv->dev)) {
5410 set_power_wells(power_domains, bdw_power_wells); 5882 set_power_wells(power_domains, bdw_power_wells);
5411 hsw_pwr = power_domains; 5883 hsw_pwr = power_domains;
5884 } else if (IS_VALLEYVIEW(dev_priv->dev)) {
5885 set_power_wells(power_domains, vlv_power_wells);
5412 } else { 5886 } else {
5413 set_power_wells(power_domains, i9xx_always_on_power_well); 5887 set_power_wells(power_domains, i9xx_always_on_power_well);
5414 } 5888 }
@@ -5416,58 +5890,38 @@ int intel_power_domains_init(struct drm_device *dev)
5416 return 0; 5890 return 0;
5417} 5891}
5418 5892
5419void intel_power_domains_remove(struct drm_device *dev) 5893void intel_power_domains_remove(struct drm_i915_private *dev_priv)
5420{ 5894{
5421 hsw_pwr = NULL; 5895 hsw_pwr = NULL;
5422} 5896}
5423 5897
5424static void intel_power_domains_resume(struct drm_device *dev) 5898static void intel_power_domains_resume(struct drm_i915_private *dev_priv)
5425{ 5899{
5426 struct drm_i915_private *dev_priv = dev->dev_private;
5427 struct i915_power_domains *power_domains = &dev_priv->power_domains; 5900 struct i915_power_domains *power_domains = &dev_priv->power_domains;
5428 struct i915_power_well *power_well; 5901 struct i915_power_well *power_well;
5429 int i; 5902 int i;
5430 5903
5431 mutex_lock(&power_domains->lock); 5904 mutex_lock(&power_domains->lock);
5432 for_each_power_well(i, power_well, POWER_DOMAIN_MASK, power_domains) { 5905 for_each_power_well(i, power_well, POWER_DOMAIN_MASK, power_domains)
5433 if (power_well->set) 5906 power_well->ops->sync_hw(dev_priv, power_well);
5434 power_well->set(dev, power_well, power_well->count > 0);
5435 }
5436 mutex_unlock(&power_domains->lock); 5907 mutex_unlock(&power_domains->lock);
5437} 5908}
5438 5909
5439/* 5910void intel_power_domains_init_hw(struct drm_i915_private *dev_priv)
5440 * Starting with Haswell, we have a "Power Down Well" that can be turned off
5441 * when not needed anymore. We have 4 registers that can request the power well
5442 * to be enabled, and it will only be disabled if none of the registers is
5443 * requesting it to be enabled.
5444 */
5445void intel_power_domains_init_hw(struct drm_device *dev)
5446{ 5911{
5447 struct drm_i915_private *dev_priv = dev->dev_private;
5448
5449 /* For now, we need the power well to be always enabled. */ 5912 /* For now, we need the power well to be always enabled. */
5450 intel_display_set_init_power(dev, true); 5913 intel_display_set_init_power(dev_priv, true);
5451 intel_power_domains_resume(dev); 5914 intel_power_domains_resume(dev_priv);
5452
5453 if (!(IS_HASWELL(dev) || IS_BROADWELL(dev)))
5454 return;
5455
5456 /* We're taking over the BIOS, so clear any requests made by it since
5457 * the driver is in charge now. */
5458 if (I915_READ(HSW_PWR_WELL_BIOS) & HSW_PWR_WELL_ENABLE_REQUEST)
5459 I915_WRITE(HSW_PWR_WELL_BIOS, 0);
5460} 5915}
5461 5916
5462/* Disables PC8 so we can use the GMBUS and DP AUX interrupts. */
5463void intel_aux_display_runtime_get(struct drm_i915_private *dev_priv) 5917void intel_aux_display_runtime_get(struct drm_i915_private *dev_priv)
5464{ 5918{
5465 hsw_disable_package_c8(dev_priv); 5919 intel_runtime_pm_get(dev_priv);
5466} 5920}
5467 5921
5468void intel_aux_display_runtime_put(struct drm_i915_private *dev_priv) 5922void intel_aux_display_runtime_put(struct drm_i915_private *dev_priv)
5469{ 5923{
5470 hsw_enable_package_c8(dev_priv); 5924 intel_runtime_pm_put(dev_priv);
5471} 5925}
5472 5926
5473void intel_runtime_pm_get(struct drm_i915_private *dev_priv) 5927void intel_runtime_pm_get(struct drm_i915_private *dev_priv)
@@ -5499,8 +5953,6 @@ void intel_init_runtime_pm(struct drm_i915_private *dev_priv)
5499 struct drm_device *dev = dev_priv->dev; 5953 struct drm_device *dev = dev_priv->dev;
5500 struct device *device = &dev->pdev->dev; 5954 struct device *device = &dev->pdev->dev;
5501 5955
5502 dev_priv->pm.suspended = false;
5503
5504 if (!HAS_RUNTIME_PM(dev)) 5956 if (!HAS_RUNTIME_PM(dev))
5505 return; 5957 return;
5506 5958
@@ -5509,6 +5961,8 @@ void intel_init_runtime_pm(struct drm_i915_private *dev_priv)
5509 pm_runtime_set_autosuspend_delay(device, 10000); /* 10s */ 5961 pm_runtime_set_autosuspend_delay(device, 10000); /* 10s */
5510 pm_runtime_mark_last_busy(device); 5962 pm_runtime_mark_last_busy(device);
5511 pm_runtime_use_autosuspend(device); 5963 pm_runtime_use_autosuspend(device);
5964
5965 pm_runtime_put_autosuspend(device);
5512} 5966}
5513 5967
5514void intel_fini_runtime_pm(struct drm_i915_private *dev_priv) 5968void intel_fini_runtime_pm(struct drm_i915_private *dev_priv)
@@ -5560,7 +6014,7 @@ void intel_init_pm(struct drm_device *dev)
5560 6014
5561 /* For FIFO watermark updates */ 6015 /* For FIFO watermark updates */
5562 if (HAS_PCH_SPLIT(dev)) { 6016 if (HAS_PCH_SPLIT(dev)) {
5563 intel_setup_wm_latency(dev); 6017 ilk_setup_wm_latency(dev);
5564 6018
5565 if ((IS_GEN5(dev) && dev_priv->wm.pri_latency[1] && 6019 if ((IS_GEN5(dev) && dev_priv->wm.pri_latency[1] &&
5566 dev_priv->wm.spr_latency[1] && dev_priv->wm.cur_latency[1]) || 6020 dev_priv->wm.spr_latency[1] && dev_priv->wm.cur_latency[1]) ||
@@ -5731,13 +6185,9 @@ void intel_pm_setup(struct drm_device *dev)
5731 6185
5732 mutex_init(&dev_priv->rps.hw_lock); 6186 mutex_init(&dev_priv->rps.hw_lock);
5733 6187
5734 mutex_init(&dev_priv->pc8.lock);
5735 dev_priv->pc8.requirements_met = false;
5736 dev_priv->pc8.gpu_idle = false;
5737 dev_priv->pc8.irqs_disabled = false;
5738 dev_priv->pc8.enabled = false;
5739 dev_priv->pc8.disable_count = 2; /* requirements_met + gpu_idle */
5740 INIT_DELAYED_WORK(&dev_priv->pc8.enable_work, hsw_enable_pc8_work);
5741 INIT_DELAYED_WORK(&dev_priv->rps.delayed_resume_work, 6188 INIT_DELAYED_WORK(&dev_priv->rps.delayed_resume_work,
5742 intel_gen6_powersave_work); 6189 intel_gen6_powersave_work);
6190
6191 dev_priv->pm.suspended = false;
6192 dev_priv->pm.irqs_disabled = false;
5743} 6193}
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-06 05:24:22 -0500