diff options
Diffstat (limited to 'drivers/gpu/drm/i915/intel_pm.c')
-rw-r--r-- | drivers/gpu/drm/i915/intel_pm.c | 29 |
1 files changed, 27 insertions, 2 deletions
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 6e0d5e075b15..3657ab43c8fd 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c | |||
@@ -5685,6 +5685,7 @@ static void __intel_set_power_well(struct drm_device *dev, bool enable) | |||
5685 | { | 5685 | { |
5686 | struct drm_i915_private *dev_priv = dev->dev_private; | 5686 | struct drm_i915_private *dev_priv = dev->dev_private; |
5687 | bool is_enabled, enable_requested; | 5687 | bool is_enabled, enable_requested; |
5688 | unsigned long irqflags; | ||
5688 | uint32_t tmp; | 5689 | uint32_t tmp; |
5689 | 5690 | ||
5690 | tmp = I915_READ(HSW_PWR_WELL_DRIVER); | 5691 | tmp = I915_READ(HSW_PWR_WELL_DRIVER); |
@@ -5702,9 +5703,24 @@ static void __intel_set_power_well(struct drm_device *dev, bool enable) | |||
5702 | HSW_PWR_WELL_STATE_ENABLED), 20)) | 5703 | HSW_PWR_WELL_STATE_ENABLED), 20)) |
5703 | DRM_ERROR("Timeout enabling power well\n"); | 5704 | DRM_ERROR("Timeout enabling power well\n"); |
5704 | } | 5705 | } |
5706 | |||
5707 | if (IS_BROADWELL(dev)) { | ||
5708 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | ||
5709 | I915_WRITE(GEN8_DE_PIPE_IMR(PIPE_B), | ||
5710 | dev_priv->de_irq_mask[PIPE_B]); | ||
5711 | I915_WRITE(GEN8_DE_PIPE_IER(PIPE_B), | ||
5712 | ~dev_priv->de_irq_mask[PIPE_B] | | ||
5713 | GEN8_PIPE_VBLANK); | ||
5714 | I915_WRITE(GEN8_DE_PIPE_IMR(PIPE_C), | ||
5715 | dev_priv->de_irq_mask[PIPE_C]); | ||
5716 | I915_WRITE(GEN8_DE_PIPE_IER(PIPE_C), | ||
5717 | ~dev_priv->de_irq_mask[PIPE_C] | | ||
5718 | GEN8_PIPE_VBLANK); | ||
5719 | POSTING_READ(GEN8_DE_PIPE_IER(PIPE_C)); | ||
5720 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); | ||
5721 | } | ||
5705 | } else { | 5722 | } else { |
5706 | if (enable_requested) { | 5723 | if (enable_requested) { |
5707 | unsigned long irqflags; | ||
5708 | enum pipe p; | 5724 | enum pipe p; |
5709 | 5725 | ||
5710 | I915_WRITE(HSW_PWR_WELL_DRIVER, 0); | 5726 | I915_WRITE(HSW_PWR_WELL_DRIVER, 0); |
@@ -6130,10 +6146,19 @@ int vlv_freq_opcode(int ddr_freq, int val) | |||
6130 | return val; | 6146 | return val; |
6131 | } | 6147 | } |
6132 | 6148 | ||
6133 | void intel_pm_init(struct drm_device *dev) | 6149 | void intel_pm_setup(struct drm_device *dev) |
6134 | { | 6150 | { |
6135 | struct drm_i915_private *dev_priv = dev->dev_private; | 6151 | struct drm_i915_private *dev_priv = dev->dev_private; |
6136 | 6152 | ||
6153 | mutex_init(&dev_priv->rps.hw_lock); | ||
6154 | |||
6155 | mutex_init(&dev_priv->pc8.lock); | ||
6156 | dev_priv->pc8.requirements_met = false; | ||
6157 | dev_priv->pc8.gpu_idle = false; | ||
6158 | dev_priv->pc8.irqs_disabled = false; | ||
6159 | dev_priv->pc8.enabled = false; | ||
6160 | dev_priv->pc8.disable_count = 2; /* requirements_met + gpu_idle */ | ||
6161 | INIT_DELAYED_WORK(&dev_priv->pc8.enable_work, hsw_enable_pc8_work); | ||
6137 | INIT_DELAYED_WORK(&dev_priv->rps.delayed_resume_work, | 6162 | INIT_DELAYED_WORK(&dev_priv->rps.delayed_resume_work, |
6138 | intel_gen6_powersave_work); | 6163 | intel_gen6_powersave_work); |
6139 | } | 6164 | } |