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path: root/drivers/gpu/drm/i915/intel_pm.c
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Diffstat (limited to 'drivers/gpu/drm/i915/intel_pm.c')
-rw-r--r--drivers/gpu/drm/i915/intel_pm.c7
1 files changed, 4 insertions, 3 deletions
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index fe19ba3360a7..0d7e2d324f1b 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3788,7 +3788,7 @@ static void valleyview_enable_rps(struct drm_device *dev)
3788{ 3788{
3789 struct drm_i915_private *dev_priv = dev->dev_private; 3789 struct drm_i915_private *dev_priv = dev->dev_private;
3790 struct intel_ring_buffer *ring; 3790 struct intel_ring_buffer *ring;
3791 u32 gtfifodbg, val; 3791 u32 gtfifodbg, val, rc6_mode = 0;
3792 int i; 3792 int i;
3793 3793
3794 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); 3794 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
@@ -3828,8 +3828,9 @@ static void valleyview_enable_rps(struct drm_device *dev)
3828 3828
3829 /* allows RC6 residency counter to work */ 3829 /* allows RC6 residency counter to work */
3830 I915_WRITE(0x138104, _MASKED_BIT_ENABLE(0x3)); 3830 I915_WRITE(0x138104, _MASKED_BIT_ENABLE(0x3));
3831 I915_WRITE(GEN6_RC_CONTROL, 3831 if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
3832 GEN7_RC_CTL_TO_MODE); 3832 rc6_mode = GEN7_RC_CTL_TO_MODE;
3833 I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
3833 3834
3834 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS); 3835 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
3835 switch ((val >> 6) & 3) { 3836 switch ((val >> 6) & 3) {