aboutsummaryrefslogtreecommitdiffstats
path: root/drivers/gpu/drm/i915/intel_lvds.c
diff options
context:
space:
mode:
Diffstat (limited to 'drivers/gpu/drm/i915/intel_lvds.c')
-rw-r--r--drivers/gpu/drm/i915/intel_lvds.c32
1 files changed, 10 insertions, 22 deletions
diff --git a/drivers/gpu/drm/i915/intel_lvds.c b/drivers/gpu/drm/i915/intel_lvds.c
index 312ac306469a..cb5821eb59b6 100644
--- a/drivers/gpu/drm/i915/intel_lvds.c
+++ b/drivers/gpu/drm/i915/intel_lvds.c
@@ -246,26 +246,20 @@ static bool intel_lvds_mode_fixup(struct drm_encoder *encoder,
246 /* If we don't have a panel mode, there is nothing we can do */ 246 /* If we don't have a panel mode, there is nothing we can do */
247 if (dev_priv->panel_fixed_mode == NULL) 247 if (dev_priv->panel_fixed_mode == NULL)
248 return true; 248 return true;
249
249 /* 250 /*
250 * We have timings from the BIOS for the panel, put them in 251 * We have timings from the BIOS for the panel, put them in
251 * to the adjusted mode. The CRTC will be set up for this mode, 252 * to the adjusted mode. The CRTC will be set up for this mode,
252 * with the panel scaling set up to source from the H/VDisplay 253 * with the panel scaling set up to source from the H/VDisplay
253 * of the original mode. 254 * of the original mode.
254 */ 255 */
255 adjusted_mode->hdisplay = dev_priv->panel_fixed_mode->hdisplay; 256 intel_fixed_panel_mode(dev_priv->panel_fixed_mode, adjusted_mode);
256 adjusted_mode->hsync_start = 257
257 dev_priv->panel_fixed_mode->hsync_start; 258 if (HAS_PCH_SPLIT(dev)) {
258 adjusted_mode->hsync_end = 259 intel_pch_panel_fitting(dev, intel_lvds->fitting_mode,
259 dev_priv->panel_fixed_mode->hsync_end; 260 mode, adjusted_mode);
260 adjusted_mode->htotal = dev_priv->panel_fixed_mode->htotal; 261 return true;
261 adjusted_mode->vdisplay = dev_priv->panel_fixed_mode->vdisplay; 262 }
262 adjusted_mode->vsync_start =
263 dev_priv->panel_fixed_mode->vsync_start;
264 adjusted_mode->vsync_end =
265 dev_priv->panel_fixed_mode->vsync_end;
266 adjusted_mode->vtotal = dev_priv->panel_fixed_mode->vtotal;
267 adjusted_mode->clock = dev_priv->panel_fixed_mode->clock;
268 drm_mode_set_crtcinfo(adjusted_mode, CRTC_INTERLACE_HALVE_V);
269 263
270 /* Make sure pre-965s set dither correctly */ 264 /* Make sure pre-965s set dither correctly */
271 if (!IS_I965G(dev)) { 265 if (!IS_I965G(dev)) {
@@ -278,10 +272,6 @@ static bool intel_lvds_mode_fixup(struct drm_encoder *encoder,
278 adjusted_mode->vdisplay == mode->vdisplay) 272 adjusted_mode->vdisplay == mode->vdisplay)
279 goto out; 273 goto out;
280 274
281 /* full screen scale for now */
282 if (HAS_PCH_SPLIT(dev))
283 goto out;
284
285 /* 965+ wants fuzzy fitting */ 275 /* 965+ wants fuzzy fitting */
286 if (IS_I965G(dev)) 276 if (IS_I965G(dev))
287 pfit_control |= ((intel_crtc->pipe << PFIT_PIPE_SHIFT) | 277 pfit_control |= ((intel_crtc->pipe << PFIT_PIPE_SHIFT) |
@@ -293,10 +283,8 @@ static bool intel_lvds_mode_fixup(struct drm_encoder *encoder,
293 * to register description and PRM. 283 * to register description and PRM.
294 * Change the value here to see the borders for debugging 284 * Change the value here to see the borders for debugging
295 */ 285 */
296 if (!HAS_PCH_SPLIT(dev)) { 286 I915_WRITE(BCLRPAT_A, 0);
297 I915_WRITE(BCLRPAT_A, 0); 287 I915_WRITE(BCLRPAT_B, 0);
298 I915_WRITE(BCLRPAT_B, 0);
299 }
300 288
301 switch (intel_lvds->fitting_mode) { 289 switch (intel_lvds->fitting_mode) {
302 case DRM_MODE_SCALE_CENTER: 290 case DRM_MODE_SCALE_CENTER: