1 files changed, 8 insertions, 0 deletions

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 7235ffb58a18..37638f8e2265 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1882,6 +1882,10 @@ static void chv_post_disable_dp(struct intel_encoder *encoder)
         mutex_lock(&dev_priv->dpio_lock);
 
         /* Propagate soft reset to data lane reset */
+        val = vlv_dpio_read(dev_priv, pipe, VLV_PCS_DW1(ch));
+        val |= CHV_PCS_REQ_SOFTRESET_EN;
+        vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(ch), val);
+
         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS_DW0(ch));
         val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(ch), val);
@@ -2023,6 +2027,10 @@ static void chv_pre_enable_dp(struct intel_encoder *encoder)
         mutex_lock(&dev_priv->dpio_lock);
 
         /* Deassert soft data lane reset*/
+        val = vlv_dpio_read(dev_priv, pipe, VLV_PCS_DW1(ch));
+        val |= CHV_PCS_REQ_SOFTRESET_EN;
+        vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(ch), val);
+
         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS_DW0(ch));
         val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(ch), val);