diff options
Diffstat (limited to 'drivers/gpu/drm/i915/intel_dp.c')
-rw-r--r-- | drivers/gpu/drm/i915/intel_dp.c | 45 |
1 files changed, 13 insertions, 32 deletions
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index ac261155b2f7..e478f6a94535 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c | |||
@@ -685,6 +685,7 @@ intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode, | |||
685 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | 685 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
686 | int lane_count = 4, bpp = 24; | 686 | int lane_count = 4, bpp = 24; |
687 | struct intel_dp_m_n m_n; | 687 | struct intel_dp_m_n m_n; |
688 | int pipe = intel_crtc->pipe; | ||
688 | 689 | ||
689 | /* | 690 | /* |
690 | * Find the lane count in the intel_encoder private | 691 | * Find the lane count in the intel_encoder private |
@@ -715,39 +716,19 @@ intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode, | |||
715 | mode->clock, adjusted_mode->clock, &m_n); | 716 | mode->clock, adjusted_mode->clock, &m_n); |
716 | 717 | ||
717 | if (HAS_PCH_SPLIT(dev)) { | 718 | if (HAS_PCH_SPLIT(dev)) { |
718 | if (intel_crtc->pipe == 0) { | 719 | I915_WRITE(TRANSDATA_M1(pipe), |
719 | I915_WRITE(TRANSA_DATA_M1, | 720 | ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) | |
720 | ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) | | 721 | m_n.gmch_m); |
721 | m_n.gmch_m); | 722 | I915_WRITE(TRANSDATA_N1(pipe), m_n.gmch_n); |
722 | I915_WRITE(TRANSA_DATA_N1, m_n.gmch_n); | 723 | I915_WRITE(TRANSDPLINK_M1(pipe), m_n.link_m); |
723 | I915_WRITE(TRANSA_DP_LINK_M1, m_n.link_m); | 724 | I915_WRITE(TRANSDPLINK_N1(pipe), m_n.link_n); |
724 | I915_WRITE(TRANSA_DP_LINK_N1, m_n.link_n); | ||
725 | } else { | ||
726 | I915_WRITE(TRANSB_DATA_M1, | ||
727 | ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) | | ||
728 | m_n.gmch_m); | ||
729 | I915_WRITE(TRANSB_DATA_N1, m_n.gmch_n); | ||
730 | I915_WRITE(TRANSB_DP_LINK_M1, m_n.link_m); | ||
731 | I915_WRITE(TRANSB_DP_LINK_N1, m_n.link_n); | ||
732 | } | ||
733 | } else { | 725 | } else { |
734 | if (intel_crtc->pipe == 0) { | 726 | I915_WRITE(PIPE_GMCH_DATA_M(pipe), |
735 | I915_WRITE(PIPEA_GMCH_DATA_M, | 727 | ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) | |
736 | ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) | | 728 | m_n.gmch_m); |
737 | m_n.gmch_m); | 729 | I915_WRITE(PIPE_GMCH_DATA_N(pipe), m_n.gmch_n); |
738 | I915_WRITE(PIPEA_GMCH_DATA_N, | 730 | I915_WRITE(PIPE_DP_LINK_M(pipe), m_n.link_m); |
739 | m_n.gmch_n); | 731 | I915_WRITE(PIPE_DP_LINK_N(pipe), m_n.link_n); |
740 | I915_WRITE(PIPEA_DP_LINK_M, m_n.link_m); | ||
741 | I915_WRITE(PIPEA_DP_LINK_N, m_n.link_n); | ||
742 | } else { | ||
743 | I915_WRITE(PIPEB_GMCH_DATA_M, | ||
744 | ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) | | ||
745 | m_n.gmch_m); | ||
746 | I915_WRITE(PIPEB_GMCH_DATA_N, | ||
747 | m_n.gmch_n); | ||
748 | I915_WRITE(PIPEB_DP_LINK_M, m_n.link_m); | ||
749 | I915_WRITE(PIPEB_DP_LINK_N, m_n.link_n); | ||
750 | } | ||
751 | } | 732 | } |
752 | } | 733 | } |
753 | 734 | ||