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path: root/drivers/gpu/drm/i915/intel_display.c
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Diffstat (limited to 'drivers/gpu/drm/i915/intel_display.c')
-rw-r--r--drivers/gpu/drm/i915/intel_display.c1079
1 files changed, 765 insertions, 314 deletions
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index e7356fb6c918..f469a84cacfd 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -742,12 +742,11 @@ bool intel_pipe_has_type (struct drm_crtc *crtc, int type)
742{ 742{
743 struct drm_device *dev = crtc->dev; 743 struct drm_device *dev = crtc->dev;
744 struct drm_mode_config *mode_config = &dev->mode_config; 744 struct drm_mode_config *mode_config = &dev->mode_config;
745 struct drm_connector *l_entry; 745 struct drm_encoder *l_entry;
746 746
747 list_for_each_entry(l_entry, &mode_config->connector_list, head) { 747 list_for_each_entry(l_entry, &mode_config->encoder_list, head) {
748 if (l_entry->encoder && 748 if (l_entry && l_entry->crtc == crtc) {
749 l_entry->encoder->crtc == crtc) { 749 struct intel_encoder *intel_encoder = enc_to_intel_encoder(l_entry);
750 struct intel_encoder *intel_encoder = to_intel_encoder(l_entry);
751 if (intel_encoder->type == type) 750 if (intel_encoder->type == type)
752 return true; 751 return true;
753 } 752 }
@@ -755,23 +754,6 @@ bool intel_pipe_has_type (struct drm_crtc *crtc, int type)
755 return false; 754 return false;
756} 755}
757 756
758static struct drm_connector *
759intel_pipe_get_connector (struct drm_crtc *crtc)
760{
761 struct drm_device *dev = crtc->dev;
762 struct drm_mode_config *mode_config = &dev->mode_config;
763 struct drm_connector *l_entry, *ret = NULL;
764
765 list_for_each_entry(l_entry, &mode_config->connector_list, head) {
766 if (l_entry->encoder &&
767 l_entry->encoder->crtc == crtc) {
768 ret = l_entry;
769 break;
770 }
771 }
772 return ret;
773}
774
775#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0) 757#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
776/** 758/**
777 * Returns whether the given set of divisors are valid for a given refclk with 759 * Returns whether the given set of divisors are valid for a given refclk with
@@ -905,9 +887,9 @@ intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
905 887
906 memset(best_clock, 0, sizeof(*best_clock)); 888 memset(best_clock, 0, sizeof(*best_clock));
907 max_n = limit->n.max; 889 max_n = limit->n.max;
908 /* based on hardware requriment prefer smaller n to precision */ 890 /* based on hardware requirement, prefer smaller n to precision */
909 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { 891 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
910 /* based on hardware requirment prefere larger m1,m2 */ 892 /* based on hardware requirement, prefere larger m1,m2 */
911 for (clock.m1 = limit->m1.max; 893 for (clock.m1 = limit->m1.max;
912 clock.m1 >= limit->m1.min; clock.m1--) { 894 clock.m1 >= limit->m1.min; clock.m1--) {
913 for (clock.m2 = limit->m2.max; 895 for (clock.m2 = limit->m2.max;
@@ -1066,9 +1048,8 @@ void i8xx_disable_fbc(struct drm_device *dev)
1066 DRM_DEBUG_KMS("disabled FBC\n"); 1048 DRM_DEBUG_KMS("disabled FBC\n");
1067} 1049}
1068 1050
1069static bool i8xx_fbc_enabled(struct drm_crtc *crtc) 1051static bool i8xx_fbc_enabled(struct drm_device *dev)
1070{ 1052{
1071 struct drm_device *dev = crtc->dev;
1072 struct drm_i915_private *dev_priv = dev->dev_private; 1053 struct drm_i915_private *dev_priv = dev->dev_private;
1073 1054
1074 return I915_READ(FBC_CONTROL) & FBC_CTL_EN; 1055 return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
@@ -1125,14 +1106,43 @@ void g4x_disable_fbc(struct drm_device *dev)
1125 DRM_DEBUG_KMS("disabled FBC\n"); 1106 DRM_DEBUG_KMS("disabled FBC\n");
1126} 1107}
1127 1108
1128static bool g4x_fbc_enabled(struct drm_crtc *crtc) 1109static bool g4x_fbc_enabled(struct drm_device *dev)
1129{ 1110{
1130 struct drm_device *dev = crtc->dev;
1131 struct drm_i915_private *dev_priv = dev->dev_private; 1111 struct drm_i915_private *dev_priv = dev->dev_private;
1132 1112
1133 return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN; 1113 return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
1134} 1114}
1135 1115
1116bool intel_fbc_enabled(struct drm_device *dev)
1117{
1118 struct drm_i915_private *dev_priv = dev->dev_private;
1119
1120 if (!dev_priv->display.fbc_enabled)
1121 return false;
1122
1123 return dev_priv->display.fbc_enabled(dev);
1124}
1125
1126void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1127{
1128 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
1129
1130 if (!dev_priv->display.enable_fbc)
1131 return;
1132
1133 dev_priv->display.enable_fbc(crtc, interval);
1134}
1135
1136void intel_disable_fbc(struct drm_device *dev)
1137{
1138 struct drm_i915_private *dev_priv = dev->dev_private;
1139
1140 if (!dev_priv->display.disable_fbc)
1141 return;
1142
1143 dev_priv->display.disable_fbc(dev);
1144}
1145
1136/** 1146/**
1137 * intel_update_fbc - enable/disable FBC as needed 1147 * intel_update_fbc - enable/disable FBC as needed
1138 * @crtc: CRTC to point the compressor at 1148 * @crtc: CRTC to point the compressor at
@@ -1167,9 +1177,7 @@ static void intel_update_fbc(struct drm_crtc *crtc,
1167 if (!i915_powersave) 1177 if (!i915_powersave)
1168 return; 1178 return;
1169 1179
1170 if (!dev_priv->display.fbc_enabled || 1180 if (!I915_HAS_FBC(dev))
1171 !dev_priv->display.enable_fbc ||
1172 !dev_priv->display.disable_fbc)
1173 return; 1181 return;
1174 1182
1175 if (!crtc->fb) 1183 if (!crtc->fb)
@@ -1216,28 +1224,25 @@ static void intel_update_fbc(struct drm_crtc *crtc,
1216 goto out_disable; 1224 goto out_disable;
1217 } 1225 }
1218 1226
1219 if (dev_priv->display.fbc_enabled(crtc)) { 1227 if (intel_fbc_enabled(dev)) {
1220 /* We can re-enable it in this case, but need to update pitch */ 1228 /* We can re-enable it in this case, but need to update pitch */
1221 if (fb->pitch > dev_priv->cfb_pitch) 1229 if ((fb->pitch > dev_priv->cfb_pitch) ||
1222 dev_priv->display.disable_fbc(dev); 1230 (obj_priv->fence_reg != dev_priv->cfb_fence) ||
1223 if (obj_priv->fence_reg != dev_priv->cfb_fence) 1231 (plane != dev_priv->cfb_plane))
1224 dev_priv->display.disable_fbc(dev); 1232 intel_disable_fbc(dev);
1225 if (plane != dev_priv->cfb_plane)
1226 dev_priv->display.disable_fbc(dev);
1227 } 1233 }
1228 1234
1229 if (!dev_priv->display.fbc_enabled(crtc)) { 1235 /* Now try to turn it back on if possible */
1230 /* Now try to turn it back on if possible */ 1236 if (!intel_fbc_enabled(dev))
1231 dev_priv->display.enable_fbc(crtc, 500); 1237 intel_enable_fbc(crtc, 500);
1232 }
1233 1238
1234 return; 1239 return;
1235 1240
1236out_disable: 1241out_disable:
1237 DRM_DEBUG_KMS("unsupported config, disabling FBC\n"); 1242 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
1238 /* Multiple disables should be harmless */ 1243 /* Multiple disables should be harmless */
1239 if (dev_priv->display.fbc_enabled(crtc)) 1244 if (intel_fbc_enabled(dev))
1240 dev_priv->display.disable_fbc(dev); 1245 intel_disable_fbc(dev);
1241} 1246}
1242 1247
1243static int 1248static int
@@ -1510,6 +1515,219 @@ static void ironlake_set_pll_edp (struct drm_crtc *crtc, int clock)
1510 udelay(500); 1515 udelay(500);
1511} 1516}
1512 1517
1518/* The FDI link training functions for ILK/Ibexpeak. */
1519static void ironlake_fdi_link_train(struct drm_crtc *crtc)
1520{
1521 struct drm_device *dev = crtc->dev;
1522 struct drm_i915_private *dev_priv = dev->dev_private;
1523 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1524 int pipe = intel_crtc->pipe;
1525 int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL;
1526 int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
1527 int fdi_rx_iir_reg = (pipe == 0) ? FDI_RXA_IIR : FDI_RXB_IIR;
1528 int fdi_rx_imr_reg = (pipe == 0) ? FDI_RXA_IMR : FDI_RXB_IMR;
1529 u32 temp, tries = 0;
1530
1531 /* enable CPU FDI TX and PCH FDI RX */
1532 temp = I915_READ(fdi_tx_reg);
1533 temp |= FDI_TX_ENABLE;
1534 temp &= ~(7 << 19);
1535 temp |= (intel_crtc->fdi_lanes - 1) << 19;
1536 temp &= ~FDI_LINK_TRAIN_NONE;
1537 temp |= FDI_LINK_TRAIN_PATTERN_1;
1538 I915_WRITE(fdi_tx_reg, temp);
1539 I915_READ(fdi_tx_reg);
1540
1541 temp = I915_READ(fdi_rx_reg);
1542 temp &= ~FDI_LINK_TRAIN_NONE;
1543 temp |= FDI_LINK_TRAIN_PATTERN_1;
1544 I915_WRITE(fdi_rx_reg, temp | FDI_RX_ENABLE);
1545 I915_READ(fdi_rx_reg);
1546 udelay(150);
1547
1548 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
1549 for train result */
1550 temp = I915_READ(fdi_rx_imr_reg);
1551 temp &= ~FDI_RX_SYMBOL_LOCK;
1552 temp &= ~FDI_RX_BIT_LOCK;
1553 I915_WRITE(fdi_rx_imr_reg, temp);
1554 I915_READ(fdi_rx_imr_reg);
1555 udelay(150);
1556
1557 for (;;) {
1558 temp = I915_READ(fdi_rx_iir_reg);
1559 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1560
1561 if ((temp & FDI_RX_BIT_LOCK)) {
1562 DRM_DEBUG_KMS("FDI train 1 done.\n");
1563 I915_WRITE(fdi_rx_iir_reg,
1564 temp | FDI_RX_BIT_LOCK);
1565 break;
1566 }
1567
1568 tries++;
1569
1570 if (tries > 5) {
1571 DRM_DEBUG_KMS("FDI train 1 fail!\n");
1572 break;
1573 }
1574 }
1575
1576 /* Train 2 */
1577 temp = I915_READ(fdi_tx_reg);
1578 temp &= ~FDI_LINK_TRAIN_NONE;
1579 temp |= FDI_LINK_TRAIN_PATTERN_2;
1580 I915_WRITE(fdi_tx_reg, temp);
1581
1582 temp = I915_READ(fdi_rx_reg);
1583 temp &= ~FDI_LINK_TRAIN_NONE;
1584 temp |= FDI_LINK_TRAIN_PATTERN_2;
1585 I915_WRITE(fdi_rx_reg, temp);
1586 udelay(150);
1587
1588 tries = 0;
1589
1590 for (;;) {
1591 temp = I915_READ(fdi_rx_iir_reg);
1592 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1593
1594 if (temp & FDI_RX_SYMBOL_LOCK) {
1595 I915_WRITE(fdi_rx_iir_reg,
1596 temp | FDI_RX_SYMBOL_LOCK);
1597 DRM_DEBUG_KMS("FDI train 2 done.\n");
1598 break;
1599 }
1600
1601 tries++;
1602
1603 if (tries > 5) {
1604 DRM_DEBUG_KMS("FDI train 2 fail!\n");
1605 break;
1606 }
1607 }
1608
1609 DRM_DEBUG_KMS("FDI train done\n");
1610}
1611
1612static int snb_b_fdi_train_param [] = {
1613 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
1614 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
1615 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
1616 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
1617};
1618
1619/* The FDI link training functions for SNB/Cougarpoint. */
1620static void gen6_fdi_link_train(struct drm_crtc *crtc)
1621{
1622 struct drm_device *dev = crtc->dev;
1623 struct drm_i915_private *dev_priv = dev->dev_private;
1624 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1625 int pipe = intel_crtc->pipe;
1626 int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL;
1627 int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
1628 int fdi_rx_iir_reg = (pipe == 0) ? FDI_RXA_IIR : FDI_RXB_IIR;
1629 int fdi_rx_imr_reg = (pipe == 0) ? FDI_RXA_IMR : FDI_RXB_IMR;
1630 u32 temp, i;
1631
1632 /* enable CPU FDI TX and PCH FDI RX */
1633 temp = I915_READ(fdi_tx_reg);
1634 temp |= FDI_TX_ENABLE;
1635 temp &= ~(7 << 19);
1636 temp |= (intel_crtc->fdi_lanes - 1) << 19;
1637 temp &= ~FDI_LINK_TRAIN_NONE;
1638 temp |= FDI_LINK_TRAIN_PATTERN_1;
1639 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1640 /* SNB-B */
1641 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
1642 I915_WRITE(fdi_tx_reg, temp);
1643 I915_READ(fdi_tx_reg);
1644
1645 temp = I915_READ(fdi_rx_reg);
1646 if (HAS_PCH_CPT(dev)) {
1647 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
1648 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
1649 } else {
1650 temp &= ~FDI_LINK_TRAIN_NONE;
1651 temp |= FDI_LINK_TRAIN_PATTERN_1;
1652 }
1653 I915_WRITE(fdi_rx_reg, temp | FDI_RX_ENABLE);
1654 I915_READ(fdi_rx_reg);
1655 udelay(150);
1656
1657 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
1658 for train result */
1659 temp = I915_READ(fdi_rx_imr_reg);
1660 temp &= ~FDI_RX_SYMBOL_LOCK;
1661 temp &= ~FDI_RX_BIT_LOCK;
1662 I915_WRITE(fdi_rx_imr_reg, temp);
1663 I915_READ(fdi_rx_imr_reg);
1664 udelay(150);
1665
1666 for (i = 0; i < 4; i++ ) {
1667 temp = I915_READ(fdi_tx_reg);
1668 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1669 temp |= snb_b_fdi_train_param[i];
1670 I915_WRITE(fdi_tx_reg, temp);
1671 udelay(500);
1672
1673 temp = I915_READ(fdi_rx_iir_reg);
1674 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1675
1676 if (temp & FDI_RX_BIT_LOCK) {
1677 I915_WRITE(fdi_rx_iir_reg,
1678 temp | FDI_RX_BIT_LOCK);
1679 DRM_DEBUG_KMS("FDI train 1 done.\n");
1680 break;
1681 }
1682 }
1683 if (i == 4)
1684 DRM_DEBUG_KMS("FDI train 1 fail!\n");
1685
1686 /* Train 2 */
1687 temp = I915_READ(fdi_tx_reg);
1688 temp &= ~FDI_LINK_TRAIN_NONE;
1689 temp |= FDI_LINK_TRAIN_PATTERN_2;
1690 if (IS_GEN6(dev)) {
1691 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1692 /* SNB-B */
1693 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
1694 }
1695 I915_WRITE(fdi_tx_reg, temp);
1696
1697 temp = I915_READ(fdi_rx_reg);
1698 if (HAS_PCH_CPT(dev)) {
1699 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
1700 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
1701 } else {
1702 temp &= ~FDI_LINK_TRAIN_NONE;
1703 temp |= FDI_LINK_TRAIN_PATTERN_2;
1704 }
1705 I915_WRITE(fdi_rx_reg, temp);
1706 udelay(150);
1707
1708 for (i = 0; i < 4; i++ ) {
1709 temp = I915_READ(fdi_tx_reg);
1710 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1711 temp |= snb_b_fdi_train_param[i];
1712 I915_WRITE(fdi_tx_reg, temp);
1713 udelay(500);
1714
1715 temp = I915_READ(fdi_rx_iir_reg);
1716 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1717
1718 if (temp & FDI_RX_SYMBOL_LOCK) {
1719 I915_WRITE(fdi_rx_iir_reg,
1720 temp | FDI_RX_SYMBOL_LOCK);
1721 DRM_DEBUG_KMS("FDI train 2 done.\n");
1722 break;
1723 }
1724 }
1725 if (i == 4)
1726 DRM_DEBUG_KMS("FDI train 2 fail!\n");
1727
1728 DRM_DEBUG_KMS("FDI train done.\n");
1729}
1730
1513static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode) 1731static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
1514{ 1732{
1515 struct drm_device *dev = crtc->dev; 1733 struct drm_device *dev = crtc->dev;
@@ -1523,8 +1741,6 @@ static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
1523 int dspbase_reg = (plane == 0) ? DSPAADDR : DSPBADDR; 1741 int dspbase_reg = (plane == 0) ? DSPAADDR : DSPBADDR;
1524 int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL; 1742 int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL;
1525 int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL; 1743 int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
1526 int fdi_rx_iir_reg = (pipe == 0) ? FDI_RXA_IIR : FDI_RXB_IIR;
1527 int fdi_rx_imr_reg = (pipe == 0) ? FDI_RXA_IMR : FDI_RXB_IMR;
1528 int transconf_reg = (pipe == 0) ? TRANSACONF : TRANSBCONF; 1744 int transconf_reg = (pipe == 0) ? TRANSACONF : TRANSBCONF;
1529 int pf_ctl_reg = (pipe == 0) ? PFA_CTL_1 : PFB_CTL_1; 1745 int pf_ctl_reg = (pipe == 0) ? PFA_CTL_1 : PFB_CTL_1;
1530 int pf_win_size = (pipe == 0) ? PFA_WIN_SZ : PFB_WIN_SZ; 1746 int pf_win_size = (pipe == 0) ? PFA_WIN_SZ : PFB_WIN_SZ;
@@ -1541,8 +1757,9 @@ static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
1541 int trans_vtot_reg = (pipe == 0) ? TRANS_VTOTAL_A : TRANS_VTOTAL_B; 1757 int trans_vtot_reg = (pipe == 0) ? TRANS_VTOTAL_A : TRANS_VTOTAL_B;
1542 int trans_vblank_reg = (pipe == 0) ? TRANS_VBLANK_A : TRANS_VBLANK_B; 1758 int trans_vblank_reg = (pipe == 0) ? TRANS_VBLANK_A : TRANS_VBLANK_B;
1543 int trans_vsync_reg = (pipe == 0) ? TRANS_VSYNC_A : TRANS_VSYNC_B; 1759 int trans_vsync_reg = (pipe == 0) ? TRANS_VSYNC_A : TRANS_VSYNC_B;
1760 int trans_dpll_sel = (pipe == 0) ? 0 : 1;
1544 u32 temp; 1761 u32 temp;
1545 int tries = 5, j, n; 1762 int n;
1546 u32 pipe_bpc; 1763 u32 pipe_bpc;
1547 1764
1548 temp = I915_READ(pipeconf_reg); 1765 temp = I915_READ(pipeconf_reg);
@@ -1569,12 +1786,6 @@ static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
1569 /* enable eDP PLL */ 1786 /* enable eDP PLL */
1570 ironlake_enable_pll_edp(crtc); 1787 ironlake_enable_pll_edp(crtc);
1571 } else { 1788 } else {
1572 /* enable PCH DPLL */
1573 temp = I915_READ(pch_dpll_reg);
1574 if ((temp & DPLL_VCO_ENABLE) == 0) {
1575 I915_WRITE(pch_dpll_reg, temp | DPLL_VCO_ENABLE);
1576 I915_READ(pch_dpll_reg);
1577 }
1578 1789
1579 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */ 1790 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
1580 temp = I915_READ(fdi_rx_reg); 1791 temp = I915_READ(fdi_rx_reg);
@@ -1584,9 +1795,15 @@ static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
1584 */ 1795 */
1585 temp &= ~(0x7 << 16); 1796 temp &= ~(0x7 << 16);
1586 temp |= (pipe_bpc << 11); 1797 temp |= (pipe_bpc << 11);
1587 I915_WRITE(fdi_rx_reg, temp | FDI_RX_PLL_ENABLE | 1798 temp &= ~(7 << 19);
1588 FDI_SEL_PCDCLK | 1799 temp |= (intel_crtc->fdi_lanes - 1) << 19;
1589 FDI_DP_PORT_WIDTH_X4); /* default 4 lanes */ 1800 I915_WRITE(fdi_rx_reg, temp | FDI_RX_PLL_ENABLE);
1801 I915_READ(fdi_rx_reg);
1802 udelay(200);
1803
1804 /* Switch from Rawclk to PCDclk */
1805 temp = I915_READ(fdi_rx_reg);
1806 I915_WRITE(fdi_rx_reg, temp | FDI_SEL_PCDCLK);
1590 I915_READ(fdi_rx_reg); 1807 I915_READ(fdi_rx_reg);
1591 udelay(200); 1808 udelay(200);
1592 1809
@@ -1629,91 +1846,32 @@ static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
1629 } 1846 }
1630 1847
1631 if (!HAS_eDP) { 1848 if (!HAS_eDP) {
1632 /* enable CPU FDI TX and PCH FDI RX */ 1849 /* For PCH output, training FDI link */
1633 temp = I915_READ(fdi_tx_reg); 1850 if (IS_GEN6(dev))
1634 temp |= FDI_TX_ENABLE; 1851 gen6_fdi_link_train(crtc);
1635 temp |= FDI_DP_PORT_WIDTH_X4; /* default */ 1852 else
1636 temp &= ~FDI_LINK_TRAIN_NONE; 1853 ironlake_fdi_link_train(crtc);
1637 temp |= FDI_LINK_TRAIN_PATTERN_1;
1638 I915_WRITE(fdi_tx_reg, temp);
1639 I915_READ(fdi_tx_reg);
1640
1641 temp = I915_READ(fdi_rx_reg);
1642 temp &= ~FDI_LINK_TRAIN_NONE;
1643 temp |= FDI_LINK_TRAIN_PATTERN_1;
1644 I915_WRITE(fdi_rx_reg, temp | FDI_RX_ENABLE);
1645 I915_READ(fdi_rx_reg);
1646
1647 udelay(150);
1648
1649 /* Train FDI. */
1650 /* umask FDI RX Interrupt symbol_lock and bit_lock bit
1651 for train result */
1652 temp = I915_READ(fdi_rx_imr_reg);
1653 temp &= ~FDI_RX_SYMBOL_LOCK;
1654 temp &= ~FDI_RX_BIT_LOCK;
1655 I915_WRITE(fdi_rx_imr_reg, temp);
1656 I915_READ(fdi_rx_imr_reg);
1657 udelay(150);
1658 1854
1659 temp = I915_READ(fdi_rx_iir_reg); 1855 /* enable PCH DPLL */
1660 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); 1856 temp = I915_READ(pch_dpll_reg);
1661 1857 if ((temp & DPLL_VCO_ENABLE) == 0) {
1662 if ((temp & FDI_RX_BIT_LOCK) == 0) { 1858 I915_WRITE(pch_dpll_reg, temp | DPLL_VCO_ENABLE);
1663 for (j = 0; j < tries; j++) { 1859 I915_READ(pch_dpll_reg);
1664 temp = I915_READ(fdi_rx_iir_reg);
1665 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n",
1666 temp);
1667 if (temp & FDI_RX_BIT_LOCK)
1668 break;
1669 udelay(200);
1670 }
1671 if (j != tries)
1672 I915_WRITE(fdi_rx_iir_reg,
1673 temp | FDI_RX_BIT_LOCK);
1674 else
1675 DRM_DEBUG_KMS("train 1 fail\n");
1676 } else {
1677 I915_WRITE(fdi_rx_iir_reg,
1678 temp | FDI_RX_BIT_LOCK);
1679 DRM_DEBUG_KMS("train 1 ok 2!\n");
1680 } 1860 }
1681 temp = I915_READ(fdi_tx_reg); 1861 udelay(200);
1682 temp &= ~FDI_LINK_TRAIN_NONE;
1683 temp |= FDI_LINK_TRAIN_PATTERN_2;
1684 I915_WRITE(fdi_tx_reg, temp);
1685
1686 temp = I915_READ(fdi_rx_reg);
1687 temp &= ~FDI_LINK_TRAIN_NONE;
1688 temp |= FDI_LINK_TRAIN_PATTERN_2;
1689 I915_WRITE(fdi_rx_reg, temp);
1690
1691 udelay(150);
1692 1862
1693 temp = I915_READ(fdi_rx_iir_reg); 1863 if (HAS_PCH_CPT(dev)) {
1694 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); 1864 /* Be sure PCH DPLL SEL is set */
1695 1865 temp = I915_READ(PCH_DPLL_SEL);
1696 if ((temp & FDI_RX_SYMBOL_LOCK) == 0) { 1866 if (trans_dpll_sel == 0 &&
1697 for (j = 0; j < tries; j++) { 1867 (temp & TRANSA_DPLL_ENABLE) == 0)
1698 temp = I915_READ(fdi_rx_iir_reg); 1868 temp |= (TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
1699 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", 1869 else if (trans_dpll_sel == 1 &&
1700 temp); 1870 (temp & TRANSB_DPLL_ENABLE) == 0)
1701 if (temp & FDI_RX_SYMBOL_LOCK) 1871 temp |= (TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
1702 break; 1872 I915_WRITE(PCH_DPLL_SEL, temp);
1703 udelay(200); 1873 I915_READ(PCH_DPLL_SEL);
1704 }
1705 if (j != tries) {
1706 I915_WRITE(fdi_rx_iir_reg,
1707 temp | FDI_RX_SYMBOL_LOCK);
1708 DRM_DEBUG_KMS("train 2 ok 1!\n");
1709 } else
1710 DRM_DEBUG_KMS("train 2 fail\n");
1711 } else {
1712 I915_WRITE(fdi_rx_iir_reg,
1713 temp | FDI_RX_SYMBOL_LOCK);
1714 DRM_DEBUG_KMS("train 2 ok 2!\n");
1715 } 1874 }
1716 DRM_DEBUG_KMS("train done\n");
1717 1875
1718 /* set transcoder timing */ 1876 /* set transcoder timing */
1719 I915_WRITE(trans_htot_reg, I915_READ(cpu_htot_reg)); 1877 I915_WRITE(trans_htot_reg, I915_READ(cpu_htot_reg));
@@ -1724,6 +1882,60 @@ static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
1724 I915_WRITE(trans_vblank_reg, I915_READ(cpu_vblank_reg)); 1882 I915_WRITE(trans_vblank_reg, I915_READ(cpu_vblank_reg));
1725 I915_WRITE(trans_vsync_reg, I915_READ(cpu_vsync_reg)); 1883 I915_WRITE(trans_vsync_reg, I915_READ(cpu_vsync_reg));
1726 1884
1885 /* enable normal train */
1886 temp = I915_READ(fdi_tx_reg);
1887 temp &= ~FDI_LINK_TRAIN_NONE;
1888 I915_WRITE(fdi_tx_reg, temp | FDI_LINK_TRAIN_NONE |
1889 FDI_TX_ENHANCE_FRAME_ENABLE);
1890 I915_READ(fdi_tx_reg);
1891
1892 temp = I915_READ(fdi_rx_reg);
1893 if (HAS_PCH_CPT(dev)) {
1894 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
1895 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
1896 } else {
1897 temp &= ~FDI_LINK_TRAIN_NONE;
1898 temp |= FDI_LINK_TRAIN_NONE;
1899 }
1900 I915_WRITE(fdi_rx_reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
1901 I915_READ(fdi_rx_reg);
1902
1903 /* wait one idle pattern time */
1904 udelay(100);
1905
1906 /* For PCH DP, enable TRANS_DP_CTL */
1907 if (HAS_PCH_CPT(dev) &&
1908 intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
1909 int trans_dp_ctl = (pipe == 0) ? TRANS_DP_CTL_A : TRANS_DP_CTL_B;
1910 int reg;
1911
1912 reg = I915_READ(trans_dp_ctl);
1913 reg &= ~TRANS_DP_PORT_SEL_MASK;
1914 reg = TRANS_DP_OUTPUT_ENABLE |
1915 TRANS_DP_ENH_FRAMING |
1916 TRANS_DP_VSYNC_ACTIVE_HIGH |
1917 TRANS_DP_HSYNC_ACTIVE_HIGH;
1918
1919 switch (intel_trans_dp_port_sel(crtc)) {
1920 case PCH_DP_B:
1921 reg |= TRANS_DP_PORT_SEL_B;
1922 break;
1923 case PCH_DP_C:
1924 reg |= TRANS_DP_PORT_SEL_C;
1925 break;
1926 case PCH_DP_D:
1927 reg |= TRANS_DP_PORT_SEL_D;
1928 break;
1929 default:
1930 DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
1931 reg |= TRANS_DP_PORT_SEL_B;
1932 break;
1933 }
1934
1935 I915_WRITE(trans_dp_ctl, reg);
1936 POSTING_READ(trans_dp_ctl);
1937 }
1938
1727 /* enable PCH transcoder */ 1939 /* enable PCH transcoder */
1728 temp = I915_READ(transconf_reg); 1940 temp = I915_READ(transconf_reg);
1729 /* 1941 /*
@@ -1738,23 +1950,6 @@ static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
1738 while ((I915_READ(transconf_reg) & TRANS_STATE_ENABLE) == 0) 1950 while ((I915_READ(transconf_reg) & TRANS_STATE_ENABLE) == 0)
1739 ; 1951 ;
1740 1952
1741 /* enable normal */
1742
1743 temp = I915_READ(fdi_tx_reg);
1744 temp &= ~FDI_LINK_TRAIN_NONE;
1745 I915_WRITE(fdi_tx_reg, temp | FDI_LINK_TRAIN_NONE |
1746 FDI_TX_ENHANCE_FRAME_ENABLE);
1747 I915_READ(fdi_tx_reg);
1748
1749 temp = I915_READ(fdi_rx_reg);
1750 temp &= ~FDI_LINK_TRAIN_NONE;
1751 I915_WRITE(fdi_rx_reg, temp | FDI_LINK_TRAIN_NONE |
1752 FDI_RX_ENHANCE_FRAME_ENABLE);
1753 I915_READ(fdi_rx_reg);
1754
1755 /* wait one idle pattern time */
1756 udelay(100);
1757
1758 } 1953 }
1759 1954
1760 intel_crtc_load_lut(crtc); 1955 intel_crtc_load_lut(crtc);
@@ -1805,6 +2000,8 @@ static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
1805 I915_READ(pf_ctl_reg); 2000 I915_READ(pf_ctl_reg);
1806 } 2001 }
1807 I915_WRITE(pf_win_size, 0); 2002 I915_WRITE(pf_win_size, 0);
2003 POSTING_READ(pf_win_size);
2004
1808 2005
1809 /* disable CPU FDI tx and PCH FDI rx */ 2006 /* disable CPU FDI tx and PCH FDI rx */
1810 temp = I915_READ(fdi_tx_reg); 2007 temp = I915_READ(fdi_tx_reg);
@@ -1825,11 +2022,18 @@ static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
1825 temp &= ~FDI_LINK_TRAIN_NONE; 2022 temp &= ~FDI_LINK_TRAIN_NONE;
1826 temp |= FDI_LINK_TRAIN_PATTERN_1; 2023 temp |= FDI_LINK_TRAIN_PATTERN_1;
1827 I915_WRITE(fdi_tx_reg, temp); 2024 I915_WRITE(fdi_tx_reg, temp);
2025 POSTING_READ(fdi_tx_reg);
1828 2026
1829 temp = I915_READ(fdi_rx_reg); 2027 temp = I915_READ(fdi_rx_reg);
1830 temp &= ~FDI_LINK_TRAIN_NONE; 2028 if (HAS_PCH_CPT(dev)) {
1831 temp |= FDI_LINK_TRAIN_PATTERN_1; 2029 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2030 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2031 } else {
2032 temp &= ~FDI_LINK_TRAIN_NONE;
2033 temp |= FDI_LINK_TRAIN_PATTERN_1;
2034 }
1832 I915_WRITE(fdi_rx_reg, temp); 2035 I915_WRITE(fdi_rx_reg, temp);
2036 POSTING_READ(fdi_rx_reg);
1833 2037
1834 udelay(100); 2038 udelay(100);
1835 2039
@@ -1859,6 +2063,7 @@ static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
1859 } 2063 }
1860 } 2064 }
1861 } 2065 }
2066
1862 temp = I915_READ(transconf_reg); 2067 temp = I915_READ(transconf_reg);
1863 /* BPC in transcoder is consistent with that in pipeconf */ 2068 /* BPC in transcoder is consistent with that in pipeconf */
1864 temp &= ~PIPE_BPC_MASK; 2069 temp &= ~PIPE_BPC_MASK;
@@ -1867,35 +2072,53 @@ static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
1867 I915_READ(transconf_reg); 2072 I915_READ(transconf_reg);
1868 udelay(100); 2073 udelay(100);
1869 2074
2075 if (HAS_PCH_CPT(dev)) {
2076 /* disable TRANS_DP_CTL */
2077 int trans_dp_ctl = (pipe == 0) ? TRANS_DP_CTL_A : TRANS_DP_CTL_B;
2078 int reg;
2079
2080 reg = I915_READ(trans_dp_ctl);
2081 reg &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
2082 I915_WRITE(trans_dp_ctl, reg);
2083 POSTING_READ(trans_dp_ctl);
2084
2085 /* disable DPLL_SEL */
2086 temp = I915_READ(PCH_DPLL_SEL);
2087 if (trans_dpll_sel == 0)
2088 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
2089 else
2090 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
2091 I915_WRITE(PCH_DPLL_SEL, temp);
2092 I915_READ(PCH_DPLL_SEL);
2093
2094 }
2095
1870 /* disable PCH DPLL */ 2096 /* disable PCH DPLL */
1871 temp = I915_READ(pch_dpll_reg); 2097 temp = I915_READ(pch_dpll_reg);
1872 if ((temp & DPLL_VCO_ENABLE) != 0) { 2098 I915_WRITE(pch_dpll_reg, temp & ~DPLL_VCO_ENABLE);
1873 I915_WRITE(pch_dpll_reg, temp & ~DPLL_VCO_ENABLE); 2099 I915_READ(pch_dpll_reg);
1874 I915_READ(pch_dpll_reg);
1875 }
1876 2100
1877 if (HAS_eDP) { 2101 if (HAS_eDP) {
1878 ironlake_disable_pll_edp(crtc); 2102 ironlake_disable_pll_edp(crtc);
1879 } 2103 }
1880 2104
2105 /* Switch from PCDclk to Rawclk */
1881 temp = I915_READ(fdi_rx_reg); 2106 temp = I915_READ(fdi_rx_reg);
1882 temp &= ~FDI_SEL_PCDCLK; 2107 temp &= ~FDI_SEL_PCDCLK;
1883 I915_WRITE(fdi_rx_reg, temp); 2108 I915_WRITE(fdi_rx_reg, temp);
1884 I915_READ(fdi_rx_reg); 2109 I915_READ(fdi_rx_reg);
1885 2110
2111 /* Disable CPU FDI TX PLL */
2112 temp = I915_READ(fdi_tx_reg);
2113 I915_WRITE(fdi_tx_reg, temp & ~FDI_TX_PLL_ENABLE);
2114 I915_READ(fdi_tx_reg);
2115 udelay(100);
2116
1886 temp = I915_READ(fdi_rx_reg); 2117 temp = I915_READ(fdi_rx_reg);
1887 temp &= ~FDI_RX_PLL_ENABLE; 2118 temp &= ~FDI_RX_PLL_ENABLE;
1888 I915_WRITE(fdi_rx_reg, temp); 2119 I915_WRITE(fdi_rx_reg, temp);
1889 I915_READ(fdi_rx_reg); 2120 I915_READ(fdi_rx_reg);
1890 2121
1891 /* Disable CPU FDI TX PLL */
1892 temp = I915_READ(fdi_tx_reg);
1893 if ((temp & FDI_TX_PLL_ENABLE) != 0) {
1894 I915_WRITE(fdi_tx_reg, temp & ~FDI_TX_PLL_ENABLE);
1895 I915_READ(fdi_tx_reg);
1896 udelay(100);
1897 }
1898
1899 /* Wait for the clocks to turn off. */ 2122 /* Wait for the clocks to turn off. */
1900 udelay(100); 2123 udelay(100);
1901 break; 2124 break;
@@ -2331,6 +2554,30 @@ static struct intel_watermark_params i830_wm_info = {
2331 I830_FIFO_LINE_SIZE 2554 I830_FIFO_LINE_SIZE
2332}; 2555};
2333 2556
2557static struct intel_watermark_params ironlake_display_wm_info = {
2558 ILK_DISPLAY_FIFO,
2559 ILK_DISPLAY_MAXWM,
2560 ILK_DISPLAY_DFTWM,
2561 2,
2562 ILK_FIFO_LINE_SIZE
2563};
2564
2565static struct intel_watermark_params ironlake_display_srwm_info = {
2566 ILK_DISPLAY_SR_FIFO,
2567 ILK_DISPLAY_MAX_SRWM,
2568 ILK_DISPLAY_DFT_SRWM,
2569 2,
2570 ILK_FIFO_LINE_SIZE
2571};
2572
2573static struct intel_watermark_params ironlake_cursor_srwm_info = {
2574 ILK_CURSOR_SR_FIFO,
2575 ILK_CURSOR_MAX_SRWM,
2576 ILK_CURSOR_DFT_SRWM,
2577 2,
2578 ILK_FIFO_LINE_SIZE
2579};
2580
2334/** 2581/**
2335 * intel_calculate_wm - calculate watermark level 2582 * intel_calculate_wm - calculate watermark level
2336 * @clock_in_khz: pixel clock 2583 * @clock_in_khz: pixel clock
@@ -2449,66 +2696,6 @@ static void pineview_disable_cxsr(struct drm_device *dev)
2449 DRM_INFO("Big FIFO is disabled\n"); 2696 DRM_INFO("Big FIFO is disabled\n");
2450} 2697}
2451 2698
2452static void pineview_enable_cxsr(struct drm_device *dev, unsigned long clock,
2453 int pixel_size)
2454{
2455 struct drm_i915_private *dev_priv = dev->dev_private;
2456 u32 reg;
2457 unsigned long wm;
2458 struct cxsr_latency *latency;
2459
2460 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->fsb_freq,
2461 dev_priv->mem_freq);
2462 if (!latency) {
2463 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
2464 pineview_disable_cxsr(dev);
2465 return;
2466 }
2467
2468 /* Display SR */
2469 wm = intel_calculate_wm(clock, &pineview_display_wm, pixel_size,
2470 latency->display_sr);
2471 reg = I915_READ(DSPFW1);
2472 reg &= 0x7fffff;
2473 reg |= wm << 23;
2474 I915_WRITE(DSPFW1, reg);
2475 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
2476
2477 /* cursor SR */
2478 wm = intel_calculate_wm(clock, &pineview_cursor_wm, pixel_size,
2479 latency->cursor_sr);
2480 reg = I915_READ(DSPFW3);
2481 reg &= ~(0x3f << 24);
2482 reg |= (wm & 0x3f) << 24;
2483 I915_WRITE(DSPFW3, reg);
2484
2485 /* Display HPLL off SR */
2486 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
2487 latency->display_hpll_disable, I915_FIFO_LINE_SIZE);
2488 reg = I915_READ(DSPFW3);
2489 reg &= 0xfffffe00;
2490 reg |= wm & 0x1ff;
2491 I915_WRITE(DSPFW3, reg);
2492
2493 /* cursor HPLL off SR */
2494 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm, pixel_size,
2495 latency->cursor_hpll_disable);
2496 reg = I915_READ(DSPFW3);
2497 reg &= ~(0x3f << 16);
2498 reg |= (wm & 0x3f) << 16;
2499 I915_WRITE(DSPFW3, reg);
2500 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
2501
2502 /* activate cxsr */
2503 reg = I915_READ(DSPFW3);
2504 reg |= PINEVIEW_SELF_REFRESH_EN;
2505 I915_WRITE(DSPFW3, reg);
2506
2507 DRM_INFO("Big FIFO is enabled\n");
2508
2509 return;
2510}
2511
2512/* 2699/*
2513 * Latency for FIFO fetches is dependent on several factors: 2700 * Latency for FIFO fetches is dependent on several factors:
2514 * - memory configuration (speed, channels) 2701 * - memory configuration (speed, channels)
@@ -2593,6 +2780,71 @@ static int i830_get_fifo_size(struct drm_device *dev, int plane)
2593 return size; 2780 return size;
2594} 2781}
2595 2782
2783static void pineview_update_wm(struct drm_device *dev, int planea_clock,
2784 int planeb_clock, int sr_hdisplay, int pixel_size)
2785{
2786 struct drm_i915_private *dev_priv = dev->dev_private;
2787 u32 reg;
2788 unsigned long wm;
2789 struct cxsr_latency *latency;
2790 int sr_clock;
2791
2792 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->fsb_freq,
2793 dev_priv->mem_freq);
2794 if (!latency) {
2795 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
2796 pineview_disable_cxsr(dev);
2797 return;
2798 }
2799
2800 if (!planea_clock || !planeb_clock) {
2801 sr_clock = planea_clock ? planea_clock : planeb_clock;
2802
2803 /* Display SR */
2804 wm = intel_calculate_wm(sr_clock, &pineview_display_wm,
2805 pixel_size, latency->display_sr);
2806 reg = I915_READ(DSPFW1);
2807 reg &= ~DSPFW_SR_MASK;
2808 reg |= wm << DSPFW_SR_SHIFT;
2809 I915_WRITE(DSPFW1, reg);
2810 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
2811
2812 /* cursor SR */
2813 wm = intel_calculate_wm(sr_clock, &pineview_cursor_wm,
2814 pixel_size, latency->cursor_sr);
2815 reg = I915_READ(DSPFW3);
2816 reg &= ~DSPFW_CURSOR_SR_MASK;
2817 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
2818 I915_WRITE(DSPFW3, reg);
2819
2820 /* Display HPLL off SR */
2821 wm = intel_calculate_wm(sr_clock, &pineview_display_hplloff_wm,
2822 pixel_size, latency->display_hpll_disable);
2823 reg = I915_READ(DSPFW3);
2824 reg &= ~DSPFW_HPLL_SR_MASK;
2825 reg |= wm & DSPFW_HPLL_SR_MASK;
2826 I915_WRITE(DSPFW3, reg);
2827
2828 /* cursor HPLL off SR */
2829 wm = intel_calculate_wm(sr_clock, &pineview_cursor_hplloff_wm,
2830 pixel_size, latency->cursor_hpll_disable);
2831 reg = I915_READ(DSPFW3);
2832 reg &= ~DSPFW_HPLL_CURSOR_MASK;
2833 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
2834 I915_WRITE(DSPFW3, reg);
2835 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
2836
2837 /* activate cxsr */
2838 reg = I915_READ(DSPFW3);
2839 reg |= PINEVIEW_SELF_REFRESH_EN;
2840 I915_WRITE(DSPFW3, reg);
2841 DRM_DEBUG_KMS("Self-refresh is enabled\n");
2842 } else {
2843 pineview_disable_cxsr(dev);
2844 DRM_DEBUG_KMS("Self-refresh is disabled\n");
2845 }
2846}
2847
2596static void g4x_update_wm(struct drm_device *dev, int planea_clock, 2848static void g4x_update_wm(struct drm_device *dev, int planea_clock,
2597 int planeb_clock, int sr_hdisplay, int pixel_size) 2849 int planeb_clock, int sr_hdisplay, int pixel_size)
2598{ 2850{
@@ -2813,6 +3065,108 @@ static void i830_update_wm(struct drm_device *dev, int planea_clock, int unused,
2813 I915_WRITE(FW_BLC, fwater_lo); 3065 I915_WRITE(FW_BLC, fwater_lo);
2814} 3066}
2815 3067
3068#define ILK_LP0_PLANE_LATENCY 700
3069
3070static void ironlake_update_wm(struct drm_device *dev, int planea_clock,
3071 int planeb_clock, int sr_hdisplay, int pixel_size)
3072{
3073 struct drm_i915_private *dev_priv = dev->dev_private;
3074 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
3075 int sr_wm, cursor_wm;
3076 unsigned long line_time_us;
3077 int sr_clock, entries_required;
3078 u32 reg_value;
3079
3080 /* Calculate and update the watermark for plane A */
3081 if (planea_clock) {
3082 entries_required = ((planea_clock / 1000) * pixel_size *
3083 ILK_LP0_PLANE_LATENCY) / 1000;
3084 entries_required = DIV_ROUND_UP(entries_required,
3085 ironlake_display_wm_info.cacheline_size);
3086 planea_wm = entries_required +
3087 ironlake_display_wm_info.guard_size;
3088
3089 if (planea_wm > (int)ironlake_display_wm_info.max_wm)
3090 planea_wm = ironlake_display_wm_info.max_wm;
3091
3092 cursora_wm = 16;
3093 reg_value = I915_READ(WM0_PIPEA_ILK);
3094 reg_value &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
3095 reg_value |= (planea_wm << WM0_PIPE_PLANE_SHIFT) |
3096 (cursora_wm & WM0_PIPE_CURSOR_MASK);
3097 I915_WRITE(WM0_PIPEA_ILK, reg_value);
3098 DRM_DEBUG_KMS("FIFO watermarks For pipe A - plane %d, "
3099 "cursor: %d\n", planea_wm, cursora_wm);
3100 }
3101 /* Calculate and update the watermark for plane B */
3102 if (planeb_clock) {
3103 entries_required = ((planeb_clock / 1000) * pixel_size *
3104 ILK_LP0_PLANE_LATENCY) / 1000;
3105 entries_required = DIV_ROUND_UP(entries_required,
3106 ironlake_display_wm_info.cacheline_size);
3107 planeb_wm = entries_required +
3108 ironlake_display_wm_info.guard_size;
3109
3110 if (planeb_wm > (int)ironlake_display_wm_info.max_wm)
3111 planeb_wm = ironlake_display_wm_info.max_wm;
3112
3113 cursorb_wm = 16;
3114 reg_value = I915_READ(WM0_PIPEB_ILK);
3115 reg_value &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
3116 reg_value |= (planeb_wm << WM0_PIPE_PLANE_SHIFT) |
3117 (cursorb_wm & WM0_PIPE_CURSOR_MASK);
3118 I915_WRITE(WM0_PIPEB_ILK, reg_value);
3119 DRM_DEBUG_KMS("FIFO watermarks For pipe B - plane %d, "
3120 "cursor: %d\n", planeb_wm, cursorb_wm);
3121 }
3122
3123 /*
3124 * Calculate and update the self-refresh watermark only when one
3125 * display plane is used.
3126 */
3127 if (!planea_clock || !planeb_clock) {
3128 int line_count;
3129 /* Read the self-refresh latency. The unit is 0.5us */
3130 int ilk_sr_latency = I915_READ(MLTR_ILK) & ILK_SRLT_MASK;
3131
3132 sr_clock = planea_clock ? planea_clock : planeb_clock;
3133 line_time_us = ((sr_hdisplay * 1000) / sr_clock);
3134
3135 /* Use ns/us then divide to preserve precision */
3136 line_count = ((ilk_sr_latency * 500) / line_time_us + 1000)
3137 / 1000;
3138
3139 /* calculate the self-refresh watermark for display plane */
3140 entries_required = line_count * sr_hdisplay * pixel_size;
3141 entries_required = DIV_ROUND_UP(entries_required,
3142 ironlake_display_srwm_info.cacheline_size);
3143 sr_wm = entries_required +
3144 ironlake_display_srwm_info.guard_size;
3145
3146 /* calculate the self-refresh watermark for display cursor */
3147 entries_required = line_count * pixel_size * 64;
3148 entries_required = DIV_ROUND_UP(entries_required,
3149 ironlake_cursor_srwm_info.cacheline_size);
3150 cursor_wm = entries_required +
3151 ironlake_cursor_srwm_info.guard_size;
3152
3153 /* configure watermark and enable self-refresh */
3154 reg_value = I915_READ(WM1_LP_ILK);
3155 reg_value &= ~(WM1_LP_LATENCY_MASK | WM1_LP_SR_MASK |
3156 WM1_LP_CURSOR_MASK);
3157 reg_value |= WM1_LP_SR_EN |
3158 (ilk_sr_latency << WM1_LP_LATENCY_SHIFT) |
3159 (sr_wm << WM1_LP_SR_SHIFT) | cursor_wm;
3160
3161 I915_WRITE(WM1_LP_ILK, reg_value);
3162 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
3163 "cursor %d\n", sr_wm, cursor_wm);
3164
3165 } else {
3166 /* Turn off self refresh if both pipes are enabled */
3167 I915_WRITE(WM1_LP_ILK, I915_READ(WM1_LP_ILK) & ~WM1_LP_SR_EN);
3168 }
3169}
2816/** 3170/**
2817 * intel_update_watermarks - update FIFO watermark values based on current modes 3171 * intel_update_watermarks - update FIFO watermark values based on current modes
2818 * 3172 *
@@ -2882,12 +3236,6 @@ static void intel_update_watermarks(struct drm_device *dev)
2882 if (enabled <= 0) 3236 if (enabled <= 0)
2883 return; 3237 return;
2884 3238
2885 /* Single plane configs can enable self refresh */
2886 if (enabled == 1 && IS_PINEVIEW(dev))
2887 pineview_enable_cxsr(dev, sr_clock, pixel_size);
2888 else if (IS_PINEVIEW(dev))
2889 pineview_disable_cxsr(dev);
2890
2891 dev_priv->display.update_wm(dev, planea_clock, planeb_clock, 3239 dev_priv->display.update_wm(dev, planea_clock, planeb_clock,
2892 sr_hdisplay, pixel_size); 3240 sr_hdisplay, pixel_size);
2893} 3241}
@@ -2924,7 +3272,8 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
2924 bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false; 3272 bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
2925 bool is_edp = false; 3273 bool is_edp = false;
2926 struct drm_mode_config *mode_config = &dev->mode_config; 3274 struct drm_mode_config *mode_config = &dev->mode_config;
2927 struct drm_connector *connector; 3275 struct drm_encoder *encoder;
3276 struct intel_encoder *intel_encoder = NULL;
2928 const intel_limit_t *limit; 3277 const intel_limit_t *limit;
2929 int ret; 3278 int ret;
2930 struct fdi_m_n m_n = {0}; 3279 struct fdi_m_n m_n = {0};
@@ -2935,6 +3284,8 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
2935 int pch_fp_reg = (pipe == 0) ? PCH_FPA0 : PCH_FPB0; 3284 int pch_fp_reg = (pipe == 0) ? PCH_FPA0 : PCH_FPB0;
2936 int pch_dpll_reg = (pipe == 0) ? PCH_DPLL_A : PCH_DPLL_B; 3285 int pch_dpll_reg = (pipe == 0) ? PCH_DPLL_A : PCH_DPLL_B;
2937 int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL; 3286 int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
3287 int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL;
3288 int trans_dpll_sel = (pipe == 0) ? 0 : 1;
2938 int lvds_reg = LVDS; 3289 int lvds_reg = LVDS;
2939 u32 temp; 3290 u32 temp;
2940 int sdvo_pixel_multiply; 3291 int sdvo_pixel_multiply;
@@ -2942,12 +3293,13 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
2942 3293
2943 drm_vblank_pre_modeset(dev, pipe); 3294 drm_vblank_pre_modeset(dev, pipe);
2944 3295
2945 list_for_each_entry(connector, &mode_config->connector_list, head) { 3296 list_for_each_entry(encoder, &mode_config->encoder_list, head) {
2946 struct intel_encoder *intel_encoder = to_intel_encoder(connector);
2947 3297
2948 if (!connector->encoder || connector->encoder->crtc != crtc) 3298 if (!encoder || encoder->crtc != crtc)
2949 continue; 3299 continue;
2950 3300
3301 intel_encoder = enc_to_intel_encoder(encoder);
3302
2951 switch (intel_encoder->type) { 3303 switch (intel_encoder->type) {
2952 case INTEL_OUTPUT_LVDS: 3304 case INTEL_OUTPUT_LVDS:
2953 is_lvds = true; 3305 is_lvds = true;
@@ -3043,14 +3395,12 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
3043 3395
3044 /* FDI link */ 3396 /* FDI link */
3045 if (HAS_PCH_SPLIT(dev)) { 3397 if (HAS_PCH_SPLIT(dev)) {
3046 int lane, link_bw, bpp; 3398 int lane = 0, link_bw, bpp;
3047 /* eDP doesn't require FDI link, so just set DP M/N 3399 /* eDP doesn't require FDI link, so just set DP M/N
3048 according to current link config */ 3400 according to current link config */
3049 if (is_edp) { 3401 if (is_edp) {
3050 struct drm_connector *edp;
3051 target_clock = mode->clock; 3402 target_clock = mode->clock;
3052 edp = intel_pipe_get_connector(crtc); 3403 intel_edp_link_config(intel_encoder,
3053 intel_edp_link_config(to_intel_encoder(edp),
3054 &lane, &link_bw); 3404 &lane, &link_bw);
3055 } else { 3405 } else {
3056 /* DP over FDI requires target mode clock 3406 /* DP over FDI requires target mode clock
@@ -3059,7 +3409,6 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
3059 target_clock = mode->clock; 3409 target_clock = mode->clock;
3060 else 3410 else
3061 target_clock = adjusted_mode->clock; 3411 target_clock = adjusted_mode->clock;
3062 lane = 4;
3063 link_bw = 270000; 3412 link_bw = 270000;
3064 } 3413 }
3065 3414
@@ -3111,6 +3460,18 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
3111 bpp = 24; 3460 bpp = 24;
3112 } 3461 }
3113 3462
3463 if (!lane) {
3464 /*
3465 * Account for spread spectrum to avoid
3466 * oversubscribing the link. Max center spread
3467 * is 2.5%; use 5% for safety's sake.
3468 */
3469 u32 bps = target_clock * bpp * 21 / 20;
3470 lane = bps / (link_bw * 8) + 1;
3471 }
3472
3473 intel_crtc->fdi_lanes = lane;
3474
3114 ironlake_compute_m_n(bpp, lane, target_clock, link_bw, &m_n); 3475 ironlake_compute_m_n(bpp, lane, target_clock, link_bw, &m_n);
3115 } 3476 }
3116 3477
@@ -3265,11 +3626,6 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
3265 pipeconf &= ~PIPEACONF_DOUBLE_WIDE; 3626 pipeconf &= ~PIPEACONF_DOUBLE_WIDE;
3266 } 3627 }
3267 3628
3268 dspcntr |= DISPLAY_PLANE_ENABLE;
3269 pipeconf |= PIPEACONF_ENABLE;
3270 dpll |= DPLL_VCO_ENABLE;
3271
3272
3273 /* Disable the panel fitter if it was on our pipe */ 3629 /* Disable the panel fitter if it was on our pipe */
3274 if (!HAS_PCH_SPLIT(dev) && intel_panel_fitter_pipe(dev) == pipe) 3630 if (!HAS_PCH_SPLIT(dev) && intel_panel_fitter_pipe(dev) == pipe)
3275 I915_WRITE(PFIT_CONTROL, 0); 3631 I915_WRITE(PFIT_CONTROL, 0);
@@ -3292,6 +3648,18 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
3292 udelay(150); 3648 udelay(150);
3293 } 3649 }
3294 3650
3651 /* enable transcoder DPLL */
3652 if (HAS_PCH_CPT(dev)) {
3653 temp = I915_READ(PCH_DPLL_SEL);
3654 if (trans_dpll_sel == 0)
3655 temp |= (TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
3656 else
3657 temp |= (TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
3658 I915_WRITE(PCH_DPLL_SEL, temp);
3659 I915_READ(PCH_DPLL_SEL);
3660 udelay(150);
3661 }
3662
3295 /* The LVDS pin pair needs to be on before the DPLLs are enabled. 3663 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
3296 * This is an exception to the general rule that mode_set doesn't turn 3664 * This is an exception to the general rule that mode_set doesn't turn
3297 * things on. 3665 * things on.
@@ -3303,7 +3671,18 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
3303 lvds_reg = PCH_LVDS; 3671 lvds_reg = PCH_LVDS;
3304 3672
3305 lvds = I915_READ(lvds_reg); 3673 lvds = I915_READ(lvds_reg);
3306 lvds |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP | LVDS_PIPEB_SELECT; 3674 lvds |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
3675 if (pipe == 1) {
3676 if (HAS_PCH_CPT(dev))
3677 lvds |= PORT_TRANS_B_SEL_CPT;
3678 else
3679 lvds |= LVDS_PIPEB_SELECT;
3680 } else {
3681 if (HAS_PCH_CPT(dev))
3682 lvds &= ~PORT_TRANS_SEL_MASK;
3683 else
3684 lvds &= ~LVDS_PIPEB_SELECT;
3685 }
3307 /* set the corresponsding LVDS_BORDER bit */ 3686 /* set the corresponsding LVDS_BORDER bit */
3308 lvds |= dev_priv->lvds_border_bits; 3687 lvds |= dev_priv->lvds_border_bits;
3309 /* Set the B0-B3 data pairs corresponding to whether we're going to 3688 /* Set the B0-B3 data pairs corresponding to whether we're going to
@@ -3321,14 +3700,16 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
3321 /* set the dithering flag */ 3700 /* set the dithering flag */
3322 if (IS_I965G(dev)) { 3701 if (IS_I965G(dev)) {
3323 if (dev_priv->lvds_dither) { 3702 if (dev_priv->lvds_dither) {
3324 if (HAS_PCH_SPLIT(dev)) 3703 if (HAS_PCH_SPLIT(dev)) {
3325 pipeconf |= PIPE_ENABLE_DITHER; 3704 pipeconf |= PIPE_ENABLE_DITHER;
3326 else 3705 pipeconf |= PIPE_DITHER_TYPE_ST01;
3706 } else
3327 lvds |= LVDS_ENABLE_DITHER; 3707 lvds |= LVDS_ENABLE_DITHER;
3328 } else { 3708 } else {
3329 if (HAS_PCH_SPLIT(dev)) 3709 if (HAS_PCH_SPLIT(dev)) {
3330 pipeconf &= ~PIPE_ENABLE_DITHER; 3710 pipeconf &= ~PIPE_ENABLE_DITHER;
3331 else 3711 pipeconf &= ~PIPE_DITHER_TYPE_MASK;
3712 } else
3332 lvds &= ~LVDS_ENABLE_DITHER; 3713 lvds &= ~LVDS_ENABLE_DITHER;
3333 } 3714 }
3334 } 3715 }
@@ -3337,6 +3718,20 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
3337 } 3718 }
3338 if (is_dp) 3719 if (is_dp)
3339 intel_dp_set_m_n(crtc, mode, adjusted_mode); 3720 intel_dp_set_m_n(crtc, mode, adjusted_mode);
3721 else if (HAS_PCH_SPLIT(dev)) {
3722 /* For non-DP output, clear any trans DP clock recovery setting.*/
3723 if (pipe == 0) {
3724 I915_WRITE(TRANSA_DATA_M1, 0);
3725 I915_WRITE(TRANSA_DATA_N1, 0);
3726 I915_WRITE(TRANSA_DP_LINK_M1, 0);
3727 I915_WRITE(TRANSA_DP_LINK_N1, 0);
3728 } else {
3729 I915_WRITE(TRANSB_DATA_M1, 0);
3730 I915_WRITE(TRANSB_DATA_N1, 0);
3731 I915_WRITE(TRANSB_DP_LINK_M1, 0);
3732 I915_WRITE(TRANSB_DP_LINK_N1, 0);
3733 }
3734 }
3340 3735
3341 if (!is_edp) { 3736 if (!is_edp) {
3342 I915_WRITE(fp_reg, fp); 3737 I915_WRITE(fp_reg, fp);
@@ -3411,6 +3806,18 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
3411 /* enable FDI RX PLL too */ 3806 /* enable FDI RX PLL too */
3412 temp = I915_READ(fdi_rx_reg); 3807 temp = I915_READ(fdi_rx_reg);
3413 I915_WRITE(fdi_rx_reg, temp | FDI_RX_PLL_ENABLE); 3808 I915_WRITE(fdi_rx_reg, temp | FDI_RX_PLL_ENABLE);
3809 I915_READ(fdi_rx_reg);
3810 udelay(200);
3811
3812 /* enable FDI TX PLL too */
3813 temp = I915_READ(fdi_tx_reg);
3814 I915_WRITE(fdi_tx_reg, temp | FDI_TX_PLL_ENABLE);
3815 I915_READ(fdi_tx_reg);
3816
3817 /* enable FDI RX PCDCLK */
3818 temp = I915_READ(fdi_rx_reg);
3819 I915_WRITE(fdi_rx_reg, temp | FDI_SEL_PCDCLK);
3820 I915_READ(fdi_rx_reg);
3414 udelay(200); 3821 udelay(200);
3415 } 3822 }
3416 } 3823 }
@@ -3671,6 +4078,7 @@ static struct drm_display_mode load_detect_mode = {
3671}; 4078};
3672 4079
3673struct drm_crtc *intel_get_load_detect_pipe(struct intel_encoder *intel_encoder, 4080struct drm_crtc *intel_get_load_detect_pipe(struct intel_encoder *intel_encoder,
4081 struct drm_connector *connector,
3674 struct drm_display_mode *mode, 4082 struct drm_display_mode *mode,
3675 int *dpms_mode) 4083 int *dpms_mode)
3676{ 4084{
@@ -3729,7 +4137,7 @@ struct drm_crtc *intel_get_load_detect_pipe(struct intel_encoder *intel_encoder,
3729 } 4137 }
3730 4138
3731 encoder->crtc = crtc; 4139 encoder->crtc = crtc;
3732 intel_encoder->base.encoder = encoder; 4140 connector->encoder = encoder;
3733 intel_encoder->load_detect_temp = true; 4141 intel_encoder->load_detect_temp = true;
3734 4142
3735 intel_crtc = to_intel_crtc(crtc); 4143 intel_crtc = to_intel_crtc(crtc);
@@ -3755,7 +4163,8 @@ struct drm_crtc *intel_get_load_detect_pipe(struct intel_encoder *intel_encoder,
3755 return crtc; 4163 return crtc;
3756} 4164}
3757 4165
3758void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder, int dpms_mode) 4166void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder,
4167 struct drm_connector *connector, int dpms_mode)
3759{ 4168{
3760 struct drm_encoder *encoder = &intel_encoder->enc; 4169 struct drm_encoder *encoder = &intel_encoder->enc;
3761 struct drm_device *dev = encoder->dev; 4170 struct drm_device *dev = encoder->dev;
@@ -3765,7 +4174,7 @@ void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder, int dpm
3765 4174
3766 if (intel_encoder->load_detect_temp) { 4175 if (intel_encoder->load_detect_temp) {
3767 encoder->crtc = NULL; 4176 encoder->crtc = NULL;
3768 intel_encoder->base.encoder = NULL; 4177 connector->encoder = NULL;
3769 intel_encoder->load_detect_temp = false; 4178 intel_encoder->load_detect_temp = false;
3770 crtc->enabled = drm_helper_crtc_in_use(crtc); 4179 crtc->enabled = drm_helper_crtc_in_use(crtc);
3771 drm_helper_disable_unused_functions(dev); 4180 drm_helper_disable_unused_functions(dev);
@@ -4392,14 +4801,14 @@ struct drm_crtc *intel_get_crtc_from_pipe(struct drm_device *dev, int pipe)
4392 return crtc; 4801 return crtc;
4393} 4802}
4394 4803
4395static int intel_connector_clones(struct drm_device *dev, int type_mask) 4804static int intel_encoder_clones(struct drm_device *dev, int type_mask)
4396{ 4805{
4397 int index_mask = 0; 4806 int index_mask = 0;
4398 struct drm_connector *connector; 4807 struct drm_encoder *encoder;
4399 int entry = 0; 4808 int entry = 0;
4400 4809
4401 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 4810 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
4402 struct intel_encoder *intel_encoder = to_intel_encoder(connector); 4811 struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
4403 if (type_mask & intel_encoder->clone_mask) 4812 if (type_mask & intel_encoder->clone_mask)
4404 index_mask |= (1 << entry); 4813 index_mask |= (1 << entry);
4405 entry++; 4814 entry++;
@@ -4411,7 +4820,7 @@ static int intel_connector_clones(struct drm_device *dev, int type_mask)
4411static void intel_setup_outputs(struct drm_device *dev) 4820static void intel_setup_outputs(struct drm_device *dev)
4412{ 4821{
4413 struct drm_i915_private *dev_priv = dev->dev_private; 4822 struct drm_i915_private *dev_priv = dev->dev_private;
4414 struct drm_connector *connector; 4823 struct drm_encoder *encoder;
4415 4824
4416 intel_crt_init(dev); 4825 intel_crt_init(dev);
4417 4826
@@ -4426,9 +4835,8 @@ static void intel_setup_outputs(struct drm_device *dev)
4426 intel_dp_init(dev, DP_A); 4835 intel_dp_init(dev, DP_A);
4427 4836
4428 if (I915_READ(HDMIB) & PORT_DETECTED) { 4837 if (I915_READ(HDMIB) & PORT_DETECTED) {
4429 /* check SDVOB */ 4838 /* PCH SDVOB multiplex with HDMIB */
4430 /* found = intel_sdvo_init(dev, HDMIB); */ 4839 found = intel_sdvo_init(dev, PCH_SDVOB);
4431 found = 0;
4432 if (!found) 4840 if (!found)
4433 intel_hdmi_init(dev, HDMIB); 4841 intel_hdmi_init(dev, HDMIB);
4434 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED)) 4842 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
@@ -4494,12 +4902,11 @@ static void intel_setup_outputs(struct drm_device *dev)
4494 if (SUPPORTS_TV(dev)) 4902 if (SUPPORTS_TV(dev))
4495 intel_tv_init(dev); 4903 intel_tv_init(dev);
4496 4904
4497 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 4905 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
4498 struct intel_encoder *intel_encoder = to_intel_encoder(connector); 4906 struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
4499 struct drm_encoder *encoder = &intel_encoder->enc;
4500 4907
4501 encoder->possible_crtcs = intel_encoder->crtc_mask; 4908 encoder->possible_crtcs = intel_encoder->crtc_mask;
4502 encoder->possible_clones = intel_connector_clones(dev, 4909 encoder->possible_clones = intel_encoder_clones(dev,
4503 intel_encoder->clone_mask); 4910 intel_encoder->clone_mask);
4504 } 4911 }
4505} 4912}
@@ -4507,10 +4914,6 @@ static void intel_setup_outputs(struct drm_device *dev)
4507static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb) 4914static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
4508{ 4915{
4509 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); 4916 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
4510 struct drm_device *dev = fb->dev;
4511
4512 if (fb->fbdev)
4513 intelfb_remove(dev, fb);
4514 4917
4515 drm_framebuffer_cleanup(fb); 4918 drm_framebuffer_cleanup(fb);
4516 drm_gem_object_unreference_unlocked(intel_fb->obj); 4919 drm_gem_object_unreference_unlocked(intel_fb->obj);
@@ -4533,18 +4936,13 @@ static const struct drm_framebuffer_funcs intel_fb_funcs = {
4533 .create_handle = intel_user_framebuffer_create_handle, 4936 .create_handle = intel_user_framebuffer_create_handle,
4534}; 4937};
4535 4938
4536int intel_framebuffer_create(struct drm_device *dev, 4939int intel_framebuffer_init(struct drm_device *dev,
4537 struct drm_mode_fb_cmd *mode_cmd, 4940 struct intel_framebuffer *intel_fb,
4538 struct drm_framebuffer **fb, 4941 struct drm_mode_fb_cmd *mode_cmd,
4539 struct drm_gem_object *obj) 4942 struct drm_gem_object *obj)
4540{ 4943{
4541 struct intel_framebuffer *intel_fb;
4542 int ret; 4944 int ret;
4543 4945
4544 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
4545 if (!intel_fb)
4546 return -ENOMEM;
4547
4548 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs); 4946 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
4549 if (ret) { 4947 if (ret) {
4550 DRM_ERROR("framebuffer init failed %d\n", ret); 4948 DRM_ERROR("framebuffer init failed %d\n", ret);
@@ -4552,40 +4950,41 @@ int intel_framebuffer_create(struct drm_device *dev,
4552 } 4950 }
4553 4951
4554 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd); 4952 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
4555
4556 intel_fb->obj = obj; 4953 intel_fb->obj = obj;
4557
4558 *fb = &intel_fb->base;
4559
4560 return 0; 4954 return 0;
4561} 4955}
4562 4956
4563
4564static struct drm_framebuffer * 4957static struct drm_framebuffer *
4565intel_user_framebuffer_create(struct drm_device *dev, 4958intel_user_framebuffer_create(struct drm_device *dev,
4566 struct drm_file *filp, 4959 struct drm_file *filp,
4567 struct drm_mode_fb_cmd *mode_cmd) 4960 struct drm_mode_fb_cmd *mode_cmd)
4568{ 4961{
4569 struct drm_gem_object *obj; 4962 struct drm_gem_object *obj;
4570 struct drm_framebuffer *fb; 4963 struct intel_framebuffer *intel_fb;
4571 int ret; 4964 int ret;
4572 4965
4573 obj = drm_gem_object_lookup(dev, filp, mode_cmd->handle); 4966 obj = drm_gem_object_lookup(dev, filp, mode_cmd->handle);
4574 if (!obj) 4967 if (!obj)
4575 return NULL; 4968 return NULL;
4576 4969
4577 ret = intel_framebuffer_create(dev, mode_cmd, &fb, obj); 4970 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
4971 if (!intel_fb)
4972 return NULL;
4973
4974 ret = intel_framebuffer_init(dev, intel_fb,
4975 mode_cmd, obj);
4578 if (ret) { 4976 if (ret) {
4579 drm_gem_object_unreference_unlocked(obj); 4977 drm_gem_object_unreference_unlocked(obj);
4978 kfree(intel_fb);
4580 return NULL; 4979 return NULL;
4581 } 4980 }
4582 4981
4583 return fb; 4982 return &intel_fb->base;
4584} 4983}
4585 4984
4586static const struct drm_mode_config_funcs intel_mode_funcs = { 4985static const struct drm_mode_config_funcs intel_mode_funcs = {
4587 .fb_create = intel_user_framebuffer_create, 4986 .fb_create = intel_user_framebuffer_create,
4588 .fb_changed = intelfb_probe, 4987 .output_poll_changed = intel_fb_output_poll_changed,
4589}; 4988};
4590 4989
4591static struct drm_gem_object * 4990static struct drm_gem_object *
@@ -4594,7 +4993,7 @@ intel_alloc_power_context(struct drm_device *dev)
4594 struct drm_gem_object *pwrctx; 4993 struct drm_gem_object *pwrctx;
4595 int ret; 4994 int ret;
4596 4995
4597 pwrctx = drm_gem_object_alloc(dev, 4096); 4996 pwrctx = i915_gem_alloc_object(dev, 4096);
4598 if (!pwrctx) { 4997 if (!pwrctx) {
4599 DRM_DEBUG("failed to alloc power context, RC6 disabled\n"); 4998 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
4600 return NULL; 4999 return NULL;
@@ -4732,6 +5131,25 @@ void intel_init_clock_gating(struct drm_device *dev)
4732 } 5131 }
4733 5132
4734 I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate); 5133 I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
5134
5135 /*
5136 * According to the spec the following bits should be set in
5137 * order to enable memory self-refresh
5138 * The bit 22/21 of 0x42004
5139 * The bit 5 of 0x42020
5140 * The bit 15 of 0x45000
5141 */
5142 if (IS_IRONLAKE(dev)) {
5143 I915_WRITE(ILK_DISPLAY_CHICKEN2,
5144 (I915_READ(ILK_DISPLAY_CHICKEN2) |
5145 ILK_DPARB_GATE | ILK_VSDPFD_FULL));
5146 I915_WRITE(ILK_DSPCLK_GATE,
5147 (I915_READ(ILK_DSPCLK_GATE) |
5148 ILK_DPARB_CLK_GATE));
5149 I915_WRITE(DISP_ARB_CTL,
5150 (I915_READ(DISP_ARB_CTL) |
5151 DISP_FBC_WM_DIS));
5152 }
4735 return; 5153 return;
4736 } else if (IS_G4X(dev)) { 5154 } else if (IS_G4X(dev)) {
4737 uint32_t dspclk_gate; 5155 uint32_t dspclk_gate;
@@ -4809,8 +5227,7 @@ static void intel_init_display(struct drm_device *dev)
4809 else 5227 else
4810 dev_priv->display.dpms = i9xx_crtc_dpms; 5228 dev_priv->display.dpms = i9xx_crtc_dpms;
4811 5229
4812 /* Only mobile has FBC, leave pointers NULL for other chips */ 5230 if (I915_HAS_FBC(dev)) {
4813 if (IS_MOBILE(dev)) {
4814 if (IS_GM45(dev)) { 5231 if (IS_GM45(dev)) {
4815 dev_priv->display.fbc_enabled = g4x_fbc_enabled; 5232 dev_priv->display.fbc_enabled = g4x_fbc_enabled;
4816 dev_priv->display.enable_fbc = g4x_enable_fbc; 5233 dev_priv->display.enable_fbc = g4x_enable_fbc;
@@ -4847,23 +5264,46 @@ static void intel_init_display(struct drm_device *dev)
4847 i830_get_display_clock_speed; 5264 i830_get_display_clock_speed;
4848 5265
4849 /* For FIFO watermark updates */ 5266 /* For FIFO watermark updates */
4850 if (HAS_PCH_SPLIT(dev)) 5267 if (HAS_PCH_SPLIT(dev)) {
4851 dev_priv->display.update_wm = NULL; 5268 if (IS_IRONLAKE(dev)) {
4852 else if (IS_G4X(dev)) 5269 if (I915_READ(MLTR_ILK) & ILK_SRLT_MASK)
5270 dev_priv->display.update_wm = ironlake_update_wm;
5271 else {
5272 DRM_DEBUG_KMS("Failed to get proper latency. "
5273 "Disable CxSR\n");
5274 dev_priv->display.update_wm = NULL;
5275 }
5276 } else
5277 dev_priv->display.update_wm = NULL;
5278 } else if (IS_PINEVIEW(dev)) {
5279 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
5280 dev_priv->fsb_freq,
5281 dev_priv->mem_freq)) {
5282 DRM_INFO("failed to find known CxSR latency "
5283 "(found fsb freq %d, mem freq %d), "
5284 "disabling CxSR\n",
5285 dev_priv->fsb_freq, dev_priv->mem_freq);
5286 /* Disable CxSR and never update its watermark again */
5287 pineview_disable_cxsr(dev);
5288 dev_priv->display.update_wm = NULL;
5289 } else
5290 dev_priv->display.update_wm = pineview_update_wm;
5291 } else if (IS_G4X(dev))
4853 dev_priv->display.update_wm = g4x_update_wm; 5292 dev_priv->display.update_wm = g4x_update_wm;
4854 else if (IS_I965G(dev)) 5293 else if (IS_I965G(dev))
4855 dev_priv->display.update_wm = i965_update_wm; 5294 dev_priv->display.update_wm = i965_update_wm;
4856 else if (IS_I9XX(dev) || IS_MOBILE(dev)) { 5295 else if (IS_I9XX(dev)) {
4857 dev_priv->display.update_wm = i9xx_update_wm; 5296 dev_priv->display.update_wm = i9xx_update_wm;
4858 dev_priv->display.get_fifo_size = i9xx_get_fifo_size; 5297 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
5298 } else if (IS_I85X(dev)) {
5299 dev_priv->display.update_wm = i9xx_update_wm;
5300 dev_priv->display.get_fifo_size = i85x_get_fifo_size;
4859 } else { 5301 } else {
4860 if (IS_I85X(dev)) 5302 dev_priv->display.update_wm = i830_update_wm;
4861 dev_priv->display.get_fifo_size = i85x_get_fifo_size; 5303 if (IS_845G(dev))
4862 else if (IS_845G(dev))
4863 dev_priv->display.get_fifo_size = i845_get_fifo_size; 5304 dev_priv->display.get_fifo_size = i845_get_fifo_size;
4864 else 5305 else
4865 dev_priv->display.get_fifo_size = i830_get_fifo_size; 5306 dev_priv->display.get_fifo_size = i830_get_fifo_size;
4866 dev_priv->display.update_wm = i830_update_wm;
4867 } 5307 }
4868} 5308}
4869 5309
@@ -4922,13 +5362,6 @@ void intel_modeset_init(struct drm_device *dev)
4922 (unsigned long)dev); 5362 (unsigned long)dev);
4923 5363
4924 intel_setup_overlay(dev); 5364 intel_setup_overlay(dev);
4925
4926 if (IS_PINEVIEW(dev) && !intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
4927 dev_priv->fsb_freq,
4928 dev_priv->mem_freq))
4929 DRM_INFO("failed to find known CxSR latency "
4930 "(found fsb freq %d, mem freq %d), disabling CxSR\n",
4931 dev_priv->fsb_freq, dev_priv->mem_freq);
4932} 5365}
4933 5366
4934void intel_modeset_cleanup(struct drm_device *dev) 5367void intel_modeset_cleanup(struct drm_device *dev)
@@ -4939,6 +5372,9 @@ void intel_modeset_cleanup(struct drm_device *dev)
4939 5372
4940 mutex_lock(&dev->struct_mutex); 5373 mutex_lock(&dev->struct_mutex);
4941 5374
5375 drm_kms_helper_poll_fini(dev);
5376 intel_fbdev_fini(dev);
5377
4942 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { 5378 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
4943 /* Skip inactive CRTCs */ 5379 /* Skip inactive CRTCs */
4944 if (!crtc->fb) 5380 if (!crtc->fb)
@@ -4973,14 +5409,29 @@ void intel_modeset_cleanup(struct drm_device *dev)
4973} 5409}
4974 5410
4975 5411
4976/* current intel driver doesn't take advantage of encoders 5412/*
4977 always give back the encoder for the connector 5413 * Return which encoder is currently attached for connector.
4978*/ 5414 */
4979struct drm_encoder *intel_best_encoder(struct drm_connector *connector) 5415struct drm_encoder *intel_attached_encoder (struct drm_connector *connector)
4980{ 5416{
4981 struct intel_encoder *intel_encoder = to_intel_encoder(connector); 5417 struct drm_mode_object *obj;
5418 struct drm_encoder *encoder;
5419 int i;
4982 5420
4983 return &intel_encoder->enc; 5421 for (i = 0; i < DRM_CONNECTOR_MAX_ENCODER; i++) {
5422 if (connector->encoder_ids[i] == 0)
5423 break;
5424
5425 obj = drm_mode_object_find(connector->dev,
5426 connector->encoder_ids[i],
5427 DRM_MODE_OBJECT_ENCODER);
5428 if (!obj)
5429 continue;
5430
5431 encoder = obj_to_encoder(obj);
5432 return encoder;
5433 }
5434 return NULL;
4984} 5435}
4985 5436
4986/* 5437/*
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-22 17:54:11 -0500