1 files changed, 38 insertions, 16 deletions

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 2a3f707caab8..f425b23e3803 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1872,7 +1872,7 @@ static void intel_update_fbc(struct drm_device *dev)
         if (enable_fbc < 0) {
                 DRM_DEBUG_KMS("fbc set to per-chip default\n");
                 enable_fbc = 1;
-                if (INTEL_INFO(dev)->gen <= 5)
+                if (INTEL_INFO(dev)->gen <= 6)
                         enable_fbc = 0;
         }
         if (!enable_fbc) {
@@ -5307,6 +5307,7 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
                 }
         }
 
+        pipeconf &= ~PIPECONF_INTERLACE_MASK;
         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
                 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
                 /* the chip adds 2 halflines automatically */
@@ -5317,7 +5318,7 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
                 adjusted_mode->crtc_vsync_end -= 1;
                 adjusted_mode->crtc_vsync_start -= 1;
         } else
-                pipeconf &= ~PIPECONF_INTERLACE_MASK; /* progressive */
+                pipeconf |= PIPECONF_PROGRESSIVE;
 
         I915_WRITE(HTOTAL(pipe),
                    (adjusted_mode->crtc_hdisplay - 1) |
@@ -5808,12 +5809,15 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
         if (is_lvds) {
                 temp = I915_READ(PCH_LVDS);
                 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
-                if (HAS_PCH_CPT(dev))
+                if (HAS_PCH_CPT(dev)) {
+                        temp &= ~PORT_TRANS_SEL_MASK;
                         temp |= PORT_TRANS_SEL_CPT(pipe);
-                else if (pipe == 1)
-                        temp |= LVDS_PIPEB_SELECT;
-                else
-                        temp &= ~LVDS_PIPEB_SELECT;
+                } else {
+                        if (pipe == 1)
+                                temp |= LVDS_PIPEB_SELECT;
+                        else
+                                temp &= ~LVDS_PIPEB_SELECT;
+                }
 
                 /* set the corresponsding LVDS_BORDER bit */
                 temp |= dev_priv->lvds_border_bits;
@@ -5899,6 +5903,7 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
                 }
         }
 
+        pipeconf &= ~PIPECONF_INTERLACE_MASK;
         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
                 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
                 /* the chip adds 2 halflines automatically */
@@ -5909,7 +5914,7 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
                 adjusted_mode->crtc_vsync_end -= 1;
                 adjusted_mode->crtc_vsync_start -= 1;
         } else
-                pipeconf &= ~PIPECONF_INTERLACE_W_FIELD_INDICATION; /* progressive */
+                pipeconf |= PIPECONF_PROGRESSIVE;
 
         I915_WRITE(HTOTAL(pipe),
                    (adjusted_mode->crtc_hdisplay - 1) |
@@ -8179,8 +8184,8 @@ void gen6_enable_rps(struct drm_i915_private *dev_priv)
         I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
 
         if (intel_enable_rc6(dev_priv->dev))
-                rc6_mask = GEN6_RC_CTL_RC6p_ENABLE |
-                        GEN6_RC_CTL_RC6_ENABLE;
+                rc6_mask = GEN6_RC_CTL_RC6_ENABLE |
+                        (IS_GEN7(dev_priv->dev)) ? GEN6_RC_CTL_RC6p_ENABLE : 0;
 
         I915_WRITE(GEN6_RC_CONTROL,
                    rc6_mask |
@@ -8458,12 +8463,32 @@ static void ivybridge_init_clock_gating(struct drm_device *dev)
         I915_WRITE(WM2_LP_ILK, 0);
         I915_WRITE(WM1_LP_ILK, 0);
 
+        /* According to the spec, bit 13 (RCZUNIT) must be set on IVB.
+         * This implements the WaDisableRCZUnitClockGating workaround.
+         */
+        I915_WRITE(GEN6_UCGCTL2, GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
+
         I915_WRITE(ILK_DSPCLK_GATE, IVB_VRHUNIT_CLK_GATE);
 
         I915_WRITE(IVB_CHICKEN3,
                    CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
                    CHICKEN3_DGMG_DONE_FIX_DISABLE);
 
+        /* Apply the WaDisableRHWOOptimizationForRenderHang workaround. */
+        I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
+                   GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
+
+        /* WaApplyL3ControlAndL3ChickenMode requires those two on Ivy Bridge */
+        I915_WRITE(GEN7_L3CNTLREG1,
+                        GEN7_WA_FOR_GEN7_L3_CONTROL);
+        I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
+                        GEN7_WA_L3_CHICKEN_MODE);
+
+        /* This is required by WaCatErrorRejectionIssue */
+        I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
+                        I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
+                        GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
+
         for_each_pipe(pipe) {
                 I915_WRITE(DSPCNTR(pipe),
                            I915_READ(DSPCNTR(pipe)) |
@@ -9025,12 +9050,9 @@ void intel_modeset_init(struct drm_device *dev)
 
         for (i = 0; i < dev_priv->num_pipe; i++) {
                 intel_crtc_init(dev, i);
-                if (HAS_PCH_SPLIT(dev)) {
-                        ret = intel_plane_init(dev, i);
-                        if (ret)
-                                DRM_ERROR("plane %d init failed: %d\n",
-                                          i, ret);
-                }
+                ret = intel_plane_init(dev, i);
+                if (ret)
+                        DRM_DEBUG_KMS("plane %d init failed: %d\n", i, ret);
         }
 
         /* Just disable it once at startup */