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path: root/drivers/gpu/drm/i915/intel_display.c
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Diffstat (limited to 'drivers/gpu/drm/i915/intel_display.c')
-rw-r--r--drivers/gpu/drm/i915/intel_display.c762
1 files changed, 405 insertions, 357 deletions
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 5ec10e02341b..979228594599 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -29,6 +29,7 @@
29#include <linux/i2c.h> 29#include <linux/i2c.h>
30#include <linux/kernel.h> 30#include <linux/kernel.h>
31#include <linux/slab.h> 31#include <linux/slab.h>
32#include <linux/vgaarb.h>
32#include "drmP.h" 33#include "drmP.h"
33#include "intel_drv.h" 34#include "intel_drv.h"
34#include "i915_drm.h" 35#include "i915_drm.h"
@@ -976,14 +977,84 @@ intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
976 return true; 977 return true;
977} 978}
978 979
979void 980/**
980intel_wait_for_vblank(struct drm_device *dev) 981 * intel_wait_for_vblank - wait for vblank on a given pipe
982 * @dev: drm device
983 * @pipe: pipe to wait for
984 *
985 * Wait for vblank to occur on a given pipe. Needed for various bits of
986 * mode setting code.
987 */
988void intel_wait_for_vblank(struct drm_device *dev, int pipe)
981{ 989{
982 /* Wait for 20ms, i.e. one cycle at 50hz. */ 990 struct drm_i915_private *dev_priv = dev->dev_private;
983 if (in_dbg_master()) 991 int pipestat_reg = (pipe == 0 ? PIPEASTAT : PIPEBSTAT);
984 mdelay(20); /* The kernel debugger cannot call msleep() */ 992
985 else 993 /* Clear existing vblank status. Note this will clear any other
986 msleep(20); 994 * sticky status fields as well.
995 *
996 * This races with i915_driver_irq_handler() with the result
997 * that either function could miss a vblank event. Here it is not
998 * fatal, as we will either wait upon the next vblank interrupt or
999 * timeout. Generally speaking intel_wait_for_vblank() is only
1000 * called during modeset at which time the GPU should be idle and
1001 * should *not* be performing page flips and thus not waiting on
1002 * vblanks...
1003 * Currently, the result of us stealing a vblank from the irq
1004 * handler is that a single frame will be skipped during swapbuffers.
1005 */
1006 I915_WRITE(pipestat_reg,
1007 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
1008
1009 /* Wait for vblank interrupt bit to set */
1010 if (wait_for((I915_READ(pipestat_reg) &
1011 PIPE_VBLANK_INTERRUPT_STATUS),
1012 50, 0))
1013 DRM_DEBUG_KMS("vblank wait timed out\n");
1014}
1015
1016/*
1017 * intel_wait_for_pipe_off - wait for pipe to turn off
1018 * @dev: drm device
1019 * @pipe: pipe to wait for
1020 *
1021 * After disabling a pipe, we can't wait for vblank in the usual way,
1022 * spinning on the vblank interrupt status bit, since we won't actually
1023 * see an interrupt when the pipe is disabled.
1024 *
1025 * On Gen4 and above:
1026 * wait for the pipe register state bit to turn off
1027 *
1028 * Otherwise:
1029 * wait for the display line value to settle (it usually
1030 * ends up stopping at the start of the next frame).
1031 *
1032 */
1033static void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
1034{
1035 struct drm_i915_private *dev_priv = dev->dev_private;
1036
1037 if (INTEL_INFO(dev)->gen >= 4) {
1038 int pipeconf_reg = (pipe == 0 ? PIPEACONF : PIPEBCONF);
1039
1040 /* Wait for the Pipe State to go off */
1041 if (wait_for((I915_READ(pipeconf_reg) & I965_PIPECONF_ACTIVE) == 0,
1042 100, 0))
1043 DRM_DEBUG_KMS("pipe_off wait timed out\n");
1044 } else {
1045 u32 last_line;
1046 int pipedsl_reg = (pipe == 0 ? PIPEADSL : PIPEBDSL);
1047 unsigned long timeout = jiffies + msecs_to_jiffies(100);
1048
1049 /* Wait for the display line to settle */
1050 do {
1051 last_line = I915_READ(pipedsl_reg) & DSL_LINEMASK;
1052 mdelay(5);
1053 } while (((I915_READ(pipedsl_reg) & DSL_LINEMASK) != last_line) &&
1054 time_after(timeout, jiffies));
1055 if (time_after(jiffies, timeout))
1056 DRM_DEBUG_KMS("pipe_off wait timed out\n");
1057 }
987} 1058}
988 1059
989/* Parameters have changed, update FBC info */ 1060/* Parameters have changed, update FBC info */
@@ -1037,7 +1108,6 @@ static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1037void i8xx_disable_fbc(struct drm_device *dev) 1108void i8xx_disable_fbc(struct drm_device *dev)
1038{ 1109{
1039 struct drm_i915_private *dev_priv = dev->dev_private; 1110 struct drm_i915_private *dev_priv = dev->dev_private;
1040 unsigned long timeout = jiffies + msecs_to_jiffies(1);
1041 u32 fbc_ctl; 1111 u32 fbc_ctl;
1042 1112
1043 if (!I915_HAS_FBC(dev)) 1113 if (!I915_HAS_FBC(dev))
@@ -1052,16 +1122,11 @@ void i8xx_disable_fbc(struct drm_device *dev)
1052 I915_WRITE(FBC_CONTROL, fbc_ctl); 1122 I915_WRITE(FBC_CONTROL, fbc_ctl);
1053 1123
1054 /* Wait for compressing bit to clear */ 1124 /* Wait for compressing bit to clear */
1055 while (I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) { 1125 if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10, 0)) {
1056 if (time_after(jiffies, timeout)) { 1126 DRM_DEBUG_KMS("FBC idle timed out\n");
1057 DRM_DEBUG_DRIVER("FBC idle timed out\n"); 1127 return;
1058 break;
1059 }
1060 ; /* do nothing */
1061 } 1128 }
1062 1129
1063 intel_wait_for_vblank(dev);
1064
1065 DRM_DEBUG_KMS("disabled FBC\n"); 1130 DRM_DEBUG_KMS("disabled FBC\n");
1066} 1131}
1067 1132
@@ -1118,7 +1183,6 @@ void g4x_disable_fbc(struct drm_device *dev)
1118 dpfc_ctl = I915_READ(DPFC_CONTROL); 1183 dpfc_ctl = I915_READ(DPFC_CONTROL);
1119 dpfc_ctl &= ~DPFC_CTL_EN; 1184 dpfc_ctl &= ~DPFC_CTL_EN;
1120 I915_WRITE(DPFC_CONTROL, dpfc_ctl); 1185 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
1121 intel_wait_for_vblank(dev);
1122 1186
1123 DRM_DEBUG_KMS("disabled FBC\n"); 1187 DRM_DEBUG_KMS("disabled FBC\n");
1124} 1188}
@@ -1179,7 +1243,6 @@ void ironlake_disable_fbc(struct drm_device *dev)
1179 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL); 1243 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
1180 dpfc_ctl &= ~DPFC_CTL_EN; 1244 dpfc_ctl &= ~DPFC_CTL_EN;
1181 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl); 1245 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
1182 intel_wait_for_vblank(dev);
1183 1246
1184 DRM_DEBUG_KMS("disabled FBC\n"); 1247 DRM_DEBUG_KMS("disabled FBC\n");
1185} 1248}
@@ -1453,7 +1516,7 @@ intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1453 dspcntr &= ~DISPPLANE_TILED; 1516 dspcntr &= ~DISPPLANE_TILED;
1454 } 1517 }
1455 1518
1456 if (IS_IRONLAKE(dev)) 1519 if (HAS_PCH_SPLIT(dev))
1457 /* must disable */ 1520 /* must disable */
1458 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; 1521 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
1459 1522
@@ -1462,23 +1525,22 @@ intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1462 Start = obj_priv->gtt_offset; 1525 Start = obj_priv->gtt_offset;
1463 Offset = y * fb->pitch + x * (fb->bits_per_pixel / 8); 1526 Offset = y * fb->pitch + x * (fb->bits_per_pixel / 8);
1464 1527
1465 DRM_DEBUG("Writing base %08lX %08lX %d %d\n", Start, Offset, x, y); 1528 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
1529 Start, Offset, x, y, fb->pitch);
1466 I915_WRITE(dspstride, fb->pitch); 1530 I915_WRITE(dspstride, fb->pitch);
1467 if (IS_I965G(dev)) { 1531 if (IS_I965G(dev)) {
1468 I915_WRITE(dspbase, Offset);
1469 I915_READ(dspbase);
1470 I915_WRITE(dspsurf, Start); 1532 I915_WRITE(dspsurf, Start);
1471 I915_READ(dspsurf);
1472 I915_WRITE(dsptileoff, (y << 16) | x); 1533 I915_WRITE(dsptileoff, (y << 16) | x);
1534 I915_WRITE(dspbase, Offset);
1473 } else { 1535 } else {
1474 I915_WRITE(dspbase, Start + Offset); 1536 I915_WRITE(dspbase, Start + Offset);
1475 I915_READ(dspbase);
1476 } 1537 }
1538 POSTING_READ(dspbase);
1477 1539
1478 if ((IS_I965G(dev) || plane == 0)) 1540 if (IS_I965G(dev) || plane == 0)
1479 intel_update_fbc(crtc, &crtc->mode); 1541 intel_update_fbc(crtc, &crtc->mode);
1480 1542
1481 intel_wait_for_vblank(dev); 1543 intel_wait_for_vblank(dev, intel_crtc->pipe);
1482 intel_increase_pllclock(crtc, true); 1544 intel_increase_pllclock(crtc, true);
1483 1545
1484 return 0; 1546 return 0;
@@ -1489,7 +1551,6 @@ intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
1489 struct drm_framebuffer *old_fb) 1551 struct drm_framebuffer *old_fb)
1490{ 1552{
1491 struct drm_device *dev = crtc->dev; 1553 struct drm_device *dev = crtc->dev;
1492 struct drm_i915_private *dev_priv = dev->dev_private;
1493 struct drm_i915_master_private *master_priv; 1554 struct drm_i915_master_private *master_priv;
1494 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 1555 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1495 struct intel_framebuffer *intel_fb; 1556 struct intel_framebuffer *intel_fb;
@@ -1497,13 +1558,6 @@ intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
1497 struct drm_gem_object *obj; 1558 struct drm_gem_object *obj;
1498 int pipe = intel_crtc->pipe; 1559 int pipe = intel_crtc->pipe;
1499 int plane = intel_crtc->plane; 1560 int plane = intel_crtc->plane;
1500 unsigned long Start, Offset;
1501 int dspbase = (plane == 0 ? DSPAADDR : DSPBADDR);
1502 int dspsurf = (plane == 0 ? DSPASURF : DSPBSURF);
1503 int dspstride = (plane == 0) ? DSPASTRIDE : DSPBSTRIDE;
1504 int dsptileoff = (plane == 0 ? DSPATILEOFF : DSPBTILEOFF);
1505 int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
1506 u32 dspcntr;
1507 int ret; 1561 int ret;
1508 1562
1509 /* no fb bound */ 1563 /* no fb bound */
@@ -1539,73 +1593,18 @@ intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
1539 return ret; 1593 return ret;
1540 } 1594 }
1541 1595
1542 dspcntr = I915_READ(dspcntr_reg); 1596 ret = intel_pipe_set_base_atomic(crtc, crtc->fb, x, y);
1543 /* Mask out pixel format bits in case we change it */ 1597 if (ret) {
1544 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1545 switch (crtc->fb->bits_per_pixel) {
1546 case 8:
1547 dspcntr |= DISPPLANE_8BPP;
1548 break;
1549 case 16:
1550 if (crtc->fb->depth == 15)
1551 dspcntr |= DISPPLANE_15_16BPP;
1552 else
1553 dspcntr |= DISPPLANE_16BPP;
1554 break;
1555 case 24:
1556 case 32:
1557 if (crtc->fb->depth == 30)
1558 dspcntr |= DISPPLANE_32BPP_30BIT_NO_ALPHA;
1559 else
1560 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
1561 break;
1562 default:
1563 DRM_ERROR("Unknown color depth\n");
1564 i915_gem_object_unpin(obj); 1598 i915_gem_object_unpin(obj);
1565 mutex_unlock(&dev->struct_mutex); 1599 mutex_unlock(&dev->struct_mutex);
1566 return -EINVAL; 1600 return ret;
1567 }
1568 if (IS_I965G(dev)) {
1569 if (obj_priv->tiling_mode != I915_TILING_NONE)
1570 dspcntr |= DISPPLANE_TILED;
1571 else
1572 dspcntr &= ~DISPPLANE_TILED;
1573 }
1574
1575 if (HAS_PCH_SPLIT(dev))
1576 /* must disable */
1577 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
1578
1579 I915_WRITE(dspcntr_reg, dspcntr);
1580
1581 Start = obj_priv->gtt_offset;
1582 Offset = y * crtc->fb->pitch + x * (crtc->fb->bits_per_pixel / 8);
1583
1584 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
1585 Start, Offset, x, y, crtc->fb->pitch);
1586 I915_WRITE(dspstride, crtc->fb->pitch);
1587 if (IS_I965G(dev)) {
1588 I915_WRITE(dspbase, Offset);
1589 I915_READ(dspbase);
1590 I915_WRITE(dspsurf, Start);
1591 I915_READ(dspsurf);
1592 I915_WRITE(dsptileoff, (y << 16) | x);
1593 } else {
1594 I915_WRITE(dspbase, Start + Offset);
1595 I915_READ(dspbase);
1596 } 1601 }
1597 1602
1598 if ((IS_I965G(dev) || plane == 0))
1599 intel_update_fbc(crtc, &crtc->mode);
1600
1601 intel_wait_for_vblank(dev);
1602
1603 if (old_fb) { 1603 if (old_fb) {
1604 intel_fb = to_intel_framebuffer(old_fb); 1604 intel_fb = to_intel_framebuffer(old_fb);
1605 obj_priv = to_intel_bo(intel_fb->obj); 1605 obj_priv = to_intel_bo(intel_fb->obj);
1606 i915_gem_object_unpin(intel_fb->obj); 1606 i915_gem_object_unpin(intel_fb->obj);
1607 } 1607 }
1608 intel_increase_pllclock(crtc, true);
1609 1608
1610 mutex_unlock(&dev->struct_mutex); 1609 mutex_unlock(&dev->struct_mutex);
1611 1610
@@ -1627,54 +1626,6 @@ intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
1627 return 0; 1626 return 0;
1628} 1627}
1629 1628
1630/* Disable the VGA plane that we never use */
1631static void i915_disable_vga (struct drm_device *dev)
1632{
1633 struct drm_i915_private *dev_priv = dev->dev_private;
1634 u8 sr1;
1635 u32 vga_reg;
1636
1637 if (HAS_PCH_SPLIT(dev))
1638 vga_reg = CPU_VGACNTRL;
1639 else
1640 vga_reg = VGACNTRL;
1641
1642 if (I915_READ(vga_reg) & VGA_DISP_DISABLE)
1643 return;
1644
1645 I915_WRITE8(VGA_SR_INDEX, 1);
1646 sr1 = I915_READ8(VGA_SR_DATA);
1647 I915_WRITE8(VGA_SR_DATA, sr1 | (1 << 5));
1648 udelay(100);
1649
1650 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
1651}
1652
1653static void ironlake_disable_pll_edp (struct drm_crtc *crtc)
1654{
1655 struct drm_device *dev = crtc->dev;
1656 struct drm_i915_private *dev_priv = dev->dev_private;
1657 u32 dpa_ctl;
1658
1659 DRM_DEBUG_KMS("\n");
1660 dpa_ctl = I915_READ(DP_A);
1661 dpa_ctl &= ~DP_PLL_ENABLE;
1662 I915_WRITE(DP_A, dpa_ctl);
1663}
1664
1665static void ironlake_enable_pll_edp (struct drm_crtc *crtc)
1666{
1667 struct drm_device *dev = crtc->dev;
1668 struct drm_i915_private *dev_priv = dev->dev_private;
1669 u32 dpa_ctl;
1670
1671 dpa_ctl = I915_READ(DP_A);
1672 dpa_ctl |= DP_PLL_ENABLE;
1673 I915_WRITE(DP_A, dpa_ctl);
1674 udelay(200);
1675}
1676
1677
1678static void ironlake_set_pll_edp (struct drm_crtc *crtc, int clock) 1629static void ironlake_set_pll_edp (struct drm_crtc *crtc, int clock)
1679{ 1630{
1680 struct drm_device *dev = crtc->dev; 1631 struct drm_device *dev = crtc->dev;
@@ -1928,9 +1879,6 @@ static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
1928 int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL; 1879 int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL;
1929 int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL; 1880 int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
1930 int transconf_reg = (pipe == 0) ? TRANSACONF : TRANSBCONF; 1881 int transconf_reg = (pipe == 0) ? TRANSACONF : TRANSBCONF;
1931 int pf_ctl_reg = (pipe == 0) ? PFA_CTL_1 : PFB_CTL_1;
1932 int pf_win_size = (pipe == 0) ? PFA_WIN_SZ : PFB_WIN_SZ;
1933 int pf_win_pos = (pipe == 0) ? PFA_WIN_POS : PFB_WIN_POS;
1934 int cpu_htot_reg = (pipe == 0) ? HTOTAL_A : HTOTAL_B; 1882 int cpu_htot_reg = (pipe == 0) ? HTOTAL_A : HTOTAL_B;
1935 int cpu_hblank_reg = (pipe == 0) ? HBLANK_A : HBLANK_B; 1883 int cpu_hblank_reg = (pipe == 0) ? HBLANK_A : HBLANK_B;
1936 int cpu_hsync_reg = (pipe == 0) ? HSYNC_A : HSYNC_B; 1884 int cpu_hsync_reg = (pipe == 0) ? HSYNC_A : HSYNC_B;
@@ -1945,7 +1893,6 @@ static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
1945 int trans_vsync_reg = (pipe == 0) ? TRANS_VSYNC_A : TRANS_VSYNC_B; 1893 int trans_vsync_reg = (pipe == 0) ? TRANS_VSYNC_A : TRANS_VSYNC_B;
1946 int trans_dpll_sel = (pipe == 0) ? 0 : 1; 1894 int trans_dpll_sel = (pipe == 0) ? 0 : 1;
1947 u32 temp; 1895 u32 temp;
1948 int n;
1949 u32 pipe_bpc; 1896 u32 pipe_bpc;
1950 1897
1951 temp = I915_READ(pipeconf_reg); 1898 temp = I915_READ(pipeconf_reg);
@@ -1958,7 +1905,7 @@ static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
1958 case DRM_MODE_DPMS_ON: 1905 case DRM_MODE_DPMS_ON:
1959 case DRM_MODE_DPMS_STANDBY: 1906 case DRM_MODE_DPMS_STANDBY:
1960 case DRM_MODE_DPMS_SUSPEND: 1907 case DRM_MODE_DPMS_SUSPEND:
1961 DRM_DEBUG_KMS("crtc %d dpms on\n", pipe); 1908 DRM_DEBUG_KMS("crtc %d/%d dpms on\n", pipe, plane);
1962 1909
1963 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { 1910 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1964 temp = I915_READ(PCH_LVDS); 1911 temp = I915_READ(PCH_LVDS);
@@ -1968,10 +1915,7 @@ static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
1968 } 1915 }
1969 } 1916 }
1970 1917
1971 if (HAS_eDP) { 1918 if (!HAS_eDP) {
1972 /* enable eDP PLL */
1973 ironlake_enable_pll_edp(crtc);
1974 } else {
1975 1919
1976 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */ 1920 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
1977 temp = I915_READ(fdi_rx_reg); 1921 temp = I915_READ(fdi_rx_reg);
@@ -2003,17 +1947,19 @@ static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
2003 } 1947 }
2004 1948
2005 /* Enable panel fitting for LVDS */ 1949 /* Enable panel fitting for LVDS */
2006 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) 1950 if (dev_priv->pch_pf_size &&
2007 || HAS_eDP || intel_pch_has_edp(crtc)) { 1951 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)
2008 temp = I915_READ(pf_ctl_reg); 1952 || HAS_eDP || intel_pch_has_edp(crtc))) {
2009 I915_WRITE(pf_ctl_reg, temp | PF_ENABLE | PF_FILTER_MED_3x3); 1953 /* Force use of hard-coded filter coefficients
2010 1954 * as some pre-programmed values are broken,
2011 /* currently full aspect */ 1955 * e.g. x201.
2012 I915_WRITE(pf_win_pos, 0); 1956 */
2013 1957 I915_WRITE(pipe ? PFB_CTL_1 : PFA_CTL_1,
2014 I915_WRITE(pf_win_size, 1958 PF_ENABLE | PF_FILTER_MED_3x3);
2015 (dev_priv->panel_fixed_mode->hdisplay << 16) | 1959 I915_WRITE(pipe ? PFB_WIN_POS : PFA_WIN_POS,
2016 (dev_priv->panel_fixed_mode->vdisplay)); 1960 dev_priv->pch_pf_pos);
1961 I915_WRITE(pipe ? PFB_WIN_SZ : PFA_WIN_SZ,
1962 dev_priv->pch_pf_size);
2017 } 1963 }
2018 1964
2019 /* Enable CPU pipe */ 1965 /* Enable CPU pipe */
@@ -2097,9 +2043,10 @@ static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
2097 int reg; 2043 int reg;
2098 2044
2099 reg = I915_READ(trans_dp_ctl); 2045 reg = I915_READ(trans_dp_ctl);
2100 reg &= ~TRANS_DP_PORT_SEL_MASK; 2046 reg &= ~(TRANS_DP_PORT_SEL_MASK |
2101 reg = TRANS_DP_OUTPUT_ENABLE | 2047 TRANS_DP_SYNC_MASK);
2102 TRANS_DP_ENH_FRAMING; 2048 reg |= (TRANS_DP_OUTPUT_ENABLE |
2049 TRANS_DP_ENH_FRAMING);
2103 2050
2104 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC) 2051 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
2105 reg |= TRANS_DP_HSYNC_ACTIVE_HIGH; 2052 reg |= TRANS_DP_HSYNC_ACTIVE_HIGH;
@@ -2137,18 +2084,17 @@ static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
2137 I915_WRITE(transconf_reg, temp | TRANS_ENABLE); 2084 I915_WRITE(transconf_reg, temp | TRANS_ENABLE);
2138 I915_READ(transconf_reg); 2085 I915_READ(transconf_reg);
2139 2086
2140 while ((I915_READ(transconf_reg) & TRANS_STATE_ENABLE) == 0) 2087 if (wait_for(I915_READ(transconf_reg) & TRANS_STATE_ENABLE, 100, 1))
2141 ; 2088 DRM_ERROR("failed to enable transcoder\n");
2142
2143 } 2089 }
2144 2090
2145 intel_crtc_load_lut(crtc); 2091 intel_crtc_load_lut(crtc);
2146 2092
2147 intel_update_fbc(crtc, &crtc->mode); 2093 intel_update_fbc(crtc, &crtc->mode);
2094 break;
2148 2095
2149 break;
2150 case DRM_MODE_DPMS_OFF: 2096 case DRM_MODE_DPMS_OFF:
2151 DRM_DEBUG_KMS("crtc %d dpms off\n", pipe); 2097 DRM_DEBUG_KMS("crtc %d/%d dpms off\n", pipe, plane);
2152 2098
2153 drm_vblank_off(dev, pipe); 2099 drm_vblank_off(dev, pipe);
2154 /* Disable display plane */ 2100 /* Disable display plane */
@@ -2164,40 +2110,22 @@ static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
2164 dev_priv->display.disable_fbc) 2110 dev_priv->display.disable_fbc)
2165 dev_priv->display.disable_fbc(dev); 2111 dev_priv->display.disable_fbc(dev);
2166 2112
2167 i915_disable_vga(dev);
2168
2169 /* disable cpu pipe, disable after all planes disabled */ 2113 /* disable cpu pipe, disable after all planes disabled */
2170 temp = I915_READ(pipeconf_reg); 2114 temp = I915_READ(pipeconf_reg);
2171 if ((temp & PIPEACONF_ENABLE) != 0) { 2115 if ((temp & PIPEACONF_ENABLE) != 0) {
2172 I915_WRITE(pipeconf_reg, temp & ~PIPEACONF_ENABLE); 2116 I915_WRITE(pipeconf_reg, temp & ~PIPEACONF_ENABLE);
2173 I915_READ(pipeconf_reg); 2117
2174 n = 0;
2175 /* wait for cpu pipe off, pipe state */ 2118 /* wait for cpu pipe off, pipe state */
2176 while ((I915_READ(pipeconf_reg) & I965_PIPECONF_ACTIVE) != 0) { 2119 if (wait_for((I915_READ(pipeconf_reg) & I965_PIPECONF_ACTIVE) == 0, 50, 1))
2177 n++; 2120 DRM_ERROR("failed to turn off cpu pipe\n");
2178 if (n < 60) {
2179 udelay(500);
2180 continue;
2181 } else {
2182 DRM_DEBUG_KMS("pipe %d off delay\n",
2183 pipe);
2184 break;
2185 }
2186 }
2187 } else 2121 } else
2188 DRM_DEBUG_KMS("crtc %d is disabled\n", pipe); 2122 DRM_DEBUG_KMS("crtc %d is disabled\n", pipe);
2189 2123
2190 udelay(100); 2124 udelay(100);
2191 2125
2192 /* Disable PF */ 2126 /* Disable PF */
2193 temp = I915_READ(pf_ctl_reg); 2127 I915_WRITE(pipe ? PFB_CTL_1 : PFA_CTL_1, 0);
2194 if ((temp & PF_ENABLE) != 0) { 2128 I915_WRITE(pipe ? PFB_WIN_SZ : PFA_WIN_SZ, 0);
2195 I915_WRITE(pf_ctl_reg, temp & ~PF_ENABLE);
2196 I915_READ(pf_ctl_reg);
2197 }
2198 I915_WRITE(pf_win_size, 0);
2199 POSTING_READ(pf_win_size);
2200
2201 2129
2202 /* disable CPU FDI tx and PCH FDI rx */ 2130 /* disable CPU FDI tx and PCH FDI rx */
2203 temp = I915_READ(fdi_tx_reg); 2131 temp = I915_READ(fdi_tx_reg);
@@ -2244,20 +2172,10 @@ static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
2244 temp = I915_READ(transconf_reg); 2172 temp = I915_READ(transconf_reg);
2245 if ((temp & TRANS_ENABLE) != 0) { 2173 if ((temp & TRANS_ENABLE) != 0) {
2246 I915_WRITE(transconf_reg, temp & ~TRANS_ENABLE); 2174 I915_WRITE(transconf_reg, temp & ~TRANS_ENABLE);
2247 I915_READ(transconf_reg); 2175
2248 n = 0;
2249 /* wait for PCH transcoder off, transcoder state */ 2176 /* wait for PCH transcoder off, transcoder state */
2250 while ((I915_READ(transconf_reg) & TRANS_STATE_ENABLE) != 0) { 2177 if (wait_for((I915_READ(transconf_reg) & TRANS_STATE_ENABLE) == 0, 50, 1))
2251 n++; 2178 DRM_ERROR("failed to disable transcoder\n");
2252 if (n < 60) {
2253 udelay(500);
2254 continue;
2255 } else {
2256 DRM_DEBUG_KMS("transcoder %d off "
2257 "delay\n", pipe);
2258 break;
2259 }
2260 }
2261 } 2179 }
2262 2180
2263 temp = I915_READ(transconf_reg); 2181 temp = I915_READ(transconf_reg);
@@ -2294,10 +2212,6 @@ static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
2294 I915_WRITE(pch_dpll_reg, temp & ~DPLL_VCO_ENABLE); 2212 I915_WRITE(pch_dpll_reg, temp & ~DPLL_VCO_ENABLE);
2295 I915_READ(pch_dpll_reg); 2213 I915_READ(pch_dpll_reg);
2296 2214
2297 if (HAS_eDP) {
2298 ironlake_disable_pll_edp(crtc);
2299 }
2300
2301 /* Switch from PCDclk to Rawclk */ 2215 /* Switch from PCDclk to Rawclk */
2302 temp = I915_READ(fdi_rx_reg); 2216 temp = I915_READ(fdi_rx_reg);
2303 temp &= ~FDI_SEL_PCDCLK; 2217 temp &= ~FDI_SEL_PCDCLK;
@@ -2372,8 +2286,6 @@ static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
2372 case DRM_MODE_DPMS_ON: 2286 case DRM_MODE_DPMS_ON:
2373 case DRM_MODE_DPMS_STANDBY: 2287 case DRM_MODE_DPMS_STANDBY:
2374 case DRM_MODE_DPMS_SUSPEND: 2288 case DRM_MODE_DPMS_SUSPEND:
2375 intel_update_watermarks(dev);
2376
2377 /* Enable the DPLL */ 2289 /* Enable the DPLL */
2378 temp = I915_READ(dpll_reg); 2290 temp = I915_READ(dpll_reg);
2379 if ((temp & DPLL_VCO_ENABLE) == 0) { 2291 if ((temp & DPLL_VCO_ENABLE) == 0) {
@@ -2413,8 +2325,6 @@ static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
2413 intel_crtc_dpms_overlay(intel_crtc, true); 2325 intel_crtc_dpms_overlay(intel_crtc, true);
2414 break; 2326 break;
2415 case DRM_MODE_DPMS_OFF: 2327 case DRM_MODE_DPMS_OFF:
2416 intel_update_watermarks(dev);
2417
2418 /* Give the overlay scaler a chance to disable if it's on this pipe */ 2328 /* Give the overlay scaler a chance to disable if it's on this pipe */
2419 intel_crtc_dpms_overlay(intel_crtc, false); 2329 intel_crtc_dpms_overlay(intel_crtc, false);
2420 drm_vblank_off(dev, pipe); 2330 drm_vblank_off(dev, pipe);
@@ -2423,9 +2333,6 @@ static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
2423 dev_priv->display.disable_fbc) 2333 dev_priv->display.disable_fbc)
2424 dev_priv->display.disable_fbc(dev); 2334 dev_priv->display.disable_fbc(dev);
2425 2335
2426 /* Disable the VGA plane that we never use */
2427 i915_disable_vga(dev);
2428
2429 /* Disable display plane */ 2336 /* Disable display plane */
2430 temp = I915_READ(dspcntr_reg); 2337 temp = I915_READ(dspcntr_reg);
2431 if ((temp & DISPLAY_PLANE_ENABLE) != 0) { 2338 if ((temp & DISPLAY_PLANE_ENABLE) != 0) {
@@ -2435,15 +2342,13 @@ static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
2435 I915_READ(dspbase_reg); 2342 I915_READ(dspbase_reg);
2436 } 2343 }
2437 2344
2438 if (!IS_I9XX(dev)) {
2439 /* Wait for vblank for the disable to take effect */
2440 intel_wait_for_vblank(dev);
2441 }
2442
2443 /* Don't disable pipe A or pipe A PLLs if needed */ 2345 /* Don't disable pipe A or pipe A PLLs if needed */
2444 if (pipeconf_reg == PIPEACONF && 2346 if (pipeconf_reg == PIPEACONF &&
2445 (dev_priv->quirks & QUIRK_PIPEA_FORCE)) 2347 (dev_priv->quirks & QUIRK_PIPEA_FORCE)) {
2348 /* Wait for vblank for the disable to take effect */
2349 intel_wait_for_vblank(dev, pipe);
2446 goto skip_pipe_off; 2350 goto skip_pipe_off;
2351 }
2447 2352
2448 /* Next, disable display pipes */ 2353 /* Next, disable display pipes */
2449 temp = I915_READ(pipeconf_reg); 2354 temp = I915_READ(pipeconf_reg);
@@ -2452,8 +2357,8 @@ static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
2452 I915_READ(pipeconf_reg); 2357 I915_READ(pipeconf_reg);
2453 } 2358 }
2454 2359
2455 /* Wait for vblank for the disable to take effect. */ 2360 /* Wait for the pipe to turn off */
2456 intel_wait_for_vblank(dev); 2361 intel_wait_for_pipe_off(dev, pipe);
2457 2362
2458 temp = I915_READ(dpll_reg); 2363 temp = I915_READ(dpll_reg);
2459 if ((temp & DPLL_VCO_ENABLE) != 0) { 2364 if ((temp & DPLL_VCO_ENABLE) != 0) {
@@ -2469,9 +2374,6 @@ static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
2469 2374
2470/** 2375/**
2471 * Sets the power management mode of the pipe and plane. 2376 * Sets the power management mode of the pipe and plane.
2472 *
2473 * This code should probably grow support for turning the cursor off and back
2474 * on appropriately at the same time as we're turning the pipe off/on.
2475 */ 2377 */
2476static void intel_crtc_dpms(struct drm_crtc *crtc, int mode) 2378static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
2477{ 2379{
@@ -2482,9 +2384,29 @@ static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
2482 int pipe = intel_crtc->pipe; 2384 int pipe = intel_crtc->pipe;
2483 bool enabled; 2385 bool enabled;
2484 2386
2485 dev_priv->display.dpms(crtc, mode); 2387 if (intel_crtc->dpms_mode == mode)
2388 return;
2486 2389
2487 intel_crtc->dpms_mode = mode; 2390 intel_crtc->dpms_mode = mode;
2391 intel_crtc->cursor_on = mode == DRM_MODE_DPMS_ON;
2392
2393 /* When switching on the display, ensure that SR is disabled
2394 * with multiple pipes prior to enabling to new pipe.
2395 *
2396 * When switching off the display, make sure the cursor is
2397 * properly hidden prior to disabling the pipe.
2398 */
2399 if (mode == DRM_MODE_DPMS_ON)
2400 intel_update_watermarks(dev);
2401 else
2402 intel_crtc_update_cursor(crtc);
2403
2404 dev_priv->display.dpms(crtc, mode);
2405
2406 if (mode == DRM_MODE_DPMS_ON)
2407 intel_crtc_update_cursor(crtc);
2408 else
2409 intel_update_watermarks(dev);
2488 2410
2489 if (!dev->primary->master) 2411 if (!dev->primary->master)
2490 return; 2412 return;
@@ -2536,16 +2458,38 @@ void intel_encoder_commit (struct drm_encoder *encoder)
2536 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON); 2458 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
2537} 2459}
2538 2460
2461void intel_encoder_destroy(struct drm_encoder *encoder)
2462{
2463 struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
2464
2465 if (intel_encoder->ddc_bus)
2466 intel_i2c_destroy(intel_encoder->ddc_bus);
2467
2468 if (intel_encoder->i2c_bus)
2469 intel_i2c_destroy(intel_encoder->i2c_bus);
2470
2471 drm_encoder_cleanup(encoder);
2472 kfree(intel_encoder);
2473}
2474
2539static bool intel_crtc_mode_fixup(struct drm_crtc *crtc, 2475static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
2540 struct drm_display_mode *mode, 2476 struct drm_display_mode *mode,
2541 struct drm_display_mode *adjusted_mode) 2477 struct drm_display_mode *adjusted_mode)
2542{ 2478{
2543 struct drm_device *dev = crtc->dev; 2479 struct drm_device *dev = crtc->dev;
2480
2544 if (HAS_PCH_SPLIT(dev)) { 2481 if (HAS_PCH_SPLIT(dev)) {
2545 /* FDI link clock is fixed at 2.7G */ 2482 /* FDI link clock is fixed at 2.7G */
2546 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4) 2483 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
2547 return false; 2484 return false;
2548 } 2485 }
2486
2487 /* XXX some encoders set the crtcinfo, others don't.
2488 * Obviously we need some form of conflict resolution here...
2489 */
2490 if (adjusted_mode->crtc_htotal == 0)
2491 drm_mode_set_crtcinfo(adjusted_mode, 0);
2492
2549 return true; 2493 return true;
2550} 2494}
2551 2495
@@ -2845,14 +2789,8 @@ static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
2845 /* Don't promote wm_size to unsigned... */ 2789 /* Don't promote wm_size to unsigned... */
2846 if (wm_size > (long)wm->max_wm) 2790 if (wm_size > (long)wm->max_wm)
2847 wm_size = wm->max_wm; 2791 wm_size = wm->max_wm;
2848 if (wm_size <= 0) { 2792 if (wm_size <= 0)
2849 wm_size = wm->default_wm; 2793 wm_size = wm->default_wm;
2850 DRM_ERROR("Insufficient FIFO for plane, expect flickering:"
2851 " entries required = %ld, available = %lu.\n",
2852 entries_required + wm->guard_size,
2853 wm->fifo_size);
2854 }
2855
2856 return wm_size; 2794 return wm_size;
2857} 2795}
2858 2796
@@ -2867,7 +2805,7 @@ struct cxsr_latency {
2867 unsigned long cursor_hpll_disable; 2805 unsigned long cursor_hpll_disable;
2868}; 2806};
2869 2807
2870static struct cxsr_latency cxsr_latency_table[] = { 2808static const struct cxsr_latency cxsr_latency_table[] = {
2871 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */ 2809 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
2872 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */ 2810 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
2873 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */ 2811 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
@@ -2905,11 +2843,13 @@ static struct cxsr_latency cxsr_latency_table[] = {
2905 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */ 2843 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
2906}; 2844};
2907 2845
2908static struct cxsr_latency *intel_get_cxsr_latency(int is_desktop, int is_ddr3, 2846static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
2909 int fsb, int mem) 2847 int is_ddr3,
2848 int fsb,
2849 int mem)
2910{ 2850{
2851 const struct cxsr_latency *latency;
2911 int i; 2852 int i;
2912 struct cxsr_latency *latency;
2913 2853
2914 if (fsb == 0 || mem == 0) 2854 if (fsb == 0 || mem == 0)
2915 return NULL; 2855 return NULL;
@@ -2930,13 +2870,9 @@ static struct cxsr_latency *intel_get_cxsr_latency(int is_desktop, int is_ddr3,
2930static void pineview_disable_cxsr(struct drm_device *dev) 2870static void pineview_disable_cxsr(struct drm_device *dev)
2931{ 2871{
2932 struct drm_i915_private *dev_priv = dev->dev_private; 2872 struct drm_i915_private *dev_priv = dev->dev_private;
2933 u32 reg;
2934 2873
2935 /* deactivate cxsr */ 2874 /* deactivate cxsr */
2936 reg = I915_READ(DSPFW3); 2875 I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN);
2937 reg &= ~(PINEVIEW_SELF_REFRESH_EN);
2938 I915_WRITE(DSPFW3, reg);
2939 DRM_INFO("Big FIFO is disabled\n");
2940} 2876}
2941 2877
2942/* 2878/*
@@ -3024,12 +2960,12 @@ static void pineview_update_wm(struct drm_device *dev, int planea_clock,
3024 int pixel_size) 2960 int pixel_size)
3025{ 2961{
3026 struct drm_i915_private *dev_priv = dev->dev_private; 2962 struct drm_i915_private *dev_priv = dev->dev_private;
2963 const struct cxsr_latency *latency;
3027 u32 reg; 2964 u32 reg;
3028 unsigned long wm; 2965 unsigned long wm;
3029 struct cxsr_latency *latency;
3030 int sr_clock; 2966 int sr_clock;
3031 2967
3032 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3, 2968 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
3033 dev_priv->fsb_freq, dev_priv->mem_freq); 2969 dev_priv->fsb_freq, dev_priv->mem_freq);
3034 if (!latency) { 2970 if (!latency) {
3035 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n"); 2971 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
@@ -3075,9 +3011,8 @@ static void pineview_update_wm(struct drm_device *dev, int planea_clock,
3075 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg); 3011 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
3076 3012
3077 /* activate cxsr */ 3013 /* activate cxsr */
3078 reg = I915_READ(DSPFW3); 3014 I915_WRITE(DSPFW3,
3079 reg |= PINEVIEW_SELF_REFRESH_EN; 3015 I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN);
3080 I915_WRITE(DSPFW3, reg);
3081 DRM_DEBUG_KMS("Self-refresh is enabled\n"); 3016 DRM_DEBUG_KMS("Self-refresh is enabled\n");
3082 } else { 3017 } else {
3083 pineview_disable_cxsr(dev); 3018 pineview_disable_cxsr(dev);
@@ -3354,12 +3289,11 @@ static void ironlake_update_wm(struct drm_device *dev, int planea_clock,
3354 int line_count; 3289 int line_count;
3355 int planea_htotal = 0, planeb_htotal = 0; 3290 int planea_htotal = 0, planeb_htotal = 0;
3356 struct drm_crtc *crtc; 3291 struct drm_crtc *crtc;
3357 struct intel_crtc *intel_crtc;
3358 3292
3359 /* Need htotal for all active display plane */ 3293 /* Need htotal for all active display plane */
3360 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { 3294 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3361 intel_crtc = to_intel_crtc(crtc); 3295 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3362 if (crtc->enabled) { 3296 if (intel_crtc->dpms_mode == DRM_MODE_DPMS_ON) {
3363 if (intel_crtc->plane == 0) 3297 if (intel_crtc->plane == 0)
3364 planea_htotal = crtc->mode.htotal; 3298 planea_htotal = crtc->mode.htotal;
3365 else 3299 else
@@ -3470,8 +3404,7 @@ static void ironlake_update_wm(struct drm_device *dev, int planea_clock,
3470 reg_value = I915_READ(WM1_LP_ILK); 3404 reg_value = I915_READ(WM1_LP_ILK);
3471 reg_value &= ~(WM1_LP_LATENCY_MASK | WM1_LP_SR_MASK | 3405 reg_value &= ~(WM1_LP_LATENCY_MASK | WM1_LP_SR_MASK |
3472 WM1_LP_CURSOR_MASK); 3406 WM1_LP_CURSOR_MASK);
3473 reg_value |= WM1_LP_SR_EN | 3407 reg_value |= (ilk_sr_latency << WM1_LP_LATENCY_SHIFT) |
3474 (ilk_sr_latency << WM1_LP_LATENCY_SHIFT) |
3475 (sr_wm << WM1_LP_SR_SHIFT) | cursor_wm; 3408 (sr_wm << WM1_LP_SR_SHIFT) | cursor_wm;
3476 3409
3477 I915_WRITE(WM1_LP_ILK, reg_value); 3410 I915_WRITE(WM1_LP_ILK, reg_value);
@@ -3519,7 +3452,6 @@ static void intel_update_watermarks(struct drm_device *dev)
3519{ 3452{
3520 struct drm_i915_private *dev_priv = dev->dev_private; 3453 struct drm_i915_private *dev_priv = dev->dev_private;
3521 struct drm_crtc *crtc; 3454 struct drm_crtc *crtc;
3522 struct intel_crtc *intel_crtc;
3523 int sr_hdisplay = 0; 3455 int sr_hdisplay = 0;
3524 unsigned long planea_clock = 0, planeb_clock = 0, sr_clock = 0; 3456 unsigned long planea_clock = 0, planeb_clock = 0, sr_clock = 0;
3525 int enabled = 0, pixel_size = 0; 3457 int enabled = 0, pixel_size = 0;
@@ -3530,8 +3462,8 @@ static void intel_update_watermarks(struct drm_device *dev)
3530 3462
3531 /* Get the clock config from both planes */ 3463 /* Get the clock config from both planes */
3532 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { 3464 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3533 intel_crtc = to_intel_crtc(crtc); 3465 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3534 if (crtc->enabled) { 3466 if (intel_crtc->dpms_mode == DRM_MODE_DPMS_ON) {
3535 enabled++; 3467 enabled++;
3536 if (intel_crtc->plane == 0) { 3468 if (intel_crtc->plane == 0) {
3537 DRM_DEBUG_KMS("plane A (pipe %d) clock: %d\n", 3469 DRM_DEBUG_KMS("plane A (pipe %d) clock: %d\n",
@@ -3589,10 +3521,9 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
3589 u32 dpll = 0, fp = 0, fp2 = 0, dspcntr, pipeconf; 3521 u32 dpll = 0, fp = 0, fp2 = 0, dspcntr, pipeconf;
3590 bool ok, has_reduced_clock = false, is_sdvo = false, is_dvo = false; 3522 bool ok, has_reduced_clock = false, is_sdvo = false, is_dvo = false;
3591 bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false; 3523 bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
3592 bool is_edp = false; 3524 struct intel_encoder *has_edp_encoder = NULL;
3593 struct drm_mode_config *mode_config = &dev->mode_config; 3525 struct drm_mode_config *mode_config = &dev->mode_config;
3594 struct drm_encoder *encoder; 3526 struct drm_encoder *encoder;
3595 struct intel_encoder *intel_encoder = NULL;
3596 const intel_limit_t *limit; 3527 const intel_limit_t *limit;
3597 int ret; 3528 int ret;
3598 struct fdi_m_n m_n = {0}; 3529 struct fdi_m_n m_n = {0};
@@ -3613,12 +3544,12 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
3613 drm_vblank_pre_modeset(dev, pipe); 3544 drm_vblank_pre_modeset(dev, pipe);
3614 3545
3615 list_for_each_entry(encoder, &mode_config->encoder_list, head) { 3546 list_for_each_entry(encoder, &mode_config->encoder_list, head) {
3547 struct intel_encoder *intel_encoder;
3616 3548
3617 if (!encoder || encoder->crtc != crtc) 3549 if (encoder->crtc != crtc)
3618 continue; 3550 continue;
3619 3551
3620 intel_encoder = enc_to_intel_encoder(encoder); 3552 intel_encoder = enc_to_intel_encoder(encoder);
3621
3622 switch (intel_encoder->type) { 3553 switch (intel_encoder->type) {
3623 case INTEL_OUTPUT_LVDS: 3554 case INTEL_OUTPUT_LVDS:
3624 is_lvds = true; 3555 is_lvds = true;
@@ -3642,7 +3573,7 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
3642 is_dp = true; 3573 is_dp = true;
3643 break; 3574 break;
3644 case INTEL_OUTPUT_EDP: 3575 case INTEL_OUTPUT_EDP:
3645 is_edp = true; 3576 has_edp_encoder = intel_encoder;
3646 break; 3577 break;
3647 } 3578 }
3648 3579
@@ -3720,10 +3651,10 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
3720 int lane = 0, link_bw, bpp; 3651 int lane = 0, link_bw, bpp;
3721 /* eDP doesn't require FDI link, so just set DP M/N 3652 /* eDP doesn't require FDI link, so just set DP M/N
3722 according to current link config */ 3653 according to current link config */
3723 if (is_edp) { 3654 if (has_edp_encoder) {
3724 target_clock = mode->clock; 3655 target_clock = mode->clock;
3725 intel_edp_link_config(intel_encoder, 3656 intel_edp_link_config(has_edp_encoder,
3726 &lane, &link_bw); 3657 &lane, &link_bw);
3727 } else { 3658 } else {
3728 /* DP over FDI requires target mode clock 3659 /* DP over FDI requires target mode clock
3729 instead of link clock */ 3660 instead of link clock */
@@ -3744,7 +3675,7 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
3744 temp |= PIPE_8BPC; 3675 temp |= PIPE_8BPC;
3745 else 3676 else
3746 temp |= PIPE_6BPC; 3677 temp |= PIPE_6BPC;
3747 } else if (is_edp || (is_dp && intel_pch_has_edp(crtc))) { 3678 } else if (has_edp_encoder || (is_dp && intel_pch_has_edp(crtc))) {
3748 switch (dev_priv->edp_bpp/3) { 3679 switch (dev_priv->edp_bpp/3) {
3749 case 8: 3680 case 8:
3750 temp |= PIPE_8BPC; 3681 temp |= PIPE_8BPC;
@@ -3817,7 +3748,7 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
3817 3748
3818 udelay(200); 3749 udelay(200);
3819 3750
3820 if (is_edp) { 3751 if (has_edp_encoder) {
3821 if (dev_priv->lvds_use_ssc) { 3752 if (dev_priv->lvds_use_ssc) {
3822 temp |= DREF_SSC1_ENABLE; 3753 temp |= DREF_SSC1_ENABLE;
3823 I915_WRITE(PCH_DREF_CONTROL, temp); 3754 I915_WRITE(PCH_DREF_CONTROL, temp);
@@ -3966,9 +3897,7 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
3966 dpll_reg = pch_dpll_reg; 3897 dpll_reg = pch_dpll_reg;
3967 } 3898 }
3968 3899
3969 if (is_edp) { 3900 if (!has_edp_encoder) {
3970 ironlake_disable_pll_edp(crtc);
3971 } else if ((dpll & DPLL_VCO_ENABLE)) {
3972 I915_WRITE(fp_reg, fp); 3901 I915_WRITE(fp_reg, fp);
3973 I915_WRITE(dpll_reg, dpll & ~DPLL_VCO_ENABLE); 3902 I915_WRITE(dpll_reg, dpll & ~DPLL_VCO_ENABLE);
3974 I915_READ(dpll_reg); 3903 I915_READ(dpll_reg);
@@ -4063,7 +3992,7 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
4063 } 3992 }
4064 } 3993 }
4065 3994
4066 if (!is_edp) { 3995 if (!has_edp_encoder) {
4067 I915_WRITE(fp_reg, fp); 3996 I915_WRITE(fp_reg, fp);
4068 I915_WRITE(dpll_reg, dpll); 3997 I915_WRITE(dpll_reg, dpll);
4069 I915_READ(dpll_reg); 3998 I915_READ(dpll_reg);
@@ -4142,7 +4071,7 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
4142 I915_WRITE(link_m1_reg, m_n.link_m); 4071 I915_WRITE(link_m1_reg, m_n.link_m);
4143 I915_WRITE(link_n1_reg, m_n.link_n); 4072 I915_WRITE(link_n1_reg, m_n.link_n);
4144 4073
4145 if (is_edp) { 4074 if (has_edp_encoder) {
4146 ironlake_set_pll_edp(crtc, adjusted_mode->clock); 4075 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
4147 } else { 4076 } else {
4148 /* enable FDI RX PLL too */ 4077 /* enable FDI RX PLL too */
@@ -4167,7 +4096,7 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
4167 I915_WRITE(pipeconf_reg, pipeconf); 4096 I915_WRITE(pipeconf_reg, pipeconf);
4168 I915_READ(pipeconf_reg); 4097 I915_READ(pipeconf_reg);
4169 4098
4170 intel_wait_for_vblank(dev); 4099 intel_wait_for_vblank(dev, pipe);
4171 4100
4172 if (IS_IRONLAKE(dev)) { 4101 if (IS_IRONLAKE(dev)) {
4173 /* enable address swizzle for tiling buffer */ 4102 /* enable address swizzle for tiling buffer */
@@ -4180,9 +4109,6 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
4180 /* Flush the plane changes */ 4109 /* Flush the plane changes */
4181 ret = intel_pipe_set_base(crtc, x, y, old_fb); 4110 ret = intel_pipe_set_base(crtc, x, y, old_fb);
4182 4111
4183 if ((IS_I965G(dev) || plane == 0))
4184 intel_update_fbc(crtc, &crtc->mode);
4185
4186 intel_update_watermarks(dev); 4112 intel_update_watermarks(dev);
4187 4113
4188 drm_vblank_post_modeset(dev, pipe); 4114 drm_vblank_post_modeset(dev, pipe);
@@ -4216,6 +4142,62 @@ void intel_crtc_load_lut(struct drm_crtc *crtc)
4216 } 4142 }
4217} 4143}
4218 4144
4145static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
4146{
4147 struct drm_device *dev = crtc->dev;
4148 struct drm_i915_private *dev_priv = dev->dev_private;
4149 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4150 bool visible = base != 0;
4151 u32 cntl;
4152
4153 if (intel_crtc->cursor_visible == visible)
4154 return;
4155
4156 cntl = I915_READ(CURACNTR);
4157 if (visible) {
4158 /* On these chipsets we can only modify the base whilst
4159 * the cursor is disabled.
4160 */
4161 I915_WRITE(CURABASE, base);
4162
4163 cntl &= ~(CURSOR_FORMAT_MASK);
4164 /* XXX width must be 64, stride 256 => 0x00 << 28 */
4165 cntl |= CURSOR_ENABLE |
4166 CURSOR_GAMMA_ENABLE |
4167 CURSOR_FORMAT_ARGB;
4168 } else
4169 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
4170 I915_WRITE(CURACNTR, cntl);
4171
4172 intel_crtc->cursor_visible = visible;
4173}
4174
4175static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
4176{
4177 struct drm_device *dev = crtc->dev;
4178 struct drm_i915_private *dev_priv = dev->dev_private;
4179 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4180 int pipe = intel_crtc->pipe;
4181 bool visible = base != 0;
4182
4183 if (intel_crtc->cursor_visible != visible) {
4184 uint32_t cntl = I915_READ(pipe == 0 ? CURACNTR : CURBCNTR);
4185 if (base) {
4186 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
4187 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
4188 cntl |= pipe << 28; /* Connect to correct pipe */
4189 } else {
4190 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
4191 cntl |= CURSOR_MODE_DISABLE;
4192 }
4193 I915_WRITE(pipe == 0 ? CURACNTR : CURBCNTR, cntl);
4194
4195 intel_crtc->cursor_visible = visible;
4196 }
4197 /* and commit changes on next vblank */
4198 I915_WRITE(pipe == 0 ? CURABASE : CURBBASE, base);
4199}
4200
4219/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */ 4201/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
4220static void intel_crtc_update_cursor(struct drm_crtc *crtc) 4202static void intel_crtc_update_cursor(struct drm_crtc *crtc)
4221{ 4203{
@@ -4225,12 +4207,12 @@ static void intel_crtc_update_cursor(struct drm_crtc *crtc)
4225 int pipe = intel_crtc->pipe; 4207 int pipe = intel_crtc->pipe;
4226 int x = intel_crtc->cursor_x; 4208 int x = intel_crtc->cursor_x;
4227 int y = intel_crtc->cursor_y; 4209 int y = intel_crtc->cursor_y;
4228 uint32_t base, pos; 4210 u32 base, pos;
4229 bool visible; 4211 bool visible;
4230 4212
4231 pos = 0; 4213 pos = 0;
4232 4214
4233 if (crtc->fb) { 4215 if (intel_crtc->cursor_on && crtc->fb) {
4234 base = intel_crtc->cursor_addr; 4216 base = intel_crtc->cursor_addr;
4235 if (x > (int) crtc->fb->width) 4217 if (x > (int) crtc->fb->width)
4236 base = 0; 4218 base = 0;
@@ -4259,37 +4241,14 @@ static void intel_crtc_update_cursor(struct drm_crtc *crtc)
4259 pos |= y << CURSOR_Y_SHIFT; 4241 pos |= y << CURSOR_Y_SHIFT;
4260 4242
4261 visible = base != 0; 4243 visible = base != 0;
4262 if (!visible && !intel_crtc->cursor_visble) 4244 if (!visible && !intel_crtc->cursor_visible)
4263 return; 4245 return;
4264 4246
4265 I915_WRITE(pipe == 0 ? CURAPOS : CURBPOS, pos); 4247 I915_WRITE(pipe == 0 ? CURAPOS : CURBPOS, pos);
4266 if (intel_crtc->cursor_visble != visible) { 4248 if (IS_845G(dev) || IS_I865G(dev))
4267 uint32_t cntl = I915_READ(pipe == 0 ? CURACNTR : CURBCNTR); 4249 i845_update_cursor(crtc, base);
4268 if (base) { 4250 else
4269 /* Hooray for CUR*CNTR differences */ 4251 i9xx_update_cursor(crtc, base);
4270 if (IS_MOBILE(dev) || IS_I9XX(dev)) {
4271 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
4272 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
4273 cntl |= pipe << 28; /* Connect to correct pipe */
4274 } else {
4275 cntl &= ~(CURSOR_FORMAT_MASK);
4276 cntl |= CURSOR_ENABLE;
4277 cntl |= CURSOR_FORMAT_ARGB | CURSOR_GAMMA_ENABLE;
4278 }
4279 } else {
4280 if (IS_MOBILE(dev) || IS_I9XX(dev)) {
4281 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
4282 cntl |= CURSOR_MODE_DISABLE;
4283 } else {
4284 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
4285 }
4286 }
4287 I915_WRITE(pipe == 0 ? CURACNTR : CURBCNTR, cntl);
4288
4289 intel_crtc->cursor_visble = visible;
4290 }
4291 /* and commit changes on next vblank */
4292 I915_WRITE(pipe == 0 ? CURABASE : CURBBASE, base);
4293 4252
4294 if (visible) 4253 if (visible)
4295 intel_mark_busy(dev, to_intel_framebuffer(crtc->fb)->obj); 4254 intel_mark_busy(dev, to_intel_framebuffer(crtc->fb)->obj);
@@ -4354,8 +4313,10 @@ static int intel_crtc_cursor_set(struct drm_crtc *crtc,
4354 4313
4355 addr = obj_priv->gtt_offset; 4314 addr = obj_priv->gtt_offset;
4356 } else { 4315 } else {
4316 int align = IS_I830(dev) ? 16 * 1024 : 256;
4357 ret = i915_gem_attach_phys_object(dev, bo, 4317 ret = i915_gem_attach_phys_object(dev, bo,
4358 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1); 4318 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
4319 align);
4359 if (ret) { 4320 if (ret) {
4360 DRM_ERROR("failed to attach phys object\n"); 4321 DRM_ERROR("failed to attach phys object\n");
4361 goto fail_locked; 4322 goto fail_locked;
@@ -4544,7 +4505,7 @@ struct drm_crtc *intel_get_load_detect_pipe(struct intel_encoder *intel_encoder,
4544 encoder_funcs->commit(encoder); 4505 encoder_funcs->commit(encoder);
4545 } 4506 }
4546 /* let the connector get through one full cycle before testing */ 4507 /* let the connector get through one full cycle before testing */
4547 intel_wait_for_vblank(dev); 4508 intel_wait_for_vblank(dev, intel_crtc->pipe);
4548 4509
4549 return crtc; 4510 return crtc;
4550} 4511}
@@ -4749,7 +4710,7 @@ static void intel_increase_pllclock(struct drm_crtc *crtc, bool schedule)
4749 dpll &= ~DISPLAY_RATE_SELECT_FPA1; 4710 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
4750 I915_WRITE(dpll_reg, dpll); 4711 I915_WRITE(dpll_reg, dpll);
4751 dpll = I915_READ(dpll_reg); 4712 dpll = I915_READ(dpll_reg);
4752 intel_wait_for_vblank(dev); 4713 intel_wait_for_vblank(dev, pipe);
4753 dpll = I915_READ(dpll_reg); 4714 dpll = I915_READ(dpll_reg);
4754 if (dpll & DISPLAY_RATE_SELECT_FPA1) 4715 if (dpll & DISPLAY_RATE_SELECT_FPA1)
4755 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n"); 4716 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
@@ -4793,7 +4754,7 @@ static void intel_decrease_pllclock(struct drm_crtc *crtc)
4793 dpll |= DISPLAY_RATE_SELECT_FPA1; 4754 dpll |= DISPLAY_RATE_SELECT_FPA1;
4794 I915_WRITE(dpll_reg, dpll); 4755 I915_WRITE(dpll_reg, dpll);
4795 dpll = I915_READ(dpll_reg); 4756 dpll = I915_READ(dpll_reg);
4796 intel_wait_for_vblank(dev); 4757 intel_wait_for_vblank(dev, pipe);
4797 dpll = I915_READ(dpll_reg); 4758 dpll = I915_READ(dpll_reg);
4798 if (!(dpll & DISPLAY_RATE_SELECT_FPA1)) 4759 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
4799 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n"); 4760 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
@@ -4916,15 +4877,6 @@ static void intel_crtc_destroy(struct drm_crtc *crtc)
4916 kfree(intel_crtc); 4877 kfree(intel_crtc);
4917} 4878}
4918 4879
4919struct intel_unpin_work {
4920 struct work_struct work;
4921 struct drm_device *dev;
4922 struct drm_gem_object *old_fb_obj;
4923 struct drm_gem_object *pending_flip_obj;
4924 struct drm_pending_vblank_event *event;
4925 int pending;
4926};
4927
4928static void intel_unpin_work_fn(struct work_struct *__work) 4880static void intel_unpin_work_fn(struct work_struct *__work)
4929{ 4881{
4930 struct intel_unpin_work *work = 4882 struct intel_unpin_work *work =
@@ -5012,7 +4964,8 @@ void intel_prepare_page_flip(struct drm_device *dev, int plane)
5012 4964
5013 spin_lock_irqsave(&dev->event_lock, flags); 4965 spin_lock_irqsave(&dev->event_lock, flags);
5014 if (intel_crtc->unpin_work) { 4966 if (intel_crtc->unpin_work) {
5015 intel_crtc->unpin_work->pending = 1; 4967 if ((++intel_crtc->unpin_work->pending) > 1)
4968 DRM_ERROR("Prepared flip multiple times\n");
5016 } else { 4969 } else {
5017 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n"); 4970 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
5018 } 4971 }
@@ -5031,9 +4984,9 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc,
5031 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 4984 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5032 struct intel_unpin_work *work; 4985 struct intel_unpin_work *work;
5033 unsigned long flags, offset; 4986 unsigned long flags, offset;
5034 int pipesrc_reg = (intel_crtc->pipe == 0) ? PIPEASRC : PIPEBSRC; 4987 int pipe = intel_crtc->pipe;
5035 int ret, pipesrc; 4988 u32 pf, pipesrc;
5036 u32 flip_mask; 4989 int ret;
5037 4990
5038 work = kzalloc(sizeof *work, GFP_KERNEL); 4991 work = kzalloc(sizeof *work, GFP_KERNEL);
5039 if (work == NULL) 4992 if (work == NULL)
@@ -5082,34 +5035,73 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc,
5082 atomic_inc(&obj_priv->pending_flip); 5035 atomic_inc(&obj_priv->pending_flip);
5083 work->pending_flip_obj = obj; 5036 work->pending_flip_obj = obj;
5084 5037
5085 if (intel_crtc->plane) 5038 if (IS_GEN3(dev) || IS_GEN2(dev)) {
5086 flip_mask = I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT; 5039 u32 flip_mask;
5087 else
5088 flip_mask = I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT;
5089 5040
5090 /* Wait for any previous flip to finish */ 5041 if (intel_crtc->plane)
5091 if (IS_GEN3(dev)) 5042 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
5092 while (I915_READ(ISR) & flip_mask) 5043 else
5093 ; 5044 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
5045
5046 BEGIN_LP_RING(2);
5047 OUT_RING(MI_WAIT_FOR_EVENT | flip_mask);
5048 OUT_RING(0);
5049 ADVANCE_LP_RING();
5050 }
5051
5052 work->enable_stall_check = true;
5094 5053
5095 /* Offset into the new buffer for cases of shared fbs between CRTCs */ 5054 /* Offset into the new buffer for cases of shared fbs between CRTCs */
5096 offset = obj_priv->gtt_offset; 5055 offset = crtc->y * fb->pitch + crtc->x * fb->bits_per_pixel/8;
5097 offset += (crtc->y * fb->pitch) + (crtc->x * (fb->bits_per_pixel) / 8);
5098 5056
5099 BEGIN_LP_RING(4); 5057 BEGIN_LP_RING(4);
5100 if (IS_I965G(dev)) { 5058 switch(INTEL_INFO(dev)->gen) {
5059 case 2:
5101 OUT_RING(MI_DISPLAY_FLIP | 5060 OUT_RING(MI_DISPLAY_FLIP |
5102 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); 5061 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5103 OUT_RING(fb->pitch); 5062 OUT_RING(fb->pitch);
5104 OUT_RING(offset | obj_priv->tiling_mode); 5063 OUT_RING(obj_priv->gtt_offset + offset);
5105 pipesrc = I915_READ(pipesrc_reg); 5064 OUT_RING(MI_NOOP);
5106 OUT_RING(pipesrc & 0x0fff0fff); 5065 break;
5107 } else { 5066
5067 case 3:
5108 OUT_RING(MI_DISPLAY_FLIP_I915 | 5068 OUT_RING(MI_DISPLAY_FLIP_I915 |
5109 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); 5069 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5110 OUT_RING(fb->pitch); 5070 OUT_RING(fb->pitch);
5111 OUT_RING(offset); 5071 OUT_RING(obj_priv->gtt_offset + offset);
5112 OUT_RING(MI_NOOP); 5072 OUT_RING(MI_NOOP);
5073 break;
5074
5075 case 4:
5076 case 5:
5077 /* i965+ uses the linear or tiled offsets from the
5078 * Display Registers (which do not change across a page-flip)
5079 * so we need only reprogram the base address.
5080 */
5081 OUT_RING(MI_DISPLAY_FLIP |
5082 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5083 OUT_RING(fb->pitch);
5084 OUT_RING(obj_priv->gtt_offset | obj_priv->tiling_mode);
5085
5086 /* XXX Enabling the panel-fitter across page-flip is so far
5087 * untested on non-native modes, so ignore it for now.
5088 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
5089 */
5090 pf = 0;
5091 pipesrc = I915_READ(pipe == 0 ? PIPEASRC : PIPEBSRC) & 0x0fff0fff;
5092 OUT_RING(pf | pipesrc);
5093 break;
5094
5095 case 6:
5096 OUT_RING(MI_DISPLAY_FLIP |
5097 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5098 OUT_RING(fb->pitch | obj_priv->tiling_mode);
5099 OUT_RING(obj_priv->gtt_offset);
5100
5101 pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
5102 pipesrc = I915_READ(pipe == 0 ? PIPEASRC : PIPEBSRC) & 0x0fff0fff;
5103 OUT_RING(pf | pipesrc);
5104 break;
5113 } 5105 }
5114 ADVANCE_LP_RING(); 5106 ADVANCE_LP_RING();
5115 5107
@@ -5190,7 +5182,7 @@ static void intel_crtc_init(struct drm_device *dev, int pipe)
5190 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base; 5182 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
5191 5183
5192 intel_crtc->cursor_addr = 0; 5184 intel_crtc->cursor_addr = 0;
5193 intel_crtc->dpms_mode = DRM_MODE_DPMS_OFF; 5185 intel_crtc->dpms_mode = -1;
5194 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs); 5186 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
5195 5187
5196 intel_crtc->busy = false; 5188 intel_crtc->busy = false;
@@ -5432,37 +5424,37 @@ static const struct drm_mode_config_funcs intel_mode_funcs = {
5432}; 5424};
5433 5425
5434static struct drm_gem_object * 5426static struct drm_gem_object *
5435intel_alloc_power_context(struct drm_device *dev) 5427intel_alloc_context_page(struct drm_device *dev)
5436{ 5428{
5437 struct drm_gem_object *pwrctx; 5429 struct drm_gem_object *ctx;
5438 int ret; 5430 int ret;
5439 5431
5440 pwrctx = i915_gem_alloc_object(dev, 4096); 5432 ctx = i915_gem_alloc_object(dev, 4096);
5441 if (!pwrctx) { 5433 if (!ctx) {
5442 DRM_DEBUG("failed to alloc power context, RC6 disabled\n"); 5434 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
5443 return NULL; 5435 return NULL;
5444 } 5436 }
5445 5437
5446 mutex_lock(&dev->struct_mutex); 5438 mutex_lock(&dev->struct_mutex);
5447 ret = i915_gem_object_pin(pwrctx, 4096); 5439 ret = i915_gem_object_pin(ctx, 4096);
5448 if (ret) { 5440 if (ret) {
5449 DRM_ERROR("failed to pin power context: %d\n", ret); 5441 DRM_ERROR("failed to pin power context: %d\n", ret);
5450 goto err_unref; 5442 goto err_unref;
5451 } 5443 }
5452 5444
5453 ret = i915_gem_object_set_to_gtt_domain(pwrctx, 1); 5445 ret = i915_gem_object_set_to_gtt_domain(ctx, 1);
5454 if (ret) { 5446 if (ret) {
5455 DRM_ERROR("failed to set-domain on power context: %d\n", ret); 5447 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
5456 goto err_unpin; 5448 goto err_unpin;
5457 } 5449 }
5458 mutex_unlock(&dev->struct_mutex); 5450 mutex_unlock(&dev->struct_mutex);
5459 5451
5460 return pwrctx; 5452 return ctx;
5461 5453
5462err_unpin: 5454err_unpin:
5463 i915_gem_object_unpin(pwrctx); 5455 i915_gem_object_unpin(ctx);
5464err_unref: 5456err_unref:
5465 drm_gem_object_unreference(pwrctx); 5457 drm_gem_object_unreference(ctx);
5466 mutex_unlock(&dev->struct_mutex); 5458 mutex_unlock(&dev->struct_mutex);
5467 return NULL; 5459 return NULL;
5468} 5460}
@@ -5494,7 +5486,6 @@ void ironlake_enable_drps(struct drm_device *dev)
5494 struct drm_i915_private *dev_priv = dev->dev_private; 5486 struct drm_i915_private *dev_priv = dev->dev_private;
5495 u32 rgvmodectl = I915_READ(MEMMODECTL); 5487 u32 rgvmodectl = I915_READ(MEMMODECTL);
5496 u8 fmax, fmin, fstart, vstart; 5488 u8 fmax, fmin, fstart, vstart;
5497 int i = 0;
5498 5489
5499 /* 100ms RC evaluation intervals */ 5490 /* 100ms RC evaluation intervals */
5500 I915_WRITE(RCUPEI, 100000); 5491 I915_WRITE(RCUPEI, 100000);
@@ -5538,13 +5529,8 @@ void ironlake_enable_drps(struct drm_device *dev)
5538 rgvmodectl |= MEMMODE_SWMODE_EN; 5529 rgvmodectl |= MEMMODE_SWMODE_EN;
5539 I915_WRITE(MEMMODECTL, rgvmodectl); 5530 I915_WRITE(MEMMODECTL, rgvmodectl);
5540 5531
5541 while (I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) { 5532 if (wait_for((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 1, 0))
5542 if (i++ > 100) { 5533 DRM_ERROR("stuck trying to change perf mode\n");
5543 DRM_ERROR("stuck trying to change perf mode\n");
5544 break;
5545 }
5546 msleep(1);
5547 }
5548 msleep(1); 5534 msleep(1);
5549 5535
5550 ironlake_set_drps(dev, fstart); 5536 ironlake_set_drps(dev, fstart);
@@ -5704,6 +5690,9 @@ void intel_init_clock_gating(struct drm_device *dev)
5704 I915_WRITE(DISP_ARB_CTL, 5690 I915_WRITE(DISP_ARB_CTL,
5705 (I915_READ(DISP_ARB_CTL) | 5691 (I915_READ(DISP_ARB_CTL) |
5706 DISP_FBC_WM_DIS)); 5692 DISP_FBC_WM_DIS));
5693 I915_WRITE(WM3_LP_ILK, 0);
5694 I915_WRITE(WM2_LP_ILK, 0);
5695 I915_WRITE(WM1_LP_ILK, 0);
5707 } 5696 }
5708 /* 5697 /*
5709 * Based on the document from hardware guys the following bits 5698 * Based on the document from hardware guys the following bits
@@ -5768,6 +5757,29 @@ void intel_init_clock_gating(struct drm_device *dev)
5768 * GPU can automatically power down the render unit if given a page 5757 * GPU can automatically power down the render unit if given a page
5769 * to save state. 5758 * to save state.
5770 */ 5759 */
5760 if (IS_IRONLAKE_M(dev)) {
5761 if (dev_priv->renderctx == NULL)
5762 dev_priv->renderctx = intel_alloc_context_page(dev);
5763 if (dev_priv->renderctx) {
5764 struct drm_i915_gem_object *obj_priv;
5765 obj_priv = to_intel_bo(dev_priv->renderctx);
5766 if (obj_priv) {
5767 BEGIN_LP_RING(4);
5768 OUT_RING(MI_SET_CONTEXT);
5769 OUT_RING(obj_priv->gtt_offset |
5770 MI_MM_SPACE_GTT |
5771 MI_SAVE_EXT_STATE_EN |
5772 MI_RESTORE_EXT_STATE_EN |
5773 MI_RESTORE_INHIBIT);
5774 OUT_RING(MI_NOOP);
5775 OUT_RING(MI_FLUSH);
5776 ADVANCE_LP_RING();
5777 }
5778 } else
5779 DRM_DEBUG_KMS("Failed to allocate render context."
5780 "Disable RC6\n");
5781 }
5782
5771 if (I915_HAS_RC6(dev) && drm_core_check_feature(dev, DRIVER_MODESET)) { 5783 if (I915_HAS_RC6(dev) && drm_core_check_feature(dev, DRIVER_MODESET)) {
5772 struct drm_i915_gem_object *obj_priv = NULL; 5784 struct drm_i915_gem_object *obj_priv = NULL;
5773 5785
@@ -5776,7 +5788,7 @@ void intel_init_clock_gating(struct drm_device *dev)
5776 } else { 5788 } else {
5777 struct drm_gem_object *pwrctx; 5789 struct drm_gem_object *pwrctx;
5778 5790
5779 pwrctx = intel_alloc_power_context(dev); 5791 pwrctx = intel_alloc_context_page(dev);
5780 if (pwrctx) { 5792 if (pwrctx) {
5781 dev_priv->pwrctx = pwrctx; 5793 dev_priv->pwrctx = pwrctx;
5782 obj_priv = to_intel_bo(pwrctx); 5794 obj_priv = to_intel_bo(pwrctx);
@@ -5948,6 +5960,29 @@ static void intel_init_quirks(struct drm_device *dev)
5948 } 5960 }
5949} 5961}
5950 5962
5963/* Disable the VGA plane that we never use */
5964static void i915_disable_vga(struct drm_device *dev)
5965{
5966 struct drm_i915_private *dev_priv = dev->dev_private;
5967 u8 sr1;
5968 u32 vga_reg;
5969
5970 if (HAS_PCH_SPLIT(dev))
5971 vga_reg = CPU_VGACNTRL;
5972 else
5973 vga_reg = VGACNTRL;
5974
5975 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
5976 outb(1, VGA_SR_INDEX);
5977 sr1 = inb(VGA_SR_DATA);
5978 outb(sr1 | 1<<5, VGA_SR_DATA);
5979 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
5980 udelay(300);
5981
5982 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
5983 POSTING_READ(vga_reg);
5984}
5985
5951void intel_modeset_init(struct drm_device *dev) 5986void intel_modeset_init(struct drm_device *dev)
5952{ 5987{
5953 struct drm_i915_private *dev_priv = dev->dev_private; 5988 struct drm_i915_private *dev_priv = dev->dev_private;
@@ -5996,6 +6031,9 @@ void intel_modeset_init(struct drm_device *dev)
5996 6031
5997 intel_init_clock_gating(dev); 6032 intel_init_clock_gating(dev);
5998 6033
6034 /* Just disable it once at startup */
6035 i915_disable_vga(dev);
6036
5999 if (IS_IRONLAKE_M(dev)) { 6037 if (IS_IRONLAKE_M(dev)) {
6000 ironlake_enable_drps(dev); 6038 ironlake_enable_drps(dev);
6001 intel_init_emon(dev); 6039 intel_init_emon(dev);
@@ -6034,6 +6072,16 @@ void intel_modeset_cleanup(struct drm_device *dev)
6034 if (dev_priv->display.disable_fbc) 6072 if (dev_priv->display.disable_fbc)
6035 dev_priv->display.disable_fbc(dev); 6073 dev_priv->display.disable_fbc(dev);
6036 6074
6075 if (dev_priv->renderctx) {
6076 struct drm_i915_gem_object *obj_priv;
6077
6078 obj_priv = to_intel_bo(dev_priv->renderctx);
6079 I915_WRITE(CCID, obj_priv->gtt_offset &~ CCID_EN);
6080 I915_READ(CCID);
6081 i915_gem_object_unpin(dev_priv->renderctx);
6082 drm_gem_object_unreference(dev_priv->renderctx);
6083 }
6084
6037 if (dev_priv->pwrctx) { 6085 if (dev_priv->pwrctx) {
6038 struct drm_i915_gem_object *obj_priv; 6086 struct drm_i915_gem_object *obj_priv;
6039 6087
generated by cgit v1.2.2 (git 2.25.0) at 2026-01-07 00:46:49 -0500