1 files changed, 24 insertions, 22 deletions

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 2489d0b4c7d2..e5822e79f912 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2249,7 +2249,7 @@ intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
                 I915_WRITE(PIPESRC(intel_crtc->pipe),
                            ((crtc->mode.hdisplay - 1) << 16) |
                            (crtc->mode.vdisplay - 1));
-                if (!intel_crtc->config.pch_pfit.size &&
+                if (!intel_crtc->config.pch_pfit.enabled &&
                     (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
                      intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
                         I915_WRITE(PF_CTL(intel_crtc->pipe), 0);
@@ -3203,7 +3203,7 @@ static void ironlake_pfit_enable(struct intel_crtc *crtc)
         struct drm_i915_private *dev_priv = dev->dev_private;
         int pipe = crtc->pipe;
 
-        if (crtc->config.pch_pfit.size) {
+        if (crtc->config.pch_pfit.enabled) {
                 /* Force use of hard-coded filter coefficients
                  * as some pre-programmed values are broken,
                  * e.g. x201.
@@ -3428,7 +3428,7 @@ static void ironlake_pfit_disable(struct intel_crtc *crtc)
 
         /* To avoid upsetting the power well on haswell only disable the pfit if
          * it's in use. The hw state code will make sure we get this right. */
-        if (crtc->config.pch_pfit.size) {
+        if (crtc->config.pch_pfit.enabled) {
                 I915_WRITE(PF_CTL(pipe), 0);
                 I915_WRITE(PF_WIN_POS(pipe), 0);
                 I915_WRITE(PF_WIN_SZ(pipe), 0);
@@ -4775,6 +4775,10 @@ static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
 
         pipeconf = 0;
 
+        if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
+            I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE)
+                pipeconf |= PIPECONF_ENABLE;
+
         if (intel_crtc->pipe == 0 && INTEL_INFO(dev)->gen < 4) {
                 /* Enable pixel doubling when the dot clock is > 90% of the (display)
                  * core speed.
@@ -4877,9 +4881,6 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
                 return -EINVAL;
         }
 
-        /* Ensure that the cursor is valid for the new mode before changing... */
-        intel_crtc_update_cursor(crtc, true);
-
         if (is_lvds && dev_priv->lvds_downclock_avail) {
                 /*
                  * Ensure we match the reduced clock's P to the target clock.
@@ -5768,9 +5769,6 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
                 intel_crtc->config.dpll.p2 = clock.p2;
         }
 
-        /* Ensure that the cursor is valid for the new mode before changing... */
-        intel_crtc_update_cursor(crtc, true);
-
         /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
         if (intel_crtc->config.has_pch_encoder) {
                 fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll);
@@ -5859,6 +5857,7 @@ static void ironlake_get_pfit_config(struct intel_crtc *crtc,
         tmp = I915_READ(PF_CTL(crtc->pipe));
 
         if (tmp & PF_ENABLE) {
+                pipe_config->pch_pfit.enabled = true;
                 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
                 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
 
@@ -6236,7 +6235,7 @@ static void haswell_modeset_global_resources(struct drm_device *dev)
                 if (!crtc->base.enabled)
                         continue;
 
-                if (crtc->pipe != PIPE_A || crtc->config.pch_pfit.size ||
+                if (crtc->pipe != PIPE_A || crtc->config.pch_pfit.enabled ||
                     crtc->config.cpu_transcoder != TRANSCODER_EDP)
                         enable = true;
         }
@@ -6259,9 +6258,6 @@ static int haswell_crtc_mode_set(struct drm_crtc *crtc,
         if (!intel_ddi_pll_mode_set(crtc))
                 return -EINVAL;
 
-        /* Ensure that the cursor is valid for the new mode before changing... */
-        intel_crtc_update_cursor(crtc, true);
-
         if (intel_crtc->config.has_dp_encoder)
                 intel_dp_set_m_n(intel_crtc);
 
@@ -6494,15 +6490,15 @@ static void haswell_write_eld(struct drm_connector *connector,
 
         /* Set ELD valid state */
         tmp = I915_READ(aud_cntrl_st2);
-        DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp);
+        DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%08x\n", tmp);
         tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
         I915_WRITE(aud_cntrl_st2, tmp);
         tmp = I915_READ(aud_cntrl_st2);
-        DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp);
+        DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%08x\n", tmp);
 
         /* Enable HDMI mode */
         tmp = I915_READ(aud_config);
-        DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp);
+        DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%08x\n", tmp);
         /* clear N_programing_enable and N_value_index */
         tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
         I915_WRITE(aud_config, tmp);
@@ -6937,7 +6933,8 @@ static int intel_crtc_cursor_set(struct drm_crtc *crtc,
         intel_crtc->cursor_width = width;
         intel_crtc->cursor_height = height;
 
-        intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
+        if (intel_crtc->active)
+                intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
 
         return 0;
 fail_unpin:
@@ -6956,7 +6953,8 @@ static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
         intel_crtc->cursor_x = x;
         intel_crtc->cursor_y = y;
 
-        intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
+        if (intel_crtc->active)
+                intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
 
         return 0;
 }
@@ -8205,9 +8203,10 @@ static void intel_dump_pipe_config(struct intel_crtc *crtc,
                       pipe_config->gmch_pfit.control,
                       pipe_config->gmch_pfit.pgm_ratios,
                       pipe_config->gmch_pfit.lvds_border_bits);
-        DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x\n",
+        DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
                       pipe_config->pch_pfit.pos,
-                      pipe_config->pch_pfit.size);
+                      pipe_config->pch_pfit.size,
+                      pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
         DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
 }
 
@@ -8603,8 +8602,11 @@ intel_pipe_config_compare(struct drm_device *dev,
         if (INTEL_INFO(dev)->gen < 4)
                 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
         PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
-        PIPE_CONF_CHECK_I(pch_pfit.pos);
-        PIPE_CONF_CHECK_I(pch_pfit.size);
+        PIPE_CONF_CHECK_I(pch_pfit.enabled);
+        if (current_config->pch_pfit.enabled) {
+                PIPE_CONF_CHECK_I(pch_pfit.pos);
+                PIPE_CONF_CHECK_I(pch_pfit.size);
+        }
 
         PIPE_CONF_CHECK_I(ips_enabled);