diff options
Diffstat (limited to 'drivers/gpu/drm/i915/intel_display.c')
-rw-r--r-- | drivers/gpu/drm/i915/intel_display.c | 21 |
1 files changed, 16 insertions, 5 deletions
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index aea48715aa1e..34286c695bcf 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c | |||
@@ -7339,6 +7339,16 @@ static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv) | |||
7339 | WARN(!dev_priv->pm.irqs_disabled, "IRQs enabled\n"); | 7339 | WARN(!dev_priv->pm.irqs_disabled, "IRQs enabled\n"); |
7340 | } | 7340 | } |
7341 | 7341 | ||
7342 | static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv) | ||
7343 | { | ||
7344 | struct drm_device *dev = dev_priv->dev; | ||
7345 | |||
7346 | if (IS_HASWELL(dev)) | ||
7347 | return I915_READ(D_COMP_HSW); | ||
7348 | else | ||
7349 | return I915_READ(D_COMP_BDW); | ||
7350 | } | ||
7351 | |||
7342 | static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val) | 7352 | static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val) |
7343 | { | 7353 | { |
7344 | struct drm_device *dev = dev_priv->dev; | 7354 | struct drm_device *dev = dev_priv->dev; |
@@ -7350,9 +7360,9 @@ static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val) | |||
7350 | DRM_ERROR("Failed to write to D_COMP\n"); | 7360 | DRM_ERROR("Failed to write to D_COMP\n"); |
7351 | mutex_unlock(&dev_priv->rps.hw_lock); | 7361 | mutex_unlock(&dev_priv->rps.hw_lock); |
7352 | } else { | 7362 | } else { |
7353 | I915_WRITE(D_COMP, val); | 7363 | I915_WRITE(D_COMP_BDW, val); |
7364 | POSTING_READ(D_COMP_BDW); | ||
7354 | } | 7365 | } |
7355 | POSTING_READ(D_COMP); | ||
7356 | } | 7366 | } |
7357 | 7367 | ||
7358 | /* | 7368 | /* |
@@ -7390,12 +7400,13 @@ static void hsw_disable_lcpll(struct drm_i915_private *dev_priv, | |||
7390 | if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1)) | 7400 | if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1)) |
7391 | DRM_ERROR("LCPLL still locked\n"); | 7401 | DRM_ERROR("LCPLL still locked\n"); |
7392 | 7402 | ||
7393 | val = I915_READ(D_COMP); | 7403 | val = hsw_read_dcomp(dev_priv); |
7394 | val |= D_COMP_COMP_DISABLE; | 7404 | val |= D_COMP_COMP_DISABLE; |
7395 | hsw_write_dcomp(dev_priv, val); | 7405 | hsw_write_dcomp(dev_priv, val); |
7396 | ndelay(100); | 7406 | ndelay(100); |
7397 | 7407 | ||
7398 | if (wait_for((I915_READ(D_COMP) & D_COMP_RCOMP_IN_PROGRESS) == 0, 1)) | 7408 | if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0, |
7409 | 1)) | ||
7399 | DRM_ERROR("D_COMP RCOMP still in progress\n"); | 7410 | DRM_ERROR("D_COMP RCOMP still in progress\n"); |
7400 | 7411 | ||
7401 | if (allow_power_down) { | 7412 | if (allow_power_down) { |
@@ -7444,7 +7455,7 @@ static void hsw_restore_lcpll(struct drm_i915_private *dev_priv) | |||
7444 | POSTING_READ(LCPLL_CTL); | 7455 | POSTING_READ(LCPLL_CTL); |
7445 | } | 7456 | } |
7446 | 7457 | ||
7447 | val = I915_READ(D_COMP); | 7458 | val = hsw_read_dcomp(dev_priv); |
7448 | val |= D_COMP_COMP_FORCE; | 7459 | val |= D_COMP_COMP_FORCE; |
7449 | val &= ~D_COMP_COMP_DISABLE; | 7460 | val &= ~D_COMP_COMP_DISABLE; |
7450 | hsw_write_dcomp(dev_priv, val); | 7461 | hsw_write_dcomp(dev_priv, val); |