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path: root/drivers/gpu/drm/i915/intel_display.c
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Diffstat (limited to 'drivers/gpu/drm/i915/intel_display.c')
-rw-r--r--drivers/gpu/drm/i915/intel_display.c37
1 files changed, 19 insertions, 18 deletions
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 914789420906..a8538ac0299d 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -6158,17 +6158,34 @@ static int intel_gen7_queue_flip(struct drm_device *dev,
6158 struct drm_i915_private *dev_priv = dev->dev_private; 6158 struct drm_i915_private *dev_priv = dev->dev_private;
6159 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 6159 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6160 struct intel_ring_buffer *ring = &dev_priv->ring[BCS]; 6160 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
6161 uint32_t plane_bit = 0;
6161 int ret; 6162 int ret;
6162 6163
6163 ret = intel_pin_and_fence_fb_obj(dev, obj, ring); 6164 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
6164 if (ret) 6165 if (ret)
6165 goto err; 6166 goto err;
6166 6167
6168 switch(intel_crtc->plane) {
6169 case PLANE_A:
6170 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
6171 break;
6172 case PLANE_B:
6173 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
6174 break;
6175 case PLANE_C:
6176 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
6177 break;
6178 default:
6179 WARN_ONCE(1, "unknown plane in flip command\n");
6180 ret = -ENODEV;
6181 goto err;
6182 }
6183
6167 ret = intel_ring_begin(ring, 4); 6184 ret = intel_ring_begin(ring, 4);
6168 if (ret) 6185 if (ret)
6169 goto err_unpin; 6186 goto err_unpin;
6170 6187
6171 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | (intel_crtc->plane << 19)); 6188 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
6172 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode)); 6189 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
6173 intel_ring_emit(ring, (obj->gtt_offset)); 6190 intel_ring_emit(ring, (obj->gtt_offset));
6174 intel_ring_emit(ring, (MI_NOOP)); 6191 intel_ring_emit(ring, (MI_NOOP));
@@ -6541,7 +6558,7 @@ static void intel_setup_outputs(struct drm_device *dev)
6541 if (I915_READ(HDMIC) & PORT_DETECTED) 6558 if (I915_READ(HDMIC) & PORT_DETECTED)
6542 intel_hdmi_init(dev, HDMIC); 6559 intel_hdmi_init(dev, HDMIC);
6543 6560
6544 if (I915_READ(HDMID) & PORT_DETECTED) 6561 if (!dpd_is_edp && I915_READ(HDMID) & PORT_DETECTED)
6545 intel_hdmi_init(dev, HDMID); 6562 intel_hdmi_init(dev, HDMID);
6546 6563
6547 if (I915_READ(PCH_DP_C) & DP_DETECTED) 6564 if (I915_READ(PCH_DP_C) & DP_DETECTED)
@@ -6904,19 +6921,6 @@ static void i915_disable_vga(struct drm_device *dev)
6904 POSTING_READ(vga_reg); 6921 POSTING_READ(vga_reg);
6905} 6922}
6906 6923
6907static void ivb_pch_pwm_override(struct drm_device *dev)
6908{
6909 struct drm_i915_private *dev_priv = dev->dev_private;
6910
6911 /*
6912 * IVB has CPU eDP backlight regs too, set things up to let the
6913 * PCH regs control the backlight
6914 */
6915 I915_WRITE(BLC_PWM_CPU_CTL2, PWM_ENABLE);
6916 I915_WRITE(BLC_PWM_CPU_CTL, 0);
6917 I915_WRITE(BLC_PWM_PCH_CTL1, PWM_ENABLE | (1<<30));
6918}
6919
6920void intel_modeset_init_hw(struct drm_device *dev) 6924void intel_modeset_init_hw(struct drm_device *dev)
6921{ 6925{
6922 struct drm_i915_private *dev_priv = dev->dev_private; 6926 struct drm_i915_private *dev_priv = dev->dev_private;
@@ -6933,9 +6937,6 @@ void intel_modeset_init_hw(struct drm_device *dev)
6933 gen6_enable_rps(dev_priv); 6937 gen6_enable_rps(dev_priv);
6934 gen6_update_ring_freq(dev_priv); 6938 gen6_update_ring_freq(dev_priv);
6935 } 6939 }
6936
6937 if (IS_IVYBRIDGE(dev))
6938 ivb_pch_pwm_override(dev);
6939} 6940}
6940 6941
6941void intel_modeset_init(struct drm_device *dev) 6942void intel_modeset_init(struct drm_device *dev)